cpucheck.c 4.3 KB

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  1. /* -*- linux-c -*- ------------------------------------------------------- *
  2. *
  3. * Copyright (C) 1991, 1992 Linus Torvalds
  4. * Copyright 2007 rPath, Inc. - All Rights Reserved
  5. *
  6. * This file is part of the Linux kernel, and is made available under
  7. * the terms of the GNU General Public License version 2.
  8. *
  9. * ----------------------------------------------------------------------- */
  10. /*
  11. * Check for obligatory CPU features and abort if the features are not
  12. * present. This code should be compilable as 16-, 32- or 64-bit
  13. * code, so be very careful with types and inline assembly.
  14. *
  15. * This code should not contain any messages; that requires an
  16. * additional wrapper.
  17. *
  18. * As written, this code is not safe for inclusion into the kernel
  19. * proper (after FPU initialization, in particular).
  20. */
  21. #ifdef _SETUP
  22. # include "boot.h"
  23. #endif
  24. #include <linux/types.h>
  25. #include <asm/processor-flags.h>
  26. #include <asm/required-features.h>
  27. #include <asm/msr-index.h>
  28. static u32 err_flags[NCAPINTS];
  29. static const int req_level = CONFIG_X86_MINIMUM_CPU_FAMILY;
  30. static const u32 req_flags[NCAPINTS] =
  31. {
  32. REQUIRED_MASK0,
  33. REQUIRED_MASK1,
  34. 0, /* REQUIRED_MASK2 not implemented in this file */
  35. 0, /* REQUIRED_MASK3 not implemented in this file */
  36. REQUIRED_MASK4,
  37. 0, /* REQUIRED_MASK5 not implemented in this file */
  38. REQUIRED_MASK6,
  39. 0, /* REQUIRED_MASK7 not implemented in this file */
  40. };
  41. #define A32(a, b, c, d) (((d) << 24)+((c) << 16)+((b) << 8)+(a))
  42. static int is_amd(void)
  43. {
  44. return cpu_vendor[0] == A32('A', 'u', 't', 'h') &&
  45. cpu_vendor[1] == A32('e', 'n', 't', 'i') &&
  46. cpu_vendor[2] == A32('c', 'A', 'M', 'D');
  47. }
  48. static int is_centaur(void)
  49. {
  50. return cpu_vendor[0] == A32('C', 'e', 'n', 't') &&
  51. cpu_vendor[1] == A32('a', 'u', 'r', 'H') &&
  52. cpu_vendor[2] == A32('a', 'u', 'l', 's');
  53. }
  54. static int is_transmeta(void)
  55. {
  56. return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&
  57. cpu_vendor[1] == A32('i', 'n', 'e', 'T') &&
  58. cpu_vendor[2] == A32('M', 'x', '8', '6');
  59. }
  60. /* Returns a bitmask of which words we have error bits in */
  61. static int check_cpuflags(void)
  62. {
  63. u32 err;
  64. int i;
  65. err = 0;
  66. for (i = 0; i < NCAPINTS; i++) {
  67. err_flags[i] = req_flags[i] & ~cpu.flags[i];
  68. if (err_flags[i])
  69. err |= 1 << i;
  70. }
  71. return err;
  72. }
  73. /*
  74. * Returns -1 on error.
  75. *
  76. * *cpu_level is set to the current CPU level; *req_level to the required
  77. * level. x86-64 is considered level 64 for this purpose.
  78. *
  79. * *err_flags_ptr is set to the flags error array if there are flags missing.
  80. */
  81. int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr)
  82. {
  83. int err;
  84. memset(&cpu.flags, 0, sizeof cpu.flags);
  85. cpu.level = 3;
  86. if (has_eflag(X86_EFLAGS_AC))
  87. cpu.level = 4;
  88. get_cpuflags();
  89. err = check_cpuflags();
  90. if (test_bit(X86_FEATURE_LM, cpu.flags))
  91. cpu.level = 64;
  92. if (err == 0x01 &&
  93. !(err_flags[0] &
  94. ~((1 << X86_FEATURE_XMM)|(1 << X86_FEATURE_XMM2))) &&
  95. is_amd()) {
  96. /* If this is an AMD and we're only missing SSE+SSE2, try to
  97. turn them on */
  98. u32 ecx = MSR_K7_HWCR;
  99. u32 eax, edx;
  100. asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
  101. eax &= ~(1 << 15);
  102. asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
  103. get_cpuflags(); /* Make sure it really did something */
  104. err = check_cpuflags();
  105. } else if (err == 0x01 &&
  106. !(err_flags[0] & ~(1 << X86_FEATURE_CX8)) &&
  107. is_centaur() && cpu.model >= 6) {
  108. /* If this is a VIA C3, we might have to enable CX8
  109. explicitly */
  110. u32 ecx = MSR_VIA_FCR;
  111. u32 eax, edx;
  112. asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
  113. eax |= (1<<1)|(1<<7);
  114. asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
  115. set_bit(X86_FEATURE_CX8, cpu.flags);
  116. err = check_cpuflags();
  117. } else if (err == 0x01 && is_transmeta()) {
  118. /* Transmeta might have masked feature bits in word 0 */
  119. u32 ecx = 0x80860004;
  120. u32 eax, edx;
  121. u32 level = 1;
  122. asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
  123. asm("wrmsr" : : "a" (~0), "d" (edx), "c" (ecx));
  124. asm("cpuid"
  125. : "+a" (level), "=d" (cpu.flags[0])
  126. : : "ecx", "ebx");
  127. asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
  128. err = check_cpuflags();
  129. }
  130. if (err_flags_ptr)
  131. *err_flags_ptr = err ? err_flags : NULL;
  132. if (cpu_level_ptr)
  133. *cpu_level_ptr = cpu.level;
  134. if (req_level_ptr)
  135. *req_level_ptr = req_level;
  136. return (cpu.level < req_level || err) ? -1 : 0;
  137. }