board-lager.c 12 KB

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  1. /*
  2. * Lager board support
  3. *
  4. * Copyright (C) 2013 Renesas Solutions Corp.
  5. * Copyright (C) 2013 Magnus Damm
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/gpio.h>
  21. #include <linux/gpio_keys.h>
  22. #include <linux/input.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/kernel.h>
  25. #include <linux/leds.h>
  26. #include <linux/mmc/host.h>
  27. #include <linux/mmc/sh_mmcif.h>
  28. #include <linux/pinctrl/machine.h>
  29. #include <linux/platform_data/gpio-rcar.h>
  30. #include <linux/platform_data/rcar-du.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/phy.h>
  33. #include <linux/regulator/driver.h>
  34. #include <linux/regulator/fixed.h>
  35. #include <linux/regulator/gpio-regulator.h>
  36. #include <linux/regulator/machine.h>
  37. #include <linux/sh_eth.h>
  38. #include <mach/common.h>
  39. #include <mach/irqs.h>
  40. #include <mach/r8a7790.h>
  41. #include <asm/mach-types.h>
  42. #include <asm/mach/arch.h>
  43. #include <linux/mtd/partitions.h>
  44. #include <linux/mtd/mtd.h>
  45. #include <linux/spi/flash.h>
  46. #include <linux/spi/rspi.h>
  47. #include <linux/spi/spi.h>
  48. /* DU */
  49. static struct rcar_du_encoder_data lager_du_encoders[] = {
  50. {
  51. .type = RCAR_DU_ENCODER_VGA,
  52. .output = RCAR_DU_OUTPUT_DPAD0,
  53. }, {
  54. .type = RCAR_DU_ENCODER_NONE,
  55. .output = RCAR_DU_OUTPUT_LVDS1,
  56. .connector.lvds.panel = {
  57. .width_mm = 210,
  58. .height_mm = 158,
  59. .mode = {
  60. .clock = 65000,
  61. .hdisplay = 1024,
  62. .hsync_start = 1048,
  63. .hsync_end = 1184,
  64. .htotal = 1344,
  65. .vdisplay = 768,
  66. .vsync_start = 771,
  67. .vsync_end = 777,
  68. .vtotal = 806,
  69. .flags = 0,
  70. },
  71. },
  72. },
  73. };
  74. static const struct rcar_du_platform_data lager_du_pdata __initconst = {
  75. .encoders = lager_du_encoders,
  76. .num_encoders = ARRAY_SIZE(lager_du_encoders),
  77. };
  78. static const struct resource du_resources[] __initconst = {
  79. DEFINE_RES_MEM(0xfeb00000, 0x70000),
  80. DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"),
  81. DEFINE_RES_MEM_NAMED(0xfeb94000, 0x1c, "lvds.1"),
  82. DEFINE_RES_IRQ(gic_spi(256)),
  83. DEFINE_RES_IRQ(gic_spi(268)),
  84. DEFINE_RES_IRQ(gic_spi(269)),
  85. };
  86. static void __init lager_add_du_device(void)
  87. {
  88. struct platform_device_info info = {
  89. .name = "rcar-du-r8a7790",
  90. .id = -1,
  91. .res = du_resources,
  92. .num_res = ARRAY_SIZE(du_resources),
  93. .data = &lager_du_pdata,
  94. .size_data = sizeof(lager_du_pdata),
  95. .dma_mask = DMA_BIT_MASK(32),
  96. };
  97. platform_device_register_full(&info);
  98. }
  99. /* LEDS */
  100. static struct gpio_led lager_leds[] = {
  101. {
  102. .name = "led8",
  103. .gpio = RCAR_GP_PIN(5, 17),
  104. .default_state = LEDS_GPIO_DEFSTATE_ON,
  105. }, {
  106. .name = "led7",
  107. .gpio = RCAR_GP_PIN(4, 23),
  108. .default_state = LEDS_GPIO_DEFSTATE_ON,
  109. }, {
  110. .name = "led6",
  111. .gpio = RCAR_GP_PIN(4, 22),
  112. .default_state = LEDS_GPIO_DEFSTATE_ON,
  113. },
  114. };
  115. static const struct gpio_led_platform_data lager_leds_pdata __initconst = {
  116. .leds = lager_leds,
  117. .num_leds = ARRAY_SIZE(lager_leds),
  118. };
  119. /* GPIO KEY */
  120. #define GPIO_KEY(c, g, d, ...) \
  121. { .code = c, .gpio = g, .desc = d, .active_low = 1, \
  122. .wakeup = 1, .debounce_interval = 20 }
  123. static struct gpio_keys_button gpio_buttons[] = {
  124. GPIO_KEY(KEY_4, RCAR_GP_PIN(1, 28), "SW2-pin4"),
  125. GPIO_KEY(KEY_3, RCAR_GP_PIN(1, 26), "SW2-pin3"),
  126. GPIO_KEY(KEY_2, RCAR_GP_PIN(1, 24), "SW2-pin2"),
  127. GPIO_KEY(KEY_1, RCAR_GP_PIN(1, 14), "SW2-pin1"),
  128. };
  129. static const struct gpio_keys_platform_data lager_keys_pdata __initconst = {
  130. .buttons = gpio_buttons,
  131. .nbuttons = ARRAY_SIZE(gpio_buttons),
  132. };
  133. /* Fixed 3.3V regulator to be used by MMCIF */
  134. static struct regulator_consumer_supply fixed3v3_power_consumers[] =
  135. {
  136. REGULATOR_SUPPLY("vmmc", "sh_mmcif.1"),
  137. };
  138. /*
  139. * SDHI regulator macro
  140. *
  141. ** FIXME**
  142. * Lager board vqmmc is provided via DA9063 PMIC chip,
  143. * and we should use ${LINK}/drivers/mfd/da9063-* driver for it.
  144. * but, it doesn't have regulator support at this point.
  145. * It uses gpio-regulator for vqmmc as quick-hack.
  146. */
  147. #define SDHI_REGULATOR(idx, vdd_pin, vccq_pin) \
  148. static struct regulator_consumer_supply vcc_sdhi##idx##_consumer = \
  149. REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi." #idx); \
  150. \
  151. static struct regulator_init_data vcc_sdhi##idx##_init_data = { \
  152. .constraints = { \
  153. .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
  154. }, \
  155. .consumer_supplies = &vcc_sdhi##idx##_consumer, \
  156. .num_consumer_supplies = 1, \
  157. }; \
  158. \
  159. static const struct fixed_voltage_config vcc_sdhi##idx##_info __initconst = {\
  160. .supply_name = "SDHI" #idx "Vcc", \
  161. .microvolts = 3300000, \
  162. .gpio = vdd_pin, \
  163. .enable_high = 1, \
  164. .init_data = &vcc_sdhi##idx##_init_data, \
  165. }; \
  166. \
  167. static struct regulator_consumer_supply vccq_sdhi##idx##_consumer = \
  168. REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi." #idx); \
  169. \
  170. static struct regulator_init_data vccq_sdhi##idx##_init_data = { \
  171. .constraints = { \
  172. .input_uV = 3300000, \
  173. .min_uV = 1800000, \
  174. .max_uV = 3300000, \
  175. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | \
  176. REGULATOR_CHANGE_STATUS, \
  177. }, \
  178. .consumer_supplies = &vccq_sdhi##idx##_consumer, \
  179. .num_consumer_supplies = 1, \
  180. }; \
  181. \
  182. static struct gpio vccq_sdhi##idx##_gpio = \
  183. { vccq_pin, GPIOF_OUT_INIT_HIGH, "vccq-sdhi" #idx }; \
  184. \
  185. static struct gpio_regulator_state vccq_sdhi##idx##_states[] = { \
  186. { .value = 1800000, .gpios = 0 }, \
  187. { .value = 3300000, .gpios = 1 }, \
  188. }; \
  189. \
  190. static const struct gpio_regulator_config vccq_sdhi##idx##_info __initconst = {\
  191. .supply_name = "vqmmc", \
  192. .gpios = &vccq_sdhi##idx##_gpio, \
  193. .nr_gpios = 1, \
  194. .states = vccq_sdhi##idx##_states, \
  195. .nr_states = ARRAY_SIZE(vccq_sdhi##idx##_states), \
  196. .type = REGULATOR_VOLTAGE, \
  197. .init_data = &vccq_sdhi##idx##_init_data, \
  198. };
  199. SDHI_REGULATOR(0, RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 29));
  200. SDHI_REGULATOR(2, RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 30));
  201. /* MMCIF */
  202. static const struct sh_mmcif_plat_data mmcif1_pdata __initconst = {
  203. .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
  204. .clk_ctrl2_present = true,
  205. .ccs_unsupported = true,
  206. };
  207. static const struct resource mmcif1_resources[] __initconst = {
  208. DEFINE_RES_MEM(0xee220000, 0x80),
  209. DEFINE_RES_IRQ(gic_spi(170)),
  210. };
  211. /* Ether */
  212. static const struct sh_eth_plat_data ether_pdata __initconst = {
  213. .phy = 0x1,
  214. .edmac_endian = EDMAC_LITTLE_ENDIAN,
  215. .phy_interface = PHY_INTERFACE_MODE_RMII,
  216. .ether_link_active_low = 1,
  217. };
  218. static const struct resource ether_resources[] __initconst = {
  219. DEFINE_RES_MEM(0xee700000, 0x400),
  220. DEFINE_RES_IRQ(gic_spi(162)),
  221. };
  222. /* SPI Flash memory (Spansion S25FL512SAGMFIG11 64Mb) */
  223. static struct mtd_partition spi_flash_part[] = {
  224. /* Reserved for user loader program, read-only */
  225. {
  226. .name = "loader",
  227. .offset = 0,
  228. .size = SZ_256K,
  229. .mask_flags = MTD_WRITEABLE,
  230. },
  231. /* Reserved for user program, read-only */
  232. {
  233. .name = "user",
  234. .offset = MTDPART_OFS_APPEND,
  235. .size = SZ_4M,
  236. .mask_flags = MTD_WRITEABLE,
  237. },
  238. /* All else is writable (e.g. JFFS2) */
  239. {
  240. .name = "flash",
  241. .offset = MTDPART_OFS_APPEND,
  242. .size = MTDPART_SIZ_FULL,
  243. .mask_flags = 0,
  244. },
  245. };
  246. static struct flash_platform_data spi_flash_data = {
  247. .name = "m25p80",
  248. .parts = spi_flash_part,
  249. .nr_parts = ARRAY_SIZE(spi_flash_part),
  250. .type = "s25fl512s",
  251. };
  252. static const struct rspi_plat_data qspi_pdata __initconst = {
  253. .num_chipselect = 1,
  254. };
  255. static const struct spi_board_info spi_info[] __initconst = {
  256. {
  257. .modalias = "m25p80",
  258. .platform_data = &spi_flash_data,
  259. .mode = SPI_MODE_0,
  260. .max_speed_hz = 30000000,
  261. .bus_num = 0,
  262. .chip_select = 0,
  263. },
  264. };
  265. /* QSPI resource */
  266. static const struct resource qspi_resources[] __initconst = {
  267. DEFINE_RES_MEM(0xe6b10000, 0x1000),
  268. DEFINE_RES_IRQ(gic_spi(184)),
  269. };
  270. static const struct pinctrl_map lager_pinctrl_map[] = {
  271. /* DU (CN10: ARGB0, CN13: LVDS) */
  272. PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
  273. "du_rgb666", "du"),
  274. PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
  275. "du_sync_1", "du"),
  276. PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
  277. "du_clk_out_0", "du"),
  278. /* SCIF0 (CN19: DEBUG SERIAL0) */
  279. PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
  280. "scif0_data", "scif0"),
  281. /* SCIF1 (CN20: DEBUG SERIAL1) */
  282. PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
  283. "scif1_data", "scif1"),
  284. /* MMCIF1 */
  285. PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
  286. "mmc1_data8", "mmc1"),
  287. PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
  288. "mmc1_ctrl", "mmc1"),
  289. /* Ether */
  290. PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
  291. "eth_link", "eth"),
  292. PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
  293. "eth_mdio", "eth"),
  294. PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
  295. "eth_rmii", "eth"),
  296. PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
  297. "intc_irq0", "intc"),
  298. };
  299. static void __init lager_add_standard_devices(void)
  300. {
  301. int fixed_regulator_idx = 0;
  302. int gpio_regulator_idx = 0;
  303. r8a7790_clock_init();
  304. pinctrl_register_mappings(lager_pinctrl_map,
  305. ARRAY_SIZE(lager_pinctrl_map));
  306. r8a7790_pinmux_init();
  307. r8a7790_add_standard_devices();
  308. platform_device_register_data(&platform_bus, "leds-gpio", -1,
  309. &lager_leds_pdata,
  310. sizeof(lager_leds_pdata));
  311. platform_device_register_data(&platform_bus, "gpio-keys", -1,
  312. &lager_keys_pdata,
  313. sizeof(lager_keys_pdata));
  314. regulator_register_always_on(fixed_regulator_idx++,
  315. "fixed-3.3V", fixed3v3_power_consumers,
  316. ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
  317. platform_device_register_resndata(&platform_bus, "sh_mmcif", 1,
  318. mmcif1_resources, ARRAY_SIZE(mmcif1_resources),
  319. &mmcif1_pdata, sizeof(mmcif1_pdata));
  320. platform_device_register_resndata(&platform_bus, "r8a7790-ether", -1,
  321. ether_resources,
  322. ARRAY_SIZE(ether_resources),
  323. &ether_pdata, sizeof(ether_pdata));
  324. lager_add_du_device();
  325. platform_device_register_resndata(&platform_bus, "qspi", 0,
  326. qspi_resources,
  327. ARRAY_SIZE(qspi_resources),
  328. &qspi_pdata, sizeof(qspi_pdata));
  329. spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
  330. platform_device_register_data(&platform_bus, "reg-fixed-voltage", fixed_regulator_idx++,
  331. &vcc_sdhi0_info, sizeof(struct fixed_voltage_config));
  332. platform_device_register_data(&platform_bus, "reg-fixed-voltage", fixed_regulator_idx++,
  333. &vcc_sdhi2_info, sizeof(struct fixed_voltage_config));
  334. platform_device_register_data(&platform_bus, "gpio-regulator", gpio_regulator_idx++,
  335. &vccq_sdhi0_info, sizeof(struct gpio_regulator_config));
  336. platform_device_register_data(&platform_bus, "gpio-regulator", gpio_regulator_idx++,
  337. &vccq_sdhi2_info, sizeof(struct gpio_regulator_config));
  338. }
  339. /*
  340. * Ether LEDs on the Lager board are named LINK and ACTIVE which corresponds
  341. * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
  342. * 14-15. We have to set them back to 01 from the default 00 value each time
  343. * the PHY is reset. It's also important because the PHY's LED0 signal is
  344. * connected to SoC's ETH_LINK signal and in the PHY's default mode it will
  345. * bounce on and off after each packet, which we apparently want to avoid.
  346. */
  347. static int lager_ksz8041_fixup(struct phy_device *phydev)
  348. {
  349. u16 phyctrl1 = phy_read(phydev, 0x1e);
  350. phyctrl1 &= ~0xc000;
  351. phyctrl1 |= 0x4000;
  352. return phy_write(phydev, 0x1e, phyctrl1);
  353. }
  354. static void __init lager_init(void)
  355. {
  356. lager_add_standard_devices();
  357. if (IS_ENABLED(CONFIG_PHYLIB))
  358. phy_register_fixup_for_id("r8a7790-ether-ff:01",
  359. lager_ksz8041_fixup);
  360. }
  361. static const char * const lager_boards_compat_dt[] __initconst = {
  362. "renesas,lager",
  363. NULL,
  364. };
  365. DT_MACHINE_START(LAGER_DT, "lager")
  366. .smp = smp_ops(r8a7790_smp_ops),
  367. .init_early = r8a7790_init_early,
  368. .init_time = rcar_gen2_timer_init,
  369. .init_machine = lager_init,
  370. .init_late = shmobile_init_late,
  371. .dt_compat = lager_boards_compat_dt,
  372. MACHINE_END