meson_crtc.c 6.7 KB

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  1. /*
  2. * Copyright (C) 2016 BayLibre, SAS
  3. * Author: Neil Armstrong <narmstrong@baylibre.com>
  4. * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
  5. * Copyright (C) 2014 Endless Mobile
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of the
  10. * License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  19. *
  20. * Written by:
  21. * Jasper St. Pierre <jstpierre@mecheye.net>
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/module.h>
  25. #include <linux/mutex.h>
  26. #include <linux/platform_device.h>
  27. #include <drm/drmP.h>
  28. #include <drm/drm_atomic.h>
  29. #include <drm/drm_atomic_helper.h>
  30. #include <drm/drm_flip_work.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include "meson_crtc.h"
  33. #include "meson_plane.h"
  34. #include "meson_venc.h"
  35. #include "meson_vpp.h"
  36. #include "meson_viu.h"
  37. #include "meson_registers.h"
  38. /* CRTC definition */
  39. struct meson_crtc {
  40. struct drm_crtc base;
  41. struct drm_pending_vblank_event *event;
  42. struct meson_drm *priv;
  43. };
  44. #define to_meson_crtc(x) container_of(x, struct meson_crtc, base)
  45. /* CRTC */
  46. static int meson_crtc_enable_vblank(struct drm_crtc *crtc)
  47. {
  48. struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  49. struct meson_drm *priv = meson_crtc->priv;
  50. meson_venc_enable_vsync(priv);
  51. return 0;
  52. }
  53. static void meson_crtc_disable_vblank(struct drm_crtc *crtc)
  54. {
  55. struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  56. struct meson_drm *priv = meson_crtc->priv;
  57. meson_venc_disable_vsync(priv);
  58. }
  59. static const struct drm_crtc_funcs meson_crtc_funcs = {
  60. .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  61. .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  62. .destroy = drm_crtc_cleanup,
  63. .page_flip = drm_atomic_helper_page_flip,
  64. .reset = drm_atomic_helper_crtc_reset,
  65. .set_config = drm_atomic_helper_set_config,
  66. .enable_vblank = meson_crtc_enable_vblank,
  67. .disable_vblank = meson_crtc_disable_vblank,
  68. };
  69. static void meson_crtc_atomic_enable(struct drm_crtc *crtc,
  70. struct drm_crtc_state *old_state)
  71. {
  72. struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  73. struct drm_crtc_state *crtc_state = crtc->state;
  74. struct meson_drm *priv = meson_crtc->priv;
  75. DRM_DEBUG_DRIVER("\n");
  76. if (!crtc_state) {
  77. DRM_ERROR("Invalid crtc_state\n");
  78. return;
  79. }
  80. /* Enable VPP Postblend */
  81. writel(crtc_state->mode.hdisplay,
  82. priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
  83. writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
  84. priv->io_base + _REG(VPP_MISC));
  85. priv->viu.osd1_enabled = true;
  86. }
  87. static void meson_crtc_atomic_disable(struct drm_crtc *crtc,
  88. struct drm_crtc_state *old_state)
  89. {
  90. struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  91. struct meson_drm *priv = meson_crtc->priv;
  92. priv->viu.osd1_enabled = false;
  93. priv->viu.osd1_commit = false;
  94. /* Disable VPP Postblend */
  95. writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
  96. priv->io_base + _REG(VPP_MISC));
  97. if (crtc->state->event && !crtc->state->active) {
  98. spin_lock_irq(&crtc->dev->event_lock);
  99. drm_crtc_send_vblank_event(crtc, crtc->state->event);
  100. spin_unlock_irq(&crtc->dev->event_lock);
  101. crtc->state->event = NULL;
  102. }
  103. }
  104. static void meson_crtc_atomic_begin(struct drm_crtc *crtc,
  105. struct drm_crtc_state *state)
  106. {
  107. struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  108. unsigned long flags;
  109. if (crtc->state->event) {
  110. WARN_ON(drm_crtc_vblank_get(crtc) != 0);
  111. spin_lock_irqsave(&crtc->dev->event_lock, flags);
  112. meson_crtc->event = crtc->state->event;
  113. spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  114. crtc->state->event = NULL;
  115. }
  116. }
  117. static void meson_crtc_atomic_flush(struct drm_crtc *crtc,
  118. struct drm_crtc_state *old_crtc_state)
  119. {
  120. struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  121. struct meson_drm *priv = meson_crtc->priv;
  122. priv->viu.osd1_commit = true;
  123. }
  124. static const struct drm_crtc_helper_funcs meson_crtc_helper_funcs = {
  125. .atomic_begin = meson_crtc_atomic_begin,
  126. .atomic_flush = meson_crtc_atomic_flush,
  127. .atomic_enable = meson_crtc_atomic_enable,
  128. .atomic_disable = meson_crtc_atomic_disable,
  129. };
  130. void meson_crtc_irq(struct meson_drm *priv)
  131. {
  132. struct meson_crtc *meson_crtc = to_meson_crtc(priv->crtc);
  133. unsigned long flags;
  134. /* Update the OSD registers */
  135. if (priv->viu.osd1_enabled && priv->viu.osd1_commit) {
  136. writel_relaxed(priv->viu.osd1_ctrl_stat,
  137. priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
  138. writel_relaxed(priv->viu.osd1_blk0_cfg[0],
  139. priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0));
  140. writel_relaxed(priv->viu.osd1_blk0_cfg[1],
  141. priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1));
  142. writel_relaxed(priv->viu.osd1_blk0_cfg[2],
  143. priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2));
  144. writel_relaxed(priv->viu.osd1_blk0_cfg[3],
  145. priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3));
  146. writel_relaxed(priv->viu.osd1_blk0_cfg[4],
  147. priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4));
  148. /* If output is interlace, make use of the Scaler */
  149. if (priv->viu.osd1_interlace) {
  150. struct drm_plane *plane = priv->primary_plane;
  151. struct drm_plane_state *state = plane->state;
  152. struct drm_rect dest = {
  153. .x1 = state->crtc_x,
  154. .y1 = state->crtc_y,
  155. .x2 = state->crtc_x + state->crtc_w,
  156. .y2 = state->crtc_y + state->crtc_h,
  157. };
  158. meson_vpp_setup_interlace_vscaler_osd1(priv, &dest);
  159. } else
  160. meson_vpp_disable_interlace_vscaler_osd1(priv);
  161. /* Enable OSD1 */
  162. writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
  163. priv->io_base + _REG(VPP_MISC));
  164. priv->viu.osd1_commit = false;
  165. }
  166. drm_crtc_handle_vblank(priv->crtc);
  167. spin_lock_irqsave(&priv->drm->event_lock, flags);
  168. if (meson_crtc->event) {
  169. drm_crtc_send_vblank_event(priv->crtc, meson_crtc->event);
  170. drm_crtc_vblank_put(priv->crtc);
  171. meson_crtc->event = NULL;
  172. }
  173. spin_unlock_irqrestore(&priv->drm->event_lock, flags);
  174. }
  175. int meson_crtc_create(struct meson_drm *priv)
  176. {
  177. struct meson_crtc *meson_crtc;
  178. struct drm_crtc *crtc;
  179. int ret;
  180. meson_crtc = devm_kzalloc(priv->drm->dev, sizeof(*meson_crtc),
  181. GFP_KERNEL);
  182. if (!meson_crtc)
  183. return -ENOMEM;
  184. meson_crtc->priv = priv;
  185. crtc = &meson_crtc->base;
  186. ret = drm_crtc_init_with_planes(priv->drm, crtc,
  187. priv->primary_plane, NULL,
  188. &meson_crtc_funcs, "meson_crtc");
  189. if (ret) {
  190. dev_err(priv->drm->dev, "Failed to init CRTC\n");
  191. return ret;
  192. }
  193. drm_crtc_helper_add(crtc, &meson_crtc_helper_funcs);
  194. priv->crtc = crtc;
  195. return 0;
  196. }