ipuv3-crtc.c 12 KB

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  1. /*
  2. * i.MX IPUv3 Graphics driver
  3. *
  4. * Copyright (C) 2011 Sascha Hauer, Pengutronix
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/component.h>
  16. #include <linux/module.h>
  17. #include <linux/export.h>
  18. #include <linux/device.h>
  19. #include <linux/platform_device.h>
  20. #include <drm/drmP.h>
  21. #include <drm/drm_atomic.h>
  22. #include <drm/drm_atomic_helper.h>
  23. #include <drm/drm_crtc_helper.h>
  24. #include <linux/clk.h>
  25. #include <linux/errno.h>
  26. #include <drm/drm_gem_cma_helper.h>
  27. #include <drm/drm_fb_cma_helper.h>
  28. #include <video/imx-ipu-v3.h>
  29. #include "imx-drm.h"
  30. #include "ipuv3-plane.h"
  31. #define DRIVER_DESC "i.MX IPUv3 Graphics"
  32. struct ipu_crtc {
  33. struct device *dev;
  34. struct drm_crtc base;
  35. struct imx_drm_crtc *imx_crtc;
  36. /* plane[0] is the full plane, plane[1] is the partial plane */
  37. struct ipu_plane *plane[2];
  38. struct ipu_dc *dc;
  39. struct ipu_di *di;
  40. int irq;
  41. };
  42. static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
  43. {
  44. return container_of(crtc, struct ipu_crtc, base);
  45. }
  46. static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,
  47. struct drm_crtc_state *old_state)
  48. {
  49. struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
  50. struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
  51. ipu_prg_enable(ipu);
  52. ipu_dc_enable(ipu);
  53. ipu_dc_enable_channel(ipu_crtc->dc);
  54. ipu_di_enable(ipu_crtc->di);
  55. }
  56. static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,
  57. struct drm_crtc_state *old_crtc_state)
  58. {
  59. bool disable_partial = false;
  60. bool disable_full = false;
  61. struct drm_plane *plane;
  62. drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {
  63. if (plane == &ipu_crtc->plane[0]->base)
  64. disable_full = true;
  65. if (&ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)
  66. disable_partial = true;
  67. }
  68. if (disable_partial)
  69. ipu_plane_disable(ipu_crtc->plane[1], true);
  70. if (disable_full)
  71. ipu_plane_disable(ipu_crtc->plane[0], false);
  72. }
  73. static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
  74. struct drm_crtc_state *old_crtc_state)
  75. {
  76. struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
  77. struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
  78. ipu_dc_disable_channel(ipu_crtc->dc);
  79. ipu_di_disable(ipu_crtc->di);
  80. /*
  81. * Planes must be disabled before DC clock is removed, as otherwise the
  82. * attached IDMACs will be left in undefined state, possibly hanging
  83. * the IPU or even system.
  84. */
  85. ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);
  86. ipu_dc_disable(ipu);
  87. ipu_prg_disable(ipu);
  88. spin_lock_irq(&crtc->dev->event_lock);
  89. if (crtc->state->event) {
  90. drm_crtc_send_vblank_event(crtc, crtc->state->event);
  91. crtc->state->event = NULL;
  92. }
  93. spin_unlock_irq(&crtc->dev->event_lock);
  94. drm_crtc_vblank_off(crtc);
  95. }
  96. static void imx_drm_crtc_reset(struct drm_crtc *crtc)
  97. {
  98. struct imx_crtc_state *state;
  99. if (crtc->state) {
  100. if (crtc->state->mode_blob)
  101. drm_property_blob_put(crtc->state->mode_blob);
  102. state = to_imx_crtc_state(crtc->state);
  103. memset(state, 0, sizeof(*state));
  104. } else {
  105. state = kzalloc(sizeof(*state), GFP_KERNEL);
  106. if (!state)
  107. return;
  108. crtc->state = &state->base;
  109. }
  110. state->base.crtc = crtc;
  111. }
  112. static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
  113. {
  114. struct imx_crtc_state *state;
  115. state = kzalloc(sizeof(*state), GFP_KERNEL);
  116. if (!state)
  117. return NULL;
  118. __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
  119. WARN_ON(state->base.crtc != crtc);
  120. state->base.crtc = crtc;
  121. return &state->base;
  122. }
  123. static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
  124. struct drm_crtc_state *state)
  125. {
  126. __drm_atomic_helper_crtc_destroy_state(state);
  127. kfree(to_imx_crtc_state(state));
  128. }
  129. static int ipu_enable_vblank(struct drm_crtc *crtc)
  130. {
  131. struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
  132. enable_irq(ipu_crtc->irq);
  133. return 0;
  134. }
  135. static void ipu_disable_vblank(struct drm_crtc *crtc)
  136. {
  137. struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
  138. disable_irq_nosync(ipu_crtc->irq);
  139. }
  140. static const struct drm_crtc_funcs ipu_crtc_funcs = {
  141. .set_config = drm_atomic_helper_set_config,
  142. .destroy = drm_crtc_cleanup,
  143. .page_flip = drm_atomic_helper_page_flip,
  144. .reset = imx_drm_crtc_reset,
  145. .atomic_duplicate_state = imx_drm_crtc_duplicate_state,
  146. .atomic_destroy_state = imx_drm_crtc_destroy_state,
  147. .enable_vblank = ipu_enable_vblank,
  148. .disable_vblank = ipu_disable_vblank,
  149. };
  150. static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
  151. {
  152. struct ipu_crtc *ipu_crtc = dev_id;
  153. drm_crtc_handle_vblank(&ipu_crtc->base);
  154. return IRQ_HANDLED;
  155. }
  156. static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
  157. const struct drm_display_mode *mode,
  158. struct drm_display_mode *adjusted_mode)
  159. {
  160. struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
  161. struct videomode vm;
  162. int ret;
  163. drm_display_mode_to_videomode(adjusted_mode, &vm);
  164. ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
  165. if (ret)
  166. return false;
  167. if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
  168. return false;
  169. drm_display_mode_from_videomode(&vm, adjusted_mode);
  170. return true;
  171. }
  172. static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
  173. struct drm_crtc_state *state)
  174. {
  175. u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);
  176. if (state->active && (primary_plane_mask & state->plane_mask) == 0)
  177. return -EINVAL;
  178. return 0;
  179. }
  180. static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
  181. struct drm_crtc_state *old_crtc_state)
  182. {
  183. drm_crtc_vblank_on(crtc);
  184. spin_lock_irq(&crtc->dev->event_lock);
  185. if (crtc->state->event) {
  186. WARN_ON(drm_crtc_vblank_get(crtc));
  187. drm_crtc_arm_vblank_event(crtc, crtc->state->event);
  188. crtc->state->event = NULL;
  189. }
  190. spin_unlock_irq(&crtc->dev->event_lock);
  191. }
  192. static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
  193. {
  194. struct drm_device *dev = crtc->dev;
  195. struct drm_encoder *encoder;
  196. struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
  197. struct drm_display_mode *mode = &crtc->state->adjusted_mode;
  198. struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
  199. struct ipu_di_signal_cfg sig_cfg = {};
  200. unsigned long encoder_types = 0;
  201. dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
  202. mode->hdisplay);
  203. dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
  204. mode->vdisplay);
  205. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  206. if (encoder->crtc == crtc)
  207. encoder_types |= BIT(encoder->encoder_type);
  208. }
  209. dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
  210. __func__, encoder_types);
  211. /*
  212. * If we have DAC or LDB, then we need the IPU DI clock to be
  213. * the same as the LDB DI clock. For TVDAC, derive the IPU DI
  214. * clock from 27 MHz TVE_DI clock, but allow to divide it.
  215. */
  216. if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
  217. BIT(DRM_MODE_ENCODER_LVDS)))
  218. sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
  219. else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
  220. sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
  221. else
  222. sig_cfg.clkflags = 0;
  223. sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
  224. /* Default to driving pixel data on negative clock edges */
  225. sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
  226. DRM_BUS_FLAG_PIXDATA_POSEDGE);
  227. sig_cfg.bus_format = imx_crtc_state->bus_format;
  228. sig_cfg.v_to_h_sync = 0;
  229. sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
  230. sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
  231. drm_display_mode_to_videomode(mode, &sig_cfg.mode);
  232. ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
  233. mode->flags & DRM_MODE_FLAG_INTERLACE,
  234. imx_crtc_state->bus_format, mode->hdisplay);
  235. ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
  236. }
  237. static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
  238. .mode_fixup = ipu_crtc_mode_fixup,
  239. .mode_set_nofb = ipu_crtc_mode_set_nofb,
  240. .atomic_check = ipu_crtc_atomic_check,
  241. .atomic_begin = ipu_crtc_atomic_begin,
  242. .atomic_disable = ipu_crtc_atomic_disable,
  243. .atomic_enable = ipu_crtc_atomic_enable,
  244. };
  245. static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
  246. {
  247. if (!IS_ERR_OR_NULL(ipu_crtc->dc))
  248. ipu_dc_put(ipu_crtc->dc);
  249. if (!IS_ERR_OR_NULL(ipu_crtc->di))
  250. ipu_di_put(ipu_crtc->di);
  251. }
  252. static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
  253. struct ipu_client_platformdata *pdata)
  254. {
  255. struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
  256. int ret;
  257. ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
  258. if (IS_ERR(ipu_crtc->dc)) {
  259. ret = PTR_ERR(ipu_crtc->dc);
  260. goto err_out;
  261. }
  262. ipu_crtc->di = ipu_di_get(ipu, pdata->di);
  263. if (IS_ERR(ipu_crtc->di)) {
  264. ret = PTR_ERR(ipu_crtc->di);
  265. goto err_out;
  266. }
  267. return 0;
  268. err_out:
  269. ipu_put_resources(ipu_crtc);
  270. return ret;
  271. }
  272. static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
  273. struct ipu_client_platformdata *pdata, struct drm_device *drm)
  274. {
  275. struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
  276. struct drm_crtc *crtc = &ipu_crtc->base;
  277. int dp = -EINVAL;
  278. int ret;
  279. ret = ipu_get_resources(ipu_crtc, pdata);
  280. if (ret) {
  281. dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
  282. ret);
  283. return ret;
  284. }
  285. if (pdata->dp >= 0)
  286. dp = IPU_DP_FLOW_SYNC_BG;
  287. ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
  288. DRM_PLANE_TYPE_PRIMARY);
  289. if (IS_ERR(ipu_crtc->plane[0])) {
  290. ret = PTR_ERR(ipu_crtc->plane[0]);
  291. goto err_put_resources;
  292. }
  293. crtc->port = pdata->of_node;
  294. drm_crtc_helper_add(crtc, &ipu_helper_funcs);
  295. drm_crtc_init_with_planes(drm, crtc, &ipu_crtc->plane[0]->base, NULL,
  296. &ipu_crtc_funcs, NULL);
  297. ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
  298. if (ret) {
  299. dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
  300. ret);
  301. goto err_put_resources;
  302. }
  303. /* If this crtc is using the DP, add an overlay plane */
  304. if (pdata->dp >= 0 && pdata->dma[1] > 0) {
  305. ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
  306. IPU_DP_FLOW_SYNC_FG,
  307. drm_crtc_mask(&ipu_crtc->base),
  308. DRM_PLANE_TYPE_OVERLAY);
  309. if (IS_ERR(ipu_crtc->plane[1])) {
  310. ipu_crtc->plane[1] = NULL;
  311. } else {
  312. ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
  313. if (ret) {
  314. dev_err(ipu_crtc->dev, "getting plane 1 "
  315. "resources failed with %d.\n", ret);
  316. goto err_put_plane0_res;
  317. }
  318. }
  319. }
  320. ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
  321. ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
  322. "imx_drm", ipu_crtc);
  323. if (ret < 0) {
  324. dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
  325. goto err_put_plane1_res;
  326. }
  327. /* Only enable IRQ when we actually need it to trigger work. */
  328. disable_irq(ipu_crtc->irq);
  329. return 0;
  330. err_put_plane1_res:
  331. if (ipu_crtc->plane[1])
  332. ipu_plane_put_resources(ipu_crtc->plane[1]);
  333. err_put_plane0_res:
  334. ipu_plane_put_resources(ipu_crtc->plane[0]);
  335. err_put_resources:
  336. ipu_put_resources(ipu_crtc);
  337. return ret;
  338. }
  339. static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
  340. {
  341. struct ipu_client_platformdata *pdata = dev->platform_data;
  342. struct drm_device *drm = data;
  343. struct ipu_crtc *ipu_crtc;
  344. int ret;
  345. ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
  346. if (!ipu_crtc)
  347. return -ENOMEM;
  348. ipu_crtc->dev = dev;
  349. ret = ipu_crtc_init(ipu_crtc, pdata, drm);
  350. if (ret)
  351. return ret;
  352. dev_set_drvdata(dev, ipu_crtc);
  353. return 0;
  354. }
  355. static void ipu_drm_unbind(struct device *dev, struct device *master,
  356. void *data)
  357. {
  358. struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
  359. ipu_put_resources(ipu_crtc);
  360. if (ipu_crtc->plane[1])
  361. ipu_plane_put_resources(ipu_crtc->plane[1]);
  362. ipu_plane_put_resources(ipu_crtc->plane[0]);
  363. }
  364. static const struct component_ops ipu_crtc_ops = {
  365. .bind = ipu_drm_bind,
  366. .unbind = ipu_drm_unbind,
  367. };
  368. static int ipu_drm_probe(struct platform_device *pdev)
  369. {
  370. struct device *dev = &pdev->dev;
  371. int ret;
  372. if (!dev->platform_data)
  373. return -EINVAL;
  374. ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
  375. if (ret)
  376. return ret;
  377. return component_add(dev, &ipu_crtc_ops);
  378. }
  379. static int ipu_drm_remove(struct platform_device *pdev)
  380. {
  381. component_del(&pdev->dev, &ipu_crtc_ops);
  382. return 0;
  383. }
  384. struct platform_driver ipu_drm_driver = {
  385. .driver = {
  386. .name = "imx-ipuv3-crtc",
  387. },
  388. .probe = ipu_drm_probe,
  389. .remove = ipu_drm_remove,
  390. };