intel_dsi.h 4.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154
  1. /*
  2. * Copyright © 2013 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. */
  23. #ifndef _INTEL_DSI_H
  24. #define _INTEL_DSI_H
  25. #include <drm/drmP.h>
  26. #include <drm/drm_crtc.h>
  27. #include <drm/drm_mipi_dsi.h>
  28. #include "intel_drv.h"
  29. /* Dual Link support */
  30. #define DSI_DUAL_LINK_NONE 0
  31. #define DSI_DUAL_LINK_FRONT_BACK 1
  32. #define DSI_DUAL_LINK_PIXEL_ALT 2
  33. struct intel_dsi_host;
  34. struct intel_dsi {
  35. struct intel_encoder base;
  36. struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS];
  37. /* GPIO Desc for CRC based Panel control */
  38. struct gpio_desc *gpio_panel;
  39. struct intel_connector *attached_connector;
  40. /* bit mask of ports being driven */
  41. u16 ports;
  42. /* if true, use HS mode, otherwise LP */
  43. bool hs;
  44. /* virtual channel */
  45. int channel;
  46. /* Video mode or command mode */
  47. u16 operation_mode;
  48. /* number of DSI lanes */
  49. unsigned int lane_count;
  50. /*
  51. * video mode pixel format
  52. *
  53. * XXX: consolidate on .format in struct mipi_dsi_device.
  54. */
  55. enum mipi_dsi_pixel_format pixel_format;
  56. /* video mode format for MIPI_VIDEO_MODE_FORMAT register */
  57. u32 video_mode_format;
  58. /* eot for MIPI_EOT_DISABLE register */
  59. u8 eotp_pkt;
  60. u8 clock_stop;
  61. u8 escape_clk_div;
  62. u8 dual_link;
  63. u16 dcs_backlight_ports;
  64. u16 dcs_cabc_ports;
  65. u8 pixel_overlap;
  66. u32 port_bits;
  67. u32 bw_timer;
  68. u32 dphy_reg;
  69. u32 video_frmt_cfg_bits;
  70. u16 lp_byte_clk;
  71. /* timeouts in byte clocks */
  72. u16 lp_rx_timeout;
  73. u16 turn_arnd_val;
  74. u16 rst_timer_val;
  75. u16 hs_to_lp_count;
  76. u16 clk_lp_to_hs_count;
  77. u16 clk_hs_to_lp_count;
  78. u16 init_count;
  79. u32 pclk;
  80. u16 burst_mode_ratio;
  81. /* all delays in ms */
  82. u16 backlight_off_delay;
  83. u16 backlight_on_delay;
  84. u16 panel_on_delay;
  85. u16 panel_off_delay;
  86. u16 panel_pwr_cycle_delay;
  87. };
  88. struct intel_dsi_host {
  89. struct mipi_dsi_host base;
  90. struct intel_dsi *intel_dsi;
  91. enum port port;
  92. /* our little hack */
  93. struct mipi_dsi_device *device;
  94. };
  95. static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h)
  96. {
  97. return container_of(h, struct intel_dsi_host, base);
  98. }
  99. #define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask)
  100. static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
  101. {
  102. return container_of(encoder, struct intel_dsi, base.base);
  103. }
  104. /* intel_dsi.c */
  105. void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
  106. enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
  107. /* intel_dsi_pll.c */
  108. bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
  109. int intel_compute_dsi_pll(struct intel_encoder *encoder,
  110. struct intel_crtc_state *config);
  111. void intel_enable_dsi_pll(struct intel_encoder *encoder,
  112. const struct intel_crtc_state *config);
  113. void intel_disable_dsi_pll(struct intel_encoder *encoder);
  114. u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
  115. struct intel_crtc_state *config);
  116. void intel_dsi_reset_clocks(struct intel_encoder *encoder,
  117. enum port port);
  118. /* intel_dsi_vbt.c */
  119. bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
  120. int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi);
  121. void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
  122. enum mipi_seq seq_id);
  123. #endif /* _INTEL_DSI_H */