amdgpu_sync.c 8.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370
  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Christian König <christian.koenig@amd.com>
  29. */
  30. #include <drm/drmP.h>
  31. #include "amdgpu.h"
  32. #include "amdgpu_trace.h"
  33. struct amdgpu_sync_entry {
  34. struct hlist_node node;
  35. struct dma_fence *fence;
  36. bool explicit;
  37. };
  38. static struct kmem_cache *amdgpu_sync_slab;
  39. /**
  40. * amdgpu_sync_create - zero init sync object
  41. *
  42. * @sync: sync object to initialize
  43. *
  44. * Just clear the sync object for now.
  45. */
  46. void amdgpu_sync_create(struct amdgpu_sync *sync)
  47. {
  48. hash_init(sync->fences);
  49. sync->last_vm_update = NULL;
  50. }
  51. /**
  52. * amdgpu_sync_same_dev - test if fence belong to us
  53. *
  54. * @adev: amdgpu device to use for the test
  55. * @f: fence to test
  56. *
  57. * Test if the fence was issued by us.
  58. */
  59. static bool amdgpu_sync_same_dev(struct amdgpu_device *adev,
  60. struct dma_fence *f)
  61. {
  62. struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
  63. if (s_fence) {
  64. struct amdgpu_ring *ring;
  65. ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
  66. return ring->adev == adev;
  67. }
  68. return false;
  69. }
  70. /**
  71. * amdgpu_sync_get_owner - extract the owner of a fence
  72. *
  73. * @fence: fence get the owner from
  74. *
  75. * Extract who originally created the fence.
  76. */
  77. static void *amdgpu_sync_get_owner(struct dma_fence *f)
  78. {
  79. struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
  80. if (s_fence)
  81. return s_fence->owner;
  82. return AMDGPU_FENCE_OWNER_UNDEFINED;
  83. }
  84. /**
  85. * amdgpu_sync_keep_later - Keep the later fence
  86. *
  87. * @keep: existing fence to test
  88. * @fence: new fence
  89. *
  90. * Either keep the existing fence or the new one, depending which one is later.
  91. */
  92. static void amdgpu_sync_keep_later(struct dma_fence **keep,
  93. struct dma_fence *fence)
  94. {
  95. if (*keep && dma_fence_is_later(*keep, fence))
  96. return;
  97. dma_fence_put(*keep);
  98. *keep = dma_fence_get(fence);
  99. }
  100. /**
  101. * amdgpu_sync_add_later - add the fence to the hash
  102. *
  103. * @sync: sync object to add the fence to
  104. * @f: fence to add
  105. *
  106. * Tries to add the fence to an existing hash entry. Returns true when an entry
  107. * was found, false otherwise.
  108. */
  109. static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f)
  110. {
  111. struct amdgpu_sync_entry *e;
  112. hash_for_each_possible(sync->fences, e, node, f->context) {
  113. if (unlikely(e->fence->context != f->context))
  114. continue;
  115. amdgpu_sync_keep_later(&e->fence, f);
  116. return true;
  117. }
  118. return false;
  119. }
  120. /**
  121. * amdgpu_sync_fence - remember to sync to this fence
  122. *
  123. * @sync: sync object to add fence to
  124. * @fence: fence to sync to
  125. *
  126. */
  127. int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
  128. struct dma_fence *f, bool explicit)
  129. {
  130. struct amdgpu_sync_entry *e;
  131. if (!f)
  132. return 0;
  133. if (amdgpu_sync_same_dev(adev, f) &&
  134. amdgpu_sync_get_owner(f) == AMDGPU_FENCE_OWNER_VM)
  135. amdgpu_sync_keep_later(&sync->last_vm_update, f);
  136. if (amdgpu_sync_add_later(sync, f))
  137. return 0;
  138. e = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL);
  139. if (!e)
  140. return -ENOMEM;
  141. e->explicit = explicit;
  142. hash_add(sync->fences, &e->node, f->context);
  143. e->fence = dma_fence_get(f);
  144. return 0;
  145. }
  146. /**
  147. * amdgpu_sync_resv - sync to a reservation object
  148. *
  149. * @sync: sync object to add fences from reservation object to
  150. * @resv: reservation object with embedded fence
  151. * @explicit_sync: true if we should only sync to the exclusive fence
  152. *
  153. * Sync to the fence
  154. */
  155. int amdgpu_sync_resv(struct amdgpu_device *adev,
  156. struct amdgpu_sync *sync,
  157. struct reservation_object *resv,
  158. void *owner, bool explicit_sync)
  159. {
  160. struct reservation_object_list *flist;
  161. struct dma_fence *f;
  162. void *fence_owner;
  163. unsigned i;
  164. int r = 0;
  165. if (resv == NULL)
  166. return -EINVAL;
  167. /* always sync to the exclusive fence */
  168. f = reservation_object_get_excl(resv);
  169. r = amdgpu_sync_fence(adev, sync, f, false);
  170. flist = reservation_object_get_list(resv);
  171. if (!flist || r)
  172. return r;
  173. for (i = 0; i < flist->shared_count; ++i) {
  174. f = rcu_dereference_protected(flist->shared[i],
  175. reservation_object_held(resv));
  176. if (amdgpu_sync_same_dev(adev, f)) {
  177. /* VM updates are only interesting
  178. * for other VM updates and moves.
  179. */
  180. fence_owner = amdgpu_sync_get_owner(f);
  181. if ((owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
  182. (fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
  183. ((owner == AMDGPU_FENCE_OWNER_VM) !=
  184. (fence_owner == AMDGPU_FENCE_OWNER_VM)))
  185. continue;
  186. /* Ignore fence from the same owner and explicit one as
  187. * long as it isn't undefined.
  188. */
  189. if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
  190. (fence_owner == owner || explicit_sync))
  191. continue;
  192. }
  193. r = amdgpu_sync_fence(adev, sync, f, false);
  194. if (r)
  195. break;
  196. }
  197. return r;
  198. }
  199. /**
  200. * amdgpu_sync_peek_fence - get the next fence not signaled yet
  201. *
  202. * @sync: the sync object
  203. * @ring: optional ring to use for test
  204. *
  205. * Returns the next fence not signaled yet without removing it from the sync
  206. * object.
  207. */
  208. struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
  209. struct amdgpu_ring *ring)
  210. {
  211. struct amdgpu_sync_entry *e;
  212. struct hlist_node *tmp;
  213. int i;
  214. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  215. struct dma_fence *f = e->fence;
  216. struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
  217. if (dma_fence_is_signaled(f)) {
  218. hash_del(&e->node);
  219. dma_fence_put(f);
  220. kmem_cache_free(amdgpu_sync_slab, e);
  221. continue;
  222. }
  223. if (ring && s_fence) {
  224. /* For fences from the same ring it is sufficient
  225. * when they are scheduled.
  226. */
  227. if (s_fence->sched == &ring->sched) {
  228. if (dma_fence_is_signaled(&s_fence->scheduled))
  229. continue;
  230. return &s_fence->scheduled;
  231. }
  232. }
  233. return f;
  234. }
  235. return NULL;
  236. }
  237. /**
  238. * amdgpu_sync_get_fence - get the next fence from the sync object
  239. *
  240. * @sync: sync object to use
  241. * @explicit: true if the next fence is explicit
  242. *
  243. * Get and removes the next fence from the sync object not signaled yet.
  244. */
  245. struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync, bool *explicit)
  246. {
  247. struct amdgpu_sync_entry *e;
  248. struct hlist_node *tmp;
  249. struct dma_fence *f;
  250. int i;
  251. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  252. f = e->fence;
  253. if (explicit)
  254. *explicit = e->explicit;
  255. hash_del(&e->node);
  256. kmem_cache_free(amdgpu_sync_slab, e);
  257. if (!dma_fence_is_signaled(f))
  258. return f;
  259. dma_fence_put(f);
  260. }
  261. return NULL;
  262. }
  263. int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr)
  264. {
  265. struct amdgpu_sync_entry *e;
  266. struct hlist_node *tmp;
  267. int i, r;
  268. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  269. r = dma_fence_wait(e->fence, intr);
  270. if (r)
  271. return r;
  272. hash_del(&e->node);
  273. dma_fence_put(e->fence);
  274. kmem_cache_free(amdgpu_sync_slab, e);
  275. }
  276. return 0;
  277. }
  278. /**
  279. * amdgpu_sync_free - free the sync object
  280. *
  281. * @sync: sync object to use
  282. *
  283. * Free the sync object.
  284. */
  285. void amdgpu_sync_free(struct amdgpu_sync *sync)
  286. {
  287. struct amdgpu_sync_entry *e;
  288. struct hlist_node *tmp;
  289. unsigned i;
  290. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  291. hash_del(&e->node);
  292. dma_fence_put(e->fence);
  293. kmem_cache_free(amdgpu_sync_slab, e);
  294. }
  295. dma_fence_put(sync->last_vm_update);
  296. }
  297. /**
  298. * amdgpu_sync_init - init sync object subsystem
  299. *
  300. * Allocate the slab allocator.
  301. */
  302. int amdgpu_sync_init(void)
  303. {
  304. amdgpu_sync_slab = kmem_cache_create(
  305. "amdgpu_sync", sizeof(struct amdgpu_sync_entry), 0,
  306. SLAB_HWCACHE_ALIGN, NULL);
  307. if (!amdgpu_sync_slab)
  308. return -ENOMEM;
  309. return 0;
  310. }
  311. /**
  312. * amdgpu_sync_fini - fini sync object subsystem
  313. *
  314. * Free the slab allocator.
  315. */
  316. void amdgpu_sync_fini(void)
  317. {
  318. kmem_cache_destroy(amdgpu_sync_slab);
  319. }