intel-pt.c 53 KB

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  1. /*
  2. * intel_pt.c: Intel Processor Trace support
  3. * Copyright (c) 2013-2015, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. */
  15. #include <stdio.h>
  16. #include <stdbool.h>
  17. #include <errno.h>
  18. #include <linux/kernel.h>
  19. #include <linux/types.h>
  20. #include "../perf.h"
  21. #include "session.h"
  22. #include "machine.h"
  23. #include "sort.h"
  24. #include "tool.h"
  25. #include "event.h"
  26. #include "evlist.h"
  27. #include "evsel.h"
  28. #include "map.h"
  29. #include "color.h"
  30. #include "util.h"
  31. #include "thread.h"
  32. #include "thread-stack.h"
  33. #include "symbol.h"
  34. #include "callchain.h"
  35. #include "dso.h"
  36. #include "debug.h"
  37. #include "auxtrace.h"
  38. #include "tsc.h"
  39. #include "intel-pt.h"
  40. #include "intel-pt-decoder/intel-pt-log.h"
  41. #include "intel-pt-decoder/intel-pt-decoder.h"
  42. #include "intel-pt-decoder/intel-pt-insn-decoder.h"
  43. #include "intel-pt-decoder/intel-pt-pkt-decoder.h"
  44. #define MAX_TIMESTAMP (~0ULL)
  45. struct intel_pt {
  46. struct auxtrace auxtrace;
  47. struct auxtrace_queues queues;
  48. struct auxtrace_heap heap;
  49. u32 auxtrace_type;
  50. struct perf_session *session;
  51. struct machine *machine;
  52. struct perf_evsel *switch_evsel;
  53. struct thread *unknown_thread;
  54. bool timeless_decoding;
  55. bool sampling_mode;
  56. bool snapshot_mode;
  57. bool per_cpu_mmaps;
  58. bool have_tsc;
  59. bool data_queued;
  60. bool est_tsc;
  61. bool sync_switch;
  62. bool mispred_all;
  63. int have_sched_switch;
  64. u32 pmu_type;
  65. u64 kernel_start;
  66. u64 switch_ip;
  67. u64 ptss_ip;
  68. struct perf_tsc_conversion tc;
  69. bool cap_user_time_zero;
  70. struct itrace_synth_opts synth_opts;
  71. bool sample_instructions;
  72. u64 instructions_sample_type;
  73. u64 instructions_sample_period;
  74. u64 instructions_id;
  75. bool sample_branches;
  76. u32 branches_filter;
  77. u64 branches_sample_type;
  78. u64 branches_id;
  79. bool sample_transactions;
  80. u64 transactions_sample_type;
  81. u64 transactions_id;
  82. bool synth_needs_swap;
  83. u64 tsc_bit;
  84. u64 mtc_bit;
  85. u64 mtc_freq_bits;
  86. u32 tsc_ctc_ratio_n;
  87. u32 tsc_ctc_ratio_d;
  88. u64 cyc_bit;
  89. u64 noretcomp_bit;
  90. unsigned max_non_turbo_ratio;
  91. };
  92. enum switch_state {
  93. INTEL_PT_SS_NOT_TRACING,
  94. INTEL_PT_SS_UNKNOWN,
  95. INTEL_PT_SS_TRACING,
  96. INTEL_PT_SS_EXPECTING_SWITCH_EVENT,
  97. INTEL_PT_SS_EXPECTING_SWITCH_IP,
  98. };
  99. struct intel_pt_queue {
  100. struct intel_pt *pt;
  101. unsigned int queue_nr;
  102. struct auxtrace_buffer *buffer;
  103. void *decoder;
  104. const struct intel_pt_state *state;
  105. struct ip_callchain *chain;
  106. struct branch_stack *last_branch;
  107. struct branch_stack *last_branch_rb;
  108. size_t last_branch_pos;
  109. union perf_event *event_buf;
  110. bool on_heap;
  111. bool stop;
  112. bool step_through_buffers;
  113. bool use_buffer_pid_tid;
  114. pid_t pid, tid;
  115. int cpu;
  116. int switch_state;
  117. pid_t next_tid;
  118. struct thread *thread;
  119. bool exclude_kernel;
  120. bool have_sample;
  121. u64 time;
  122. u64 timestamp;
  123. u32 flags;
  124. u16 insn_len;
  125. u64 last_insn_cnt;
  126. };
  127. static void intel_pt_dump(struct intel_pt *pt __maybe_unused,
  128. unsigned char *buf, size_t len)
  129. {
  130. struct intel_pt_pkt packet;
  131. size_t pos = 0;
  132. int ret, pkt_len, i;
  133. char desc[INTEL_PT_PKT_DESC_MAX];
  134. const char *color = PERF_COLOR_BLUE;
  135. color_fprintf(stdout, color,
  136. ". ... Intel Processor Trace data: size %zu bytes\n",
  137. len);
  138. while (len) {
  139. ret = intel_pt_get_packet(buf, len, &packet);
  140. if (ret > 0)
  141. pkt_len = ret;
  142. else
  143. pkt_len = 1;
  144. printf(".");
  145. color_fprintf(stdout, color, " %08x: ", pos);
  146. for (i = 0; i < pkt_len; i++)
  147. color_fprintf(stdout, color, " %02x", buf[i]);
  148. for (; i < 16; i++)
  149. color_fprintf(stdout, color, " ");
  150. if (ret > 0) {
  151. ret = intel_pt_pkt_desc(&packet, desc,
  152. INTEL_PT_PKT_DESC_MAX);
  153. if (ret > 0)
  154. color_fprintf(stdout, color, " %s\n", desc);
  155. } else {
  156. color_fprintf(stdout, color, " Bad packet!\n");
  157. }
  158. pos += pkt_len;
  159. buf += pkt_len;
  160. len -= pkt_len;
  161. }
  162. }
  163. static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf,
  164. size_t len)
  165. {
  166. printf(".\n");
  167. intel_pt_dump(pt, buf, len);
  168. }
  169. static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a,
  170. struct auxtrace_buffer *b)
  171. {
  172. void *start;
  173. start = intel_pt_find_overlap(a->data, a->size, b->data, b->size,
  174. pt->have_tsc);
  175. if (!start)
  176. return -EINVAL;
  177. b->use_size = b->data + b->size - start;
  178. b->use_data = start;
  179. return 0;
  180. }
  181. static void intel_pt_use_buffer_pid_tid(struct intel_pt_queue *ptq,
  182. struct auxtrace_queue *queue,
  183. struct auxtrace_buffer *buffer)
  184. {
  185. if (queue->cpu == -1 && buffer->cpu != -1)
  186. ptq->cpu = buffer->cpu;
  187. ptq->pid = buffer->pid;
  188. ptq->tid = buffer->tid;
  189. intel_pt_log("queue %u cpu %d pid %d tid %d\n",
  190. ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  191. thread__zput(ptq->thread);
  192. if (ptq->tid != -1) {
  193. if (ptq->pid != -1)
  194. ptq->thread = machine__findnew_thread(ptq->pt->machine,
  195. ptq->pid,
  196. ptq->tid);
  197. else
  198. ptq->thread = machine__find_thread(ptq->pt->machine, -1,
  199. ptq->tid);
  200. }
  201. }
  202. /* This function assumes data is processed sequentially only */
  203. static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data)
  204. {
  205. struct intel_pt_queue *ptq = data;
  206. struct auxtrace_buffer *buffer = ptq->buffer, *old_buffer = buffer;
  207. struct auxtrace_queue *queue;
  208. if (ptq->stop) {
  209. b->len = 0;
  210. return 0;
  211. }
  212. queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
  213. buffer = auxtrace_buffer__next(queue, buffer);
  214. if (!buffer) {
  215. if (old_buffer)
  216. auxtrace_buffer__drop_data(old_buffer);
  217. b->len = 0;
  218. return 0;
  219. }
  220. ptq->buffer = buffer;
  221. if (!buffer->data) {
  222. int fd = perf_data_file__fd(ptq->pt->session->file);
  223. buffer->data = auxtrace_buffer__get_data(buffer, fd);
  224. if (!buffer->data)
  225. return -ENOMEM;
  226. }
  227. if (ptq->pt->snapshot_mode && !buffer->consecutive && old_buffer &&
  228. intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer))
  229. return -ENOMEM;
  230. if (old_buffer)
  231. auxtrace_buffer__drop_data(old_buffer);
  232. if (buffer->use_data) {
  233. b->len = buffer->use_size;
  234. b->buf = buffer->use_data;
  235. } else {
  236. b->len = buffer->size;
  237. b->buf = buffer->data;
  238. }
  239. b->ref_timestamp = buffer->reference;
  240. if (!old_buffer || ptq->pt->sampling_mode || (ptq->pt->snapshot_mode &&
  241. !buffer->consecutive)) {
  242. b->consecutive = false;
  243. b->trace_nr = buffer->buffer_nr + 1;
  244. } else {
  245. b->consecutive = true;
  246. }
  247. if (ptq->use_buffer_pid_tid && (ptq->pid != buffer->pid ||
  248. ptq->tid != buffer->tid))
  249. intel_pt_use_buffer_pid_tid(ptq, queue, buffer);
  250. if (ptq->step_through_buffers)
  251. ptq->stop = true;
  252. if (!b->len)
  253. return intel_pt_get_trace(b, data);
  254. return 0;
  255. }
  256. struct intel_pt_cache_entry {
  257. struct auxtrace_cache_entry entry;
  258. u64 insn_cnt;
  259. u64 byte_cnt;
  260. enum intel_pt_insn_op op;
  261. enum intel_pt_insn_branch branch;
  262. int length;
  263. int32_t rel;
  264. };
  265. static int intel_pt_config_div(const char *var, const char *value, void *data)
  266. {
  267. int *d = data;
  268. long val;
  269. if (!strcmp(var, "intel-pt.cache-divisor")) {
  270. val = strtol(value, NULL, 0);
  271. if (val > 0 && val <= INT_MAX)
  272. *d = val;
  273. }
  274. return 0;
  275. }
  276. static int intel_pt_cache_divisor(void)
  277. {
  278. static int d;
  279. if (d)
  280. return d;
  281. perf_config(intel_pt_config_div, &d);
  282. if (!d)
  283. d = 64;
  284. return d;
  285. }
  286. static unsigned int intel_pt_cache_size(struct dso *dso,
  287. struct machine *machine)
  288. {
  289. off_t size;
  290. size = dso__data_size(dso, machine);
  291. size /= intel_pt_cache_divisor();
  292. if (size < 1000)
  293. return 10;
  294. if (size > (1 << 21))
  295. return 21;
  296. return 32 - __builtin_clz(size);
  297. }
  298. static struct auxtrace_cache *intel_pt_cache(struct dso *dso,
  299. struct machine *machine)
  300. {
  301. struct auxtrace_cache *c;
  302. unsigned int bits;
  303. if (dso->auxtrace_cache)
  304. return dso->auxtrace_cache;
  305. bits = intel_pt_cache_size(dso, machine);
  306. /* Ignoring cache creation failure */
  307. c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200);
  308. dso->auxtrace_cache = c;
  309. return c;
  310. }
  311. static int intel_pt_cache_add(struct dso *dso, struct machine *machine,
  312. u64 offset, u64 insn_cnt, u64 byte_cnt,
  313. struct intel_pt_insn *intel_pt_insn)
  314. {
  315. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  316. struct intel_pt_cache_entry *e;
  317. int err;
  318. if (!c)
  319. return -ENOMEM;
  320. e = auxtrace_cache__alloc_entry(c);
  321. if (!e)
  322. return -ENOMEM;
  323. e->insn_cnt = insn_cnt;
  324. e->byte_cnt = byte_cnt;
  325. e->op = intel_pt_insn->op;
  326. e->branch = intel_pt_insn->branch;
  327. e->length = intel_pt_insn->length;
  328. e->rel = intel_pt_insn->rel;
  329. err = auxtrace_cache__add(c, offset, &e->entry);
  330. if (err)
  331. auxtrace_cache__free_entry(c, e);
  332. return err;
  333. }
  334. static struct intel_pt_cache_entry *
  335. intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset)
  336. {
  337. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  338. if (!c)
  339. return NULL;
  340. return auxtrace_cache__lookup(dso->auxtrace_cache, offset);
  341. }
  342. static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn,
  343. uint64_t *insn_cnt_ptr, uint64_t *ip,
  344. uint64_t to_ip, uint64_t max_insn_cnt,
  345. void *data)
  346. {
  347. struct intel_pt_queue *ptq = data;
  348. struct machine *machine = ptq->pt->machine;
  349. struct thread *thread;
  350. struct addr_location al;
  351. unsigned char buf[1024];
  352. size_t bufsz;
  353. ssize_t len;
  354. int x86_64;
  355. u8 cpumode;
  356. u64 offset, start_offset, start_ip;
  357. u64 insn_cnt = 0;
  358. bool one_map = true;
  359. if (to_ip && *ip == to_ip)
  360. goto out_no_cache;
  361. bufsz = intel_pt_insn_max_size();
  362. if (*ip >= ptq->pt->kernel_start)
  363. cpumode = PERF_RECORD_MISC_KERNEL;
  364. else
  365. cpumode = PERF_RECORD_MISC_USER;
  366. thread = ptq->thread;
  367. if (!thread) {
  368. if (cpumode != PERF_RECORD_MISC_KERNEL)
  369. return -EINVAL;
  370. thread = ptq->pt->unknown_thread;
  371. }
  372. while (1) {
  373. thread__find_addr_map(thread, cpumode, MAP__FUNCTION, *ip, &al);
  374. if (!al.map || !al.map->dso)
  375. return -EINVAL;
  376. if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR &&
  377. dso__data_status_seen(al.map->dso,
  378. DSO_DATA_STATUS_SEEN_ITRACE))
  379. return -ENOENT;
  380. offset = al.map->map_ip(al.map, *ip);
  381. if (!to_ip && one_map) {
  382. struct intel_pt_cache_entry *e;
  383. e = intel_pt_cache_lookup(al.map->dso, machine, offset);
  384. if (e &&
  385. (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) {
  386. *insn_cnt_ptr = e->insn_cnt;
  387. *ip += e->byte_cnt;
  388. intel_pt_insn->op = e->op;
  389. intel_pt_insn->branch = e->branch;
  390. intel_pt_insn->length = e->length;
  391. intel_pt_insn->rel = e->rel;
  392. intel_pt_log_insn_no_data(intel_pt_insn, *ip);
  393. return 0;
  394. }
  395. }
  396. start_offset = offset;
  397. start_ip = *ip;
  398. /* Load maps to ensure dso->is_64_bit has been updated */
  399. map__load(al.map, machine->symbol_filter);
  400. x86_64 = al.map->dso->is_64_bit;
  401. while (1) {
  402. len = dso__data_read_offset(al.map->dso, machine,
  403. offset, buf, bufsz);
  404. if (len <= 0)
  405. return -EINVAL;
  406. if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn))
  407. return -EINVAL;
  408. intel_pt_log_insn(intel_pt_insn, *ip);
  409. insn_cnt += 1;
  410. if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH)
  411. goto out;
  412. if (max_insn_cnt && insn_cnt >= max_insn_cnt)
  413. goto out_no_cache;
  414. *ip += intel_pt_insn->length;
  415. if (to_ip && *ip == to_ip)
  416. goto out_no_cache;
  417. if (*ip >= al.map->end)
  418. break;
  419. offset += intel_pt_insn->length;
  420. }
  421. one_map = false;
  422. }
  423. out:
  424. *insn_cnt_ptr = insn_cnt;
  425. if (!one_map)
  426. goto out_no_cache;
  427. /*
  428. * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate
  429. * entries.
  430. */
  431. if (to_ip) {
  432. struct intel_pt_cache_entry *e;
  433. e = intel_pt_cache_lookup(al.map->dso, machine, start_offset);
  434. if (e)
  435. return 0;
  436. }
  437. /* Ignore cache errors */
  438. intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt,
  439. *ip - start_ip, intel_pt_insn);
  440. return 0;
  441. out_no_cache:
  442. *insn_cnt_ptr = insn_cnt;
  443. return 0;
  444. }
  445. static bool intel_pt_get_config(struct intel_pt *pt,
  446. struct perf_event_attr *attr, u64 *config)
  447. {
  448. if (attr->type == pt->pmu_type) {
  449. if (config)
  450. *config = attr->config;
  451. return true;
  452. }
  453. return false;
  454. }
  455. static bool intel_pt_exclude_kernel(struct intel_pt *pt)
  456. {
  457. struct perf_evsel *evsel;
  458. evlist__for_each(pt->session->evlist, evsel) {
  459. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  460. !evsel->attr.exclude_kernel)
  461. return false;
  462. }
  463. return true;
  464. }
  465. static bool intel_pt_return_compression(struct intel_pt *pt)
  466. {
  467. struct perf_evsel *evsel;
  468. u64 config;
  469. if (!pt->noretcomp_bit)
  470. return true;
  471. evlist__for_each(pt->session->evlist, evsel) {
  472. if (intel_pt_get_config(pt, &evsel->attr, &config) &&
  473. (config & pt->noretcomp_bit))
  474. return false;
  475. }
  476. return true;
  477. }
  478. static unsigned int intel_pt_mtc_period(struct intel_pt *pt)
  479. {
  480. struct perf_evsel *evsel;
  481. unsigned int shift;
  482. u64 config;
  483. if (!pt->mtc_freq_bits)
  484. return 0;
  485. for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++)
  486. config >>= 1;
  487. evlist__for_each(pt->session->evlist, evsel) {
  488. if (intel_pt_get_config(pt, &evsel->attr, &config))
  489. return (config & pt->mtc_freq_bits) >> shift;
  490. }
  491. return 0;
  492. }
  493. static bool intel_pt_timeless_decoding(struct intel_pt *pt)
  494. {
  495. struct perf_evsel *evsel;
  496. bool timeless_decoding = true;
  497. u64 config;
  498. if (!pt->tsc_bit || !pt->cap_user_time_zero)
  499. return true;
  500. evlist__for_each(pt->session->evlist, evsel) {
  501. if (!(evsel->attr.sample_type & PERF_SAMPLE_TIME))
  502. return true;
  503. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  504. if (config & pt->tsc_bit)
  505. timeless_decoding = false;
  506. else
  507. return true;
  508. }
  509. }
  510. return timeless_decoding;
  511. }
  512. static bool intel_pt_tracing_kernel(struct intel_pt *pt)
  513. {
  514. struct perf_evsel *evsel;
  515. evlist__for_each(pt->session->evlist, evsel) {
  516. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  517. !evsel->attr.exclude_kernel)
  518. return true;
  519. }
  520. return false;
  521. }
  522. static bool intel_pt_have_tsc(struct intel_pt *pt)
  523. {
  524. struct perf_evsel *evsel;
  525. bool have_tsc = false;
  526. u64 config;
  527. if (!pt->tsc_bit)
  528. return false;
  529. evlist__for_each(pt->session->evlist, evsel) {
  530. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  531. if (config & pt->tsc_bit)
  532. have_tsc = true;
  533. else
  534. return false;
  535. }
  536. }
  537. return have_tsc;
  538. }
  539. static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns)
  540. {
  541. u64 quot, rem;
  542. quot = ns / pt->tc.time_mult;
  543. rem = ns % pt->tc.time_mult;
  544. return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) /
  545. pt->tc.time_mult;
  546. }
  547. static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt,
  548. unsigned int queue_nr)
  549. {
  550. struct intel_pt_params params = { .get_trace = 0, };
  551. struct intel_pt_queue *ptq;
  552. ptq = zalloc(sizeof(struct intel_pt_queue));
  553. if (!ptq)
  554. return NULL;
  555. if (pt->synth_opts.callchain) {
  556. size_t sz = sizeof(struct ip_callchain);
  557. sz += pt->synth_opts.callchain_sz * sizeof(u64);
  558. ptq->chain = zalloc(sz);
  559. if (!ptq->chain)
  560. goto out_free;
  561. }
  562. if (pt->synth_opts.last_branch) {
  563. size_t sz = sizeof(struct branch_stack);
  564. sz += pt->synth_opts.last_branch_sz *
  565. sizeof(struct branch_entry);
  566. ptq->last_branch = zalloc(sz);
  567. if (!ptq->last_branch)
  568. goto out_free;
  569. ptq->last_branch_rb = zalloc(sz);
  570. if (!ptq->last_branch_rb)
  571. goto out_free;
  572. }
  573. ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE);
  574. if (!ptq->event_buf)
  575. goto out_free;
  576. ptq->pt = pt;
  577. ptq->queue_nr = queue_nr;
  578. ptq->exclude_kernel = intel_pt_exclude_kernel(pt);
  579. ptq->pid = -1;
  580. ptq->tid = -1;
  581. ptq->cpu = -1;
  582. ptq->next_tid = -1;
  583. params.get_trace = intel_pt_get_trace;
  584. params.walk_insn = intel_pt_walk_next_insn;
  585. params.data = ptq;
  586. params.return_compression = intel_pt_return_compression(pt);
  587. params.max_non_turbo_ratio = pt->max_non_turbo_ratio;
  588. params.mtc_period = intel_pt_mtc_period(pt);
  589. params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n;
  590. params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d;
  591. if (pt->synth_opts.instructions) {
  592. if (pt->synth_opts.period) {
  593. switch (pt->synth_opts.period_type) {
  594. case PERF_ITRACE_PERIOD_INSTRUCTIONS:
  595. params.period_type =
  596. INTEL_PT_PERIOD_INSTRUCTIONS;
  597. params.period = pt->synth_opts.period;
  598. break;
  599. case PERF_ITRACE_PERIOD_TICKS:
  600. params.period_type = INTEL_PT_PERIOD_TICKS;
  601. params.period = pt->synth_opts.period;
  602. break;
  603. case PERF_ITRACE_PERIOD_NANOSECS:
  604. params.period_type = INTEL_PT_PERIOD_TICKS;
  605. params.period = intel_pt_ns_to_ticks(pt,
  606. pt->synth_opts.period);
  607. break;
  608. default:
  609. break;
  610. }
  611. }
  612. if (!params.period) {
  613. params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS;
  614. params.period = 1;
  615. }
  616. }
  617. ptq->decoder = intel_pt_decoder_new(&params);
  618. if (!ptq->decoder)
  619. goto out_free;
  620. return ptq;
  621. out_free:
  622. zfree(&ptq->event_buf);
  623. zfree(&ptq->last_branch);
  624. zfree(&ptq->last_branch_rb);
  625. zfree(&ptq->chain);
  626. free(ptq);
  627. return NULL;
  628. }
  629. static void intel_pt_free_queue(void *priv)
  630. {
  631. struct intel_pt_queue *ptq = priv;
  632. if (!ptq)
  633. return;
  634. thread__zput(ptq->thread);
  635. intel_pt_decoder_free(ptq->decoder);
  636. zfree(&ptq->event_buf);
  637. zfree(&ptq->last_branch);
  638. zfree(&ptq->last_branch_rb);
  639. zfree(&ptq->chain);
  640. free(ptq);
  641. }
  642. static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt,
  643. struct auxtrace_queue *queue)
  644. {
  645. struct intel_pt_queue *ptq = queue->priv;
  646. if (queue->tid == -1 || pt->have_sched_switch) {
  647. ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu);
  648. thread__zput(ptq->thread);
  649. }
  650. if (!ptq->thread && ptq->tid != -1)
  651. ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid);
  652. if (ptq->thread) {
  653. ptq->pid = ptq->thread->pid_;
  654. if (queue->cpu == -1)
  655. ptq->cpu = ptq->thread->cpu;
  656. }
  657. }
  658. static void intel_pt_sample_flags(struct intel_pt_queue *ptq)
  659. {
  660. if (ptq->state->flags & INTEL_PT_ABORT_TX) {
  661. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT;
  662. } else if (ptq->state->flags & INTEL_PT_ASYNC) {
  663. if (ptq->state->to_ip)
  664. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
  665. PERF_IP_FLAG_ASYNC |
  666. PERF_IP_FLAG_INTERRUPT;
  667. else
  668. ptq->flags = PERF_IP_FLAG_BRANCH |
  669. PERF_IP_FLAG_TRACE_END;
  670. ptq->insn_len = 0;
  671. } else {
  672. if (ptq->state->from_ip)
  673. ptq->flags = intel_pt_insn_type(ptq->state->insn_op);
  674. else
  675. ptq->flags = PERF_IP_FLAG_BRANCH |
  676. PERF_IP_FLAG_TRACE_BEGIN;
  677. if (ptq->state->flags & INTEL_PT_IN_TX)
  678. ptq->flags |= PERF_IP_FLAG_IN_TX;
  679. ptq->insn_len = ptq->state->insn_len;
  680. }
  681. }
  682. static int intel_pt_setup_queue(struct intel_pt *pt,
  683. struct auxtrace_queue *queue,
  684. unsigned int queue_nr)
  685. {
  686. struct intel_pt_queue *ptq = queue->priv;
  687. if (list_empty(&queue->head))
  688. return 0;
  689. if (!ptq) {
  690. ptq = intel_pt_alloc_queue(pt, queue_nr);
  691. if (!ptq)
  692. return -ENOMEM;
  693. queue->priv = ptq;
  694. if (queue->cpu != -1)
  695. ptq->cpu = queue->cpu;
  696. ptq->tid = queue->tid;
  697. if (pt->sampling_mode) {
  698. if (pt->timeless_decoding)
  699. ptq->step_through_buffers = true;
  700. if (pt->timeless_decoding || !pt->have_sched_switch)
  701. ptq->use_buffer_pid_tid = true;
  702. }
  703. }
  704. if (!ptq->on_heap &&
  705. (!pt->sync_switch ||
  706. ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) {
  707. const struct intel_pt_state *state;
  708. int ret;
  709. if (pt->timeless_decoding)
  710. return 0;
  711. intel_pt_log("queue %u getting timestamp\n", queue_nr);
  712. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  713. queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  714. while (1) {
  715. state = intel_pt_decode(ptq->decoder);
  716. if (state->err) {
  717. if (state->err == INTEL_PT_ERR_NODATA) {
  718. intel_pt_log("queue %u has no timestamp\n",
  719. queue_nr);
  720. return 0;
  721. }
  722. continue;
  723. }
  724. if (state->timestamp)
  725. break;
  726. }
  727. ptq->timestamp = state->timestamp;
  728. intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n",
  729. queue_nr, ptq->timestamp);
  730. ptq->state = state;
  731. ptq->have_sample = true;
  732. intel_pt_sample_flags(ptq);
  733. ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp);
  734. if (ret)
  735. return ret;
  736. ptq->on_heap = true;
  737. }
  738. return 0;
  739. }
  740. static int intel_pt_setup_queues(struct intel_pt *pt)
  741. {
  742. unsigned int i;
  743. int ret;
  744. for (i = 0; i < pt->queues.nr_queues; i++) {
  745. ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i);
  746. if (ret)
  747. return ret;
  748. }
  749. return 0;
  750. }
  751. static inline void intel_pt_copy_last_branch_rb(struct intel_pt_queue *ptq)
  752. {
  753. struct branch_stack *bs_src = ptq->last_branch_rb;
  754. struct branch_stack *bs_dst = ptq->last_branch;
  755. size_t nr = 0;
  756. bs_dst->nr = bs_src->nr;
  757. if (!bs_src->nr)
  758. return;
  759. nr = ptq->pt->synth_opts.last_branch_sz - ptq->last_branch_pos;
  760. memcpy(&bs_dst->entries[0],
  761. &bs_src->entries[ptq->last_branch_pos],
  762. sizeof(struct branch_entry) * nr);
  763. if (bs_src->nr >= ptq->pt->synth_opts.last_branch_sz) {
  764. memcpy(&bs_dst->entries[nr],
  765. &bs_src->entries[0],
  766. sizeof(struct branch_entry) * ptq->last_branch_pos);
  767. }
  768. }
  769. static inline void intel_pt_reset_last_branch_rb(struct intel_pt_queue *ptq)
  770. {
  771. ptq->last_branch_pos = 0;
  772. ptq->last_branch_rb->nr = 0;
  773. }
  774. static void intel_pt_update_last_branch_rb(struct intel_pt_queue *ptq)
  775. {
  776. const struct intel_pt_state *state = ptq->state;
  777. struct branch_stack *bs = ptq->last_branch_rb;
  778. struct branch_entry *be;
  779. if (!ptq->last_branch_pos)
  780. ptq->last_branch_pos = ptq->pt->synth_opts.last_branch_sz;
  781. ptq->last_branch_pos -= 1;
  782. be = &bs->entries[ptq->last_branch_pos];
  783. be->from = state->from_ip;
  784. be->to = state->to_ip;
  785. be->flags.abort = !!(state->flags & INTEL_PT_ABORT_TX);
  786. be->flags.in_tx = !!(state->flags & INTEL_PT_IN_TX);
  787. /* No support for mispredict */
  788. be->flags.mispred = ptq->pt->mispred_all;
  789. if (bs->nr < ptq->pt->synth_opts.last_branch_sz)
  790. bs->nr += 1;
  791. }
  792. static int intel_pt_inject_event(union perf_event *event,
  793. struct perf_sample *sample, u64 type,
  794. bool swapped)
  795. {
  796. event->header.size = perf_event__sample_event_size(sample, type, 0);
  797. return perf_event__synthesize_sample(event, type, 0, sample, swapped);
  798. }
  799. static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq)
  800. {
  801. int ret;
  802. struct intel_pt *pt = ptq->pt;
  803. union perf_event *event = ptq->event_buf;
  804. struct perf_sample sample = { .ip = 0, };
  805. struct dummy_branch_stack {
  806. u64 nr;
  807. struct branch_entry entries;
  808. } dummy_bs;
  809. if (pt->branches_filter && !(pt->branches_filter & ptq->flags))
  810. return 0;
  811. event->sample.header.type = PERF_RECORD_SAMPLE;
  812. event->sample.header.misc = PERF_RECORD_MISC_USER;
  813. event->sample.header.size = sizeof(struct perf_event_header);
  814. if (!pt->timeless_decoding)
  815. sample.time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  816. sample.ip = ptq->state->from_ip;
  817. sample.pid = ptq->pid;
  818. sample.tid = ptq->tid;
  819. sample.addr = ptq->state->to_ip;
  820. sample.id = ptq->pt->branches_id;
  821. sample.stream_id = ptq->pt->branches_id;
  822. sample.period = 1;
  823. sample.cpu = ptq->cpu;
  824. sample.flags = ptq->flags;
  825. sample.insn_len = ptq->insn_len;
  826. /*
  827. * perf report cannot handle events without a branch stack when using
  828. * SORT_MODE__BRANCH so make a dummy one.
  829. */
  830. if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) {
  831. dummy_bs = (struct dummy_branch_stack){
  832. .nr = 1,
  833. .entries = {
  834. .from = sample.ip,
  835. .to = sample.addr,
  836. },
  837. };
  838. sample.branch_stack = (struct branch_stack *)&dummy_bs;
  839. }
  840. if (pt->synth_opts.inject) {
  841. ret = intel_pt_inject_event(event, &sample,
  842. pt->branches_sample_type,
  843. pt->synth_needs_swap);
  844. if (ret)
  845. return ret;
  846. }
  847. ret = perf_session__deliver_synth_event(pt->session, event, &sample);
  848. if (ret)
  849. pr_err("Intel Processor Trace: failed to deliver branch event, error %d\n",
  850. ret);
  851. return ret;
  852. }
  853. static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq)
  854. {
  855. int ret;
  856. struct intel_pt *pt = ptq->pt;
  857. union perf_event *event = ptq->event_buf;
  858. struct perf_sample sample = { .ip = 0, };
  859. event->sample.header.type = PERF_RECORD_SAMPLE;
  860. event->sample.header.misc = PERF_RECORD_MISC_USER;
  861. event->sample.header.size = sizeof(struct perf_event_header);
  862. if (!pt->timeless_decoding)
  863. sample.time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  864. sample.ip = ptq->state->from_ip;
  865. sample.pid = ptq->pid;
  866. sample.tid = ptq->tid;
  867. sample.addr = ptq->state->to_ip;
  868. sample.id = ptq->pt->instructions_id;
  869. sample.stream_id = ptq->pt->instructions_id;
  870. sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt;
  871. sample.cpu = ptq->cpu;
  872. sample.flags = ptq->flags;
  873. sample.insn_len = ptq->insn_len;
  874. ptq->last_insn_cnt = ptq->state->tot_insn_cnt;
  875. if (pt->synth_opts.callchain) {
  876. thread_stack__sample(ptq->thread, ptq->chain,
  877. pt->synth_opts.callchain_sz, sample.ip);
  878. sample.callchain = ptq->chain;
  879. }
  880. if (pt->synth_opts.last_branch) {
  881. intel_pt_copy_last_branch_rb(ptq);
  882. sample.branch_stack = ptq->last_branch;
  883. }
  884. if (pt->synth_opts.inject) {
  885. ret = intel_pt_inject_event(event, &sample,
  886. pt->instructions_sample_type,
  887. pt->synth_needs_swap);
  888. if (ret)
  889. return ret;
  890. }
  891. ret = perf_session__deliver_synth_event(pt->session, event, &sample);
  892. if (ret)
  893. pr_err("Intel Processor Trace: failed to deliver instruction event, error %d\n",
  894. ret);
  895. if (pt->synth_opts.last_branch)
  896. intel_pt_reset_last_branch_rb(ptq);
  897. return ret;
  898. }
  899. static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq)
  900. {
  901. int ret;
  902. struct intel_pt *pt = ptq->pt;
  903. union perf_event *event = ptq->event_buf;
  904. struct perf_sample sample = { .ip = 0, };
  905. event->sample.header.type = PERF_RECORD_SAMPLE;
  906. event->sample.header.misc = PERF_RECORD_MISC_USER;
  907. event->sample.header.size = sizeof(struct perf_event_header);
  908. if (!pt->timeless_decoding)
  909. sample.time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  910. sample.ip = ptq->state->from_ip;
  911. sample.pid = ptq->pid;
  912. sample.tid = ptq->tid;
  913. sample.addr = ptq->state->to_ip;
  914. sample.id = ptq->pt->transactions_id;
  915. sample.stream_id = ptq->pt->transactions_id;
  916. sample.period = 1;
  917. sample.cpu = ptq->cpu;
  918. sample.flags = ptq->flags;
  919. sample.insn_len = ptq->insn_len;
  920. if (pt->synth_opts.callchain) {
  921. thread_stack__sample(ptq->thread, ptq->chain,
  922. pt->synth_opts.callchain_sz, sample.ip);
  923. sample.callchain = ptq->chain;
  924. }
  925. if (pt->synth_opts.last_branch) {
  926. intel_pt_copy_last_branch_rb(ptq);
  927. sample.branch_stack = ptq->last_branch;
  928. }
  929. if (pt->synth_opts.inject) {
  930. ret = intel_pt_inject_event(event, &sample,
  931. pt->transactions_sample_type,
  932. pt->synth_needs_swap);
  933. if (ret)
  934. return ret;
  935. }
  936. ret = perf_session__deliver_synth_event(pt->session, event, &sample);
  937. if (ret)
  938. pr_err("Intel Processor Trace: failed to deliver transaction event, error %d\n",
  939. ret);
  940. if (pt->synth_opts.callchain)
  941. intel_pt_reset_last_branch_rb(ptq);
  942. return ret;
  943. }
  944. static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu,
  945. pid_t pid, pid_t tid, u64 ip)
  946. {
  947. union perf_event event;
  948. char msg[MAX_AUXTRACE_ERROR_MSG];
  949. int err;
  950. intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG);
  951. auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE,
  952. code, cpu, pid, tid, ip, msg);
  953. err = perf_session__deliver_synth_event(pt->session, &event, NULL);
  954. if (err)
  955. pr_err("Intel Processor Trace: failed to deliver error event, error %d\n",
  956. err);
  957. return err;
  958. }
  959. static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq)
  960. {
  961. struct auxtrace_queue *queue;
  962. pid_t tid = ptq->next_tid;
  963. int err;
  964. if (tid == -1)
  965. return 0;
  966. intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid);
  967. err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid);
  968. queue = &pt->queues.queue_array[ptq->queue_nr];
  969. intel_pt_set_pid_tid_cpu(pt, queue);
  970. ptq->next_tid = -1;
  971. return err;
  972. }
  973. static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip)
  974. {
  975. struct intel_pt *pt = ptq->pt;
  976. return ip == pt->switch_ip &&
  977. (ptq->flags & PERF_IP_FLAG_BRANCH) &&
  978. !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC |
  979. PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT));
  980. }
  981. static int intel_pt_sample(struct intel_pt_queue *ptq)
  982. {
  983. const struct intel_pt_state *state = ptq->state;
  984. struct intel_pt *pt = ptq->pt;
  985. int err;
  986. if (!ptq->have_sample)
  987. return 0;
  988. ptq->have_sample = false;
  989. if (pt->sample_instructions &&
  990. (state->type & INTEL_PT_INSTRUCTION)) {
  991. err = intel_pt_synth_instruction_sample(ptq);
  992. if (err)
  993. return err;
  994. }
  995. if (pt->sample_transactions &&
  996. (state->type & INTEL_PT_TRANSACTION)) {
  997. err = intel_pt_synth_transaction_sample(ptq);
  998. if (err)
  999. return err;
  1000. }
  1001. if (!(state->type & INTEL_PT_BRANCH))
  1002. return 0;
  1003. if (pt->synth_opts.callchain)
  1004. thread_stack__event(ptq->thread, ptq->flags, state->from_ip,
  1005. state->to_ip, ptq->insn_len,
  1006. state->trace_nr);
  1007. else
  1008. thread_stack__set_trace_nr(ptq->thread, state->trace_nr);
  1009. if (pt->sample_branches) {
  1010. err = intel_pt_synth_branch_sample(ptq);
  1011. if (err)
  1012. return err;
  1013. }
  1014. if (pt->synth_opts.last_branch)
  1015. intel_pt_update_last_branch_rb(ptq);
  1016. if (!pt->sync_switch)
  1017. return 0;
  1018. if (intel_pt_is_switch_ip(ptq, state->to_ip)) {
  1019. switch (ptq->switch_state) {
  1020. case INTEL_PT_SS_UNKNOWN:
  1021. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1022. err = intel_pt_next_tid(pt, ptq);
  1023. if (err)
  1024. return err;
  1025. ptq->switch_state = INTEL_PT_SS_TRACING;
  1026. break;
  1027. default:
  1028. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT;
  1029. return 1;
  1030. }
  1031. } else if (!state->to_ip) {
  1032. ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
  1033. } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) {
  1034. ptq->switch_state = INTEL_PT_SS_UNKNOWN;
  1035. } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1036. state->to_ip == pt->ptss_ip &&
  1037. (ptq->flags & PERF_IP_FLAG_CALL)) {
  1038. ptq->switch_state = INTEL_PT_SS_TRACING;
  1039. }
  1040. return 0;
  1041. }
  1042. static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip)
  1043. {
  1044. struct machine *machine = pt->machine;
  1045. struct map *map;
  1046. struct symbol *sym, *start;
  1047. u64 ip, switch_ip = 0;
  1048. const char *ptss;
  1049. if (ptss_ip)
  1050. *ptss_ip = 0;
  1051. map = machine__kernel_map(machine);
  1052. if (!map)
  1053. return 0;
  1054. if (map__load(map, machine->symbol_filter))
  1055. return 0;
  1056. start = dso__first_symbol(map->dso, MAP__FUNCTION);
  1057. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1058. if (sym->binding == STB_GLOBAL &&
  1059. !strcmp(sym->name, "__switch_to")) {
  1060. ip = map->unmap_ip(map, sym->start);
  1061. if (ip >= map->start && ip < map->end) {
  1062. switch_ip = ip;
  1063. break;
  1064. }
  1065. }
  1066. }
  1067. if (!switch_ip || !ptss_ip)
  1068. return 0;
  1069. if (pt->have_sched_switch == 1)
  1070. ptss = "perf_trace_sched_switch";
  1071. else
  1072. ptss = "__perf_event_task_sched_out";
  1073. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1074. if (!strcmp(sym->name, ptss)) {
  1075. ip = map->unmap_ip(map, sym->start);
  1076. if (ip >= map->start && ip < map->end) {
  1077. *ptss_ip = ip;
  1078. break;
  1079. }
  1080. }
  1081. }
  1082. return switch_ip;
  1083. }
  1084. static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp)
  1085. {
  1086. const struct intel_pt_state *state = ptq->state;
  1087. struct intel_pt *pt = ptq->pt;
  1088. int err;
  1089. if (!pt->kernel_start) {
  1090. pt->kernel_start = machine__kernel_start(pt->machine);
  1091. if (pt->per_cpu_mmaps &&
  1092. (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) &&
  1093. !pt->timeless_decoding && intel_pt_tracing_kernel(pt) &&
  1094. !pt->sampling_mode) {
  1095. pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip);
  1096. if (pt->switch_ip) {
  1097. intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n",
  1098. pt->switch_ip, pt->ptss_ip);
  1099. pt->sync_switch = true;
  1100. }
  1101. }
  1102. }
  1103. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  1104. ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  1105. while (1) {
  1106. err = intel_pt_sample(ptq);
  1107. if (err)
  1108. return err;
  1109. state = intel_pt_decode(ptq->decoder);
  1110. if (state->err) {
  1111. if (state->err == INTEL_PT_ERR_NODATA)
  1112. return 1;
  1113. if (pt->sync_switch &&
  1114. state->from_ip >= pt->kernel_start) {
  1115. pt->sync_switch = false;
  1116. intel_pt_next_tid(pt, ptq);
  1117. }
  1118. if (pt->synth_opts.errors) {
  1119. err = intel_pt_synth_error(pt, state->err,
  1120. ptq->cpu, ptq->pid,
  1121. ptq->tid,
  1122. state->from_ip);
  1123. if (err)
  1124. return err;
  1125. }
  1126. continue;
  1127. }
  1128. ptq->state = state;
  1129. ptq->have_sample = true;
  1130. intel_pt_sample_flags(ptq);
  1131. /* Use estimated TSC upon return to user space */
  1132. if (pt->est_tsc &&
  1133. (state->from_ip >= pt->kernel_start || !state->from_ip) &&
  1134. state->to_ip && state->to_ip < pt->kernel_start) {
  1135. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1136. state->timestamp, state->est_timestamp);
  1137. ptq->timestamp = state->est_timestamp;
  1138. /* Use estimated TSC in unknown switch state */
  1139. } else if (pt->sync_switch &&
  1140. ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1141. intel_pt_is_switch_ip(ptq, state->to_ip) &&
  1142. ptq->next_tid == -1) {
  1143. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1144. state->timestamp, state->est_timestamp);
  1145. ptq->timestamp = state->est_timestamp;
  1146. } else if (state->timestamp > ptq->timestamp) {
  1147. ptq->timestamp = state->timestamp;
  1148. }
  1149. if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) {
  1150. *timestamp = ptq->timestamp;
  1151. return 0;
  1152. }
  1153. }
  1154. return 0;
  1155. }
  1156. static inline int intel_pt_update_queues(struct intel_pt *pt)
  1157. {
  1158. if (pt->queues.new_data) {
  1159. pt->queues.new_data = false;
  1160. return intel_pt_setup_queues(pt);
  1161. }
  1162. return 0;
  1163. }
  1164. static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp)
  1165. {
  1166. unsigned int queue_nr;
  1167. u64 ts;
  1168. int ret;
  1169. while (1) {
  1170. struct auxtrace_queue *queue;
  1171. struct intel_pt_queue *ptq;
  1172. if (!pt->heap.heap_cnt)
  1173. return 0;
  1174. if (pt->heap.heap_array[0].ordinal >= timestamp)
  1175. return 0;
  1176. queue_nr = pt->heap.heap_array[0].queue_nr;
  1177. queue = &pt->queues.queue_array[queue_nr];
  1178. ptq = queue->priv;
  1179. intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n",
  1180. queue_nr, pt->heap.heap_array[0].ordinal,
  1181. timestamp);
  1182. auxtrace_heap__pop(&pt->heap);
  1183. if (pt->heap.heap_cnt) {
  1184. ts = pt->heap.heap_array[0].ordinal + 1;
  1185. if (ts > timestamp)
  1186. ts = timestamp;
  1187. } else {
  1188. ts = timestamp;
  1189. }
  1190. intel_pt_set_pid_tid_cpu(pt, queue);
  1191. ret = intel_pt_run_decoder(ptq, &ts);
  1192. if (ret < 0) {
  1193. auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1194. return ret;
  1195. }
  1196. if (!ret) {
  1197. ret = auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1198. if (ret < 0)
  1199. return ret;
  1200. } else {
  1201. ptq->on_heap = false;
  1202. }
  1203. }
  1204. return 0;
  1205. }
  1206. static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid,
  1207. u64 time_)
  1208. {
  1209. struct auxtrace_queues *queues = &pt->queues;
  1210. unsigned int i;
  1211. u64 ts = 0;
  1212. for (i = 0; i < queues->nr_queues; i++) {
  1213. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1214. struct intel_pt_queue *ptq = queue->priv;
  1215. if (ptq && (tid == -1 || ptq->tid == tid)) {
  1216. ptq->time = time_;
  1217. intel_pt_set_pid_tid_cpu(pt, queue);
  1218. intel_pt_run_decoder(ptq, &ts);
  1219. }
  1220. }
  1221. return 0;
  1222. }
  1223. static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample)
  1224. {
  1225. return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu,
  1226. sample->pid, sample->tid, 0);
  1227. }
  1228. static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu)
  1229. {
  1230. unsigned i, j;
  1231. if (cpu < 0 || !pt->queues.nr_queues)
  1232. return NULL;
  1233. if ((unsigned)cpu >= pt->queues.nr_queues)
  1234. i = pt->queues.nr_queues - 1;
  1235. else
  1236. i = cpu;
  1237. if (pt->queues.queue_array[i].cpu == cpu)
  1238. return pt->queues.queue_array[i].priv;
  1239. for (j = 0; i > 0; j++) {
  1240. if (pt->queues.queue_array[--i].cpu == cpu)
  1241. return pt->queues.queue_array[i].priv;
  1242. }
  1243. for (; j < pt->queues.nr_queues; j++) {
  1244. if (pt->queues.queue_array[j].cpu == cpu)
  1245. return pt->queues.queue_array[j].priv;
  1246. }
  1247. return NULL;
  1248. }
  1249. static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid,
  1250. u64 timestamp)
  1251. {
  1252. struct intel_pt_queue *ptq;
  1253. int err;
  1254. if (!pt->sync_switch)
  1255. return 1;
  1256. ptq = intel_pt_cpu_to_ptq(pt, cpu);
  1257. if (!ptq)
  1258. return 1;
  1259. switch (ptq->switch_state) {
  1260. case INTEL_PT_SS_NOT_TRACING:
  1261. ptq->next_tid = -1;
  1262. break;
  1263. case INTEL_PT_SS_UNKNOWN:
  1264. case INTEL_PT_SS_TRACING:
  1265. ptq->next_tid = tid;
  1266. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP;
  1267. return 0;
  1268. case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
  1269. if (!ptq->on_heap) {
  1270. ptq->timestamp = perf_time_to_tsc(timestamp,
  1271. &pt->tc);
  1272. err = auxtrace_heap__add(&pt->heap, ptq->queue_nr,
  1273. ptq->timestamp);
  1274. if (err)
  1275. return err;
  1276. ptq->on_heap = true;
  1277. }
  1278. ptq->switch_state = INTEL_PT_SS_TRACING;
  1279. break;
  1280. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1281. ptq->next_tid = tid;
  1282. intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu);
  1283. break;
  1284. default:
  1285. break;
  1286. }
  1287. return 1;
  1288. }
  1289. static int intel_pt_process_switch(struct intel_pt *pt,
  1290. struct perf_sample *sample)
  1291. {
  1292. struct perf_evsel *evsel;
  1293. pid_t tid;
  1294. int cpu, ret;
  1295. evsel = perf_evlist__id2evsel(pt->session->evlist, sample->id);
  1296. if (evsel != pt->switch_evsel)
  1297. return 0;
  1298. tid = perf_evsel__intval(evsel, sample, "next_pid");
  1299. cpu = sample->cpu;
  1300. intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1301. cpu, tid, sample->time, perf_time_to_tsc(sample->time,
  1302. &pt->tc));
  1303. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1304. if (ret <= 0)
  1305. return ret;
  1306. return machine__set_current_tid(pt->machine, cpu, -1, tid);
  1307. }
  1308. static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event,
  1309. struct perf_sample *sample)
  1310. {
  1311. bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT;
  1312. pid_t pid, tid;
  1313. int cpu, ret;
  1314. cpu = sample->cpu;
  1315. if (pt->have_sched_switch == 3) {
  1316. if (!out)
  1317. return 0;
  1318. if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) {
  1319. pr_err("Expecting CPU-wide context switch event\n");
  1320. return -EINVAL;
  1321. }
  1322. pid = event->context_switch.next_prev_pid;
  1323. tid = event->context_switch.next_prev_tid;
  1324. } else {
  1325. if (out)
  1326. return 0;
  1327. pid = sample->pid;
  1328. tid = sample->tid;
  1329. }
  1330. if (tid == -1) {
  1331. pr_err("context_switch event has no tid\n");
  1332. return -EINVAL;
  1333. }
  1334. intel_pt_log("context_switch: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1335. cpu, pid, tid, sample->time, perf_time_to_tsc(sample->time,
  1336. &pt->tc));
  1337. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1338. if (ret <= 0)
  1339. return ret;
  1340. return machine__set_current_tid(pt->machine, cpu, pid, tid);
  1341. }
  1342. static int intel_pt_process_itrace_start(struct intel_pt *pt,
  1343. union perf_event *event,
  1344. struct perf_sample *sample)
  1345. {
  1346. if (!pt->per_cpu_mmaps)
  1347. return 0;
  1348. intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1349. sample->cpu, event->itrace_start.pid,
  1350. event->itrace_start.tid, sample->time,
  1351. perf_time_to_tsc(sample->time, &pt->tc));
  1352. return machine__set_current_tid(pt->machine, sample->cpu,
  1353. event->itrace_start.pid,
  1354. event->itrace_start.tid);
  1355. }
  1356. static int intel_pt_process_event(struct perf_session *session,
  1357. union perf_event *event,
  1358. struct perf_sample *sample,
  1359. struct perf_tool *tool)
  1360. {
  1361. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1362. auxtrace);
  1363. u64 timestamp;
  1364. int err = 0;
  1365. if (dump_trace)
  1366. return 0;
  1367. if (!tool->ordered_events) {
  1368. pr_err("Intel Processor Trace requires ordered events\n");
  1369. return -EINVAL;
  1370. }
  1371. if (sample->time && sample->time != (u64)-1)
  1372. timestamp = perf_time_to_tsc(sample->time, &pt->tc);
  1373. else
  1374. timestamp = 0;
  1375. if (timestamp || pt->timeless_decoding) {
  1376. err = intel_pt_update_queues(pt);
  1377. if (err)
  1378. return err;
  1379. }
  1380. if (pt->timeless_decoding) {
  1381. if (event->header.type == PERF_RECORD_EXIT) {
  1382. err = intel_pt_process_timeless_queues(pt,
  1383. event->fork.tid,
  1384. sample->time);
  1385. }
  1386. } else if (timestamp) {
  1387. err = intel_pt_process_queues(pt, timestamp);
  1388. }
  1389. if (err)
  1390. return err;
  1391. if (event->header.type == PERF_RECORD_AUX &&
  1392. (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) &&
  1393. pt->synth_opts.errors) {
  1394. err = intel_pt_lost(pt, sample);
  1395. if (err)
  1396. return err;
  1397. }
  1398. if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE)
  1399. err = intel_pt_process_switch(pt, sample);
  1400. else if (event->header.type == PERF_RECORD_ITRACE_START)
  1401. err = intel_pt_process_itrace_start(pt, event, sample);
  1402. else if (event->header.type == PERF_RECORD_SWITCH ||
  1403. event->header.type == PERF_RECORD_SWITCH_CPU_WIDE)
  1404. err = intel_pt_context_switch(pt, event, sample);
  1405. intel_pt_log("event %s (%u): cpu %d time %"PRIu64" tsc %#"PRIx64"\n",
  1406. perf_event__name(event->header.type), event->header.type,
  1407. sample->cpu, sample->time, timestamp);
  1408. return err;
  1409. }
  1410. static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool)
  1411. {
  1412. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1413. auxtrace);
  1414. int ret;
  1415. if (dump_trace)
  1416. return 0;
  1417. if (!tool->ordered_events)
  1418. return -EINVAL;
  1419. ret = intel_pt_update_queues(pt);
  1420. if (ret < 0)
  1421. return ret;
  1422. if (pt->timeless_decoding)
  1423. return intel_pt_process_timeless_queues(pt, -1,
  1424. MAX_TIMESTAMP - 1);
  1425. return intel_pt_process_queues(pt, MAX_TIMESTAMP);
  1426. }
  1427. static void intel_pt_free_events(struct perf_session *session)
  1428. {
  1429. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1430. auxtrace);
  1431. struct auxtrace_queues *queues = &pt->queues;
  1432. unsigned int i;
  1433. for (i = 0; i < queues->nr_queues; i++) {
  1434. intel_pt_free_queue(queues->queue_array[i].priv);
  1435. queues->queue_array[i].priv = NULL;
  1436. }
  1437. intel_pt_log_disable();
  1438. auxtrace_queues__free(queues);
  1439. }
  1440. static void intel_pt_free(struct perf_session *session)
  1441. {
  1442. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1443. auxtrace);
  1444. auxtrace_heap__free(&pt->heap);
  1445. intel_pt_free_events(session);
  1446. session->auxtrace = NULL;
  1447. thread__put(pt->unknown_thread);
  1448. free(pt);
  1449. }
  1450. static int intel_pt_process_auxtrace_event(struct perf_session *session,
  1451. union perf_event *event,
  1452. struct perf_tool *tool __maybe_unused)
  1453. {
  1454. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1455. auxtrace);
  1456. if (pt->sampling_mode)
  1457. return 0;
  1458. if (!pt->data_queued) {
  1459. struct auxtrace_buffer *buffer;
  1460. off_t data_offset;
  1461. int fd = perf_data_file__fd(session->file);
  1462. int err;
  1463. if (perf_data_file__is_pipe(session->file)) {
  1464. data_offset = 0;
  1465. } else {
  1466. data_offset = lseek(fd, 0, SEEK_CUR);
  1467. if (data_offset == -1)
  1468. return -errno;
  1469. }
  1470. err = auxtrace_queues__add_event(&pt->queues, session, event,
  1471. data_offset, &buffer);
  1472. if (err)
  1473. return err;
  1474. /* Dump here now we have copied a piped trace out of the pipe */
  1475. if (dump_trace) {
  1476. if (auxtrace_buffer__get_data(buffer, fd)) {
  1477. intel_pt_dump_event(pt, buffer->data,
  1478. buffer->size);
  1479. auxtrace_buffer__put_data(buffer);
  1480. }
  1481. }
  1482. }
  1483. return 0;
  1484. }
  1485. struct intel_pt_synth {
  1486. struct perf_tool dummy_tool;
  1487. struct perf_session *session;
  1488. };
  1489. static int intel_pt_event_synth(struct perf_tool *tool,
  1490. union perf_event *event,
  1491. struct perf_sample *sample __maybe_unused,
  1492. struct machine *machine __maybe_unused)
  1493. {
  1494. struct intel_pt_synth *intel_pt_synth =
  1495. container_of(tool, struct intel_pt_synth, dummy_tool);
  1496. return perf_session__deliver_synth_event(intel_pt_synth->session, event,
  1497. NULL);
  1498. }
  1499. static int intel_pt_synth_event(struct perf_session *session,
  1500. struct perf_event_attr *attr, u64 id)
  1501. {
  1502. struct intel_pt_synth intel_pt_synth;
  1503. memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth));
  1504. intel_pt_synth.session = session;
  1505. return perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1,
  1506. &id, intel_pt_event_synth);
  1507. }
  1508. static int intel_pt_synth_events(struct intel_pt *pt,
  1509. struct perf_session *session)
  1510. {
  1511. struct perf_evlist *evlist = session->evlist;
  1512. struct perf_evsel *evsel;
  1513. struct perf_event_attr attr;
  1514. bool found = false;
  1515. u64 id;
  1516. int err;
  1517. evlist__for_each(evlist, evsel) {
  1518. if (evsel->attr.type == pt->pmu_type && evsel->ids) {
  1519. found = true;
  1520. break;
  1521. }
  1522. }
  1523. if (!found) {
  1524. pr_debug("There are no selected events with Intel Processor Trace data\n");
  1525. return 0;
  1526. }
  1527. memset(&attr, 0, sizeof(struct perf_event_attr));
  1528. attr.size = sizeof(struct perf_event_attr);
  1529. attr.type = PERF_TYPE_HARDWARE;
  1530. attr.sample_type = evsel->attr.sample_type & PERF_SAMPLE_MASK;
  1531. attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
  1532. PERF_SAMPLE_PERIOD;
  1533. if (pt->timeless_decoding)
  1534. attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
  1535. else
  1536. attr.sample_type |= PERF_SAMPLE_TIME;
  1537. if (!pt->per_cpu_mmaps)
  1538. attr.sample_type &= ~(u64)PERF_SAMPLE_CPU;
  1539. attr.exclude_user = evsel->attr.exclude_user;
  1540. attr.exclude_kernel = evsel->attr.exclude_kernel;
  1541. attr.exclude_hv = evsel->attr.exclude_hv;
  1542. attr.exclude_host = evsel->attr.exclude_host;
  1543. attr.exclude_guest = evsel->attr.exclude_guest;
  1544. attr.sample_id_all = evsel->attr.sample_id_all;
  1545. attr.read_format = evsel->attr.read_format;
  1546. id = evsel->id[0] + 1000000000;
  1547. if (!id)
  1548. id = 1;
  1549. if (pt->synth_opts.instructions) {
  1550. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1551. if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS)
  1552. attr.sample_period =
  1553. intel_pt_ns_to_ticks(pt, pt->synth_opts.period);
  1554. else
  1555. attr.sample_period = pt->synth_opts.period;
  1556. pt->instructions_sample_period = attr.sample_period;
  1557. if (pt->synth_opts.callchain)
  1558. attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
  1559. if (pt->synth_opts.last_branch)
  1560. attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
  1561. pr_debug("Synthesizing 'instructions' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  1562. id, (u64)attr.sample_type);
  1563. err = intel_pt_synth_event(session, &attr, id);
  1564. if (err) {
  1565. pr_err("%s: failed to synthesize 'instructions' event type\n",
  1566. __func__);
  1567. return err;
  1568. }
  1569. pt->sample_instructions = true;
  1570. pt->instructions_sample_type = attr.sample_type;
  1571. pt->instructions_id = id;
  1572. id += 1;
  1573. }
  1574. if (pt->synth_opts.transactions) {
  1575. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1576. attr.sample_period = 1;
  1577. if (pt->synth_opts.callchain)
  1578. attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
  1579. if (pt->synth_opts.last_branch)
  1580. attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
  1581. pr_debug("Synthesizing 'transactions' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  1582. id, (u64)attr.sample_type);
  1583. err = intel_pt_synth_event(session, &attr, id);
  1584. if (err) {
  1585. pr_err("%s: failed to synthesize 'transactions' event type\n",
  1586. __func__);
  1587. return err;
  1588. }
  1589. pt->sample_transactions = true;
  1590. pt->transactions_id = id;
  1591. id += 1;
  1592. evlist__for_each(evlist, evsel) {
  1593. if (evsel->id && evsel->id[0] == pt->transactions_id) {
  1594. if (evsel->name)
  1595. zfree(&evsel->name);
  1596. evsel->name = strdup("transactions");
  1597. break;
  1598. }
  1599. }
  1600. }
  1601. if (pt->synth_opts.branches) {
  1602. attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
  1603. attr.sample_period = 1;
  1604. attr.sample_type |= PERF_SAMPLE_ADDR;
  1605. attr.sample_type &= ~(u64)PERF_SAMPLE_CALLCHAIN;
  1606. attr.sample_type &= ~(u64)PERF_SAMPLE_BRANCH_STACK;
  1607. pr_debug("Synthesizing 'branches' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  1608. id, (u64)attr.sample_type);
  1609. err = intel_pt_synth_event(session, &attr, id);
  1610. if (err) {
  1611. pr_err("%s: failed to synthesize 'branches' event type\n",
  1612. __func__);
  1613. return err;
  1614. }
  1615. pt->sample_branches = true;
  1616. pt->branches_sample_type = attr.sample_type;
  1617. pt->branches_id = id;
  1618. }
  1619. pt->synth_needs_swap = evsel->needs_swap;
  1620. return 0;
  1621. }
  1622. static struct perf_evsel *intel_pt_find_sched_switch(struct perf_evlist *evlist)
  1623. {
  1624. struct perf_evsel *evsel;
  1625. evlist__for_each_reverse(evlist, evsel) {
  1626. const char *name = perf_evsel__name(evsel);
  1627. if (!strcmp(name, "sched:sched_switch"))
  1628. return evsel;
  1629. }
  1630. return NULL;
  1631. }
  1632. static bool intel_pt_find_switch(struct perf_evlist *evlist)
  1633. {
  1634. struct perf_evsel *evsel;
  1635. evlist__for_each(evlist, evsel) {
  1636. if (evsel->attr.context_switch)
  1637. return true;
  1638. }
  1639. return false;
  1640. }
  1641. static int intel_pt_perf_config(const char *var, const char *value, void *data)
  1642. {
  1643. struct intel_pt *pt = data;
  1644. if (!strcmp(var, "intel-pt.mispred-all"))
  1645. pt->mispred_all = perf_config_bool(var, value);
  1646. return 0;
  1647. }
  1648. static const char * const intel_pt_info_fmts[] = {
  1649. [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n",
  1650. [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n",
  1651. [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n",
  1652. [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n",
  1653. [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n",
  1654. [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n",
  1655. [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n",
  1656. [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n",
  1657. [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n",
  1658. [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n",
  1659. [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n",
  1660. [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n",
  1661. [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n",
  1662. [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n",
  1663. };
  1664. static void intel_pt_print_info(u64 *arr, int start, int finish)
  1665. {
  1666. int i;
  1667. if (!dump_trace)
  1668. return;
  1669. for (i = start; i <= finish; i++)
  1670. fprintf(stdout, intel_pt_info_fmts[i], arr[i]);
  1671. }
  1672. int intel_pt_process_auxtrace_info(union perf_event *event,
  1673. struct perf_session *session)
  1674. {
  1675. struct auxtrace_info_event *auxtrace_info = &event->auxtrace_info;
  1676. size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS;
  1677. struct intel_pt *pt;
  1678. int err;
  1679. if (auxtrace_info->header.size < sizeof(struct auxtrace_info_event) +
  1680. min_sz)
  1681. return -EINVAL;
  1682. pt = zalloc(sizeof(struct intel_pt));
  1683. if (!pt)
  1684. return -ENOMEM;
  1685. perf_config(intel_pt_perf_config, pt);
  1686. err = auxtrace_queues__init(&pt->queues);
  1687. if (err)
  1688. goto err_free;
  1689. intel_pt_log_set_name(INTEL_PT_PMU_NAME);
  1690. pt->session = session;
  1691. pt->machine = &session->machines.host; /* No kvm support */
  1692. pt->auxtrace_type = auxtrace_info->type;
  1693. pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE];
  1694. pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT];
  1695. pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT];
  1696. pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO];
  1697. pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO];
  1698. pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT];
  1699. pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT];
  1700. pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH];
  1701. pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE];
  1702. pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS];
  1703. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE,
  1704. INTEL_PT_PER_CPU_MMAPS);
  1705. if (auxtrace_info->header.size >= sizeof(struct auxtrace_info_event) +
  1706. (sizeof(u64) * INTEL_PT_CYC_BIT)) {
  1707. pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT];
  1708. pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS];
  1709. pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N];
  1710. pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D];
  1711. pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT];
  1712. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT,
  1713. INTEL_PT_CYC_BIT);
  1714. }
  1715. pt->timeless_decoding = intel_pt_timeless_decoding(pt);
  1716. pt->have_tsc = intel_pt_have_tsc(pt);
  1717. pt->sampling_mode = false;
  1718. pt->est_tsc = !pt->timeless_decoding;
  1719. pt->unknown_thread = thread__new(999999999, 999999999);
  1720. if (!pt->unknown_thread) {
  1721. err = -ENOMEM;
  1722. goto err_free_queues;
  1723. }
  1724. err = thread__set_comm(pt->unknown_thread, "unknown", 0);
  1725. if (err)
  1726. goto err_delete_thread;
  1727. if (thread__init_map_groups(pt->unknown_thread, pt->machine)) {
  1728. err = -ENOMEM;
  1729. goto err_delete_thread;
  1730. }
  1731. pt->auxtrace.process_event = intel_pt_process_event;
  1732. pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event;
  1733. pt->auxtrace.flush_events = intel_pt_flush;
  1734. pt->auxtrace.free_events = intel_pt_free_events;
  1735. pt->auxtrace.free = intel_pt_free;
  1736. session->auxtrace = &pt->auxtrace;
  1737. if (dump_trace)
  1738. return 0;
  1739. if (pt->have_sched_switch == 1) {
  1740. pt->switch_evsel = intel_pt_find_sched_switch(session->evlist);
  1741. if (!pt->switch_evsel) {
  1742. pr_err("%s: missing sched_switch event\n", __func__);
  1743. goto err_delete_thread;
  1744. }
  1745. } else if (pt->have_sched_switch == 2 &&
  1746. !intel_pt_find_switch(session->evlist)) {
  1747. pr_err("%s: missing context_switch attribute flag\n", __func__);
  1748. goto err_delete_thread;
  1749. }
  1750. if (session->itrace_synth_opts && session->itrace_synth_opts->set) {
  1751. pt->synth_opts = *session->itrace_synth_opts;
  1752. } else {
  1753. itrace_synth_opts__set_default(&pt->synth_opts);
  1754. if (use_browser != -1) {
  1755. pt->synth_opts.branches = false;
  1756. pt->synth_opts.callchain = true;
  1757. }
  1758. }
  1759. if (pt->synth_opts.log)
  1760. intel_pt_log_enable();
  1761. /* Maximum non-turbo ratio is TSC freq / 100 MHz */
  1762. if (pt->tc.time_mult) {
  1763. u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000);
  1764. pt->max_non_turbo_ratio = (tsc_freq + 50000000) / 100000000;
  1765. intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq);
  1766. intel_pt_log("Maximum non-turbo ratio %u\n",
  1767. pt->max_non_turbo_ratio);
  1768. }
  1769. if (pt->synth_opts.calls)
  1770. pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC |
  1771. PERF_IP_FLAG_TRACE_END;
  1772. if (pt->synth_opts.returns)
  1773. pt->branches_filter |= PERF_IP_FLAG_RETURN |
  1774. PERF_IP_FLAG_TRACE_BEGIN;
  1775. if (pt->synth_opts.callchain && !symbol_conf.use_callchain) {
  1776. symbol_conf.use_callchain = true;
  1777. if (callchain_register_param(&callchain_param) < 0) {
  1778. symbol_conf.use_callchain = false;
  1779. pt->synth_opts.callchain = false;
  1780. }
  1781. }
  1782. err = intel_pt_synth_events(pt, session);
  1783. if (err)
  1784. goto err_delete_thread;
  1785. err = auxtrace_queues__process_index(&pt->queues, session);
  1786. if (err)
  1787. goto err_delete_thread;
  1788. if (pt->queues.populated)
  1789. pt->data_queued = true;
  1790. if (pt->timeless_decoding)
  1791. pr_debug2("Intel PT decoding without timestamps\n");
  1792. return 0;
  1793. err_delete_thread:
  1794. thread__zput(pt->unknown_thread);
  1795. err_free_queues:
  1796. intel_pt_log_disable();
  1797. auxtrace_queues__free(&pt->queues);
  1798. session->auxtrace = NULL;
  1799. err_free:
  1800. free(pt);
  1801. return err;
  1802. }