hw_irq.h 8.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
  4. */
  5. #ifndef _ASM_POWERPC_HW_IRQ_H
  6. #define _ASM_POWERPC_HW_IRQ_H
  7. #ifdef __KERNEL__
  8. #include <linux/errno.h>
  9. #include <linux/compiler.h>
  10. #include <asm/ptrace.h>
  11. #include <asm/processor.h>
  12. #ifdef CONFIG_PPC64
  13. /*
  14. * PACA flags in paca->irq_happened.
  15. *
  16. * This bits are set when interrupts occur while soft-disabled
  17. * and allow a proper replay. Additionally, PACA_IRQ_HARD_DIS
  18. * is set whenever we manually hard disable.
  19. */
  20. #define PACA_IRQ_HARD_DIS 0x01
  21. #define PACA_IRQ_DBELL 0x02
  22. #define PACA_IRQ_EE 0x04
  23. #define PACA_IRQ_DEC 0x08 /* Or FIT */
  24. #define PACA_IRQ_EE_EDGE 0x10 /* BookE only */
  25. #define PACA_IRQ_HMI 0x20
  26. #define PACA_IRQ_PMI 0x40
  27. /*
  28. * flags for paca->irq_soft_mask
  29. */
  30. #define IRQS_ENABLED 0
  31. #define IRQS_DISABLED 1 /* local_irq_disable() interrupts */
  32. #define IRQS_PMI_DISABLED 2
  33. #define IRQS_ALL_DISABLED (IRQS_DISABLED | IRQS_PMI_DISABLED)
  34. #endif /* CONFIG_PPC64 */
  35. #ifndef __ASSEMBLY__
  36. extern void replay_system_reset(void);
  37. extern void __replay_interrupt(unsigned int vector);
  38. extern void timer_interrupt(struct pt_regs *);
  39. extern void performance_monitor_exception(struct pt_regs *regs);
  40. extern void WatchdogException(struct pt_regs *regs);
  41. extern void unknown_exception(struct pt_regs *regs);
  42. #ifdef CONFIG_PPC64
  43. #include <asm/paca.h>
  44. static inline notrace unsigned long irq_soft_mask_return(void)
  45. {
  46. unsigned long flags;
  47. asm volatile(
  48. "lbz %0,%1(13)"
  49. : "=r" (flags)
  50. : "i" (offsetof(struct paca_struct, irq_soft_mask)));
  51. return flags;
  52. }
  53. /*
  54. * The "memory" clobber acts as both a compiler barrier
  55. * for the critical section and as a clobber because
  56. * we changed paca->irq_soft_mask
  57. */
  58. static inline notrace void irq_soft_mask_set(unsigned long mask)
  59. {
  60. #ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
  61. /*
  62. * The irq mask must always include the STD bit if any are set.
  63. *
  64. * and interrupts don't get replayed until the standard
  65. * interrupt (local_irq_disable()) is unmasked.
  66. *
  67. * Other masks must only provide additional masking beyond
  68. * the standard, and they are also not replayed until the
  69. * standard interrupt becomes unmasked.
  70. *
  71. * This could be changed, but it will require partial
  72. * unmasks to be replayed, among other things. For now, take
  73. * the simple approach.
  74. */
  75. WARN_ON(mask && !(mask & IRQS_DISABLED));
  76. #endif
  77. asm volatile(
  78. "stb %0,%1(13)"
  79. :
  80. : "r" (mask),
  81. "i" (offsetof(struct paca_struct, irq_soft_mask))
  82. : "memory");
  83. }
  84. static inline notrace unsigned long irq_soft_mask_set_return(unsigned long mask)
  85. {
  86. unsigned long flags;
  87. #ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
  88. WARN_ON(mask && !(mask & IRQS_DISABLED));
  89. #endif
  90. asm volatile(
  91. "lbz %0,%1(13); stb %2,%1(13)"
  92. : "=&r" (flags)
  93. : "i" (offsetof(struct paca_struct, irq_soft_mask)),
  94. "r" (mask)
  95. : "memory");
  96. return flags;
  97. }
  98. static inline notrace unsigned long irq_soft_mask_or_return(unsigned long mask)
  99. {
  100. unsigned long flags, tmp;
  101. asm volatile(
  102. "lbz %0,%2(13); or %1,%0,%3; stb %1,%2(13)"
  103. : "=&r" (flags), "=r" (tmp)
  104. : "i" (offsetof(struct paca_struct, irq_soft_mask)),
  105. "r" (mask)
  106. : "memory");
  107. #ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
  108. WARN_ON((mask | flags) && !((mask | flags) & IRQS_DISABLED));
  109. #endif
  110. return flags;
  111. }
  112. static inline unsigned long arch_local_save_flags(void)
  113. {
  114. return irq_soft_mask_return();
  115. }
  116. static inline void arch_local_irq_disable(void)
  117. {
  118. irq_soft_mask_set(IRQS_DISABLED);
  119. }
  120. extern void arch_local_irq_restore(unsigned long);
  121. static inline void arch_local_irq_enable(void)
  122. {
  123. arch_local_irq_restore(IRQS_ENABLED);
  124. }
  125. static inline unsigned long arch_local_irq_save(void)
  126. {
  127. return irq_soft_mask_set_return(IRQS_DISABLED);
  128. }
  129. static inline bool arch_irqs_disabled_flags(unsigned long flags)
  130. {
  131. return flags & IRQS_DISABLED;
  132. }
  133. static inline bool arch_irqs_disabled(void)
  134. {
  135. return arch_irqs_disabled_flags(arch_local_save_flags());
  136. }
  137. #ifdef CONFIG_PPC_BOOK3S
  138. /*
  139. * To support disabling and enabling of irq with PMI, set of
  140. * new powerpc_local_irq_pmu_save() and powerpc_local_irq_restore()
  141. * functions are added. These macros are implemented using generic
  142. * linux local_irq_* code from include/linux/irqflags.h.
  143. */
  144. #define raw_local_irq_pmu_save(flags) \
  145. do { \
  146. typecheck(unsigned long, flags); \
  147. flags = irq_soft_mask_or_return(IRQS_DISABLED | \
  148. IRQS_PMI_DISABLED); \
  149. } while(0)
  150. #define raw_local_irq_pmu_restore(flags) \
  151. do { \
  152. typecheck(unsigned long, flags); \
  153. arch_local_irq_restore(flags); \
  154. } while(0)
  155. #ifdef CONFIG_TRACE_IRQFLAGS
  156. #define powerpc_local_irq_pmu_save(flags) \
  157. do { \
  158. raw_local_irq_pmu_save(flags); \
  159. trace_hardirqs_off(); \
  160. } while(0)
  161. #define powerpc_local_irq_pmu_restore(flags) \
  162. do { \
  163. if (raw_irqs_disabled_flags(flags)) { \
  164. raw_local_irq_pmu_restore(flags); \
  165. trace_hardirqs_off(); \
  166. } else { \
  167. trace_hardirqs_on(); \
  168. raw_local_irq_pmu_restore(flags); \
  169. } \
  170. } while(0)
  171. #else
  172. #define powerpc_local_irq_pmu_save(flags) \
  173. do { \
  174. raw_local_irq_pmu_save(flags); \
  175. } while(0)
  176. #define powerpc_local_irq_pmu_restore(flags) \
  177. do { \
  178. raw_local_irq_pmu_restore(flags); \
  179. } while (0)
  180. #endif /* CONFIG_TRACE_IRQFLAGS */
  181. #endif /* CONFIG_PPC_BOOK3S */
  182. #ifdef CONFIG_PPC_BOOK3E
  183. #define __hard_irq_enable() asm volatile("wrteei 1" : : : "memory")
  184. #define __hard_irq_disable() asm volatile("wrteei 0" : : : "memory")
  185. #else
  186. #define __hard_irq_enable() __mtmsrd(local_paca->kernel_msr | MSR_EE, 1)
  187. #define __hard_irq_disable() __mtmsrd(local_paca->kernel_msr, 1)
  188. #endif
  189. #define hard_irq_disable() do { \
  190. unsigned long flags; \
  191. __hard_irq_disable(); \
  192. flags = irq_soft_mask_set_return(IRQS_ALL_DISABLED); \
  193. local_paca->irq_happened |= PACA_IRQ_HARD_DIS; \
  194. if (!arch_irqs_disabled_flags(flags)) \
  195. trace_hardirqs_off(); \
  196. } while(0)
  197. static inline bool lazy_irq_pending(void)
  198. {
  199. return !!(get_paca()->irq_happened & ~PACA_IRQ_HARD_DIS);
  200. }
  201. /*
  202. * This is called by asynchronous interrupts to conditionally
  203. * re-enable hard interrupts when soft-disabled after having
  204. * cleared the source of the interrupt
  205. */
  206. static inline void may_hard_irq_enable(void)
  207. {
  208. get_paca()->irq_happened &= ~PACA_IRQ_HARD_DIS;
  209. if (!(get_paca()->irq_happened & PACA_IRQ_EE))
  210. __hard_irq_enable();
  211. }
  212. static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
  213. {
  214. return (regs->softe & IRQS_DISABLED);
  215. }
  216. extern bool prep_irq_for_idle(void);
  217. extern bool prep_irq_for_idle_irqsoff(void);
  218. extern void irq_set_pending_from_srr1(unsigned long srr1);
  219. #define fini_irq_for_idle_irqsoff() trace_hardirqs_off();
  220. extern void force_external_irq_replay(void);
  221. #else /* CONFIG_PPC64 */
  222. #define SET_MSR_EE(x) mtmsr(x)
  223. static inline unsigned long arch_local_save_flags(void)
  224. {
  225. return mfmsr();
  226. }
  227. static inline void arch_local_irq_restore(unsigned long flags)
  228. {
  229. #if defined(CONFIG_BOOKE)
  230. asm volatile("wrtee %0" : : "r" (flags) : "memory");
  231. #else
  232. mtmsr(flags);
  233. #endif
  234. }
  235. static inline unsigned long arch_local_irq_save(void)
  236. {
  237. unsigned long flags = arch_local_save_flags();
  238. #ifdef CONFIG_BOOKE
  239. asm volatile("wrteei 0" : : : "memory");
  240. #elif defined(CONFIG_PPC_8xx)
  241. wrtspr(SPRN_EID);
  242. #else
  243. SET_MSR_EE(flags & ~MSR_EE);
  244. #endif
  245. return flags;
  246. }
  247. static inline void arch_local_irq_disable(void)
  248. {
  249. #ifdef CONFIG_BOOKE
  250. asm volatile("wrteei 0" : : : "memory");
  251. #elif defined(CONFIG_PPC_8xx)
  252. wrtspr(SPRN_EID);
  253. #else
  254. arch_local_irq_save();
  255. #endif
  256. }
  257. static inline void arch_local_irq_enable(void)
  258. {
  259. #ifdef CONFIG_BOOKE
  260. asm volatile("wrteei 1" : : : "memory");
  261. #elif defined(CONFIG_PPC_8xx)
  262. wrtspr(SPRN_EIE);
  263. #else
  264. unsigned long msr = mfmsr();
  265. SET_MSR_EE(msr | MSR_EE);
  266. #endif
  267. }
  268. static inline bool arch_irqs_disabled_flags(unsigned long flags)
  269. {
  270. return (flags & MSR_EE) == 0;
  271. }
  272. static inline bool arch_irqs_disabled(void)
  273. {
  274. return arch_irqs_disabled_flags(arch_local_save_flags());
  275. }
  276. #define hard_irq_disable() arch_local_irq_disable()
  277. static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
  278. {
  279. return !(regs->msr & MSR_EE);
  280. }
  281. static inline void may_hard_irq_enable(void) { }
  282. #endif /* CONFIG_PPC64 */
  283. #define ARCH_IRQ_INIT_FLAGS IRQ_NOREQUEST
  284. /*
  285. * interrupt-retrigger: should we handle this via lost interrupts and IPIs
  286. * or should we not care like we do now ? --BenH.
  287. */
  288. struct irq_chip;
  289. #endif /* __ASSEMBLY__ */
  290. #endif /* __KERNEL__ */
  291. #endif /* _ASM_POWERPC_HW_IRQ_H */