tpm_tis_core.c 21 KB

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  1. /*
  2. * Copyright (C) 2005, 2006 IBM Corporation
  3. * Copyright (C) 2014, 2015 Intel Corporation
  4. *
  5. * Authors:
  6. * Leendert van Doorn <leendert@watson.ibm.com>
  7. * Kylene Hall <kjhall@us.ibm.com>
  8. *
  9. * Maintained by: <tpmdd-devel@lists.sourceforge.net>
  10. *
  11. * Device driver for TCG/TCPA TPM (trusted platform module).
  12. * Specifications at www.trustedcomputinggroup.org
  13. *
  14. * This device driver implements the TPM interface as defined in
  15. * the TCG TPM Interface Spec version 1.2, revision 1.0.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation, version 2 of the
  20. * License.
  21. */
  22. #include <linux/init.h>
  23. #include <linux/module.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/pnp.h>
  26. #include <linux/slab.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/wait.h>
  29. #include <linux/acpi.h>
  30. #include <linux/freezer.h>
  31. #include "tpm.h"
  32. #include "tpm_tis_core.h"
  33. /* Before we attempt to access the TPM we must see that the valid bit is set.
  34. * The specification says that this bit is 0 at reset and remains 0 until the
  35. * 'TPM has gone through its self test and initialization and has established
  36. * correct values in the other bits.'
  37. */
  38. static int wait_startup(struct tpm_chip *chip, int l)
  39. {
  40. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  41. unsigned long stop = jiffies + chip->timeout_a;
  42. do {
  43. int rc;
  44. u8 access;
  45. rc = tpm_tis_read8(priv, TPM_ACCESS(l), &access);
  46. if (rc < 0)
  47. return rc;
  48. if (access & TPM_ACCESS_VALID)
  49. return 0;
  50. msleep(TPM_TIMEOUT);
  51. } while (time_before(jiffies, stop));
  52. return -1;
  53. }
  54. static bool check_locality(struct tpm_chip *chip, int l)
  55. {
  56. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  57. int rc;
  58. u8 access;
  59. rc = tpm_tis_read8(priv, TPM_ACCESS(l), &access);
  60. if (rc < 0)
  61. return false;
  62. if ((access & (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
  63. (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) {
  64. priv->locality = l;
  65. return true;
  66. }
  67. return false;
  68. }
  69. static void release_locality(struct tpm_chip *chip, int l)
  70. {
  71. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  72. tpm_tis_write8(priv, TPM_ACCESS(l), TPM_ACCESS_ACTIVE_LOCALITY);
  73. }
  74. static int request_locality(struct tpm_chip *chip, int l)
  75. {
  76. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  77. unsigned long stop, timeout;
  78. long rc;
  79. if (check_locality(chip, l))
  80. return l;
  81. rc = tpm_tis_write8(priv, TPM_ACCESS(l), TPM_ACCESS_REQUEST_USE);
  82. if (rc < 0)
  83. return rc;
  84. stop = jiffies + chip->timeout_a;
  85. if (chip->flags & TPM_CHIP_FLAG_IRQ) {
  86. again:
  87. timeout = stop - jiffies;
  88. if ((long)timeout <= 0)
  89. return -1;
  90. rc = wait_event_interruptible_timeout(priv->int_queue,
  91. (check_locality
  92. (chip, l)),
  93. timeout);
  94. if (rc > 0)
  95. return l;
  96. if (rc == -ERESTARTSYS && freezing(current)) {
  97. clear_thread_flag(TIF_SIGPENDING);
  98. goto again;
  99. }
  100. } else {
  101. /* wait for burstcount */
  102. do {
  103. if (check_locality(chip, l))
  104. return l;
  105. msleep(TPM_TIMEOUT);
  106. } while (time_before(jiffies, stop));
  107. }
  108. return -1;
  109. }
  110. static u8 tpm_tis_status(struct tpm_chip *chip)
  111. {
  112. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  113. int rc;
  114. u8 status;
  115. rc = tpm_tis_read8(priv, TPM_STS(priv->locality), &status);
  116. if (rc < 0)
  117. return 0;
  118. return status;
  119. }
  120. static void tpm_tis_ready(struct tpm_chip *chip)
  121. {
  122. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  123. /* this causes the current command to be aborted */
  124. tpm_tis_write8(priv, TPM_STS(priv->locality), TPM_STS_COMMAND_READY);
  125. }
  126. static int get_burstcount(struct tpm_chip *chip)
  127. {
  128. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  129. unsigned long stop;
  130. int burstcnt, rc;
  131. u32 value;
  132. /* wait for burstcount */
  133. if (chip->flags & TPM_CHIP_FLAG_TPM2)
  134. stop = jiffies + chip->timeout_a;
  135. else
  136. stop = jiffies + chip->timeout_d;
  137. do {
  138. rc = tpm_tis_read32(priv, TPM_STS(priv->locality), &value);
  139. if (rc < 0)
  140. return rc;
  141. burstcnt = (value >> 8) & 0xFFFF;
  142. if (burstcnt)
  143. return burstcnt;
  144. msleep(TPM_TIMEOUT);
  145. } while (time_before(jiffies, stop));
  146. return -EBUSY;
  147. }
  148. static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
  149. {
  150. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  151. int size = 0, burstcnt, rc;
  152. while (size < count) {
  153. rc = wait_for_tpm_stat(chip,
  154. TPM_STS_DATA_AVAIL | TPM_STS_VALID,
  155. chip->timeout_c,
  156. &priv->read_queue, true);
  157. if (rc < 0)
  158. return rc;
  159. burstcnt = get_burstcount(chip);
  160. if (burstcnt < 0) {
  161. dev_err(&chip->dev, "Unable to read burstcount\n");
  162. return burstcnt;
  163. }
  164. burstcnt = min_t(int, burstcnt, count - size);
  165. rc = tpm_tis_read_bytes(priv, TPM_DATA_FIFO(priv->locality),
  166. burstcnt, buf + size);
  167. if (rc < 0)
  168. return rc;
  169. size += burstcnt;
  170. }
  171. return size;
  172. }
  173. static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
  174. {
  175. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  176. int size = 0;
  177. int expected, status;
  178. if (count < TPM_HEADER_SIZE) {
  179. size = -EIO;
  180. goto out;
  181. }
  182. size = recv_data(chip, buf, TPM_HEADER_SIZE);
  183. /* read first 10 bytes, including tag, paramsize, and result */
  184. if (size < TPM_HEADER_SIZE) {
  185. dev_err(&chip->dev, "Unable to read header\n");
  186. goto out;
  187. }
  188. expected = be32_to_cpu(*(__be32 *) (buf + 2));
  189. if (expected > count) {
  190. size = -EIO;
  191. goto out;
  192. }
  193. size += recv_data(chip, &buf[TPM_HEADER_SIZE],
  194. expected - TPM_HEADER_SIZE);
  195. if (size < expected) {
  196. dev_err(&chip->dev, "Unable to read remainder of result\n");
  197. size = -ETIME;
  198. goto out;
  199. }
  200. if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
  201. &priv->int_queue, false) < 0) {
  202. size = -ETIME;
  203. goto out;
  204. }
  205. status = tpm_tis_status(chip);
  206. if (status & TPM_STS_DATA_AVAIL) { /* retry? */
  207. dev_err(&chip->dev, "Error left over data\n");
  208. size = -EIO;
  209. goto out;
  210. }
  211. out:
  212. tpm_tis_ready(chip);
  213. return size;
  214. }
  215. /*
  216. * If interrupts are used (signaled by an irq set in the vendor structure)
  217. * tpm.c can skip polling for the data to be available as the interrupt is
  218. * waited for here
  219. */
  220. static int tpm_tis_send_data(struct tpm_chip *chip, u8 *buf, size_t len)
  221. {
  222. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  223. int rc, status, burstcnt;
  224. size_t count = 0;
  225. bool itpm = priv->flags & TPM_TIS_ITPM_WORKAROUND;
  226. status = tpm_tis_status(chip);
  227. if ((status & TPM_STS_COMMAND_READY) == 0) {
  228. tpm_tis_ready(chip);
  229. if (wait_for_tpm_stat
  230. (chip, TPM_STS_COMMAND_READY, chip->timeout_b,
  231. &priv->int_queue, false) < 0) {
  232. rc = -ETIME;
  233. goto out_err;
  234. }
  235. }
  236. while (count < len - 1) {
  237. burstcnt = get_burstcount(chip);
  238. if (burstcnt < 0) {
  239. dev_err(&chip->dev, "Unable to read burstcount\n");
  240. rc = burstcnt;
  241. goto out_err;
  242. }
  243. burstcnt = min_t(int, burstcnt, len - count - 1);
  244. rc = tpm_tis_write_bytes(priv, TPM_DATA_FIFO(priv->locality),
  245. burstcnt, buf + count);
  246. if (rc < 0)
  247. goto out_err;
  248. count += burstcnt;
  249. if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
  250. &priv->int_queue, false) < 0) {
  251. rc = -ETIME;
  252. goto out_err;
  253. }
  254. status = tpm_tis_status(chip);
  255. if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) {
  256. rc = -EIO;
  257. goto out_err;
  258. }
  259. }
  260. /* write last byte */
  261. rc = tpm_tis_write8(priv, TPM_DATA_FIFO(priv->locality), buf[count]);
  262. if (rc < 0)
  263. goto out_err;
  264. if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
  265. &priv->int_queue, false) < 0) {
  266. rc = -ETIME;
  267. goto out_err;
  268. }
  269. status = tpm_tis_status(chip);
  270. if (!itpm && (status & TPM_STS_DATA_EXPECT) != 0) {
  271. rc = -EIO;
  272. goto out_err;
  273. }
  274. return 0;
  275. out_err:
  276. tpm_tis_ready(chip);
  277. return rc;
  278. }
  279. static void disable_interrupts(struct tpm_chip *chip)
  280. {
  281. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  282. u32 intmask;
  283. int rc;
  284. rc = tpm_tis_read32(priv, TPM_INT_ENABLE(priv->locality), &intmask);
  285. if (rc < 0)
  286. intmask = 0;
  287. intmask &= ~TPM_GLOBAL_INT_ENABLE;
  288. rc = tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality), intmask);
  289. devm_free_irq(chip->dev.parent, priv->irq, chip);
  290. priv->irq = 0;
  291. chip->flags &= ~TPM_CHIP_FLAG_IRQ;
  292. }
  293. /*
  294. * If interrupts are used (signaled by an irq set in the vendor structure)
  295. * tpm.c can skip polling for the data to be available as the interrupt is
  296. * waited for here
  297. */
  298. static int tpm_tis_send_main(struct tpm_chip *chip, u8 *buf, size_t len)
  299. {
  300. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  301. int rc;
  302. u32 ordinal;
  303. unsigned long dur;
  304. rc = tpm_tis_send_data(chip, buf, len);
  305. if (rc < 0)
  306. return rc;
  307. /* go and do it */
  308. rc = tpm_tis_write8(priv, TPM_STS(priv->locality), TPM_STS_GO);
  309. if (rc < 0)
  310. goto out_err;
  311. if (chip->flags & TPM_CHIP_FLAG_IRQ) {
  312. ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
  313. if (chip->flags & TPM_CHIP_FLAG_TPM2)
  314. dur = tpm2_calc_ordinal_duration(chip, ordinal);
  315. else
  316. dur = tpm_calc_ordinal_duration(chip, ordinal);
  317. if (wait_for_tpm_stat
  318. (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID, dur,
  319. &priv->read_queue, false) < 0) {
  320. rc = -ETIME;
  321. goto out_err;
  322. }
  323. }
  324. return len;
  325. out_err:
  326. tpm_tis_ready(chip);
  327. return rc;
  328. }
  329. static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len)
  330. {
  331. int rc, irq;
  332. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  333. if (!(chip->flags & TPM_CHIP_FLAG_IRQ) || priv->irq_tested)
  334. return tpm_tis_send_main(chip, buf, len);
  335. /* Verify receipt of the expected IRQ */
  336. irq = priv->irq;
  337. priv->irq = 0;
  338. chip->flags &= ~TPM_CHIP_FLAG_IRQ;
  339. rc = tpm_tis_send_main(chip, buf, len);
  340. priv->irq = irq;
  341. chip->flags |= TPM_CHIP_FLAG_IRQ;
  342. if (!priv->irq_tested)
  343. msleep(1);
  344. if (!priv->irq_tested)
  345. disable_interrupts(chip);
  346. priv->irq_tested = true;
  347. return rc;
  348. }
  349. struct tis_vendor_timeout_override {
  350. u32 did_vid;
  351. unsigned long timeout_us[4];
  352. };
  353. static const struct tis_vendor_timeout_override vendor_timeout_overrides[] = {
  354. /* Atmel 3204 */
  355. { 0x32041114, { (TIS_SHORT_TIMEOUT*1000), (TIS_LONG_TIMEOUT*1000),
  356. (TIS_SHORT_TIMEOUT*1000), (TIS_SHORT_TIMEOUT*1000) } },
  357. };
  358. static bool tpm_tis_update_timeouts(struct tpm_chip *chip,
  359. unsigned long *timeout_cap)
  360. {
  361. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  362. int i, rc;
  363. u32 did_vid;
  364. rc = tpm_tis_read32(priv, TPM_DID_VID(0), &did_vid);
  365. if (rc < 0)
  366. return rc;
  367. for (i = 0; i != ARRAY_SIZE(vendor_timeout_overrides); i++) {
  368. if (vendor_timeout_overrides[i].did_vid != did_vid)
  369. continue;
  370. memcpy(timeout_cap, vendor_timeout_overrides[i].timeout_us,
  371. sizeof(vendor_timeout_overrides[i].timeout_us));
  372. return true;
  373. }
  374. return false;
  375. }
  376. /*
  377. * Early probing for iTPM with STS_DATA_EXPECT flaw.
  378. * Try sending command without itpm flag set and if that
  379. * fails, repeat with itpm flag set.
  380. */
  381. static int probe_itpm(struct tpm_chip *chip)
  382. {
  383. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  384. int rc = 0;
  385. u8 cmd_getticks[] = {
  386. 0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a,
  387. 0x00, 0x00, 0x00, 0xf1
  388. };
  389. size_t len = sizeof(cmd_getticks);
  390. u16 vendor;
  391. if (priv->flags & TPM_TIS_ITPM_WORKAROUND)
  392. return 0;
  393. rc = tpm_tis_read16(priv, TPM_DID_VID(0), &vendor);
  394. if (rc < 0)
  395. return rc;
  396. /* probe only iTPMS */
  397. if (vendor != TPM_VID_INTEL)
  398. return 0;
  399. if (request_locality(chip, 0) != 0)
  400. return -EBUSY;
  401. rc = tpm_tis_send_data(chip, cmd_getticks, len);
  402. if (rc == 0)
  403. goto out;
  404. tpm_tis_ready(chip);
  405. priv->flags |= TPM_TIS_ITPM_WORKAROUND;
  406. rc = tpm_tis_send_data(chip, cmd_getticks, len);
  407. if (rc == 0)
  408. dev_info(&chip->dev, "Detected an iTPM.\n");
  409. else {
  410. priv->flags &= ~TPM_TIS_ITPM_WORKAROUND;
  411. rc = -EFAULT;
  412. }
  413. out:
  414. tpm_tis_ready(chip);
  415. release_locality(chip, priv->locality);
  416. return rc;
  417. }
  418. static bool tpm_tis_req_canceled(struct tpm_chip *chip, u8 status)
  419. {
  420. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  421. switch (priv->manufacturer_id) {
  422. case TPM_VID_WINBOND:
  423. return ((status == TPM_STS_VALID) ||
  424. (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY)));
  425. case TPM_VID_STM:
  426. return (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY));
  427. default:
  428. return (status == TPM_STS_COMMAND_READY);
  429. }
  430. }
  431. static irqreturn_t tis_int_handler(int dummy, void *dev_id)
  432. {
  433. struct tpm_chip *chip = dev_id;
  434. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  435. u32 interrupt;
  436. int i, rc;
  437. rc = tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), &interrupt);
  438. if (rc < 0)
  439. return IRQ_NONE;
  440. if (interrupt == 0)
  441. return IRQ_NONE;
  442. priv->irq_tested = true;
  443. if (interrupt & TPM_INTF_DATA_AVAIL_INT)
  444. wake_up_interruptible(&priv->read_queue);
  445. if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
  446. for (i = 0; i < 5; i++)
  447. if (check_locality(chip, i))
  448. break;
  449. if (interrupt &
  450. (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT |
  451. TPM_INTF_CMD_READY_INT))
  452. wake_up_interruptible(&priv->int_queue);
  453. /* Clear interrupts handled with TPM_EOI */
  454. rc = tpm_tis_write32(priv, TPM_INT_STATUS(priv->locality), interrupt);
  455. if (rc < 0)
  456. return IRQ_NONE;
  457. tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), &interrupt);
  458. return IRQ_HANDLED;
  459. }
  460. static int tpm_tis_gen_interrupt(struct tpm_chip *chip)
  461. {
  462. const char *desc = "attempting to generate an interrupt";
  463. u32 cap2;
  464. cap_t cap;
  465. if (chip->flags & TPM_CHIP_FLAG_TPM2)
  466. return tpm2_get_tpm_pt(chip, 0x100, &cap2, desc);
  467. else
  468. return tpm_getcap(chip, TPM_CAP_PROP_TIS_TIMEOUT, &cap, desc,
  469. 0);
  470. }
  471. /* Register the IRQ and issue a command that will cause an interrupt. If an
  472. * irq is seen then leave the chip setup for IRQ operation, otherwise reverse
  473. * everything and leave in polling mode. Returns 0 on success.
  474. */
  475. static int tpm_tis_probe_irq_single(struct tpm_chip *chip, u32 intmask,
  476. int flags, int irq)
  477. {
  478. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  479. u8 original_int_vec;
  480. int rc;
  481. u32 int_status;
  482. if (devm_request_irq(chip->dev.parent, irq, tis_int_handler, flags,
  483. dev_name(&chip->dev), chip) != 0) {
  484. dev_info(&chip->dev, "Unable to request irq: %d for probe\n",
  485. irq);
  486. return -1;
  487. }
  488. priv->irq = irq;
  489. rc = tpm_tis_read8(priv, TPM_INT_VECTOR(priv->locality),
  490. &original_int_vec);
  491. if (rc < 0)
  492. return rc;
  493. rc = tpm_tis_write8(priv, TPM_INT_VECTOR(priv->locality), irq);
  494. if (rc < 0)
  495. return rc;
  496. rc = tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), &int_status);
  497. if (rc < 0)
  498. return rc;
  499. /* Clear all existing */
  500. rc = tpm_tis_write32(priv, TPM_INT_STATUS(priv->locality), int_status);
  501. if (rc < 0)
  502. return rc;
  503. /* Turn on */
  504. rc = tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality),
  505. intmask | TPM_GLOBAL_INT_ENABLE);
  506. if (rc < 0)
  507. return rc;
  508. priv->irq_tested = false;
  509. /* Generate an interrupt by having the core call through to
  510. * tpm_tis_send
  511. */
  512. rc = tpm_tis_gen_interrupt(chip);
  513. if (rc < 0)
  514. return rc;
  515. /* tpm_tis_send will either confirm the interrupt is working or it
  516. * will call disable_irq which undoes all of the above.
  517. */
  518. if (!(chip->flags & TPM_CHIP_FLAG_IRQ)) {
  519. rc = tpm_tis_write8(priv, original_int_vec,
  520. TPM_INT_VECTOR(priv->locality));
  521. if (rc < 0)
  522. return rc;
  523. return 1;
  524. }
  525. return 0;
  526. }
  527. /* Try to find the IRQ the TPM is using. This is for legacy x86 systems that
  528. * do not have ACPI/etc. We typically expect the interrupt to be declared if
  529. * present.
  530. */
  531. static void tpm_tis_probe_irq(struct tpm_chip *chip, u32 intmask)
  532. {
  533. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  534. u8 original_int_vec;
  535. int i, rc;
  536. rc = tpm_tis_read8(priv, TPM_INT_VECTOR(priv->locality),
  537. &original_int_vec);
  538. if (rc < 0)
  539. return;
  540. if (!original_int_vec) {
  541. if (IS_ENABLED(CONFIG_X86))
  542. for (i = 3; i <= 15; i++)
  543. if (!tpm_tis_probe_irq_single(chip, intmask, 0,
  544. i))
  545. return;
  546. } else if (!tpm_tis_probe_irq_single(chip, intmask, 0,
  547. original_int_vec))
  548. return;
  549. }
  550. void tpm_tis_remove(struct tpm_chip *chip)
  551. {
  552. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  553. u32 reg = TPM_INT_ENABLE(priv->locality);
  554. u32 interrupt;
  555. int rc;
  556. rc = tpm_tis_read32(priv, reg, &interrupt);
  557. if (rc < 0)
  558. interrupt = 0;
  559. tpm_tis_write32(priv, reg, ~TPM_GLOBAL_INT_ENABLE & interrupt);
  560. }
  561. EXPORT_SYMBOL_GPL(tpm_tis_remove);
  562. static const struct tpm_class_ops tpm_tis = {
  563. .flags = TPM_OPS_AUTO_STARTUP,
  564. .status = tpm_tis_status,
  565. .recv = tpm_tis_recv,
  566. .send = tpm_tis_send,
  567. .cancel = tpm_tis_ready,
  568. .update_timeouts = tpm_tis_update_timeouts,
  569. .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
  570. .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
  571. .req_canceled = tpm_tis_req_canceled,
  572. .request_locality = request_locality,
  573. .relinquish_locality = release_locality,
  574. };
  575. int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
  576. const struct tpm_tis_phy_ops *phy_ops,
  577. acpi_handle acpi_dev_handle)
  578. {
  579. u32 vendor, intfcaps, intmask;
  580. u8 rid;
  581. int rc, probe;
  582. struct tpm_chip *chip;
  583. chip = tpmm_chip_alloc(dev, &tpm_tis);
  584. if (IS_ERR(chip))
  585. return PTR_ERR(chip);
  586. #ifdef CONFIG_ACPI
  587. chip->acpi_dev_handle = acpi_dev_handle;
  588. #endif
  589. /* Maximum timeouts */
  590. chip->timeout_a = msecs_to_jiffies(TIS_TIMEOUT_A_MAX);
  591. chip->timeout_b = msecs_to_jiffies(TIS_TIMEOUT_B_MAX);
  592. chip->timeout_c = msecs_to_jiffies(TIS_TIMEOUT_C_MAX);
  593. chip->timeout_d = msecs_to_jiffies(TIS_TIMEOUT_D_MAX);
  594. priv->phy_ops = phy_ops;
  595. dev_set_drvdata(&chip->dev, priv);
  596. if (wait_startup(chip, 0) != 0) {
  597. rc = -ENODEV;
  598. goto out_err;
  599. }
  600. /* Take control of the TPM's interrupt hardware and shut it off */
  601. rc = tpm_tis_read32(priv, TPM_INT_ENABLE(priv->locality), &intmask);
  602. if (rc < 0)
  603. goto out_err;
  604. intmask |= TPM_INTF_CMD_READY_INT | TPM_INTF_LOCALITY_CHANGE_INT |
  605. TPM_INTF_DATA_AVAIL_INT | TPM_INTF_STS_VALID_INT;
  606. intmask &= ~TPM_GLOBAL_INT_ENABLE;
  607. tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality), intmask);
  608. rc = tpm2_probe(chip);
  609. if (rc)
  610. goto out_err;
  611. rc = tpm_tis_read32(priv, TPM_DID_VID(0), &vendor);
  612. if (rc < 0)
  613. goto out_err;
  614. priv->manufacturer_id = vendor;
  615. rc = tpm_tis_read8(priv, TPM_RID(0), &rid);
  616. if (rc < 0)
  617. goto out_err;
  618. dev_info(dev, "%s TPM (device-id 0x%X, rev-id %d)\n",
  619. (chip->flags & TPM_CHIP_FLAG_TPM2) ? "2.0" : "1.2",
  620. vendor >> 16, rid);
  621. probe = probe_itpm(chip);
  622. if (probe < 0) {
  623. rc = -ENODEV;
  624. goto out_err;
  625. }
  626. /* Figure out the capabilities */
  627. rc = tpm_tis_read32(priv, TPM_INTF_CAPS(priv->locality), &intfcaps);
  628. if (rc < 0)
  629. goto out_err;
  630. dev_dbg(dev, "TPM interface capabilities (0x%x):\n",
  631. intfcaps);
  632. if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
  633. dev_dbg(dev, "\tBurst Count Static\n");
  634. if (intfcaps & TPM_INTF_CMD_READY_INT)
  635. dev_dbg(dev, "\tCommand Ready Int Support\n");
  636. if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
  637. dev_dbg(dev, "\tInterrupt Edge Falling\n");
  638. if (intfcaps & TPM_INTF_INT_EDGE_RISING)
  639. dev_dbg(dev, "\tInterrupt Edge Rising\n");
  640. if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
  641. dev_dbg(dev, "\tInterrupt Level Low\n");
  642. if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
  643. dev_dbg(dev, "\tInterrupt Level High\n");
  644. if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
  645. dev_dbg(dev, "\tLocality Change Int Support\n");
  646. if (intfcaps & TPM_INTF_STS_VALID_INT)
  647. dev_dbg(dev, "\tSts Valid Int Support\n");
  648. if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
  649. dev_dbg(dev, "\tData Avail Int Support\n");
  650. /* INTERRUPT Setup */
  651. init_waitqueue_head(&priv->read_queue);
  652. init_waitqueue_head(&priv->int_queue);
  653. if (irq != -1) {
  654. /* Before doing irq testing issue a command to the TPM in polling mode
  655. * to make sure it works. May as well use that command to set the
  656. * proper timeouts for the driver.
  657. */
  658. if (tpm_get_timeouts(chip)) {
  659. dev_err(dev, "Could not get TPM timeouts and durations\n");
  660. rc = -ENODEV;
  661. goto out_err;
  662. }
  663. if (irq) {
  664. tpm_tis_probe_irq_single(chip, intmask, IRQF_SHARED,
  665. irq);
  666. if (!(chip->flags & TPM_CHIP_FLAG_IRQ))
  667. dev_err(&chip->dev, FW_BUG
  668. "TPM interrupt not working, polling instead\n");
  669. } else {
  670. tpm_tis_probe_irq(chip, intmask);
  671. }
  672. }
  673. return tpm_chip_register(chip);
  674. out_err:
  675. tpm_tis_remove(chip);
  676. return rc;
  677. }
  678. EXPORT_SYMBOL_GPL(tpm_tis_core_init);
  679. #ifdef CONFIG_PM_SLEEP
  680. static void tpm_tis_reenable_interrupts(struct tpm_chip *chip)
  681. {
  682. struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
  683. u32 intmask;
  684. int rc;
  685. /* reenable interrupts that device may have lost or
  686. * BIOS/firmware may have disabled
  687. */
  688. rc = tpm_tis_write8(priv, TPM_INT_VECTOR(priv->locality), priv->irq);
  689. if (rc < 0)
  690. return;
  691. rc = tpm_tis_read32(priv, TPM_INT_ENABLE(priv->locality), &intmask);
  692. if (rc < 0)
  693. return;
  694. intmask |= TPM_INTF_CMD_READY_INT
  695. | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
  696. | TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE;
  697. tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality), intmask);
  698. }
  699. int tpm_tis_resume(struct device *dev)
  700. {
  701. struct tpm_chip *chip = dev_get_drvdata(dev);
  702. int ret;
  703. if (chip->flags & TPM_CHIP_FLAG_IRQ)
  704. tpm_tis_reenable_interrupts(chip);
  705. ret = tpm_pm_resume(dev);
  706. if (ret)
  707. return ret;
  708. /* TPM 1.2 requires self-test on resume. This function actually returns
  709. * an error code but for unknown reason it isn't handled.
  710. */
  711. if (!(chip->flags & TPM_CHIP_FLAG_TPM2))
  712. tpm_do_selftest(chip);
  713. return 0;
  714. }
  715. EXPORT_SYMBOL_GPL(tpm_tis_resume);
  716. #endif
  717. MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
  718. MODULE_DESCRIPTION("TPM Driver");
  719. MODULE_VERSION("2.0");
  720. MODULE_LICENSE("GPL");