irq.c 10 KB

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  1. /*
  2. * Common interrupt code for 32 and 64 bit
  3. */
  4. #include <linux/cpu.h>
  5. #include <linux/interrupt.h>
  6. #include <linux/kernel_stat.h>
  7. #include <linux/of.h>
  8. #include <linux/seq_file.h>
  9. #include <linux/smp.h>
  10. #include <linux/ftrace.h>
  11. #include <linux/delay.h>
  12. #include <linux/export.h>
  13. #include <asm/apic.h>
  14. #include <asm/io_apic.h>
  15. #include <asm/irq.h>
  16. #include <asm/mce.h>
  17. #include <asm/hw_irq.h>
  18. #include <asm/desc.h>
  19. #define CREATE_TRACE_POINTS
  20. #include <asm/trace/irq_vectors.h>
  21. DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
  22. EXPORT_PER_CPU_SYMBOL(irq_stat);
  23. DEFINE_PER_CPU(struct pt_regs *, irq_regs);
  24. EXPORT_PER_CPU_SYMBOL(irq_regs);
  25. atomic_t irq_err_count;
  26. /*
  27. * 'what should we do if we get a hw irq event on an illegal vector'.
  28. * each architecture has to answer this themselves.
  29. */
  30. void ack_bad_irq(unsigned int irq)
  31. {
  32. if (printk_ratelimit())
  33. pr_err("unexpected IRQ trap at vector %02x\n", irq);
  34. /*
  35. * Currently unexpected vectors happen only on SMP and APIC.
  36. * We _must_ ack these because every local APIC has only N
  37. * irq slots per priority level, and a 'hanging, unacked' IRQ
  38. * holds up an irq slot - in excessive cases (when multiple
  39. * unexpected vectors occur) that might lock up the APIC
  40. * completely.
  41. * But only ack when the APIC is enabled -AK
  42. */
  43. ack_APIC_irq();
  44. }
  45. #define irq_stats(x) (&per_cpu(irq_stat, x))
  46. /*
  47. * /proc/interrupts printing for arch specific interrupts
  48. */
  49. int arch_show_interrupts(struct seq_file *p, int prec)
  50. {
  51. int j;
  52. seq_printf(p, "%*s: ", prec, "NMI");
  53. for_each_online_cpu(j)
  54. seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
  55. seq_puts(p, " Non-maskable interrupts\n");
  56. #ifdef CONFIG_X86_LOCAL_APIC
  57. seq_printf(p, "%*s: ", prec, "LOC");
  58. for_each_online_cpu(j)
  59. seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
  60. seq_puts(p, " Local timer interrupts\n");
  61. seq_printf(p, "%*s: ", prec, "SPU");
  62. for_each_online_cpu(j)
  63. seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
  64. seq_puts(p, " Spurious interrupts\n");
  65. seq_printf(p, "%*s: ", prec, "PMI");
  66. for_each_online_cpu(j)
  67. seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
  68. seq_puts(p, " Performance monitoring interrupts\n");
  69. seq_printf(p, "%*s: ", prec, "IWI");
  70. for_each_online_cpu(j)
  71. seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
  72. seq_puts(p, " IRQ work interrupts\n");
  73. seq_printf(p, "%*s: ", prec, "RTR");
  74. for_each_online_cpu(j)
  75. seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
  76. seq_puts(p, " APIC ICR read retries\n");
  77. if (x86_platform_ipi_callback) {
  78. seq_printf(p, "%*s: ", prec, "PLT");
  79. for_each_online_cpu(j)
  80. seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
  81. seq_puts(p, " Platform interrupts\n");
  82. }
  83. #endif
  84. #ifdef CONFIG_SMP
  85. seq_printf(p, "%*s: ", prec, "RES");
  86. for_each_online_cpu(j)
  87. seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
  88. seq_puts(p, " Rescheduling interrupts\n");
  89. seq_printf(p, "%*s: ", prec, "CAL");
  90. for_each_online_cpu(j)
  91. seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
  92. seq_puts(p, " Function call interrupts\n");
  93. seq_printf(p, "%*s: ", prec, "TLB");
  94. for_each_online_cpu(j)
  95. seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
  96. seq_puts(p, " TLB shootdowns\n");
  97. #endif
  98. #ifdef CONFIG_X86_THERMAL_VECTOR
  99. seq_printf(p, "%*s: ", prec, "TRM");
  100. for_each_online_cpu(j)
  101. seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
  102. seq_puts(p, " Thermal event interrupts\n");
  103. #endif
  104. #ifdef CONFIG_X86_MCE_THRESHOLD
  105. seq_printf(p, "%*s: ", prec, "THR");
  106. for_each_online_cpu(j)
  107. seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
  108. seq_puts(p, " Threshold APIC interrupts\n");
  109. #endif
  110. #ifdef CONFIG_X86_MCE_AMD
  111. seq_printf(p, "%*s: ", prec, "DFR");
  112. for_each_online_cpu(j)
  113. seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
  114. seq_puts(p, " Deferred Error APIC interrupts\n");
  115. #endif
  116. #ifdef CONFIG_X86_MCE
  117. seq_printf(p, "%*s: ", prec, "MCE");
  118. for_each_online_cpu(j)
  119. seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
  120. seq_puts(p, " Machine check exceptions\n");
  121. seq_printf(p, "%*s: ", prec, "MCP");
  122. for_each_online_cpu(j)
  123. seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
  124. seq_puts(p, " Machine check polls\n");
  125. #endif
  126. #if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
  127. if (test_bit(HYPERVISOR_CALLBACK_VECTOR, system_vectors)) {
  128. seq_printf(p, "%*s: ", prec, "HYP");
  129. for_each_online_cpu(j)
  130. seq_printf(p, "%10u ",
  131. irq_stats(j)->irq_hv_callback_count);
  132. seq_puts(p, " Hypervisor callback interrupts\n");
  133. }
  134. #endif
  135. seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
  136. #if defined(CONFIG_X86_IO_APIC)
  137. seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
  138. #endif
  139. #ifdef CONFIG_HAVE_KVM
  140. seq_printf(p, "%*s: ", prec, "PIN");
  141. for_each_online_cpu(j)
  142. seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
  143. seq_puts(p, " Posted-interrupt notification event\n");
  144. seq_printf(p, "%*s: ", prec, "NPI");
  145. for_each_online_cpu(j)
  146. seq_printf(p, "%10u ",
  147. irq_stats(j)->kvm_posted_intr_nested_ipis);
  148. seq_puts(p, " Nested posted-interrupt event\n");
  149. seq_printf(p, "%*s: ", prec, "PIW");
  150. for_each_online_cpu(j)
  151. seq_printf(p, "%10u ",
  152. irq_stats(j)->kvm_posted_intr_wakeup_ipis);
  153. seq_puts(p, " Posted-interrupt wakeup event\n");
  154. #endif
  155. return 0;
  156. }
  157. /*
  158. * /proc/stat helpers
  159. */
  160. u64 arch_irq_stat_cpu(unsigned int cpu)
  161. {
  162. u64 sum = irq_stats(cpu)->__nmi_count;
  163. #ifdef CONFIG_X86_LOCAL_APIC
  164. sum += irq_stats(cpu)->apic_timer_irqs;
  165. sum += irq_stats(cpu)->irq_spurious_count;
  166. sum += irq_stats(cpu)->apic_perf_irqs;
  167. sum += irq_stats(cpu)->apic_irq_work_irqs;
  168. sum += irq_stats(cpu)->icr_read_retry_count;
  169. if (x86_platform_ipi_callback)
  170. sum += irq_stats(cpu)->x86_platform_ipis;
  171. #endif
  172. #ifdef CONFIG_SMP
  173. sum += irq_stats(cpu)->irq_resched_count;
  174. sum += irq_stats(cpu)->irq_call_count;
  175. #endif
  176. #ifdef CONFIG_X86_THERMAL_VECTOR
  177. sum += irq_stats(cpu)->irq_thermal_count;
  178. #endif
  179. #ifdef CONFIG_X86_MCE_THRESHOLD
  180. sum += irq_stats(cpu)->irq_threshold_count;
  181. #endif
  182. #ifdef CONFIG_X86_MCE
  183. sum += per_cpu(mce_exception_count, cpu);
  184. sum += per_cpu(mce_poll_count, cpu);
  185. #endif
  186. return sum;
  187. }
  188. u64 arch_irq_stat(void)
  189. {
  190. u64 sum = atomic_read(&irq_err_count);
  191. return sum;
  192. }
  193. /*
  194. * do_IRQ handles all normal device IRQ's (the special
  195. * SMP cross-CPU interrupts have their own specific
  196. * handlers).
  197. */
  198. __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
  199. {
  200. struct pt_regs *old_regs = set_irq_regs(regs);
  201. struct irq_desc * desc;
  202. /* high bit used in ret_from_ code */
  203. unsigned vector = ~regs->orig_ax;
  204. entering_irq();
  205. /* entering_irq() tells RCU that we're not quiescent. Check it. */
  206. RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
  207. desc = __this_cpu_read(vector_irq[vector]);
  208. if (!handle_irq(desc, regs)) {
  209. ack_APIC_irq();
  210. if (desc != VECTOR_RETRIGGERED) {
  211. pr_emerg_ratelimited("%s: %d.%d No irq handler for vector\n",
  212. __func__, smp_processor_id(),
  213. vector);
  214. } else {
  215. __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
  216. }
  217. }
  218. exiting_irq();
  219. set_irq_regs(old_regs);
  220. return 1;
  221. }
  222. #ifdef CONFIG_X86_LOCAL_APIC
  223. /* Function pointer for generic interrupt vector handling */
  224. void (*x86_platform_ipi_callback)(void) = NULL;
  225. /*
  226. * Handler for X86_PLATFORM_IPI_VECTOR.
  227. */
  228. __visible void __irq_entry smp_x86_platform_ipi(struct pt_regs *regs)
  229. {
  230. struct pt_regs *old_regs = set_irq_regs(regs);
  231. entering_ack_irq();
  232. trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
  233. inc_irq_stat(x86_platform_ipis);
  234. if (x86_platform_ipi_callback)
  235. x86_platform_ipi_callback();
  236. trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
  237. exiting_irq();
  238. set_irq_regs(old_regs);
  239. }
  240. #endif
  241. #ifdef CONFIG_HAVE_KVM
  242. static void dummy_handler(void) {}
  243. static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
  244. void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
  245. {
  246. if (handler)
  247. kvm_posted_intr_wakeup_handler = handler;
  248. else
  249. kvm_posted_intr_wakeup_handler = dummy_handler;
  250. }
  251. EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
  252. /*
  253. * Handler for POSTED_INTERRUPT_VECTOR.
  254. */
  255. __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
  256. {
  257. struct pt_regs *old_regs = set_irq_regs(regs);
  258. entering_ack_irq();
  259. inc_irq_stat(kvm_posted_intr_ipis);
  260. exiting_irq();
  261. set_irq_regs(old_regs);
  262. }
  263. /*
  264. * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
  265. */
  266. __visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs)
  267. {
  268. struct pt_regs *old_regs = set_irq_regs(regs);
  269. entering_ack_irq();
  270. inc_irq_stat(kvm_posted_intr_wakeup_ipis);
  271. kvm_posted_intr_wakeup_handler();
  272. exiting_irq();
  273. set_irq_regs(old_regs);
  274. }
  275. /*
  276. * Handler for POSTED_INTERRUPT_NESTED_VECTOR.
  277. */
  278. __visible void smp_kvm_posted_intr_nested_ipi(struct pt_regs *regs)
  279. {
  280. struct pt_regs *old_regs = set_irq_regs(regs);
  281. entering_ack_irq();
  282. inc_irq_stat(kvm_posted_intr_nested_ipis);
  283. exiting_irq();
  284. set_irq_regs(old_regs);
  285. }
  286. #endif
  287. #ifdef CONFIG_HOTPLUG_CPU
  288. /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
  289. void fixup_irqs(void)
  290. {
  291. unsigned int irr, vector;
  292. struct irq_desc *desc;
  293. struct irq_data *data;
  294. struct irq_chip *chip;
  295. irq_migrate_all_off_this_cpu();
  296. /*
  297. * We can remove mdelay() and then send spuriuous interrupts to
  298. * new cpu targets for all the irqs that were handled previously by
  299. * this cpu. While it works, I have seen spurious interrupt messages
  300. * (nothing wrong but still...).
  301. *
  302. * So for now, retain mdelay(1) and check the IRR and then send those
  303. * interrupts to new targets as this cpu is already offlined...
  304. */
  305. mdelay(1);
  306. /*
  307. * We can walk the vector array of this cpu without holding
  308. * vector_lock because the cpu is already marked !online, so
  309. * nothing else will touch it.
  310. */
  311. for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
  312. if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
  313. continue;
  314. irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
  315. if (irr & (1 << (vector % 32))) {
  316. desc = __this_cpu_read(vector_irq[vector]);
  317. raw_spin_lock(&desc->lock);
  318. data = irq_desc_get_irq_data(desc);
  319. chip = irq_data_get_irq_chip(data);
  320. if (chip->irq_retrigger) {
  321. chip->irq_retrigger(data);
  322. __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
  323. }
  324. raw_spin_unlock(&desc->lock);
  325. }
  326. if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
  327. __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
  328. }
  329. }
  330. #endif