omap_drv.c 22 KB

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  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_drv.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Rob Clark <rob@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/wait.h>
  20. #include <drm/drm_atomic.h>
  21. #include <drm/drm_atomic_helper.h>
  22. #include <drm/drm_crtc_helper.h>
  23. #include <drm/drm_fb_helper.h>
  24. #include "omap_dmm_tiler.h"
  25. #include "omap_drv.h"
  26. #define DRIVER_NAME MODULE_NAME
  27. #define DRIVER_DESC "OMAP DRM"
  28. #define DRIVER_DATE "20110917"
  29. #define DRIVER_MAJOR 1
  30. #define DRIVER_MINOR 0
  31. #define DRIVER_PATCHLEVEL 0
  32. static int num_crtc = CONFIG_DRM_OMAP_NUM_CRTCS;
  33. MODULE_PARM_DESC(num_crtc, "Number of overlays to use as CRTCs");
  34. module_param(num_crtc, int, 0600);
  35. /*
  36. * mode config funcs
  37. */
  38. /* Notes about mapping DSS and DRM entities:
  39. * CRTC: overlay
  40. * encoder: manager.. with some extension to allow one primary CRTC
  41. * and zero or more video CRTC's to be mapped to one encoder?
  42. * connector: dssdev.. manager can be attached/detached from different
  43. * devices
  44. */
  45. static void omap_fb_output_poll_changed(struct drm_device *dev)
  46. {
  47. struct omap_drm_private *priv = dev->dev_private;
  48. DBG("dev=%p", dev);
  49. if (priv->fbdev)
  50. drm_fb_helper_hotplug_event(priv->fbdev);
  51. }
  52. struct omap_atomic_state_commit {
  53. struct work_struct work;
  54. struct drm_device *dev;
  55. struct drm_atomic_state *state;
  56. u32 crtcs;
  57. };
  58. static void omap_atomic_wait_for_completion(struct drm_device *dev,
  59. struct drm_atomic_state *old_state)
  60. {
  61. struct drm_crtc_state *old_crtc_state;
  62. struct drm_crtc *crtc;
  63. unsigned int i;
  64. int ret;
  65. for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  66. if (!crtc->state->enable)
  67. continue;
  68. ret = omap_crtc_wait_pending(crtc);
  69. if (!ret)
  70. dev_warn(dev->dev,
  71. "atomic complete timeout (pipe %u)!\n", i);
  72. }
  73. }
  74. static void omap_atomic_complete(struct omap_atomic_state_commit *commit)
  75. {
  76. struct drm_device *dev = commit->dev;
  77. struct omap_drm_private *priv = dev->dev_private;
  78. struct drm_atomic_state *old_state = commit->state;
  79. /* Apply the atomic update. */
  80. dispc_runtime_get();
  81. drm_atomic_helper_commit_modeset_disables(dev, old_state);
  82. drm_atomic_helper_commit_planes(dev, old_state,
  83. DRM_PLANE_COMMIT_ACTIVE_ONLY);
  84. drm_atomic_helper_commit_modeset_enables(dev, old_state);
  85. omap_atomic_wait_for_completion(dev, old_state);
  86. drm_atomic_helper_cleanup_planes(dev, old_state);
  87. dispc_runtime_put();
  88. drm_atomic_state_put(old_state);
  89. /* Complete the commit, wake up any waiter. */
  90. spin_lock(&priv->commit.lock);
  91. priv->commit.pending &= ~commit->crtcs;
  92. spin_unlock(&priv->commit.lock);
  93. wake_up_all(&priv->commit.wait);
  94. kfree(commit);
  95. }
  96. static void omap_atomic_work(struct work_struct *work)
  97. {
  98. struct omap_atomic_state_commit *commit =
  99. container_of(work, struct omap_atomic_state_commit, work);
  100. omap_atomic_complete(commit);
  101. }
  102. static bool omap_atomic_is_pending(struct omap_drm_private *priv,
  103. struct omap_atomic_state_commit *commit)
  104. {
  105. bool pending;
  106. spin_lock(&priv->commit.lock);
  107. pending = priv->commit.pending & commit->crtcs;
  108. spin_unlock(&priv->commit.lock);
  109. return pending;
  110. }
  111. static int omap_atomic_commit(struct drm_device *dev,
  112. struct drm_atomic_state *state, bool nonblock)
  113. {
  114. struct omap_drm_private *priv = dev->dev_private;
  115. struct omap_atomic_state_commit *commit;
  116. struct drm_crtc *crtc;
  117. struct drm_crtc_state *crtc_state;
  118. int i, ret;
  119. ret = drm_atomic_helper_prepare_planes(dev, state);
  120. if (ret)
  121. return ret;
  122. /* Allocate the commit object. */
  123. commit = kzalloc(sizeof(*commit), GFP_KERNEL);
  124. if (commit == NULL) {
  125. ret = -ENOMEM;
  126. goto error;
  127. }
  128. INIT_WORK(&commit->work, omap_atomic_work);
  129. commit->dev = dev;
  130. commit->state = state;
  131. /* Wait until all affected CRTCs have completed previous commits and
  132. * mark them as pending.
  133. */
  134. for_each_crtc_in_state(state, crtc, crtc_state, i)
  135. commit->crtcs |= drm_crtc_mask(crtc);
  136. wait_event(priv->commit.wait, !omap_atomic_is_pending(priv, commit));
  137. spin_lock(&priv->commit.lock);
  138. priv->commit.pending |= commit->crtcs;
  139. spin_unlock(&priv->commit.lock);
  140. /* Swap the state, this is the point of no return. */
  141. drm_atomic_helper_swap_state(state, true);
  142. drm_atomic_state_get(state);
  143. if (nonblock)
  144. schedule_work(&commit->work);
  145. else
  146. omap_atomic_complete(commit);
  147. return 0;
  148. error:
  149. drm_atomic_helper_cleanup_planes(dev, state);
  150. return ret;
  151. }
  152. static const struct drm_mode_config_funcs omap_mode_config_funcs = {
  153. .fb_create = omap_framebuffer_create,
  154. .output_poll_changed = omap_fb_output_poll_changed,
  155. .atomic_check = drm_atomic_helper_check,
  156. .atomic_commit = omap_atomic_commit,
  157. };
  158. static int get_connector_type(struct omap_dss_device *dssdev)
  159. {
  160. switch (dssdev->type) {
  161. case OMAP_DISPLAY_TYPE_HDMI:
  162. return DRM_MODE_CONNECTOR_HDMIA;
  163. case OMAP_DISPLAY_TYPE_DVI:
  164. return DRM_MODE_CONNECTOR_DVID;
  165. case OMAP_DISPLAY_TYPE_DSI:
  166. return DRM_MODE_CONNECTOR_DSI;
  167. default:
  168. return DRM_MODE_CONNECTOR_Unknown;
  169. }
  170. }
  171. static bool channel_used(struct drm_device *dev, enum omap_channel channel)
  172. {
  173. struct omap_drm_private *priv = dev->dev_private;
  174. int i;
  175. for (i = 0; i < priv->num_crtcs; i++) {
  176. struct drm_crtc *crtc = priv->crtcs[i];
  177. if (omap_crtc_channel(crtc) == channel)
  178. return true;
  179. }
  180. return false;
  181. }
  182. static void omap_disconnect_dssdevs(void)
  183. {
  184. struct omap_dss_device *dssdev = NULL;
  185. for_each_dss_dev(dssdev)
  186. dssdev->driver->disconnect(dssdev);
  187. }
  188. static int omap_connect_dssdevs(void)
  189. {
  190. int r;
  191. struct omap_dss_device *dssdev = NULL;
  192. bool no_displays = true;
  193. for_each_dss_dev(dssdev) {
  194. r = dssdev->driver->connect(dssdev);
  195. if (r == -EPROBE_DEFER) {
  196. omap_dss_put_device(dssdev);
  197. goto cleanup;
  198. } else if (r) {
  199. dev_warn(dssdev->dev, "could not connect display: %s\n",
  200. dssdev->name);
  201. } else {
  202. no_displays = false;
  203. }
  204. }
  205. if (no_displays)
  206. return -EPROBE_DEFER;
  207. return 0;
  208. cleanup:
  209. /*
  210. * if we are deferring probe, we disconnect the devices we previously
  211. * connected
  212. */
  213. omap_disconnect_dssdevs();
  214. return r;
  215. }
  216. static int omap_modeset_create_crtc(struct drm_device *dev, int id,
  217. enum omap_channel channel,
  218. u32 possible_crtcs)
  219. {
  220. struct omap_drm_private *priv = dev->dev_private;
  221. struct drm_plane *plane;
  222. struct drm_crtc *crtc;
  223. plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_PRIMARY,
  224. possible_crtcs);
  225. if (IS_ERR(plane))
  226. return PTR_ERR(plane);
  227. crtc = omap_crtc_init(dev, plane, channel, id);
  228. BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs));
  229. priv->crtcs[id] = crtc;
  230. priv->num_crtcs++;
  231. priv->planes[id] = plane;
  232. priv->num_planes++;
  233. return 0;
  234. }
  235. static int omap_modeset_init_properties(struct drm_device *dev)
  236. {
  237. struct omap_drm_private *priv = dev->dev_private;
  238. priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, 3);
  239. if (!priv->zorder_prop)
  240. return -ENOMEM;
  241. return 0;
  242. }
  243. static int omap_modeset_init(struct drm_device *dev)
  244. {
  245. struct omap_drm_private *priv = dev->dev_private;
  246. struct omap_dss_device *dssdev = NULL;
  247. int num_ovls = dss_feat_get_num_ovls();
  248. int num_mgrs = dss_feat_get_num_mgrs();
  249. int num_crtcs;
  250. int i, id = 0;
  251. int ret;
  252. u32 possible_crtcs;
  253. drm_mode_config_init(dev);
  254. ret = omap_modeset_init_properties(dev);
  255. if (ret < 0)
  256. return ret;
  257. /*
  258. * We usually don't want to create a CRTC for each manager, at least
  259. * not until we have a way to expose private planes to userspace.
  260. * Otherwise there would not be enough video pipes left for drm planes.
  261. * We use the num_crtc argument to limit the number of crtcs we create.
  262. */
  263. num_crtcs = min3(num_crtc, num_mgrs, num_ovls);
  264. possible_crtcs = (1 << num_crtcs) - 1;
  265. dssdev = NULL;
  266. for_each_dss_dev(dssdev) {
  267. struct drm_connector *connector;
  268. struct drm_encoder *encoder;
  269. enum omap_channel channel;
  270. struct omap_dss_device *out;
  271. if (!omapdss_device_is_connected(dssdev))
  272. continue;
  273. encoder = omap_encoder_init(dev, dssdev);
  274. if (!encoder) {
  275. dev_err(dev->dev, "could not create encoder: %s\n",
  276. dssdev->name);
  277. return -ENOMEM;
  278. }
  279. connector = omap_connector_init(dev,
  280. get_connector_type(dssdev), dssdev, encoder);
  281. if (!connector) {
  282. dev_err(dev->dev, "could not create connector: %s\n",
  283. dssdev->name);
  284. return -ENOMEM;
  285. }
  286. BUG_ON(priv->num_encoders >= ARRAY_SIZE(priv->encoders));
  287. BUG_ON(priv->num_connectors >= ARRAY_SIZE(priv->connectors));
  288. priv->encoders[priv->num_encoders++] = encoder;
  289. priv->connectors[priv->num_connectors++] = connector;
  290. drm_mode_connector_attach_encoder(connector, encoder);
  291. /*
  292. * if we have reached the limit of the crtcs we are allowed to
  293. * create, let's not try to look for a crtc for this
  294. * panel/encoder and onwards, we will, of course, populate the
  295. * the possible_crtcs field for all the encoders with the final
  296. * set of crtcs we create
  297. */
  298. if (id == num_crtcs)
  299. continue;
  300. /*
  301. * get the recommended DISPC channel for this encoder. For now,
  302. * we only try to get create a crtc out of the recommended, the
  303. * other possible channels to which the encoder can connect are
  304. * not considered.
  305. */
  306. out = omapdss_find_output_from_display(dssdev);
  307. channel = out->dispc_channel;
  308. omap_dss_put_device(out);
  309. /*
  310. * if this channel hasn't already been taken by a previously
  311. * allocated crtc, we create a new crtc for it
  312. */
  313. if (!channel_used(dev, channel)) {
  314. ret = omap_modeset_create_crtc(dev, id, channel,
  315. possible_crtcs);
  316. if (ret < 0) {
  317. dev_err(dev->dev,
  318. "could not create CRTC (channel %u)\n",
  319. channel);
  320. return ret;
  321. }
  322. id++;
  323. }
  324. }
  325. /*
  326. * we have allocated crtcs according to the need of the panels/encoders,
  327. * adding more crtcs here if needed
  328. */
  329. for (; id < num_crtcs; id++) {
  330. /* find a free manager for this crtc */
  331. for (i = 0; i < num_mgrs; i++) {
  332. if (!channel_used(dev, i))
  333. break;
  334. }
  335. if (i == num_mgrs) {
  336. /* this shouldn't really happen */
  337. dev_err(dev->dev, "no managers left for crtc\n");
  338. return -ENOMEM;
  339. }
  340. ret = omap_modeset_create_crtc(dev, id, i,
  341. possible_crtcs);
  342. if (ret < 0) {
  343. dev_err(dev->dev,
  344. "could not create CRTC (channel %u)\n", i);
  345. return ret;
  346. }
  347. }
  348. /*
  349. * Create normal planes for the remaining overlays:
  350. */
  351. for (; id < num_ovls; id++) {
  352. struct drm_plane *plane;
  353. plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_OVERLAY,
  354. possible_crtcs);
  355. if (IS_ERR(plane))
  356. return PTR_ERR(plane);
  357. BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes));
  358. priv->planes[priv->num_planes++] = plane;
  359. }
  360. for (i = 0; i < priv->num_encoders; i++) {
  361. struct drm_encoder *encoder = priv->encoders[i];
  362. struct omap_dss_device *dssdev =
  363. omap_encoder_get_dssdev(encoder);
  364. struct omap_dss_device *output;
  365. output = omapdss_find_output_from_display(dssdev);
  366. /* figure out which crtc's we can connect the encoder to: */
  367. encoder->possible_crtcs = 0;
  368. for (id = 0; id < priv->num_crtcs; id++) {
  369. struct drm_crtc *crtc = priv->crtcs[id];
  370. enum omap_channel crtc_channel;
  371. crtc_channel = omap_crtc_channel(crtc);
  372. if (output->dispc_channel == crtc_channel) {
  373. encoder->possible_crtcs |= (1 << id);
  374. break;
  375. }
  376. }
  377. omap_dss_put_device(output);
  378. }
  379. DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
  380. priv->num_planes, priv->num_crtcs, priv->num_encoders,
  381. priv->num_connectors);
  382. dev->mode_config.min_width = 32;
  383. dev->mode_config.min_height = 32;
  384. /* note: eventually will need some cpu_is_omapXYZ() type stuff here
  385. * to fill in these limits properly on different OMAP generations..
  386. */
  387. dev->mode_config.max_width = 2048;
  388. dev->mode_config.max_height = 2048;
  389. dev->mode_config.funcs = &omap_mode_config_funcs;
  390. drm_mode_config_reset(dev);
  391. omap_drm_irq_install(dev);
  392. return 0;
  393. }
  394. /*
  395. * drm ioctl funcs
  396. */
  397. static int ioctl_get_param(struct drm_device *dev, void *data,
  398. struct drm_file *file_priv)
  399. {
  400. struct omap_drm_private *priv = dev->dev_private;
  401. struct drm_omap_param *args = data;
  402. DBG("%p: param=%llu", dev, args->param);
  403. switch (args->param) {
  404. case OMAP_PARAM_CHIPSET_ID:
  405. args->value = priv->omaprev;
  406. break;
  407. default:
  408. DBG("unknown parameter %lld", args->param);
  409. return -EINVAL;
  410. }
  411. return 0;
  412. }
  413. static int ioctl_set_param(struct drm_device *dev, void *data,
  414. struct drm_file *file_priv)
  415. {
  416. struct drm_omap_param *args = data;
  417. switch (args->param) {
  418. default:
  419. DBG("unknown parameter %lld", args->param);
  420. return -EINVAL;
  421. }
  422. return 0;
  423. }
  424. #define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */
  425. static int ioctl_gem_new(struct drm_device *dev, void *data,
  426. struct drm_file *file_priv)
  427. {
  428. struct drm_omap_gem_new *args = data;
  429. u32 flags = args->flags & OMAP_BO_USER_MASK;
  430. VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
  431. args->size.bytes, flags);
  432. return omap_gem_new_handle(dev, file_priv, args->size, flags,
  433. &args->handle);
  434. }
  435. static int ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
  436. struct drm_file *file_priv)
  437. {
  438. struct drm_omap_gem_cpu_prep *args = data;
  439. struct drm_gem_object *obj;
  440. int ret;
  441. VERB("%p:%p: handle=%d, op=%x", dev, file_priv, args->handle, args->op);
  442. obj = drm_gem_object_lookup(file_priv, args->handle);
  443. if (!obj)
  444. return -ENOENT;
  445. ret = omap_gem_op_sync(obj, args->op);
  446. if (!ret)
  447. ret = omap_gem_op_start(obj, args->op);
  448. drm_gem_object_unreference_unlocked(obj);
  449. return ret;
  450. }
  451. static int ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
  452. struct drm_file *file_priv)
  453. {
  454. struct drm_omap_gem_cpu_fini *args = data;
  455. struct drm_gem_object *obj;
  456. int ret;
  457. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  458. obj = drm_gem_object_lookup(file_priv, args->handle);
  459. if (!obj)
  460. return -ENOENT;
  461. /* XXX flushy, flushy */
  462. ret = 0;
  463. if (!ret)
  464. ret = omap_gem_op_finish(obj, args->op);
  465. drm_gem_object_unreference_unlocked(obj);
  466. return ret;
  467. }
  468. static int ioctl_gem_info(struct drm_device *dev, void *data,
  469. struct drm_file *file_priv)
  470. {
  471. struct drm_omap_gem_info *args = data;
  472. struct drm_gem_object *obj;
  473. int ret = 0;
  474. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  475. obj = drm_gem_object_lookup(file_priv, args->handle);
  476. if (!obj)
  477. return -ENOENT;
  478. args->size = omap_gem_mmap_size(obj);
  479. args->offset = omap_gem_mmap_offset(obj);
  480. drm_gem_object_unreference_unlocked(obj);
  481. return ret;
  482. }
  483. static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
  484. DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, DRM_AUTH),
  485. DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  486. DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_AUTH),
  487. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, DRM_AUTH),
  488. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, DRM_AUTH),
  489. DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, DRM_AUTH),
  490. };
  491. /*
  492. * drm driver funcs
  493. */
  494. static int dev_open(struct drm_device *dev, struct drm_file *file)
  495. {
  496. file->driver_priv = NULL;
  497. DBG("open: dev=%p, file=%p", dev, file);
  498. return 0;
  499. }
  500. /**
  501. * lastclose - clean up after all DRM clients have exited
  502. * @dev: DRM device
  503. *
  504. * Take care of cleaning up after all DRM clients have exited. In the
  505. * mode setting case, we want to restore the kernel's initial mode (just
  506. * in case the last client left us in a bad state).
  507. */
  508. static void dev_lastclose(struct drm_device *dev)
  509. {
  510. int i;
  511. /* we don't support vga_switcheroo.. so just make sure the fbdev
  512. * mode is active
  513. */
  514. struct omap_drm_private *priv = dev->dev_private;
  515. int ret;
  516. DBG("lastclose: dev=%p", dev);
  517. /* need to restore default rotation state.. not sure
  518. * if there is a cleaner way to restore properties to
  519. * default state? Maybe a flag that properties should
  520. * automatically be restored to default state on
  521. * lastclose?
  522. */
  523. for (i = 0; i < priv->num_crtcs; i++) {
  524. struct drm_crtc *crtc = priv->crtcs[i];
  525. if (!crtc->primary->rotation_property)
  526. continue;
  527. drm_object_property_set_value(&crtc->base,
  528. crtc->primary->rotation_property,
  529. DRM_ROTATE_0);
  530. }
  531. for (i = 0; i < priv->num_planes; i++) {
  532. struct drm_plane *plane = priv->planes[i];
  533. if (!plane->rotation_property)
  534. continue;
  535. drm_object_property_set_value(&plane->base,
  536. plane->rotation_property,
  537. DRM_ROTATE_0);
  538. }
  539. if (priv->fbdev) {
  540. ret = drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
  541. if (ret)
  542. DBG("failed to restore crtc mode");
  543. }
  544. }
  545. static const struct vm_operations_struct omap_gem_vm_ops = {
  546. .fault = omap_gem_fault,
  547. .open = drm_gem_vm_open,
  548. .close = drm_gem_vm_close,
  549. };
  550. static const struct file_operations omapdriver_fops = {
  551. .owner = THIS_MODULE,
  552. .open = drm_open,
  553. .unlocked_ioctl = drm_ioctl,
  554. .release = drm_release,
  555. .mmap = omap_gem_mmap,
  556. .poll = drm_poll,
  557. .read = drm_read,
  558. .llseek = noop_llseek,
  559. };
  560. static struct drm_driver omap_drm_driver = {
  561. .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
  562. DRIVER_ATOMIC,
  563. .open = dev_open,
  564. .lastclose = dev_lastclose,
  565. .get_vblank_counter = drm_vblank_no_hw_counter,
  566. .enable_vblank = omap_irq_enable_vblank,
  567. .disable_vblank = omap_irq_disable_vblank,
  568. #ifdef CONFIG_DEBUG_FS
  569. .debugfs_init = omap_debugfs_init,
  570. #endif
  571. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  572. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  573. .gem_prime_export = omap_gem_prime_export,
  574. .gem_prime_import = omap_gem_prime_import,
  575. .gem_free_object = omap_gem_free_object,
  576. .gem_vm_ops = &omap_gem_vm_ops,
  577. .dumb_create = omap_gem_dumb_create,
  578. .dumb_map_offset = omap_gem_dumb_map_offset,
  579. .dumb_destroy = drm_gem_dumb_destroy,
  580. .ioctls = ioctls,
  581. .num_ioctls = DRM_OMAP_NUM_IOCTLS,
  582. .fops = &omapdriver_fops,
  583. .name = DRIVER_NAME,
  584. .desc = DRIVER_DESC,
  585. .date = DRIVER_DATE,
  586. .major = DRIVER_MAJOR,
  587. .minor = DRIVER_MINOR,
  588. .patchlevel = DRIVER_PATCHLEVEL,
  589. };
  590. static int pdev_probe(struct platform_device *pdev)
  591. {
  592. struct omap_drm_platform_data *pdata = pdev->dev.platform_data;
  593. struct omap_drm_private *priv;
  594. struct drm_device *ddev;
  595. unsigned int i;
  596. int ret;
  597. DBG("%s", pdev->name);
  598. if (omapdss_is_initialized() == false)
  599. return -EPROBE_DEFER;
  600. omap_crtc_pre_init();
  601. ret = omap_connect_dssdevs();
  602. if (ret)
  603. goto err_crtc_uninit;
  604. /* Allocate and initialize the driver private structure. */
  605. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  606. if (!priv) {
  607. ret = -ENOMEM;
  608. goto err_disconnect_dssdevs;
  609. }
  610. priv->omaprev = pdata->omaprev;
  611. priv->wq = alloc_ordered_workqueue("omapdrm", 0);
  612. init_waitqueue_head(&priv->commit.wait);
  613. spin_lock_init(&priv->commit.lock);
  614. spin_lock_init(&priv->list_lock);
  615. INIT_LIST_HEAD(&priv->obj_list);
  616. /* Allocate and initialize the DRM device. */
  617. ddev = drm_dev_alloc(&omap_drm_driver, &pdev->dev);
  618. if (IS_ERR(ddev)) {
  619. ret = PTR_ERR(ddev);
  620. goto err_free_priv;
  621. }
  622. ddev->dev_private = priv;
  623. platform_set_drvdata(pdev, ddev);
  624. omap_gem_init(ddev);
  625. ret = omap_modeset_init(ddev);
  626. if (ret) {
  627. dev_err(&pdev->dev, "omap_modeset_init failed: ret=%d\n", ret);
  628. goto err_free_drm_dev;
  629. }
  630. /* Initialize vblank handling, start with all CRTCs disabled. */
  631. ret = drm_vblank_init(ddev, priv->num_crtcs);
  632. if (ret) {
  633. dev_err(&pdev->dev, "could not init vblank\n");
  634. goto err_cleanup_modeset;
  635. }
  636. for (i = 0; i < priv->num_crtcs; i++)
  637. drm_crtc_vblank_off(priv->crtcs[i]);
  638. priv->fbdev = omap_fbdev_init(ddev);
  639. drm_kms_helper_poll_init(ddev);
  640. /*
  641. * Register the DRM device with the core and the connectors with
  642. * sysfs.
  643. */
  644. ret = drm_dev_register(ddev, 0);
  645. if (ret)
  646. goto err_cleanup_helpers;
  647. return 0;
  648. err_cleanup_helpers:
  649. drm_kms_helper_poll_fini(ddev);
  650. if (priv->fbdev)
  651. omap_fbdev_free(ddev);
  652. err_cleanup_modeset:
  653. drm_mode_config_cleanup(ddev);
  654. omap_drm_irq_uninstall(ddev);
  655. err_free_drm_dev:
  656. omap_gem_deinit(ddev);
  657. drm_dev_unref(ddev);
  658. err_free_priv:
  659. destroy_workqueue(priv->wq);
  660. kfree(priv);
  661. err_disconnect_dssdevs:
  662. omap_disconnect_dssdevs();
  663. err_crtc_uninit:
  664. omap_crtc_pre_uninit();
  665. return ret;
  666. }
  667. static int pdev_remove(struct platform_device *pdev)
  668. {
  669. struct drm_device *ddev = platform_get_drvdata(pdev);
  670. struct omap_drm_private *priv = ddev->dev_private;
  671. DBG("");
  672. drm_dev_unregister(ddev);
  673. drm_kms_helper_poll_fini(ddev);
  674. if (priv->fbdev)
  675. omap_fbdev_free(ddev);
  676. drm_mode_config_cleanup(ddev);
  677. omap_drm_irq_uninstall(ddev);
  678. omap_gem_deinit(ddev);
  679. drm_dev_unref(ddev);
  680. destroy_workqueue(priv->wq);
  681. kfree(priv);
  682. omap_disconnect_dssdevs();
  683. omap_crtc_pre_uninit();
  684. return 0;
  685. }
  686. #ifdef CONFIG_PM_SLEEP
  687. static int omap_drm_suspend_all_displays(void)
  688. {
  689. struct omap_dss_device *dssdev = NULL;
  690. for_each_dss_dev(dssdev) {
  691. if (!dssdev->driver)
  692. continue;
  693. if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
  694. dssdev->driver->disable(dssdev);
  695. dssdev->activate_after_resume = true;
  696. } else {
  697. dssdev->activate_after_resume = false;
  698. }
  699. }
  700. return 0;
  701. }
  702. static int omap_drm_resume_all_displays(void)
  703. {
  704. struct omap_dss_device *dssdev = NULL;
  705. for_each_dss_dev(dssdev) {
  706. if (!dssdev->driver)
  707. continue;
  708. if (dssdev->activate_after_resume) {
  709. dssdev->driver->enable(dssdev);
  710. dssdev->activate_after_resume = false;
  711. }
  712. }
  713. return 0;
  714. }
  715. static int omap_drm_suspend(struct device *dev)
  716. {
  717. struct drm_device *drm_dev = dev_get_drvdata(dev);
  718. drm_kms_helper_poll_disable(drm_dev);
  719. drm_modeset_lock_all(drm_dev);
  720. omap_drm_suspend_all_displays();
  721. drm_modeset_unlock_all(drm_dev);
  722. return 0;
  723. }
  724. static int omap_drm_resume(struct device *dev)
  725. {
  726. struct drm_device *drm_dev = dev_get_drvdata(dev);
  727. drm_modeset_lock_all(drm_dev);
  728. omap_drm_resume_all_displays();
  729. drm_modeset_unlock_all(drm_dev);
  730. drm_kms_helper_poll_enable(drm_dev);
  731. return omap_gem_resume(dev);
  732. }
  733. #endif
  734. static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
  735. static struct platform_driver pdev = {
  736. .driver = {
  737. .name = DRIVER_NAME,
  738. .pm = &omapdrm_pm_ops,
  739. },
  740. .probe = pdev_probe,
  741. .remove = pdev_remove,
  742. };
  743. static struct platform_driver * const drivers[] = {
  744. &omap_dmm_driver,
  745. &pdev,
  746. };
  747. static int __init omap_drm_init(void)
  748. {
  749. DBG("init");
  750. return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
  751. }
  752. static void __exit omap_drm_fini(void)
  753. {
  754. DBG("fini");
  755. platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
  756. }
  757. /* need late_initcall() so we load after dss_driver's are loaded */
  758. late_initcall(omap_drm_init);
  759. module_exit(omap_drm_fini);
  760. MODULE_AUTHOR("Rob Clark <rob@ti.com>");
  761. MODULE_DESCRIPTION("OMAP DRM Display Driver");
  762. MODULE_ALIAS("platform:" DRIVER_NAME);
  763. MODULE_LICENSE("GPL v2");