ymfpci_main.c 72 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496
  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  3. * Routines for control of YMF724/740/744/754 chips
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. *
  19. */
  20. #include <linux/delay.h>
  21. #include <linux/firmware.h>
  22. #include <linux/init.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/pci.h>
  25. #include <linux/sched.h>
  26. #include <linux/slab.h>
  27. #include <linux/mutex.h>
  28. #include <linux/module.h>
  29. #include <sound/core.h>
  30. #include <sound/control.h>
  31. #include <sound/info.h>
  32. #include <sound/tlv.h>
  33. #include "ymfpci.h"
  34. #include <sound/asoundef.h>
  35. #include <sound/mpu401.h>
  36. #include <asm/io.h>
  37. #include <asm/byteorder.h>
  38. /*
  39. * common I/O routines
  40. */
  41. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip);
  42. static inline u8 snd_ymfpci_readb(struct snd_ymfpci *chip, u32 offset)
  43. {
  44. return readb(chip->reg_area_virt + offset);
  45. }
  46. static inline void snd_ymfpci_writeb(struct snd_ymfpci *chip, u32 offset, u8 val)
  47. {
  48. writeb(val, chip->reg_area_virt + offset);
  49. }
  50. static inline u16 snd_ymfpci_readw(struct snd_ymfpci *chip, u32 offset)
  51. {
  52. return readw(chip->reg_area_virt + offset);
  53. }
  54. static inline void snd_ymfpci_writew(struct snd_ymfpci *chip, u32 offset, u16 val)
  55. {
  56. writew(val, chip->reg_area_virt + offset);
  57. }
  58. static inline u32 snd_ymfpci_readl(struct snd_ymfpci *chip, u32 offset)
  59. {
  60. return readl(chip->reg_area_virt + offset);
  61. }
  62. static inline void snd_ymfpci_writel(struct snd_ymfpci *chip, u32 offset, u32 val)
  63. {
  64. writel(val, chip->reg_area_virt + offset);
  65. }
  66. static int snd_ymfpci_codec_ready(struct snd_ymfpci *chip, int secondary)
  67. {
  68. unsigned long end_time;
  69. u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
  70. end_time = jiffies + msecs_to_jiffies(750);
  71. do {
  72. if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
  73. return 0;
  74. schedule_timeout_uninterruptible(1);
  75. } while (time_before(jiffies, end_time));
  76. dev_err(chip->card->dev,
  77. "codec_ready: codec %i is not ready [0x%x]\n",
  78. secondary, snd_ymfpci_readw(chip, reg));
  79. return -EBUSY;
  80. }
  81. static void snd_ymfpci_codec_write(struct snd_ac97 *ac97, u16 reg, u16 val)
  82. {
  83. struct snd_ymfpci *chip = ac97->private_data;
  84. u32 cmd;
  85. snd_ymfpci_codec_ready(chip, 0);
  86. cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val;
  87. snd_ymfpci_writel(chip, YDSXGR_AC97CMDDATA, cmd);
  88. }
  89. static u16 snd_ymfpci_codec_read(struct snd_ac97 *ac97, u16 reg)
  90. {
  91. struct snd_ymfpci *chip = ac97->private_data;
  92. if (snd_ymfpci_codec_ready(chip, 0))
  93. return ~0;
  94. snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg);
  95. if (snd_ymfpci_codec_ready(chip, 0))
  96. return ~0;
  97. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_744 && chip->rev < 2) {
  98. int i;
  99. for (i = 0; i < 600; i++)
  100. snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  101. }
  102. return snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  103. }
  104. /*
  105. * Misc routines
  106. */
  107. static u32 snd_ymfpci_calc_delta(u32 rate)
  108. {
  109. switch (rate) {
  110. case 8000: return 0x02aaab00;
  111. case 11025: return 0x03accd00;
  112. case 16000: return 0x05555500;
  113. case 22050: return 0x07599a00;
  114. case 32000: return 0x0aaaab00;
  115. case 44100: return 0x0eb33300;
  116. default: return ((rate << 16) / 375) << 5;
  117. }
  118. }
  119. static u32 def_rate[8] = {
  120. 100, 2000, 8000, 11025, 16000, 22050, 32000, 48000
  121. };
  122. static u32 snd_ymfpci_calc_lpfK(u32 rate)
  123. {
  124. u32 i;
  125. static u32 val[8] = {
  126. 0x00570000, 0x06AA0000, 0x18B20000, 0x20930000,
  127. 0x2B9A0000, 0x35A10000, 0x3EAA0000, 0x40000000
  128. };
  129. if (rate == 44100)
  130. return 0x40000000; /* FIXME: What's the right value? */
  131. for (i = 0; i < 8; i++)
  132. if (rate <= def_rate[i])
  133. return val[i];
  134. return val[0];
  135. }
  136. static u32 snd_ymfpci_calc_lpfQ(u32 rate)
  137. {
  138. u32 i;
  139. static u32 val[8] = {
  140. 0x35280000, 0x34A70000, 0x32020000, 0x31770000,
  141. 0x31390000, 0x31C90000, 0x33D00000, 0x40000000
  142. };
  143. if (rate == 44100)
  144. return 0x370A0000;
  145. for (i = 0; i < 8; i++)
  146. if (rate <= def_rate[i])
  147. return val[i];
  148. return val[0];
  149. }
  150. /*
  151. * Hardware start management
  152. */
  153. static void snd_ymfpci_hw_start(struct snd_ymfpci *chip)
  154. {
  155. unsigned long flags;
  156. spin_lock_irqsave(&chip->reg_lock, flags);
  157. if (chip->start_count++ > 0)
  158. goto __end;
  159. snd_ymfpci_writel(chip, YDSXGR_MODE,
  160. snd_ymfpci_readl(chip, YDSXGR_MODE) | 3);
  161. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  162. __end:
  163. spin_unlock_irqrestore(&chip->reg_lock, flags);
  164. }
  165. static void snd_ymfpci_hw_stop(struct snd_ymfpci *chip)
  166. {
  167. unsigned long flags;
  168. long timeout = 1000;
  169. spin_lock_irqsave(&chip->reg_lock, flags);
  170. if (--chip->start_count > 0)
  171. goto __end;
  172. snd_ymfpci_writel(chip, YDSXGR_MODE,
  173. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~3);
  174. while (timeout-- > 0) {
  175. if ((snd_ymfpci_readl(chip, YDSXGR_STATUS) & 2) == 0)
  176. break;
  177. }
  178. if (atomic_read(&chip->interrupt_sleep_count)) {
  179. atomic_set(&chip->interrupt_sleep_count, 0);
  180. wake_up(&chip->interrupt_sleep);
  181. }
  182. __end:
  183. spin_unlock_irqrestore(&chip->reg_lock, flags);
  184. }
  185. /*
  186. * Playback voice management
  187. */
  188. static int voice_alloc(struct snd_ymfpci *chip,
  189. enum snd_ymfpci_voice_type type, int pair,
  190. struct snd_ymfpci_voice **rvoice)
  191. {
  192. struct snd_ymfpci_voice *voice, *voice2;
  193. int idx;
  194. *rvoice = NULL;
  195. for (idx = 0; idx < YDSXG_PLAYBACK_VOICES; idx += pair ? 2 : 1) {
  196. voice = &chip->voices[idx];
  197. voice2 = pair ? &chip->voices[idx+1] : NULL;
  198. if (voice->use || (voice2 && voice2->use))
  199. continue;
  200. voice->use = 1;
  201. if (voice2)
  202. voice2->use = 1;
  203. switch (type) {
  204. case YMFPCI_PCM:
  205. voice->pcm = 1;
  206. if (voice2)
  207. voice2->pcm = 1;
  208. break;
  209. case YMFPCI_SYNTH:
  210. voice->synth = 1;
  211. break;
  212. case YMFPCI_MIDI:
  213. voice->midi = 1;
  214. break;
  215. }
  216. snd_ymfpci_hw_start(chip);
  217. if (voice2)
  218. snd_ymfpci_hw_start(chip);
  219. *rvoice = voice;
  220. return 0;
  221. }
  222. return -ENOMEM;
  223. }
  224. static int snd_ymfpci_voice_alloc(struct snd_ymfpci *chip,
  225. enum snd_ymfpci_voice_type type, int pair,
  226. struct snd_ymfpci_voice **rvoice)
  227. {
  228. unsigned long flags;
  229. int result;
  230. if (snd_BUG_ON(!rvoice))
  231. return -EINVAL;
  232. if (snd_BUG_ON(pair && type != YMFPCI_PCM))
  233. return -EINVAL;
  234. spin_lock_irqsave(&chip->voice_lock, flags);
  235. for (;;) {
  236. result = voice_alloc(chip, type, pair, rvoice);
  237. if (result == 0 || type != YMFPCI_PCM)
  238. break;
  239. /* TODO: synth/midi voice deallocation */
  240. break;
  241. }
  242. spin_unlock_irqrestore(&chip->voice_lock, flags);
  243. return result;
  244. }
  245. static int snd_ymfpci_voice_free(struct snd_ymfpci *chip, struct snd_ymfpci_voice *pvoice)
  246. {
  247. unsigned long flags;
  248. if (snd_BUG_ON(!pvoice))
  249. return -EINVAL;
  250. snd_ymfpci_hw_stop(chip);
  251. spin_lock_irqsave(&chip->voice_lock, flags);
  252. if (pvoice->number == chip->src441_used) {
  253. chip->src441_used = -1;
  254. pvoice->ypcm->use_441_slot = 0;
  255. }
  256. pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = 0;
  257. pvoice->ypcm = NULL;
  258. pvoice->interrupt = NULL;
  259. spin_unlock_irqrestore(&chip->voice_lock, flags);
  260. return 0;
  261. }
  262. /*
  263. * PCM part
  264. */
  265. static void snd_ymfpci_pcm_interrupt(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice)
  266. {
  267. struct snd_ymfpci_pcm *ypcm;
  268. u32 pos, delta;
  269. if ((ypcm = voice->ypcm) == NULL)
  270. return;
  271. if (ypcm->substream == NULL)
  272. return;
  273. spin_lock(&chip->reg_lock);
  274. if (ypcm->running) {
  275. pos = le32_to_cpu(voice->bank[chip->active_bank].start);
  276. if (pos < ypcm->last_pos)
  277. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  278. else
  279. delta = pos - ypcm->last_pos;
  280. ypcm->period_pos += delta;
  281. ypcm->last_pos = pos;
  282. if (ypcm->period_pos >= ypcm->period_size) {
  283. /*
  284. dev_dbg(chip->card->dev,
  285. "done - active_bank = 0x%x, start = 0x%x\n",
  286. chip->active_bank,
  287. voice->bank[chip->active_bank].start);
  288. */
  289. ypcm->period_pos %= ypcm->period_size;
  290. spin_unlock(&chip->reg_lock);
  291. snd_pcm_period_elapsed(ypcm->substream);
  292. spin_lock(&chip->reg_lock);
  293. }
  294. if (unlikely(ypcm->update_pcm_vol)) {
  295. unsigned int subs = ypcm->substream->number;
  296. unsigned int next_bank = 1 - chip->active_bank;
  297. struct snd_ymfpci_playback_bank *bank;
  298. u32 volume;
  299. bank = &voice->bank[next_bank];
  300. volume = cpu_to_le32(chip->pcm_mixer[subs].left << 15);
  301. bank->left_gain_end = volume;
  302. if (ypcm->output_rear)
  303. bank->eff2_gain_end = volume;
  304. if (ypcm->voices[1])
  305. bank = &ypcm->voices[1]->bank[next_bank];
  306. volume = cpu_to_le32(chip->pcm_mixer[subs].right << 15);
  307. bank->right_gain_end = volume;
  308. if (ypcm->output_rear)
  309. bank->eff3_gain_end = volume;
  310. ypcm->update_pcm_vol--;
  311. }
  312. }
  313. spin_unlock(&chip->reg_lock);
  314. }
  315. static void snd_ymfpci_pcm_capture_interrupt(struct snd_pcm_substream *substream)
  316. {
  317. struct snd_pcm_runtime *runtime = substream->runtime;
  318. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  319. struct snd_ymfpci *chip = ypcm->chip;
  320. u32 pos, delta;
  321. spin_lock(&chip->reg_lock);
  322. if (ypcm->running) {
  323. pos = le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  324. if (pos < ypcm->last_pos)
  325. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  326. else
  327. delta = pos - ypcm->last_pos;
  328. ypcm->period_pos += delta;
  329. ypcm->last_pos = pos;
  330. if (ypcm->period_pos >= ypcm->period_size) {
  331. ypcm->period_pos %= ypcm->period_size;
  332. /*
  333. dev_dbg(chip->card->dev,
  334. "done - active_bank = 0x%x, start = 0x%x\n",
  335. chip->active_bank,
  336. voice->bank[chip->active_bank].start);
  337. */
  338. spin_unlock(&chip->reg_lock);
  339. snd_pcm_period_elapsed(substream);
  340. spin_lock(&chip->reg_lock);
  341. }
  342. }
  343. spin_unlock(&chip->reg_lock);
  344. }
  345. static int snd_ymfpci_playback_trigger(struct snd_pcm_substream *substream,
  346. int cmd)
  347. {
  348. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  349. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  350. struct snd_kcontrol *kctl = NULL;
  351. int result = 0;
  352. spin_lock(&chip->reg_lock);
  353. if (ypcm->voices[0] == NULL) {
  354. result = -EINVAL;
  355. goto __unlock;
  356. }
  357. switch (cmd) {
  358. case SNDRV_PCM_TRIGGER_START:
  359. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  360. case SNDRV_PCM_TRIGGER_RESUME:
  361. chip->ctrl_playback[ypcm->voices[0]->number + 1] = cpu_to_le32(ypcm->voices[0]->bank_addr);
  362. if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
  363. chip->ctrl_playback[ypcm->voices[1]->number + 1] = cpu_to_le32(ypcm->voices[1]->bank_addr);
  364. ypcm->running = 1;
  365. break;
  366. case SNDRV_PCM_TRIGGER_STOP:
  367. if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
  368. kctl = chip->pcm_mixer[substream->number].ctl;
  369. kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  370. }
  371. /* fall through */
  372. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  373. case SNDRV_PCM_TRIGGER_SUSPEND:
  374. chip->ctrl_playback[ypcm->voices[0]->number + 1] = 0;
  375. if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
  376. chip->ctrl_playback[ypcm->voices[1]->number + 1] = 0;
  377. ypcm->running = 0;
  378. break;
  379. default:
  380. result = -EINVAL;
  381. break;
  382. }
  383. __unlock:
  384. spin_unlock(&chip->reg_lock);
  385. if (kctl)
  386. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  387. return result;
  388. }
  389. static int snd_ymfpci_capture_trigger(struct snd_pcm_substream *substream,
  390. int cmd)
  391. {
  392. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  393. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  394. int result = 0;
  395. u32 tmp;
  396. spin_lock(&chip->reg_lock);
  397. switch (cmd) {
  398. case SNDRV_PCM_TRIGGER_START:
  399. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  400. case SNDRV_PCM_TRIGGER_RESUME:
  401. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) | (1 << ypcm->capture_bank_number);
  402. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  403. ypcm->running = 1;
  404. break;
  405. case SNDRV_PCM_TRIGGER_STOP:
  406. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  407. case SNDRV_PCM_TRIGGER_SUSPEND:
  408. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) & ~(1 << ypcm->capture_bank_number);
  409. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  410. ypcm->running = 0;
  411. break;
  412. default:
  413. result = -EINVAL;
  414. break;
  415. }
  416. spin_unlock(&chip->reg_lock);
  417. return result;
  418. }
  419. static int snd_ymfpci_pcm_voice_alloc(struct snd_ymfpci_pcm *ypcm, int voices)
  420. {
  421. int err;
  422. if (ypcm->voices[1] != NULL && voices < 2) {
  423. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[1]);
  424. ypcm->voices[1] = NULL;
  425. }
  426. if (voices == 1 && ypcm->voices[0] != NULL)
  427. return 0; /* already allocated */
  428. if (voices == 2 && ypcm->voices[0] != NULL && ypcm->voices[1] != NULL)
  429. return 0; /* already allocated */
  430. if (voices > 1) {
  431. if (ypcm->voices[0] != NULL && ypcm->voices[1] == NULL) {
  432. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[0]);
  433. ypcm->voices[0] = NULL;
  434. }
  435. }
  436. err = snd_ymfpci_voice_alloc(ypcm->chip, YMFPCI_PCM, voices > 1, &ypcm->voices[0]);
  437. if (err < 0)
  438. return err;
  439. ypcm->voices[0]->ypcm = ypcm;
  440. ypcm->voices[0]->interrupt = snd_ymfpci_pcm_interrupt;
  441. if (voices > 1) {
  442. ypcm->voices[1] = &ypcm->chip->voices[ypcm->voices[0]->number + 1];
  443. ypcm->voices[1]->ypcm = ypcm;
  444. }
  445. return 0;
  446. }
  447. static void snd_ymfpci_pcm_init_voice(struct snd_ymfpci_pcm *ypcm, unsigned int voiceidx,
  448. struct snd_pcm_runtime *runtime,
  449. int has_pcm_volume)
  450. {
  451. struct snd_ymfpci_voice *voice = ypcm->voices[voiceidx];
  452. u32 format;
  453. u32 delta = snd_ymfpci_calc_delta(runtime->rate);
  454. u32 lpfQ = snd_ymfpci_calc_lpfQ(runtime->rate);
  455. u32 lpfK = snd_ymfpci_calc_lpfK(runtime->rate);
  456. struct snd_ymfpci_playback_bank *bank;
  457. unsigned int nbank;
  458. u32 vol_left, vol_right;
  459. u8 use_left, use_right;
  460. unsigned long flags;
  461. if (snd_BUG_ON(!voice))
  462. return;
  463. if (runtime->channels == 1) {
  464. use_left = 1;
  465. use_right = 1;
  466. } else {
  467. use_left = (voiceidx & 1) == 0;
  468. use_right = !use_left;
  469. }
  470. if (has_pcm_volume) {
  471. vol_left = cpu_to_le32(ypcm->chip->pcm_mixer
  472. [ypcm->substream->number].left << 15);
  473. vol_right = cpu_to_le32(ypcm->chip->pcm_mixer
  474. [ypcm->substream->number].right << 15);
  475. } else {
  476. vol_left = cpu_to_le32(0x40000000);
  477. vol_right = cpu_to_le32(0x40000000);
  478. }
  479. spin_lock_irqsave(&ypcm->chip->voice_lock, flags);
  480. format = runtime->channels == 2 ? 0x00010000 : 0;
  481. if (snd_pcm_format_width(runtime->format) == 8)
  482. format |= 0x80000000;
  483. else if (ypcm->chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  484. runtime->rate == 44100 && runtime->channels == 2 &&
  485. voiceidx == 0 && (ypcm->chip->src441_used == -1 ||
  486. ypcm->chip->src441_used == voice->number)) {
  487. ypcm->chip->src441_used = voice->number;
  488. ypcm->use_441_slot = 1;
  489. format |= 0x10000000;
  490. }
  491. if (ypcm->chip->src441_used == voice->number &&
  492. (format & 0x10000000) == 0) {
  493. ypcm->chip->src441_used = -1;
  494. ypcm->use_441_slot = 0;
  495. }
  496. if (runtime->channels == 2 && (voiceidx & 1) != 0)
  497. format |= 1;
  498. spin_unlock_irqrestore(&ypcm->chip->voice_lock, flags);
  499. for (nbank = 0; nbank < 2; nbank++) {
  500. bank = &voice->bank[nbank];
  501. memset(bank, 0, sizeof(*bank));
  502. bank->format = cpu_to_le32(format);
  503. bank->base = cpu_to_le32(runtime->dma_addr);
  504. bank->loop_end = cpu_to_le32(ypcm->buffer_size);
  505. bank->lpfQ = cpu_to_le32(lpfQ);
  506. bank->delta =
  507. bank->delta_end = cpu_to_le32(delta);
  508. bank->lpfK =
  509. bank->lpfK_end = cpu_to_le32(lpfK);
  510. bank->eg_gain =
  511. bank->eg_gain_end = cpu_to_le32(0x40000000);
  512. if (ypcm->output_front) {
  513. if (use_left) {
  514. bank->left_gain =
  515. bank->left_gain_end = vol_left;
  516. }
  517. if (use_right) {
  518. bank->right_gain =
  519. bank->right_gain_end = vol_right;
  520. }
  521. }
  522. if (ypcm->output_rear) {
  523. if (!ypcm->swap_rear) {
  524. if (use_left) {
  525. bank->eff2_gain =
  526. bank->eff2_gain_end = vol_left;
  527. }
  528. if (use_right) {
  529. bank->eff3_gain =
  530. bank->eff3_gain_end = vol_right;
  531. }
  532. } else {
  533. /* The SPDIF out channels seem to be swapped, so we have
  534. * to swap them here, too. The rear analog out channels
  535. * will be wrong, but otherwise AC3 would not work.
  536. */
  537. if (use_left) {
  538. bank->eff3_gain =
  539. bank->eff3_gain_end = vol_left;
  540. }
  541. if (use_right) {
  542. bank->eff2_gain =
  543. bank->eff2_gain_end = vol_right;
  544. }
  545. }
  546. }
  547. }
  548. }
  549. static int snd_ymfpci_ac3_init(struct snd_ymfpci *chip)
  550. {
  551. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  552. 4096, &chip->ac3_tmp_base) < 0)
  553. return -ENOMEM;
  554. chip->bank_effect[3][0]->base =
  555. chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr);
  556. chip->bank_effect[3][0]->loop_end =
  557. chip->bank_effect[3][1]->loop_end = cpu_to_le32(1024);
  558. chip->bank_effect[4][0]->base =
  559. chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048);
  560. chip->bank_effect[4][0]->loop_end =
  561. chip->bank_effect[4][1]->loop_end = cpu_to_le32(1024);
  562. spin_lock_irq(&chip->reg_lock);
  563. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  564. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) | 3 << 3);
  565. spin_unlock_irq(&chip->reg_lock);
  566. return 0;
  567. }
  568. static int snd_ymfpci_ac3_done(struct snd_ymfpci *chip)
  569. {
  570. spin_lock_irq(&chip->reg_lock);
  571. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  572. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) & ~(3 << 3));
  573. spin_unlock_irq(&chip->reg_lock);
  574. // snd_ymfpci_irq_wait(chip);
  575. if (chip->ac3_tmp_base.area) {
  576. snd_dma_free_pages(&chip->ac3_tmp_base);
  577. chip->ac3_tmp_base.area = NULL;
  578. }
  579. return 0;
  580. }
  581. static int snd_ymfpci_playback_hw_params(struct snd_pcm_substream *substream,
  582. struct snd_pcm_hw_params *hw_params)
  583. {
  584. struct snd_pcm_runtime *runtime = substream->runtime;
  585. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  586. int err;
  587. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  588. return err;
  589. if ((err = snd_ymfpci_pcm_voice_alloc(ypcm, params_channels(hw_params))) < 0)
  590. return err;
  591. return 0;
  592. }
  593. static int snd_ymfpci_playback_hw_free(struct snd_pcm_substream *substream)
  594. {
  595. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  596. struct snd_pcm_runtime *runtime = substream->runtime;
  597. struct snd_ymfpci_pcm *ypcm;
  598. if (runtime->private_data == NULL)
  599. return 0;
  600. ypcm = runtime->private_data;
  601. /* wait, until the PCI operations are not finished */
  602. snd_ymfpci_irq_wait(chip);
  603. snd_pcm_lib_free_pages(substream);
  604. if (ypcm->voices[1]) {
  605. snd_ymfpci_voice_free(chip, ypcm->voices[1]);
  606. ypcm->voices[1] = NULL;
  607. }
  608. if (ypcm->voices[0]) {
  609. snd_ymfpci_voice_free(chip, ypcm->voices[0]);
  610. ypcm->voices[0] = NULL;
  611. }
  612. return 0;
  613. }
  614. static int snd_ymfpci_playback_prepare(struct snd_pcm_substream *substream)
  615. {
  616. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  617. struct snd_pcm_runtime *runtime = substream->runtime;
  618. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  619. struct snd_kcontrol *kctl;
  620. unsigned int nvoice;
  621. ypcm->period_size = runtime->period_size;
  622. ypcm->buffer_size = runtime->buffer_size;
  623. ypcm->period_pos = 0;
  624. ypcm->last_pos = 0;
  625. for (nvoice = 0; nvoice < runtime->channels; nvoice++)
  626. snd_ymfpci_pcm_init_voice(ypcm, nvoice, runtime,
  627. substream->pcm == chip->pcm);
  628. if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
  629. kctl = chip->pcm_mixer[substream->number].ctl;
  630. kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  631. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  632. }
  633. return 0;
  634. }
  635. static int snd_ymfpci_capture_hw_params(struct snd_pcm_substream *substream,
  636. struct snd_pcm_hw_params *hw_params)
  637. {
  638. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  639. }
  640. static int snd_ymfpci_capture_hw_free(struct snd_pcm_substream *substream)
  641. {
  642. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  643. /* wait, until the PCI operations are not finished */
  644. snd_ymfpci_irq_wait(chip);
  645. return snd_pcm_lib_free_pages(substream);
  646. }
  647. static int snd_ymfpci_capture_prepare(struct snd_pcm_substream *substream)
  648. {
  649. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  650. struct snd_pcm_runtime *runtime = substream->runtime;
  651. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  652. struct snd_ymfpci_capture_bank * bank;
  653. int nbank;
  654. u32 rate, format;
  655. ypcm->period_size = runtime->period_size;
  656. ypcm->buffer_size = runtime->buffer_size;
  657. ypcm->period_pos = 0;
  658. ypcm->last_pos = 0;
  659. ypcm->shift = 0;
  660. rate = ((48000 * 4096) / runtime->rate) - 1;
  661. format = 0;
  662. if (runtime->channels == 2) {
  663. format |= 2;
  664. ypcm->shift++;
  665. }
  666. if (snd_pcm_format_width(runtime->format) == 8)
  667. format |= 1;
  668. else
  669. ypcm->shift++;
  670. switch (ypcm->capture_bank_number) {
  671. case 0:
  672. snd_ymfpci_writel(chip, YDSXGR_RECFORMAT, format);
  673. snd_ymfpci_writel(chip, YDSXGR_RECSLOTSR, rate);
  674. break;
  675. case 1:
  676. snd_ymfpci_writel(chip, YDSXGR_ADCFORMAT, format);
  677. snd_ymfpci_writel(chip, YDSXGR_ADCSLOTSR, rate);
  678. break;
  679. }
  680. for (nbank = 0; nbank < 2; nbank++) {
  681. bank = chip->bank_capture[ypcm->capture_bank_number][nbank];
  682. bank->base = cpu_to_le32(runtime->dma_addr);
  683. bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);
  684. bank->start = 0;
  685. bank->num_of_loops = 0;
  686. }
  687. return 0;
  688. }
  689. static snd_pcm_uframes_t snd_ymfpci_playback_pointer(struct snd_pcm_substream *substream)
  690. {
  691. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  692. struct snd_pcm_runtime *runtime = substream->runtime;
  693. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  694. struct snd_ymfpci_voice *voice = ypcm->voices[0];
  695. if (!(ypcm->running && voice))
  696. return 0;
  697. return le32_to_cpu(voice->bank[chip->active_bank].start);
  698. }
  699. static snd_pcm_uframes_t snd_ymfpci_capture_pointer(struct snd_pcm_substream *substream)
  700. {
  701. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  702. struct snd_pcm_runtime *runtime = substream->runtime;
  703. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  704. if (!ypcm->running)
  705. return 0;
  706. return le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  707. }
  708. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip)
  709. {
  710. wait_queue_t wait;
  711. int loops = 4;
  712. while (loops-- > 0) {
  713. if ((snd_ymfpci_readl(chip, YDSXGR_MODE) & 3) == 0)
  714. continue;
  715. init_waitqueue_entry(&wait, current);
  716. add_wait_queue(&chip->interrupt_sleep, &wait);
  717. atomic_inc(&chip->interrupt_sleep_count);
  718. schedule_timeout_uninterruptible(msecs_to_jiffies(50));
  719. remove_wait_queue(&chip->interrupt_sleep, &wait);
  720. }
  721. }
  722. static irqreturn_t snd_ymfpci_interrupt(int irq, void *dev_id)
  723. {
  724. struct snd_ymfpci *chip = dev_id;
  725. u32 status, nvoice, mode;
  726. struct snd_ymfpci_voice *voice;
  727. status = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  728. if (status & 0x80000000) {
  729. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  730. spin_lock(&chip->voice_lock);
  731. for (nvoice = 0; nvoice < YDSXG_PLAYBACK_VOICES; nvoice++) {
  732. voice = &chip->voices[nvoice];
  733. if (voice->interrupt)
  734. voice->interrupt(chip, voice);
  735. }
  736. for (nvoice = 0; nvoice < YDSXG_CAPTURE_VOICES; nvoice++) {
  737. if (chip->capture_substream[nvoice])
  738. snd_ymfpci_pcm_capture_interrupt(chip->capture_substream[nvoice]);
  739. }
  740. #if 0
  741. for (nvoice = 0; nvoice < YDSXG_EFFECT_VOICES; nvoice++) {
  742. if (chip->effect_substream[nvoice])
  743. snd_ymfpci_pcm_effect_interrupt(chip->effect_substream[nvoice]);
  744. }
  745. #endif
  746. spin_unlock(&chip->voice_lock);
  747. spin_lock(&chip->reg_lock);
  748. snd_ymfpci_writel(chip, YDSXGR_STATUS, 0x80000000);
  749. mode = snd_ymfpci_readl(chip, YDSXGR_MODE) | 2;
  750. snd_ymfpci_writel(chip, YDSXGR_MODE, mode);
  751. spin_unlock(&chip->reg_lock);
  752. if (atomic_read(&chip->interrupt_sleep_count)) {
  753. atomic_set(&chip->interrupt_sleep_count, 0);
  754. wake_up(&chip->interrupt_sleep);
  755. }
  756. }
  757. status = snd_ymfpci_readw(chip, YDSXGR_INTFLAG);
  758. if (status & 1) {
  759. if (chip->timer)
  760. snd_timer_interrupt(chip->timer, chip->timer_ticks);
  761. }
  762. snd_ymfpci_writew(chip, YDSXGR_INTFLAG, status);
  763. if (chip->rawmidi)
  764. snd_mpu401_uart_interrupt(irq, chip->rawmidi->private_data);
  765. return IRQ_HANDLED;
  766. }
  767. static struct snd_pcm_hardware snd_ymfpci_playback =
  768. {
  769. .info = (SNDRV_PCM_INFO_MMAP |
  770. SNDRV_PCM_INFO_MMAP_VALID |
  771. SNDRV_PCM_INFO_INTERLEAVED |
  772. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  773. SNDRV_PCM_INFO_PAUSE |
  774. SNDRV_PCM_INFO_RESUME),
  775. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  776. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  777. .rate_min = 8000,
  778. .rate_max = 48000,
  779. .channels_min = 1,
  780. .channels_max = 2,
  781. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  782. .period_bytes_min = 64,
  783. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  784. .periods_min = 3,
  785. .periods_max = 1024,
  786. .fifo_size = 0,
  787. };
  788. static struct snd_pcm_hardware snd_ymfpci_capture =
  789. {
  790. .info = (SNDRV_PCM_INFO_MMAP |
  791. SNDRV_PCM_INFO_MMAP_VALID |
  792. SNDRV_PCM_INFO_INTERLEAVED |
  793. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  794. SNDRV_PCM_INFO_PAUSE |
  795. SNDRV_PCM_INFO_RESUME),
  796. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  797. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  798. .rate_min = 8000,
  799. .rate_max = 48000,
  800. .channels_min = 1,
  801. .channels_max = 2,
  802. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  803. .period_bytes_min = 64,
  804. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  805. .periods_min = 3,
  806. .periods_max = 1024,
  807. .fifo_size = 0,
  808. };
  809. static void snd_ymfpci_pcm_free_substream(struct snd_pcm_runtime *runtime)
  810. {
  811. kfree(runtime->private_data);
  812. }
  813. static int snd_ymfpci_playback_open_1(struct snd_pcm_substream *substream)
  814. {
  815. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  816. struct snd_pcm_runtime *runtime = substream->runtime;
  817. struct snd_ymfpci_pcm *ypcm;
  818. int err;
  819. runtime->hw = snd_ymfpci_playback;
  820. /* FIXME? True value is 256/48 = 5.33333 ms */
  821. err = snd_pcm_hw_constraint_minmax(runtime,
  822. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  823. 5334, UINT_MAX);
  824. if (err < 0)
  825. return err;
  826. err = snd_pcm_hw_rule_noresample(runtime, 48000);
  827. if (err < 0)
  828. return err;
  829. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  830. if (ypcm == NULL)
  831. return -ENOMEM;
  832. ypcm->chip = chip;
  833. ypcm->type = PLAYBACK_VOICE;
  834. ypcm->substream = substream;
  835. runtime->private_data = ypcm;
  836. runtime->private_free = snd_ymfpci_pcm_free_substream;
  837. return 0;
  838. }
  839. /* call with spinlock held */
  840. static void ymfpci_open_extension(struct snd_ymfpci *chip)
  841. {
  842. if (! chip->rear_opened) {
  843. if (! chip->spdif_opened) /* set AC3 */
  844. snd_ymfpci_writel(chip, YDSXGR_MODE,
  845. snd_ymfpci_readl(chip, YDSXGR_MODE) | (1 << 30));
  846. /* enable second codec (4CHEN) */
  847. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  848. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) | 0x0010);
  849. }
  850. }
  851. /* call with spinlock held */
  852. static void ymfpci_close_extension(struct snd_ymfpci *chip)
  853. {
  854. if (! chip->rear_opened) {
  855. if (! chip->spdif_opened)
  856. snd_ymfpci_writel(chip, YDSXGR_MODE,
  857. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~(1 << 30));
  858. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  859. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) & ~0x0010);
  860. }
  861. }
  862. static int snd_ymfpci_playback_open(struct snd_pcm_substream *substream)
  863. {
  864. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  865. struct snd_pcm_runtime *runtime = substream->runtime;
  866. struct snd_ymfpci_pcm *ypcm;
  867. int err;
  868. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  869. return err;
  870. ypcm = runtime->private_data;
  871. ypcm->output_front = 1;
  872. ypcm->output_rear = chip->mode_dup4ch ? 1 : 0;
  873. ypcm->swap_rear = 0;
  874. spin_lock_irq(&chip->reg_lock);
  875. if (ypcm->output_rear) {
  876. ymfpci_open_extension(chip);
  877. chip->rear_opened++;
  878. }
  879. spin_unlock_irq(&chip->reg_lock);
  880. return 0;
  881. }
  882. static int snd_ymfpci_playback_spdif_open(struct snd_pcm_substream *substream)
  883. {
  884. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  885. struct snd_pcm_runtime *runtime = substream->runtime;
  886. struct snd_ymfpci_pcm *ypcm;
  887. int err;
  888. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  889. return err;
  890. ypcm = runtime->private_data;
  891. ypcm->output_front = 0;
  892. ypcm->output_rear = 1;
  893. ypcm->swap_rear = 1;
  894. spin_lock_irq(&chip->reg_lock);
  895. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  896. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) | 2);
  897. ymfpci_open_extension(chip);
  898. chip->spdif_pcm_bits = chip->spdif_bits;
  899. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  900. chip->spdif_opened++;
  901. spin_unlock_irq(&chip->reg_lock);
  902. chip->spdif_pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  903. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  904. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  905. return 0;
  906. }
  907. static int snd_ymfpci_playback_4ch_open(struct snd_pcm_substream *substream)
  908. {
  909. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  910. struct snd_pcm_runtime *runtime = substream->runtime;
  911. struct snd_ymfpci_pcm *ypcm;
  912. int err;
  913. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  914. return err;
  915. ypcm = runtime->private_data;
  916. ypcm->output_front = 0;
  917. ypcm->output_rear = 1;
  918. ypcm->swap_rear = 0;
  919. spin_lock_irq(&chip->reg_lock);
  920. ymfpci_open_extension(chip);
  921. chip->rear_opened++;
  922. spin_unlock_irq(&chip->reg_lock);
  923. return 0;
  924. }
  925. static int snd_ymfpci_capture_open(struct snd_pcm_substream *substream,
  926. u32 capture_bank_number)
  927. {
  928. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  929. struct snd_pcm_runtime *runtime = substream->runtime;
  930. struct snd_ymfpci_pcm *ypcm;
  931. int err;
  932. runtime->hw = snd_ymfpci_capture;
  933. /* FIXME? True value is 256/48 = 5.33333 ms */
  934. err = snd_pcm_hw_constraint_minmax(runtime,
  935. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  936. 5334, UINT_MAX);
  937. if (err < 0)
  938. return err;
  939. err = snd_pcm_hw_rule_noresample(runtime, 48000);
  940. if (err < 0)
  941. return err;
  942. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  943. if (ypcm == NULL)
  944. return -ENOMEM;
  945. ypcm->chip = chip;
  946. ypcm->type = capture_bank_number + CAPTURE_REC;
  947. ypcm->substream = substream;
  948. ypcm->capture_bank_number = capture_bank_number;
  949. chip->capture_substream[capture_bank_number] = substream;
  950. runtime->private_data = ypcm;
  951. runtime->private_free = snd_ymfpci_pcm_free_substream;
  952. snd_ymfpci_hw_start(chip);
  953. return 0;
  954. }
  955. static int snd_ymfpci_capture_rec_open(struct snd_pcm_substream *substream)
  956. {
  957. return snd_ymfpci_capture_open(substream, 0);
  958. }
  959. static int snd_ymfpci_capture_ac97_open(struct snd_pcm_substream *substream)
  960. {
  961. return snd_ymfpci_capture_open(substream, 1);
  962. }
  963. static int snd_ymfpci_playback_close_1(struct snd_pcm_substream *substream)
  964. {
  965. return 0;
  966. }
  967. static int snd_ymfpci_playback_close(struct snd_pcm_substream *substream)
  968. {
  969. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  970. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  971. spin_lock_irq(&chip->reg_lock);
  972. if (ypcm->output_rear && chip->rear_opened > 0) {
  973. chip->rear_opened--;
  974. ymfpci_close_extension(chip);
  975. }
  976. spin_unlock_irq(&chip->reg_lock);
  977. return snd_ymfpci_playback_close_1(substream);
  978. }
  979. static int snd_ymfpci_playback_spdif_close(struct snd_pcm_substream *substream)
  980. {
  981. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  982. spin_lock_irq(&chip->reg_lock);
  983. chip->spdif_opened = 0;
  984. ymfpci_close_extension(chip);
  985. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  986. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & ~2);
  987. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  988. spin_unlock_irq(&chip->reg_lock);
  989. chip->spdif_pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  990. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  991. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  992. return snd_ymfpci_playback_close_1(substream);
  993. }
  994. static int snd_ymfpci_playback_4ch_close(struct snd_pcm_substream *substream)
  995. {
  996. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  997. spin_lock_irq(&chip->reg_lock);
  998. if (chip->rear_opened > 0) {
  999. chip->rear_opened--;
  1000. ymfpci_close_extension(chip);
  1001. }
  1002. spin_unlock_irq(&chip->reg_lock);
  1003. return snd_ymfpci_playback_close_1(substream);
  1004. }
  1005. static int snd_ymfpci_capture_close(struct snd_pcm_substream *substream)
  1006. {
  1007. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  1008. struct snd_pcm_runtime *runtime = substream->runtime;
  1009. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  1010. if (ypcm != NULL) {
  1011. chip->capture_substream[ypcm->capture_bank_number] = NULL;
  1012. snd_ymfpci_hw_stop(chip);
  1013. }
  1014. return 0;
  1015. }
  1016. static struct snd_pcm_ops snd_ymfpci_playback_ops = {
  1017. .open = snd_ymfpci_playback_open,
  1018. .close = snd_ymfpci_playback_close,
  1019. .ioctl = snd_pcm_lib_ioctl,
  1020. .hw_params = snd_ymfpci_playback_hw_params,
  1021. .hw_free = snd_ymfpci_playback_hw_free,
  1022. .prepare = snd_ymfpci_playback_prepare,
  1023. .trigger = snd_ymfpci_playback_trigger,
  1024. .pointer = snd_ymfpci_playback_pointer,
  1025. };
  1026. static struct snd_pcm_ops snd_ymfpci_capture_rec_ops = {
  1027. .open = snd_ymfpci_capture_rec_open,
  1028. .close = snd_ymfpci_capture_close,
  1029. .ioctl = snd_pcm_lib_ioctl,
  1030. .hw_params = snd_ymfpci_capture_hw_params,
  1031. .hw_free = snd_ymfpci_capture_hw_free,
  1032. .prepare = snd_ymfpci_capture_prepare,
  1033. .trigger = snd_ymfpci_capture_trigger,
  1034. .pointer = snd_ymfpci_capture_pointer,
  1035. };
  1036. int snd_ymfpci_pcm(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm)
  1037. {
  1038. struct snd_pcm *pcm;
  1039. int err;
  1040. if (rpcm)
  1041. *rpcm = NULL;
  1042. if ((err = snd_pcm_new(chip->card, "YMFPCI", device, 32, 1, &pcm)) < 0)
  1043. return err;
  1044. pcm->private_data = chip;
  1045. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_ops);
  1046. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_rec_ops);
  1047. /* global setup */
  1048. pcm->info_flags = 0;
  1049. strcpy(pcm->name, "YMFPCI");
  1050. chip->pcm = pcm;
  1051. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1052. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1053. err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1054. snd_pcm_std_chmaps, 2, 0, NULL);
  1055. if (err < 0)
  1056. return err;
  1057. if (rpcm)
  1058. *rpcm = pcm;
  1059. return 0;
  1060. }
  1061. static struct snd_pcm_ops snd_ymfpci_capture_ac97_ops = {
  1062. .open = snd_ymfpci_capture_ac97_open,
  1063. .close = snd_ymfpci_capture_close,
  1064. .ioctl = snd_pcm_lib_ioctl,
  1065. .hw_params = snd_ymfpci_capture_hw_params,
  1066. .hw_free = snd_ymfpci_capture_hw_free,
  1067. .prepare = snd_ymfpci_capture_prepare,
  1068. .trigger = snd_ymfpci_capture_trigger,
  1069. .pointer = snd_ymfpci_capture_pointer,
  1070. };
  1071. int snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm)
  1072. {
  1073. struct snd_pcm *pcm;
  1074. int err;
  1075. if (rpcm)
  1076. *rpcm = NULL;
  1077. if ((err = snd_pcm_new(chip->card, "YMFPCI - PCM2", device, 0, 1, &pcm)) < 0)
  1078. return err;
  1079. pcm->private_data = chip;
  1080. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_ac97_ops);
  1081. /* global setup */
  1082. pcm->info_flags = 0;
  1083. sprintf(pcm->name, "YMFPCI - %s",
  1084. chip->device_id == PCI_DEVICE_ID_YAMAHA_754 ? "Direct Recording" : "AC'97");
  1085. chip->pcm2 = pcm;
  1086. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1087. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1088. if (rpcm)
  1089. *rpcm = pcm;
  1090. return 0;
  1091. }
  1092. static struct snd_pcm_ops snd_ymfpci_playback_spdif_ops = {
  1093. .open = snd_ymfpci_playback_spdif_open,
  1094. .close = snd_ymfpci_playback_spdif_close,
  1095. .ioctl = snd_pcm_lib_ioctl,
  1096. .hw_params = snd_ymfpci_playback_hw_params,
  1097. .hw_free = snd_ymfpci_playback_hw_free,
  1098. .prepare = snd_ymfpci_playback_prepare,
  1099. .trigger = snd_ymfpci_playback_trigger,
  1100. .pointer = snd_ymfpci_playback_pointer,
  1101. };
  1102. int snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device,
  1103. struct snd_pcm **rpcm)
  1104. {
  1105. struct snd_pcm *pcm;
  1106. int err;
  1107. if (rpcm)
  1108. *rpcm = NULL;
  1109. if ((err = snd_pcm_new(chip->card, "YMFPCI - IEC958", device, 1, 0, &pcm)) < 0)
  1110. return err;
  1111. pcm->private_data = chip;
  1112. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_spdif_ops);
  1113. /* global setup */
  1114. pcm->info_flags = 0;
  1115. strcpy(pcm->name, "YMFPCI - IEC958");
  1116. chip->pcm_spdif = pcm;
  1117. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1118. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1119. if (rpcm)
  1120. *rpcm = pcm;
  1121. return 0;
  1122. }
  1123. static struct snd_pcm_ops snd_ymfpci_playback_4ch_ops = {
  1124. .open = snd_ymfpci_playback_4ch_open,
  1125. .close = snd_ymfpci_playback_4ch_close,
  1126. .ioctl = snd_pcm_lib_ioctl,
  1127. .hw_params = snd_ymfpci_playback_hw_params,
  1128. .hw_free = snd_ymfpci_playback_hw_free,
  1129. .prepare = snd_ymfpci_playback_prepare,
  1130. .trigger = snd_ymfpci_playback_trigger,
  1131. .pointer = snd_ymfpci_playback_pointer,
  1132. };
  1133. static const struct snd_pcm_chmap_elem surround_map[] = {
  1134. { .channels = 1,
  1135. .map = { SNDRV_CHMAP_MONO } },
  1136. { .channels = 2,
  1137. .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
  1138. { }
  1139. };
  1140. int snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device,
  1141. struct snd_pcm **rpcm)
  1142. {
  1143. struct snd_pcm *pcm;
  1144. int err;
  1145. if (rpcm)
  1146. *rpcm = NULL;
  1147. if ((err = snd_pcm_new(chip->card, "YMFPCI - Rear", device, 1, 0, &pcm)) < 0)
  1148. return err;
  1149. pcm->private_data = chip;
  1150. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_4ch_ops);
  1151. /* global setup */
  1152. pcm->info_flags = 0;
  1153. strcpy(pcm->name, "YMFPCI - Rear PCM");
  1154. chip->pcm_4ch = pcm;
  1155. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1156. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1157. err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1158. surround_map, 2, 0, NULL);
  1159. if (err < 0)
  1160. return err;
  1161. if (rpcm)
  1162. *rpcm = pcm;
  1163. return 0;
  1164. }
  1165. static int snd_ymfpci_spdif_default_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1166. {
  1167. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1168. uinfo->count = 1;
  1169. return 0;
  1170. }
  1171. static int snd_ymfpci_spdif_default_get(struct snd_kcontrol *kcontrol,
  1172. struct snd_ctl_elem_value *ucontrol)
  1173. {
  1174. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1175. spin_lock_irq(&chip->reg_lock);
  1176. ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
  1177. ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
  1178. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1179. spin_unlock_irq(&chip->reg_lock);
  1180. return 0;
  1181. }
  1182. static int snd_ymfpci_spdif_default_put(struct snd_kcontrol *kcontrol,
  1183. struct snd_ctl_elem_value *ucontrol)
  1184. {
  1185. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1186. unsigned int val;
  1187. int change;
  1188. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1189. (ucontrol->value.iec958.status[1] << 8);
  1190. spin_lock_irq(&chip->reg_lock);
  1191. change = chip->spdif_bits != val;
  1192. chip->spdif_bits = val;
  1193. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 1) && chip->pcm_spdif == NULL)
  1194. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1195. spin_unlock_irq(&chip->reg_lock);
  1196. return change;
  1197. }
  1198. static struct snd_kcontrol_new snd_ymfpci_spdif_default =
  1199. {
  1200. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1201. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1202. .info = snd_ymfpci_spdif_default_info,
  1203. .get = snd_ymfpci_spdif_default_get,
  1204. .put = snd_ymfpci_spdif_default_put
  1205. };
  1206. static int snd_ymfpci_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1207. {
  1208. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1209. uinfo->count = 1;
  1210. return 0;
  1211. }
  1212. static int snd_ymfpci_spdif_mask_get(struct snd_kcontrol *kcontrol,
  1213. struct snd_ctl_elem_value *ucontrol)
  1214. {
  1215. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1216. spin_lock_irq(&chip->reg_lock);
  1217. ucontrol->value.iec958.status[0] = 0x3e;
  1218. ucontrol->value.iec958.status[1] = 0xff;
  1219. spin_unlock_irq(&chip->reg_lock);
  1220. return 0;
  1221. }
  1222. static struct snd_kcontrol_new snd_ymfpci_spdif_mask =
  1223. {
  1224. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1225. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1226. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1227. .info = snd_ymfpci_spdif_mask_info,
  1228. .get = snd_ymfpci_spdif_mask_get,
  1229. };
  1230. static int snd_ymfpci_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1231. {
  1232. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1233. uinfo->count = 1;
  1234. return 0;
  1235. }
  1236. static int snd_ymfpci_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1237. struct snd_ctl_elem_value *ucontrol)
  1238. {
  1239. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1240. spin_lock_irq(&chip->reg_lock);
  1241. ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
  1242. ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
  1243. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1244. spin_unlock_irq(&chip->reg_lock);
  1245. return 0;
  1246. }
  1247. static int snd_ymfpci_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1248. struct snd_ctl_elem_value *ucontrol)
  1249. {
  1250. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1251. unsigned int val;
  1252. int change;
  1253. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1254. (ucontrol->value.iec958.status[1] << 8);
  1255. spin_lock_irq(&chip->reg_lock);
  1256. change = chip->spdif_pcm_bits != val;
  1257. chip->spdif_pcm_bits = val;
  1258. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 2))
  1259. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  1260. spin_unlock_irq(&chip->reg_lock);
  1261. return change;
  1262. }
  1263. static struct snd_kcontrol_new snd_ymfpci_spdif_stream =
  1264. {
  1265. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1266. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1267. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1268. .info = snd_ymfpci_spdif_stream_info,
  1269. .get = snd_ymfpci_spdif_stream_get,
  1270. .put = snd_ymfpci_spdif_stream_put
  1271. };
  1272. static int snd_ymfpci_drec_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *info)
  1273. {
  1274. static const char *const texts[3] = {"AC'97", "IEC958", "ZV Port"};
  1275. return snd_ctl_enum_info(info, 1, 3, texts);
  1276. }
  1277. static int snd_ymfpci_drec_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1278. {
  1279. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1280. u16 reg;
  1281. spin_lock_irq(&chip->reg_lock);
  1282. reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1283. spin_unlock_irq(&chip->reg_lock);
  1284. if (!(reg & 0x100))
  1285. value->value.enumerated.item[0] = 0;
  1286. else
  1287. value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0);
  1288. return 0;
  1289. }
  1290. static int snd_ymfpci_drec_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1291. {
  1292. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1293. u16 reg, old_reg;
  1294. spin_lock_irq(&chip->reg_lock);
  1295. old_reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1296. if (value->value.enumerated.item[0] == 0)
  1297. reg = old_reg & ~0x100;
  1298. else
  1299. reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9);
  1300. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg);
  1301. spin_unlock_irq(&chip->reg_lock);
  1302. return reg != old_reg;
  1303. }
  1304. static struct snd_kcontrol_new snd_ymfpci_drec_source = {
  1305. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1306. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1307. .name = "Direct Recording Source",
  1308. .info = snd_ymfpci_drec_source_info,
  1309. .get = snd_ymfpci_drec_source_get,
  1310. .put = snd_ymfpci_drec_source_put
  1311. };
  1312. /*
  1313. * Mixer controls
  1314. */
  1315. #define YMFPCI_SINGLE(xname, xindex, reg, shift) \
  1316. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1317. .info = snd_ymfpci_info_single, \
  1318. .get = snd_ymfpci_get_single, .put = snd_ymfpci_put_single, \
  1319. .private_value = ((reg) | ((shift) << 16)) }
  1320. #define snd_ymfpci_info_single snd_ctl_boolean_mono_info
  1321. static int snd_ymfpci_get_single(struct snd_kcontrol *kcontrol,
  1322. struct snd_ctl_elem_value *ucontrol)
  1323. {
  1324. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1325. int reg = kcontrol->private_value & 0xffff;
  1326. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1327. unsigned int mask = 1;
  1328. switch (reg) {
  1329. case YDSXGR_SPDIFOUTCTRL: break;
  1330. case YDSXGR_SPDIFINCTRL: break;
  1331. default: return -EINVAL;
  1332. }
  1333. ucontrol->value.integer.value[0] =
  1334. (snd_ymfpci_readl(chip, reg) >> shift) & mask;
  1335. return 0;
  1336. }
  1337. static int snd_ymfpci_put_single(struct snd_kcontrol *kcontrol,
  1338. struct snd_ctl_elem_value *ucontrol)
  1339. {
  1340. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1341. int reg = kcontrol->private_value & 0xffff;
  1342. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1343. unsigned int mask = 1;
  1344. int change;
  1345. unsigned int val, oval;
  1346. switch (reg) {
  1347. case YDSXGR_SPDIFOUTCTRL: break;
  1348. case YDSXGR_SPDIFINCTRL: break;
  1349. default: return -EINVAL;
  1350. }
  1351. val = (ucontrol->value.integer.value[0] & mask);
  1352. val <<= shift;
  1353. spin_lock_irq(&chip->reg_lock);
  1354. oval = snd_ymfpci_readl(chip, reg);
  1355. val = (oval & ~(mask << shift)) | val;
  1356. change = val != oval;
  1357. snd_ymfpci_writel(chip, reg, val);
  1358. spin_unlock_irq(&chip->reg_lock);
  1359. return change;
  1360. }
  1361. static const DECLARE_TLV_DB_LINEAR(db_scale_native, TLV_DB_GAIN_MUTE, 0);
  1362. #define YMFPCI_DOUBLE(xname, xindex, reg) \
  1363. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1364. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
  1365. .info = snd_ymfpci_info_double, \
  1366. .get = snd_ymfpci_get_double, .put = snd_ymfpci_put_double, \
  1367. .private_value = reg, \
  1368. .tlv = { .p = db_scale_native } }
  1369. static int snd_ymfpci_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1370. {
  1371. unsigned int reg = kcontrol->private_value;
  1372. if (reg < 0x80 || reg >= 0xc0)
  1373. return -EINVAL;
  1374. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1375. uinfo->count = 2;
  1376. uinfo->value.integer.min = 0;
  1377. uinfo->value.integer.max = 16383;
  1378. return 0;
  1379. }
  1380. static int snd_ymfpci_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1381. {
  1382. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1383. unsigned int reg = kcontrol->private_value;
  1384. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1385. unsigned int val;
  1386. if (reg < 0x80 || reg >= 0xc0)
  1387. return -EINVAL;
  1388. spin_lock_irq(&chip->reg_lock);
  1389. val = snd_ymfpci_readl(chip, reg);
  1390. spin_unlock_irq(&chip->reg_lock);
  1391. ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
  1392. ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
  1393. return 0;
  1394. }
  1395. static int snd_ymfpci_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1396. {
  1397. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1398. unsigned int reg = kcontrol->private_value;
  1399. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1400. int change;
  1401. unsigned int val1, val2, oval;
  1402. if (reg < 0x80 || reg >= 0xc0)
  1403. return -EINVAL;
  1404. val1 = ucontrol->value.integer.value[0] & mask;
  1405. val2 = ucontrol->value.integer.value[1] & mask;
  1406. val1 <<= shift_left;
  1407. val2 <<= shift_right;
  1408. spin_lock_irq(&chip->reg_lock);
  1409. oval = snd_ymfpci_readl(chip, reg);
  1410. val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1411. change = val1 != oval;
  1412. snd_ymfpci_writel(chip, reg, val1);
  1413. spin_unlock_irq(&chip->reg_lock);
  1414. return change;
  1415. }
  1416. static int snd_ymfpci_put_nativedacvol(struct snd_kcontrol *kcontrol,
  1417. struct snd_ctl_elem_value *ucontrol)
  1418. {
  1419. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1420. unsigned int reg = YDSXGR_NATIVEDACOUTVOL;
  1421. unsigned int reg2 = YDSXGR_BUF441OUTVOL;
  1422. int change;
  1423. unsigned int value, oval;
  1424. value = ucontrol->value.integer.value[0] & 0x3fff;
  1425. value |= (ucontrol->value.integer.value[1] & 0x3fff) << 16;
  1426. spin_lock_irq(&chip->reg_lock);
  1427. oval = snd_ymfpci_readl(chip, reg);
  1428. change = value != oval;
  1429. snd_ymfpci_writel(chip, reg, value);
  1430. snd_ymfpci_writel(chip, reg2, value);
  1431. spin_unlock_irq(&chip->reg_lock);
  1432. return change;
  1433. }
  1434. /*
  1435. * 4ch duplication
  1436. */
  1437. #define snd_ymfpci_info_dup4ch snd_ctl_boolean_mono_info
  1438. static int snd_ymfpci_get_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1439. {
  1440. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1441. ucontrol->value.integer.value[0] = chip->mode_dup4ch;
  1442. return 0;
  1443. }
  1444. static int snd_ymfpci_put_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1445. {
  1446. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1447. int change;
  1448. change = (ucontrol->value.integer.value[0] != chip->mode_dup4ch);
  1449. if (change)
  1450. chip->mode_dup4ch = !!ucontrol->value.integer.value[0];
  1451. return change;
  1452. }
  1453. static struct snd_kcontrol_new snd_ymfpci_dup4ch = {
  1454. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1455. .name = "4ch Duplication",
  1456. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1457. .info = snd_ymfpci_info_dup4ch,
  1458. .get = snd_ymfpci_get_dup4ch,
  1459. .put = snd_ymfpci_put_dup4ch,
  1460. };
  1461. static struct snd_kcontrol_new snd_ymfpci_controls[] = {
  1462. {
  1463. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1464. .name = "Wave Playback Volume",
  1465. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1466. SNDRV_CTL_ELEM_ACCESS_TLV_READ,
  1467. .info = snd_ymfpci_info_double,
  1468. .get = snd_ymfpci_get_double,
  1469. .put = snd_ymfpci_put_nativedacvol,
  1470. .private_value = YDSXGR_NATIVEDACOUTVOL,
  1471. .tlv = { .p = db_scale_native },
  1472. },
  1473. YMFPCI_DOUBLE("Wave Capture Volume", 0, YDSXGR_NATIVEDACLOOPVOL),
  1474. YMFPCI_DOUBLE("Digital Capture Volume", 0, YDSXGR_NATIVEDACINVOL),
  1475. YMFPCI_DOUBLE("Digital Capture Volume", 1, YDSXGR_NATIVEADCINVOL),
  1476. YMFPCI_DOUBLE("ADC Playback Volume", 0, YDSXGR_PRIADCOUTVOL),
  1477. YMFPCI_DOUBLE("ADC Capture Volume", 0, YDSXGR_PRIADCLOOPVOL),
  1478. YMFPCI_DOUBLE("ADC Playback Volume", 1, YDSXGR_SECADCOUTVOL),
  1479. YMFPCI_DOUBLE("ADC Capture Volume", 1, YDSXGR_SECADCLOOPVOL),
  1480. YMFPCI_DOUBLE("FM Legacy Playback Volume", 0, YDSXGR_LEGACYOUTVOL),
  1481. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ", PLAYBACK,VOLUME), 0, YDSXGR_ZVOUTVOL),
  1482. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("", CAPTURE,VOLUME), 0, YDSXGR_ZVLOOPVOL),
  1483. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ",PLAYBACK,VOLUME), 1, YDSXGR_SPDIFOUTVOL),
  1484. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,VOLUME), 1, YDSXGR_SPDIFLOOPVOL),
  1485. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), 0, YDSXGR_SPDIFOUTCTRL, 0),
  1486. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, YDSXGR_SPDIFINCTRL, 0),
  1487. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("Loop",NONE,NONE), 0, YDSXGR_SPDIFINCTRL, 4),
  1488. };
  1489. /*
  1490. * GPIO
  1491. */
  1492. static int snd_ymfpci_get_gpio_out(struct snd_ymfpci *chip, int pin)
  1493. {
  1494. u16 reg, mode;
  1495. unsigned long flags;
  1496. spin_lock_irqsave(&chip->reg_lock, flags);
  1497. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1498. reg &= ~(1 << (pin + 8));
  1499. reg |= (1 << pin);
  1500. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1501. /* set the level mode for input line */
  1502. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOTYPECONFIG);
  1503. mode &= ~(3 << (pin * 2));
  1504. snd_ymfpci_writew(chip, YDSXGR_GPIOTYPECONFIG, mode);
  1505. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1506. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOINSTATUS);
  1507. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1508. return (mode >> pin) & 1;
  1509. }
  1510. static int snd_ymfpci_set_gpio_out(struct snd_ymfpci *chip, int pin, int enable)
  1511. {
  1512. u16 reg;
  1513. unsigned long flags;
  1514. spin_lock_irqsave(&chip->reg_lock, flags);
  1515. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1516. reg &= ~(1 << pin);
  1517. reg &= ~(1 << (pin + 8));
  1518. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1519. snd_ymfpci_writew(chip, YDSXGR_GPIOOUTCTRL, enable << pin);
  1520. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1521. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1522. return 0;
  1523. }
  1524. #define snd_ymfpci_gpio_sw_info snd_ctl_boolean_mono_info
  1525. static int snd_ymfpci_gpio_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1526. {
  1527. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1528. int pin = (int)kcontrol->private_value;
  1529. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1530. return 0;
  1531. }
  1532. static int snd_ymfpci_gpio_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1533. {
  1534. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1535. int pin = (int)kcontrol->private_value;
  1536. if (snd_ymfpci_get_gpio_out(chip, pin) != ucontrol->value.integer.value[0]) {
  1537. snd_ymfpci_set_gpio_out(chip, pin, !!ucontrol->value.integer.value[0]);
  1538. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1539. return 1;
  1540. }
  1541. return 0;
  1542. }
  1543. static struct snd_kcontrol_new snd_ymfpci_rear_shared = {
  1544. .name = "Shared Rear/Line-In Switch",
  1545. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1546. .info = snd_ymfpci_gpio_sw_info,
  1547. .get = snd_ymfpci_gpio_sw_get,
  1548. .put = snd_ymfpci_gpio_sw_put,
  1549. .private_value = 2,
  1550. };
  1551. /*
  1552. * PCM voice volume
  1553. */
  1554. static int snd_ymfpci_pcm_vol_info(struct snd_kcontrol *kcontrol,
  1555. struct snd_ctl_elem_info *uinfo)
  1556. {
  1557. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1558. uinfo->count = 2;
  1559. uinfo->value.integer.min = 0;
  1560. uinfo->value.integer.max = 0x8000;
  1561. return 0;
  1562. }
  1563. static int snd_ymfpci_pcm_vol_get(struct snd_kcontrol *kcontrol,
  1564. struct snd_ctl_elem_value *ucontrol)
  1565. {
  1566. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1567. unsigned int subs = kcontrol->id.subdevice;
  1568. ucontrol->value.integer.value[0] = chip->pcm_mixer[subs].left;
  1569. ucontrol->value.integer.value[1] = chip->pcm_mixer[subs].right;
  1570. return 0;
  1571. }
  1572. static int snd_ymfpci_pcm_vol_put(struct snd_kcontrol *kcontrol,
  1573. struct snd_ctl_elem_value *ucontrol)
  1574. {
  1575. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1576. unsigned int subs = kcontrol->id.subdevice;
  1577. struct snd_pcm_substream *substream;
  1578. unsigned long flags;
  1579. if (ucontrol->value.integer.value[0] != chip->pcm_mixer[subs].left ||
  1580. ucontrol->value.integer.value[1] != chip->pcm_mixer[subs].right) {
  1581. chip->pcm_mixer[subs].left = ucontrol->value.integer.value[0];
  1582. chip->pcm_mixer[subs].right = ucontrol->value.integer.value[1];
  1583. if (chip->pcm_mixer[subs].left > 0x8000)
  1584. chip->pcm_mixer[subs].left = 0x8000;
  1585. if (chip->pcm_mixer[subs].right > 0x8000)
  1586. chip->pcm_mixer[subs].right = 0x8000;
  1587. substream = (struct snd_pcm_substream *)kcontrol->private_value;
  1588. spin_lock_irqsave(&chip->voice_lock, flags);
  1589. if (substream->runtime && substream->runtime->private_data) {
  1590. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  1591. if (!ypcm->use_441_slot)
  1592. ypcm->update_pcm_vol = 2;
  1593. }
  1594. spin_unlock_irqrestore(&chip->voice_lock, flags);
  1595. return 1;
  1596. }
  1597. return 0;
  1598. }
  1599. static struct snd_kcontrol_new snd_ymfpci_pcm_volume = {
  1600. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1601. .name = "PCM Playback Volume",
  1602. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1603. SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1604. .info = snd_ymfpci_pcm_vol_info,
  1605. .get = snd_ymfpci_pcm_vol_get,
  1606. .put = snd_ymfpci_pcm_vol_put,
  1607. };
  1608. /*
  1609. * Mixer routines
  1610. */
  1611. static void snd_ymfpci_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1612. {
  1613. struct snd_ymfpci *chip = bus->private_data;
  1614. chip->ac97_bus = NULL;
  1615. }
  1616. static void snd_ymfpci_mixer_free_ac97(struct snd_ac97 *ac97)
  1617. {
  1618. struct snd_ymfpci *chip = ac97->private_data;
  1619. chip->ac97 = NULL;
  1620. }
  1621. int snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch)
  1622. {
  1623. struct snd_ac97_template ac97;
  1624. struct snd_kcontrol *kctl;
  1625. struct snd_pcm_substream *substream;
  1626. unsigned int idx;
  1627. int err;
  1628. static struct snd_ac97_bus_ops ops = {
  1629. .write = snd_ymfpci_codec_write,
  1630. .read = snd_ymfpci_codec_read,
  1631. };
  1632. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1633. return err;
  1634. chip->ac97_bus->private_free = snd_ymfpci_mixer_free_ac97_bus;
  1635. chip->ac97_bus->no_vra = 1; /* YMFPCI doesn't need VRA */
  1636. memset(&ac97, 0, sizeof(ac97));
  1637. ac97.private_data = chip;
  1638. ac97.private_free = snd_ymfpci_mixer_free_ac97;
  1639. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1640. return err;
  1641. /* to be sure */
  1642. snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS,
  1643. AC97_EA_VRA|AC97_EA_VRM, 0);
  1644. for (idx = 0; idx < ARRAY_SIZE(snd_ymfpci_controls); idx++) {
  1645. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_controls[idx], chip))) < 0)
  1646. return err;
  1647. }
  1648. if (chip->ac97->ext_id & AC97_EI_SDAC) {
  1649. kctl = snd_ctl_new1(&snd_ymfpci_dup4ch, chip);
  1650. err = snd_ctl_add(chip->card, kctl);
  1651. if (err < 0)
  1652. return err;
  1653. }
  1654. /* add S/PDIF control */
  1655. if (snd_BUG_ON(!chip->pcm_spdif))
  1656. return -ENXIO;
  1657. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_default, chip))) < 0)
  1658. return err;
  1659. kctl->id.device = chip->pcm_spdif->device;
  1660. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_mask, chip))) < 0)
  1661. return err;
  1662. kctl->id.device = chip->pcm_spdif->device;
  1663. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_stream, chip))) < 0)
  1664. return err;
  1665. kctl->id.device = chip->pcm_spdif->device;
  1666. chip->spdif_pcm_ctl = kctl;
  1667. /* direct recording source */
  1668. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  1669. (err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_drec_source, chip))) < 0)
  1670. return err;
  1671. /*
  1672. * shared rear/line-in
  1673. */
  1674. if (rear_switch) {
  1675. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_rear_shared, chip))) < 0)
  1676. return err;
  1677. }
  1678. /* per-voice volume */
  1679. substream = chip->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  1680. for (idx = 0; idx < 32; ++idx) {
  1681. kctl = snd_ctl_new1(&snd_ymfpci_pcm_volume, chip);
  1682. if (!kctl)
  1683. return -ENOMEM;
  1684. kctl->id.device = chip->pcm->device;
  1685. kctl->id.subdevice = idx;
  1686. kctl->private_value = (unsigned long)substream;
  1687. if ((err = snd_ctl_add(chip->card, kctl)) < 0)
  1688. return err;
  1689. chip->pcm_mixer[idx].left = 0x8000;
  1690. chip->pcm_mixer[idx].right = 0x8000;
  1691. chip->pcm_mixer[idx].ctl = kctl;
  1692. substream = substream->next;
  1693. }
  1694. return 0;
  1695. }
  1696. /*
  1697. * timer
  1698. */
  1699. static int snd_ymfpci_timer_start(struct snd_timer *timer)
  1700. {
  1701. struct snd_ymfpci *chip;
  1702. unsigned long flags;
  1703. unsigned int count;
  1704. chip = snd_timer_chip(timer);
  1705. spin_lock_irqsave(&chip->reg_lock, flags);
  1706. if (timer->sticks > 1) {
  1707. chip->timer_ticks = timer->sticks;
  1708. count = timer->sticks - 1;
  1709. } else {
  1710. /*
  1711. * Divisor 1 is not allowed; fake it by using divisor 2 and
  1712. * counting two ticks for each interrupt.
  1713. */
  1714. chip->timer_ticks = 2;
  1715. count = 2 - 1;
  1716. }
  1717. snd_ymfpci_writew(chip, YDSXGR_TIMERCOUNT, count);
  1718. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x03);
  1719. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1720. return 0;
  1721. }
  1722. static int snd_ymfpci_timer_stop(struct snd_timer *timer)
  1723. {
  1724. struct snd_ymfpci *chip;
  1725. unsigned long flags;
  1726. chip = snd_timer_chip(timer);
  1727. spin_lock_irqsave(&chip->reg_lock, flags);
  1728. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x00);
  1729. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1730. return 0;
  1731. }
  1732. static int snd_ymfpci_timer_precise_resolution(struct snd_timer *timer,
  1733. unsigned long *num, unsigned long *den)
  1734. {
  1735. *num = 1;
  1736. *den = 96000;
  1737. return 0;
  1738. }
  1739. static struct snd_timer_hardware snd_ymfpci_timer_hw = {
  1740. .flags = SNDRV_TIMER_HW_AUTO,
  1741. .resolution = 10417, /* 1 / 96 kHz = 10.41666...us */
  1742. .ticks = 0x10000,
  1743. .start = snd_ymfpci_timer_start,
  1744. .stop = snd_ymfpci_timer_stop,
  1745. .precise_resolution = snd_ymfpci_timer_precise_resolution,
  1746. };
  1747. int snd_ymfpci_timer(struct snd_ymfpci *chip, int device)
  1748. {
  1749. struct snd_timer *timer = NULL;
  1750. struct snd_timer_id tid;
  1751. int err;
  1752. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1753. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1754. tid.card = chip->card->number;
  1755. tid.device = device;
  1756. tid.subdevice = 0;
  1757. if ((err = snd_timer_new(chip->card, "YMFPCI", &tid, &timer)) >= 0) {
  1758. strcpy(timer->name, "YMFPCI timer");
  1759. timer->private_data = chip;
  1760. timer->hw = snd_ymfpci_timer_hw;
  1761. }
  1762. chip->timer = timer;
  1763. return err;
  1764. }
  1765. /*
  1766. * proc interface
  1767. */
  1768. static void snd_ymfpci_proc_read(struct snd_info_entry *entry,
  1769. struct snd_info_buffer *buffer)
  1770. {
  1771. struct snd_ymfpci *chip = entry->private_data;
  1772. int i;
  1773. snd_iprintf(buffer, "YMFPCI\n\n");
  1774. for (i = 0; i <= YDSXGR_WORKBASE; i += 4)
  1775. snd_iprintf(buffer, "%04x: %04x\n", i, snd_ymfpci_readl(chip, i));
  1776. }
  1777. static int snd_ymfpci_proc_init(struct snd_card *card, struct snd_ymfpci *chip)
  1778. {
  1779. struct snd_info_entry *entry;
  1780. if (! snd_card_proc_new(card, "ymfpci", &entry))
  1781. snd_info_set_text_ops(entry, chip, snd_ymfpci_proc_read);
  1782. return 0;
  1783. }
  1784. /*
  1785. * initialization routines
  1786. */
  1787. static void snd_ymfpci_aclink_reset(struct pci_dev * pci)
  1788. {
  1789. u8 cmd;
  1790. pci_read_config_byte(pci, PCIR_DSXG_CTRL, &cmd);
  1791. #if 0 // force to reset
  1792. if (cmd & 0x03) {
  1793. #endif
  1794. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1795. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd | 0x03);
  1796. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1797. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL1, 0);
  1798. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL2, 0);
  1799. #if 0
  1800. }
  1801. #endif
  1802. }
  1803. static void snd_ymfpci_enable_dsp(struct snd_ymfpci *chip)
  1804. {
  1805. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000001);
  1806. }
  1807. static void snd_ymfpci_disable_dsp(struct snd_ymfpci *chip)
  1808. {
  1809. u32 val;
  1810. int timeout = 1000;
  1811. val = snd_ymfpci_readl(chip, YDSXGR_CONFIG);
  1812. if (val)
  1813. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000000);
  1814. while (timeout-- > 0) {
  1815. val = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  1816. if ((val & 0x00000002) == 0)
  1817. break;
  1818. }
  1819. }
  1820. static int snd_ymfpci_request_firmware(struct snd_ymfpci *chip)
  1821. {
  1822. int err, is_1e;
  1823. const char *name;
  1824. err = request_firmware(&chip->dsp_microcode, "yamaha/ds1_dsp.fw",
  1825. &chip->pci->dev);
  1826. if (err >= 0) {
  1827. if (chip->dsp_microcode->size != YDSXG_DSPLENGTH) {
  1828. dev_err(chip->card->dev,
  1829. "DSP microcode has wrong size\n");
  1830. err = -EINVAL;
  1831. }
  1832. }
  1833. if (err < 0)
  1834. return err;
  1835. is_1e = chip->device_id == PCI_DEVICE_ID_YAMAHA_724F ||
  1836. chip->device_id == PCI_DEVICE_ID_YAMAHA_740C ||
  1837. chip->device_id == PCI_DEVICE_ID_YAMAHA_744 ||
  1838. chip->device_id == PCI_DEVICE_ID_YAMAHA_754;
  1839. name = is_1e ? "yamaha/ds1e_ctrl.fw" : "yamaha/ds1_ctrl.fw";
  1840. err = request_firmware(&chip->controller_microcode, name,
  1841. &chip->pci->dev);
  1842. if (err >= 0) {
  1843. if (chip->controller_microcode->size != YDSXG_CTRLLENGTH) {
  1844. dev_err(chip->card->dev,
  1845. "controller microcode has wrong size\n");
  1846. err = -EINVAL;
  1847. }
  1848. }
  1849. if (err < 0)
  1850. return err;
  1851. return 0;
  1852. }
  1853. MODULE_FIRMWARE("yamaha/ds1_dsp.fw");
  1854. MODULE_FIRMWARE("yamaha/ds1_ctrl.fw");
  1855. MODULE_FIRMWARE("yamaha/ds1e_ctrl.fw");
  1856. static void snd_ymfpci_download_image(struct snd_ymfpci *chip)
  1857. {
  1858. int i;
  1859. u16 ctrl;
  1860. const __le32 *inst;
  1861. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x00000000);
  1862. snd_ymfpci_disable_dsp(chip);
  1863. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00010000);
  1864. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00000000);
  1865. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, 0x00000000);
  1866. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT, 0x00000000);
  1867. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0x00000000);
  1868. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0x00000000);
  1869. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0x00000000);
  1870. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1871. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1872. /* setup DSP instruction code */
  1873. inst = (const __le32 *)chip->dsp_microcode->data;
  1874. for (i = 0; i < YDSXG_DSPLENGTH / 4; i++)
  1875. snd_ymfpci_writel(chip, YDSXGR_DSPINSTRAM + (i << 2),
  1876. le32_to_cpu(inst[i]));
  1877. /* setup control instruction code */
  1878. inst = (const __le32 *)chip->controller_microcode->data;
  1879. for (i = 0; i < YDSXG_CTRLLENGTH / 4; i++)
  1880. snd_ymfpci_writel(chip, YDSXGR_CTRLINSTRAM + (i << 2),
  1881. le32_to_cpu(inst[i]));
  1882. snd_ymfpci_enable_dsp(chip);
  1883. }
  1884. static int snd_ymfpci_memalloc(struct snd_ymfpci *chip)
  1885. {
  1886. long size, playback_ctrl_size;
  1887. int voice, bank, reg;
  1888. u8 *ptr;
  1889. dma_addr_t ptr_addr;
  1890. playback_ctrl_size = 4 + 4 * YDSXG_PLAYBACK_VOICES;
  1891. chip->bank_size_playback = snd_ymfpci_readl(chip, YDSXGR_PLAYCTRLSIZE) << 2;
  1892. chip->bank_size_capture = snd_ymfpci_readl(chip, YDSXGR_RECCTRLSIZE) << 2;
  1893. chip->bank_size_effect = snd_ymfpci_readl(chip, YDSXGR_EFFCTRLSIZE) << 2;
  1894. chip->work_size = YDSXG_DEFAULT_WORK_SIZE;
  1895. size = ALIGN(playback_ctrl_size, 0x100) +
  1896. ALIGN(chip->bank_size_playback * 2 * YDSXG_PLAYBACK_VOICES, 0x100) +
  1897. ALIGN(chip->bank_size_capture * 2 * YDSXG_CAPTURE_VOICES, 0x100) +
  1898. ALIGN(chip->bank_size_effect * 2 * YDSXG_EFFECT_VOICES, 0x100) +
  1899. chip->work_size;
  1900. /* work_ptr must be aligned to 256 bytes, but it's already
  1901. covered with the kernel page allocation mechanism */
  1902. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1903. size, &chip->work_ptr) < 0)
  1904. return -ENOMEM;
  1905. ptr = chip->work_ptr.area;
  1906. ptr_addr = chip->work_ptr.addr;
  1907. memset(ptr, 0, size); /* for sure */
  1908. chip->bank_base_playback = ptr;
  1909. chip->bank_base_playback_addr = ptr_addr;
  1910. chip->ctrl_playback = (u32 *)ptr;
  1911. chip->ctrl_playback[0] = cpu_to_le32(YDSXG_PLAYBACK_VOICES);
  1912. ptr += ALIGN(playback_ctrl_size, 0x100);
  1913. ptr_addr += ALIGN(playback_ctrl_size, 0x100);
  1914. for (voice = 0; voice < YDSXG_PLAYBACK_VOICES; voice++) {
  1915. chip->voices[voice].number = voice;
  1916. chip->voices[voice].bank = (struct snd_ymfpci_playback_bank *)ptr;
  1917. chip->voices[voice].bank_addr = ptr_addr;
  1918. for (bank = 0; bank < 2; bank++) {
  1919. chip->bank_playback[voice][bank] = (struct snd_ymfpci_playback_bank *)ptr;
  1920. ptr += chip->bank_size_playback;
  1921. ptr_addr += chip->bank_size_playback;
  1922. }
  1923. }
  1924. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1925. ptr_addr = ALIGN(ptr_addr, 0x100);
  1926. chip->bank_base_capture = ptr;
  1927. chip->bank_base_capture_addr = ptr_addr;
  1928. for (voice = 0; voice < YDSXG_CAPTURE_VOICES; voice++)
  1929. for (bank = 0; bank < 2; bank++) {
  1930. chip->bank_capture[voice][bank] = (struct snd_ymfpci_capture_bank *)ptr;
  1931. ptr += chip->bank_size_capture;
  1932. ptr_addr += chip->bank_size_capture;
  1933. }
  1934. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1935. ptr_addr = ALIGN(ptr_addr, 0x100);
  1936. chip->bank_base_effect = ptr;
  1937. chip->bank_base_effect_addr = ptr_addr;
  1938. for (voice = 0; voice < YDSXG_EFFECT_VOICES; voice++)
  1939. for (bank = 0; bank < 2; bank++) {
  1940. chip->bank_effect[voice][bank] = (struct snd_ymfpci_effect_bank *)ptr;
  1941. ptr += chip->bank_size_effect;
  1942. ptr_addr += chip->bank_size_effect;
  1943. }
  1944. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1945. ptr_addr = ALIGN(ptr_addr, 0x100);
  1946. chip->work_base = ptr;
  1947. chip->work_base_addr = ptr_addr;
  1948. snd_BUG_ON(ptr + chip->work_size !=
  1949. chip->work_ptr.area + chip->work_ptr.bytes);
  1950. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, chip->bank_base_playback_addr);
  1951. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, chip->bank_base_capture_addr);
  1952. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, chip->bank_base_effect_addr);
  1953. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, chip->work_base_addr);
  1954. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, chip->work_size >> 2);
  1955. /* S/PDIF output initialization */
  1956. chip->spdif_bits = chip->spdif_pcm_bits = SNDRV_PCM_DEFAULT_CON_SPDIF & 0xffff;
  1957. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL, 0);
  1958. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1959. /* S/PDIF input initialization */
  1960. snd_ymfpci_writew(chip, YDSXGR_SPDIFINCTRL, 0);
  1961. /* digital mixer setup */
  1962. for (reg = 0x80; reg < 0xc0; reg += 4)
  1963. snd_ymfpci_writel(chip, reg, 0);
  1964. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff);
  1965. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0x3fff3fff);
  1966. snd_ymfpci_writel(chip, YDSXGR_ZVOUTVOL, 0x3fff3fff);
  1967. snd_ymfpci_writel(chip, YDSXGR_SPDIFOUTVOL, 0x3fff3fff);
  1968. snd_ymfpci_writel(chip, YDSXGR_NATIVEADCINVOL, 0x3fff3fff);
  1969. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACINVOL, 0x3fff3fff);
  1970. snd_ymfpci_writel(chip, YDSXGR_PRIADCLOOPVOL, 0x3fff3fff);
  1971. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0x3fff3fff);
  1972. return 0;
  1973. }
  1974. static int snd_ymfpci_free(struct snd_ymfpci *chip)
  1975. {
  1976. u16 ctrl;
  1977. if (snd_BUG_ON(!chip))
  1978. return -EINVAL;
  1979. if (chip->res_reg_area) { /* don't touch busy hardware */
  1980. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1981. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  1982. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0);
  1983. snd_ymfpci_writel(chip, YDSXGR_STATUS, ~0);
  1984. snd_ymfpci_disable_dsp(chip);
  1985. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0);
  1986. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0);
  1987. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0);
  1988. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, 0);
  1989. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, 0);
  1990. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1991. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1992. }
  1993. snd_ymfpci_ac3_done(chip);
  1994. /* Set PCI device to D3 state */
  1995. #if 0
  1996. /* FIXME: temporarily disabled, otherwise we cannot fire up
  1997. * the chip again unless reboot. ACPI bug?
  1998. */
  1999. pci_set_power_state(chip->pci, PCI_D3hot);
  2000. #endif
  2001. #ifdef CONFIG_PM_SLEEP
  2002. kfree(chip->saved_regs);
  2003. #endif
  2004. if (chip->irq >= 0)
  2005. free_irq(chip->irq, chip);
  2006. release_and_free_resource(chip->mpu_res);
  2007. release_and_free_resource(chip->fm_res);
  2008. snd_ymfpci_free_gameport(chip);
  2009. if (chip->reg_area_virt)
  2010. iounmap(chip->reg_area_virt);
  2011. if (chip->work_ptr.area)
  2012. snd_dma_free_pages(&chip->work_ptr);
  2013. release_and_free_resource(chip->res_reg_area);
  2014. pci_write_config_word(chip->pci, 0x40, chip->old_legacy_ctrl);
  2015. pci_disable_device(chip->pci);
  2016. release_firmware(chip->dsp_microcode);
  2017. release_firmware(chip->controller_microcode);
  2018. kfree(chip);
  2019. return 0;
  2020. }
  2021. static int snd_ymfpci_dev_free(struct snd_device *device)
  2022. {
  2023. struct snd_ymfpci *chip = device->device_data;
  2024. return snd_ymfpci_free(chip);
  2025. }
  2026. #ifdef CONFIG_PM_SLEEP
  2027. static int saved_regs_index[] = {
  2028. /* spdif */
  2029. YDSXGR_SPDIFOUTCTRL,
  2030. YDSXGR_SPDIFOUTSTATUS,
  2031. YDSXGR_SPDIFINCTRL,
  2032. /* volumes */
  2033. YDSXGR_PRIADCLOOPVOL,
  2034. YDSXGR_NATIVEDACINVOL,
  2035. YDSXGR_NATIVEDACOUTVOL,
  2036. YDSXGR_BUF441OUTVOL,
  2037. YDSXGR_NATIVEADCINVOL,
  2038. YDSXGR_SPDIFLOOPVOL,
  2039. YDSXGR_SPDIFOUTVOL,
  2040. YDSXGR_ZVOUTVOL,
  2041. YDSXGR_LEGACYOUTVOL,
  2042. /* address bases */
  2043. YDSXGR_PLAYCTRLBASE,
  2044. YDSXGR_RECCTRLBASE,
  2045. YDSXGR_EFFCTRLBASE,
  2046. YDSXGR_WORKBASE,
  2047. /* capture set up */
  2048. YDSXGR_MAPOFREC,
  2049. YDSXGR_RECFORMAT,
  2050. YDSXGR_RECSLOTSR,
  2051. YDSXGR_ADCFORMAT,
  2052. YDSXGR_ADCSLOTSR,
  2053. };
  2054. #define YDSXGR_NUM_SAVED_REGS ARRAY_SIZE(saved_regs_index)
  2055. static int snd_ymfpci_suspend(struct device *dev)
  2056. {
  2057. struct pci_dev *pci = to_pci_dev(dev);
  2058. struct snd_card *card = dev_get_drvdata(dev);
  2059. struct snd_ymfpci *chip = card->private_data;
  2060. unsigned int i;
  2061. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2062. snd_pcm_suspend_all(chip->pcm);
  2063. snd_pcm_suspend_all(chip->pcm2);
  2064. snd_pcm_suspend_all(chip->pcm_spdif);
  2065. snd_pcm_suspend_all(chip->pcm_4ch);
  2066. snd_ac97_suspend(chip->ac97);
  2067. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  2068. chip->saved_regs[i] = snd_ymfpci_readl(chip, saved_regs_index[i]);
  2069. chip->saved_ydsxgr_mode = snd_ymfpci_readl(chip, YDSXGR_MODE);
  2070. pci_read_config_word(chip->pci, PCIR_DSXG_LEGACY,
  2071. &chip->saved_dsxg_legacy);
  2072. pci_read_config_word(chip->pci, PCIR_DSXG_ELEGACY,
  2073. &chip->saved_dsxg_elegacy);
  2074. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  2075. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  2076. snd_ymfpci_disable_dsp(chip);
  2077. pci_disable_device(pci);
  2078. pci_save_state(pci);
  2079. pci_set_power_state(pci, PCI_D3hot);
  2080. return 0;
  2081. }
  2082. static int snd_ymfpci_resume(struct device *dev)
  2083. {
  2084. struct pci_dev *pci = to_pci_dev(dev);
  2085. struct snd_card *card = dev_get_drvdata(dev);
  2086. struct snd_ymfpci *chip = card->private_data;
  2087. unsigned int i;
  2088. pci_set_power_state(pci, PCI_D0);
  2089. pci_restore_state(pci);
  2090. if (pci_enable_device(pci) < 0) {
  2091. dev_err(dev, "pci_enable_device failed, disabling device\n");
  2092. snd_card_disconnect(card);
  2093. return -EIO;
  2094. }
  2095. pci_set_master(pci);
  2096. snd_ymfpci_aclink_reset(pci);
  2097. snd_ymfpci_codec_ready(chip, 0);
  2098. snd_ymfpci_download_image(chip);
  2099. udelay(100);
  2100. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  2101. snd_ymfpci_writel(chip, saved_regs_index[i], chip->saved_regs[i]);
  2102. snd_ac97_resume(chip->ac97);
  2103. pci_write_config_word(chip->pci, PCIR_DSXG_LEGACY,
  2104. chip->saved_dsxg_legacy);
  2105. pci_write_config_word(chip->pci, PCIR_DSXG_ELEGACY,
  2106. chip->saved_dsxg_elegacy);
  2107. /* start hw again */
  2108. if (chip->start_count > 0) {
  2109. spin_lock_irq(&chip->reg_lock);
  2110. snd_ymfpci_writel(chip, YDSXGR_MODE, chip->saved_ydsxgr_mode);
  2111. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT);
  2112. spin_unlock_irq(&chip->reg_lock);
  2113. }
  2114. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2115. return 0;
  2116. }
  2117. SIMPLE_DEV_PM_OPS(snd_ymfpci_pm, snd_ymfpci_suspend, snd_ymfpci_resume);
  2118. #endif /* CONFIG_PM_SLEEP */
  2119. int snd_ymfpci_create(struct snd_card *card,
  2120. struct pci_dev *pci,
  2121. unsigned short old_legacy_ctrl,
  2122. struct snd_ymfpci **rchip)
  2123. {
  2124. struct snd_ymfpci *chip;
  2125. int err;
  2126. static struct snd_device_ops ops = {
  2127. .dev_free = snd_ymfpci_dev_free,
  2128. };
  2129. *rchip = NULL;
  2130. /* enable PCI device */
  2131. if ((err = pci_enable_device(pci)) < 0)
  2132. return err;
  2133. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  2134. if (chip == NULL) {
  2135. pci_disable_device(pci);
  2136. return -ENOMEM;
  2137. }
  2138. chip->old_legacy_ctrl = old_legacy_ctrl;
  2139. spin_lock_init(&chip->reg_lock);
  2140. spin_lock_init(&chip->voice_lock);
  2141. init_waitqueue_head(&chip->interrupt_sleep);
  2142. atomic_set(&chip->interrupt_sleep_count, 0);
  2143. chip->card = card;
  2144. chip->pci = pci;
  2145. chip->irq = -1;
  2146. chip->device_id = pci->device;
  2147. chip->rev = pci->revision;
  2148. chip->reg_area_phys = pci_resource_start(pci, 0);
  2149. chip->reg_area_virt = ioremap_nocache(chip->reg_area_phys, 0x8000);
  2150. pci_set_master(pci);
  2151. chip->src441_used = -1;
  2152. if ((chip->res_reg_area = request_mem_region(chip->reg_area_phys, 0x8000, "YMFPCI")) == NULL) {
  2153. dev_err(chip->card->dev,
  2154. "unable to grab memory region 0x%lx-0x%lx\n",
  2155. chip->reg_area_phys, chip->reg_area_phys + 0x8000 - 1);
  2156. snd_ymfpci_free(chip);
  2157. return -EBUSY;
  2158. }
  2159. if (request_irq(pci->irq, snd_ymfpci_interrupt, IRQF_SHARED,
  2160. KBUILD_MODNAME, chip)) {
  2161. dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
  2162. snd_ymfpci_free(chip);
  2163. return -EBUSY;
  2164. }
  2165. chip->irq = pci->irq;
  2166. snd_ymfpci_aclink_reset(pci);
  2167. if (snd_ymfpci_codec_ready(chip, 0) < 0) {
  2168. snd_ymfpci_free(chip);
  2169. return -EIO;
  2170. }
  2171. err = snd_ymfpci_request_firmware(chip);
  2172. if (err < 0) {
  2173. dev_err(chip->card->dev, "firmware request failed: %d\n", err);
  2174. snd_ymfpci_free(chip);
  2175. return err;
  2176. }
  2177. snd_ymfpci_download_image(chip);
  2178. udelay(100); /* seems we need a delay after downloading image.. */
  2179. if (snd_ymfpci_memalloc(chip) < 0) {
  2180. snd_ymfpci_free(chip);
  2181. return -EIO;
  2182. }
  2183. if ((err = snd_ymfpci_ac3_init(chip)) < 0) {
  2184. snd_ymfpci_free(chip);
  2185. return err;
  2186. }
  2187. #ifdef CONFIG_PM_SLEEP
  2188. chip->saved_regs = kmalloc(YDSXGR_NUM_SAVED_REGS * sizeof(u32),
  2189. GFP_KERNEL);
  2190. if (chip->saved_regs == NULL) {
  2191. snd_ymfpci_free(chip);
  2192. return -ENOMEM;
  2193. }
  2194. #endif
  2195. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  2196. snd_ymfpci_free(chip);
  2197. return err;
  2198. }
  2199. snd_ymfpci_proc_init(card, chip);
  2200. *rchip = chip;
  2201. return 0;
  2202. }