ice1712.c 84 KB

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  1. /*
  2. * ALSA driver for ICEnsemble ICE1712 (Envy24)
  3. *
  4. * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. /*
  22. NOTES:
  23. - spdif nonaudio consumer mode does not work (at least with my
  24. Sony STR-DB830)
  25. */
  26. /*
  27. * Changes:
  28. *
  29. * 2002.09.09 Takashi Iwai <tiwai@suse.de>
  30. * split the code to several files. each low-level routine
  31. * is stored in the local file and called from registration
  32. * function from card_info struct.
  33. *
  34. * 2002.11.26 James Stafford <jstafford@ampltd.com>
  35. * Added support for VT1724 (Envy24HT)
  36. * I have left out support for 176.4 and 192 KHz for the moment.
  37. * I also haven't done anything with the internal S/PDIF transmitter or the MPU-401
  38. *
  39. * 2003.02.20 Taksahi Iwai <tiwai@suse.de>
  40. * Split vt1724 part to an independent driver.
  41. * The GPIO is accessed through the callback functions now.
  42. *
  43. * 2004.03.31 Doug McLain <nostar@comcast.net>
  44. * Added support for Event Electronics EZ8 card to hoontech.c.
  45. */
  46. #include <linux/delay.h>
  47. #include <linux/interrupt.h>
  48. #include <linux/init.h>
  49. #include <linux/pci.h>
  50. #include <linux/dma-mapping.h>
  51. #include <linux/slab.h>
  52. #include <linux/module.h>
  53. #include <linux/mutex.h>
  54. #include <sound/core.h>
  55. #include <sound/cs8427.h>
  56. #include <sound/info.h>
  57. #include <sound/initval.h>
  58. #include <sound/tlv.h>
  59. #include <sound/asoundef.h>
  60. #include "ice1712.h"
  61. /* lowlevel routines */
  62. #include "delta.h"
  63. #include "ews.h"
  64. #include "hoontech.h"
  65. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  66. MODULE_DESCRIPTION("ICEnsemble ICE1712 (Envy24)");
  67. MODULE_LICENSE("GPL");
  68. MODULE_SUPPORTED_DEVICE("{"
  69. HOONTECH_DEVICE_DESC
  70. DELTA_DEVICE_DESC
  71. EWS_DEVICE_DESC
  72. "{ICEnsemble,Generic ICE1712},"
  73. "{ICEnsemble,Generic Envy24}}");
  74. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  75. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  76. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  77. static char *model[SNDRV_CARDS];
  78. static bool omni[SNDRV_CARDS]; /* Delta44 & 66 Omni I/O support */
  79. static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transceiver reset timeout value in msec */
  80. static int dxr_enable[SNDRV_CARDS]; /* DXR enable for DMX6FIRE */
  81. module_param_array(index, int, NULL, 0444);
  82. MODULE_PARM_DESC(index, "Index value for ICE1712 soundcard.");
  83. module_param_array(id, charp, NULL, 0444);
  84. MODULE_PARM_DESC(id, "ID string for ICE1712 soundcard.");
  85. module_param_array(enable, bool, NULL, 0444);
  86. MODULE_PARM_DESC(enable, "Enable ICE1712 soundcard.");
  87. module_param_array(omni, bool, NULL, 0444);
  88. MODULE_PARM_DESC(omni, "Enable Midiman M-Audio Delta Omni I/O support.");
  89. module_param_array(cs8427_timeout, int, NULL, 0444);
  90. MODULE_PARM_DESC(cs8427_timeout, "Define reset timeout for cs8427 chip in msec resolution.");
  91. module_param_array(model, charp, NULL, 0444);
  92. MODULE_PARM_DESC(model, "Use the given board model.");
  93. module_param_array(dxr_enable, int, NULL, 0444);
  94. MODULE_PARM_DESC(dxr_enable, "Enable DXR support for Terratec DMX6FIRE.");
  95. static DEFINE_PCI_DEVICE_TABLE(snd_ice1712_ids) = {
  96. { PCI_VDEVICE(ICE, PCI_DEVICE_ID_ICE_1712), 0 }, /* ICE1712 */
  97. { 0, }
  98. };
  99. MODULE_DEVICE_TABLE(pci, snd_ice1712_ids);
  100. static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice);
  101. static int snd_ice1712_build_controls(struct snd_ice1712 *ice);
  102. static int PRO_RATE_LOCKED;
  103. static int PRO_RATE_RESET = 1;
  104. static unsigned int PRO_RATE_DEFAULT = 44100;
  105. /*
  106. * Basic I/O
  107. */
  108. /* check whether the clock mode is spdif-in */
  109. static inline int is_spdif_master(struct snd_ice1712 *ice)
  110. {
  111. return (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER) ? 1 : 0;
  112. }
  113. static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
  114. {
  115. return is_spdif_master(ice) || PRO_RATE_LOCKED;
  116. }
  117. static inline void snd_ice1712_ds_write(struct snd_ice1712 *ice, u8 channel, u8 addr, u32 data)
  118. {
  119. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  120. outl(data, ICEDS(ice, DATA));
  121. }
  122. static inline u32 snd_ice1712_ds_read(struct snd_ice1712 *ice, u8 channel, u8 addr)
  123. {
  124. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  125. return inl(ICEDS(ice, DATA));
  126. }
  127. static void snd_ice1712_ac97_write(struct snd_ac97 *ac97,
  128. unsigned short reg,
  129. unsigned short val)
  130. {
  131. struct snd_ice1712 *ice = ac97->private_data;
  132. int tm;
  133. unsigned char old_cmd = 0;
  134. for (tm = 0; tm < 0x10000; tm++) {
  135. old_cmd = inb(ICEREG(ice, AC97_CMD));
  136. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  137. continue;
  138. if (!(old_cmd & ICE1712_AC97_READY))
  139. continue;
  140. break;
  141. }
  142. outb(reg, ICEREG(ice, AC97_INDEX));
  143. outw(val, ICEREG(ice, AC97_DATA));
  144. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  145. outb(old_cmd | ICE1712_AC97_WRITE, ICEREG(ice, AC97_CMD));
  146. for (tm = 0; tm < 0x10000; tm++)
  147. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  148. break;
  149. }
  150. static unsigned short snd_ice1712_ac97_read(struct snd_ac97 *ac97,
  151. unsigned short reg)
  152. {
  153. struct snd_ice1712 *ice = ac97->private_data;
  154. int tm;
  155. unsigned char old_cmd = 0;
  156. for (tm = 0; tm < 0x10000; tm++) {
  157. old_cmd = inb(ICEREG(ice, AC97_CMD));
  158. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  159. continue;
  160. if (!(old_cmd & ICE1712_AC97_READY))
  161. continue;
  162. break;
  163. }
  164. outb(reg, ICEREG(ice, AC97_INDEX));
  165. outb(old_cmd | ICE1712_AC97_READ, ICEREG(ice, AC97_CMD));
  166. for (tm = 0; tm < 0x10000; tm++)
  167. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  168. break;
  169. if (tm >= 0x10000) /* timeout */
  170. return ~0;
  171. return inw(ICEREG(ice, AC97_DATA));
  172. }
  173. /*
  174. * pro ac97 section
  175. */
  176. static void snd_ice1712_pro_ac97_write(struct snd_ac97 *ac97,
  177. unsigned short reg,
  178. unsigned short val)
  179. {
  180. struct snd_ice1712 *ice = ac97->private_data;
  181. int tm;
  182. unsigned char old_cmd = 0;
  183. for (tm = 0; tm < 0x10000; tm++) {
  184. old_cmd = inb(ICEMT(ice, AC97_CMD));
  185. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  186. continue;
  187. if (!(old_cmd & ICE1712_AC97_READY))
  188. continue;
  189. break;
  190. }
  191. outb(reg, ICEMT(ice, AC97_INDEX));
  192. outw(val, ICEMT(ice, AC97_DATA));
  193. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  194. outb(old_cmd | ICE1712_AC97_WRITE, ICEMT(ice, AC97_CMD));
  195. for (tm = 0; tm < 0x10000; tm++)
  196. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  197. break;
  198. }
  199. static unsigned short snd_ice1712_pro_ac97_read(struct snd_ac97 *ac97,
  200. unsigned short reg)
  201. {
  202. struct snd_ice1712 *ice = ac97->private_data;
  203. int tm;
  204. unsigned char old_cmd = 0;
  205. for (tm = 0; tm < 0x10000; tm++) {
  206. old_cmd = inb(ICEMT(ice, AC97_CMD));
  207. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  208. continue;
  209. if (!(old_cmd & ICE1712_AC97_READY))
  210. continue;
  211. break;
  212. }
  213. outb(reg, ICEMT(ice, AC97_INDEX));
  214. outb(old_cmd | ICE1712_AC97_READ, ICEMT(ice, AC97_CMD));
  215. for (tm = 0; tm < 0x10000; tm++)
  216. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  217. break;
  218. if (tm >= 0x10000) /* timeout */
  219. return ~0;
  220. return inw(ICEMT(ice, AC97_DATA));
  221. }
  222. /*
  223. * consumer ac97 digital mix
  224. */
  225. #define snd_ice1712_digmix_route_ac97_info snd_ctl_boolean_mono_info
  226. static int snd_ice1712_digmix_route_ac97_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  227. {
  228. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  229. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_ROUTECTRL)) & ICE1712_ROUTE_AC97 ? 1 : 0;
  230. return 0;
  231. }
  232. static int snd_ice1712_digmix_route_ac97_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  233. {
  234. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  235. unsigned char val, nval;
  236. spin_lock_irq(&ice->reg_lock);
  237. val = inb(ICEMT(ice, MONITOR_ROUTECTRL));
  238. nval = val & ~ICE1712_ROUTE_AC97;
  239. if (ucontrol->value.integer.value[0])
  240. nval |= ICE1712_ROUTE_AC97;
  241. outb(nval, ICEMT(ice, MONITOR_ROUTECTRL));
  242. spin_unlock_irq(&ice->reg_lock);
  243. return val != nval;
  244. }
  245. static struct snd_kcontrol_new snd_ice1712_mixer_digmix_route_ac97 = {
  246. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  247. .name = "Digital Mixer To AC97",
  248. .info = snd_ice1712_digmix_route_ac97_info,
  249. .get = snd_ice1712_digmix_route_ac97_get,
  250. .put = snd_ice1712_digmix_route_ac97_put,
  251. };
  252. /*
  253. * gpio operations
  254. */
  255. static void snd_ice1712_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
  256. {
  257. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, data);
  258. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  259. }
  260. static unsigned int snd_ice1712_get_gpio_dir(struct snd_ice1712 *ice)
  261. {
  262. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION);
  263. }
  264. static unsigned int snd_ice1712_get_gpio_mask(struct snd_ice1712 *ice)
  265. {
  266. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK);
  267. }
  268. static void snd_ice1712_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
  269. {
  270. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, data);
  271. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  272. }
  273. static unsigned int snd_ice1712_get_gpio_data(struct snd_ice1712 *ice)
  274. {
  275. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
  276. }
  277. static void snd_ice1712_set_gpio_data(struct snd_ice1712 *ice, unsigned int val)
  278. {
  279. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, val);
  280. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  281. }
  282. /*
  283. *
  284. * CS8427 interface
  285. *
  286. */
  287. /*
  288. * change the input clock selection
  289. * spdif_clock = 1 - IEC958 input, 0 - Envy24
  290. */
  291. static int snd_ice1712_cs8427_set_input_clock(struct snd_ice1712 *ice, int spdif_clock)
  292. {
  293. unsigned char reg[2] = { 0x80 | 4, 0 }; /* CS8427 auto increment | register number 4 + data */
  294. unsigned char val, nval;
  295. int res = 0;
  296. snd_i2c_lock(ice->i2c);
  297. if (snd_i2c_sendbytes(ice->cs8427, reg, 1) != 1) {
  298. snd_i2c_unlock(ice->i2c);
  299. return -EIO;
  300. }
  301. if (snd_i2c_readbytes(ice->cs8427, &val, 1) != 1) {
  302. snd_i2c_unlock(ice->i2c);
  303. return -EIO;
  304. }
  305. nval = val & 0xf0;
  306. if (spdif_clock)
  307. nval |= 0x01;
  308. else
  309. nval |= 0x04;
  310. if (val != nval) {
  311. reg[1] = nval;
  312. if (snd_i2c_sendbytes(ice->cs8427, reg, 2) != 2) {
  313. res = -EIO;
  314. } else {
  315. res++;
  316. }
  317. }
  318. snd_i2c_unlock(ice->i2c);
  319. return res;
  320. }
  321. /*
  322. * spdif callbacks
  323. */
  324. static void open_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  325. {
  326. snd_cs8427_iec958_active(ice->cs8427, 1);
  327. }
  328. static void close_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  329. {
  330. snd_cs8427_iec958_active(ice->cs8427, 0);
  331. }
  332. static void setup_cs8427(struct snd_ice1712 *ice, int rate)
  333. {
  334. snd_cs8427_iec958_pcm(ice->cs8427, rate);
  335. }
  336. /*
  337. * create and initialize callbacks for cs8427 interface
  338. */
  339. int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr)
  340. {
  341. int err;
  342. err = snd_cs8427_create(ice->i2c, addr,
  343. (ice->cs8427_timeout * HZ) / 1000, &ice->cs8427);
  344. if (err < 0) {
  345. dev_err(ice->card->dev, "CS8427 initialization failed\n");
  346. return err;
  347. }
  348. ice->spdif.ops.open = open_cs8427;
  349. ice->spdif.ops.close = close_cs8427;
  350. ice->spdif.ops.setup_rate = setup_cs8427;
  351. return 0;
  352. }
  353. static void snd_ice1712_set_input_clock_source(struct snd_ice1712 *ice, int spdif_is_master)
  354. {
  355. /* change CS8427 clock source too */
  356. if (ice->cs8427)
  357. snd_ice1712_cs8427_set_input_clock(ice, spdif_is_master);
  358. /* notify ak4524 chip as well */
  359. if (spdif_is_master) {
  360. unsigned int i;
  361. for (i = 0; i < ice->akm_codecs; i++) {
  362. if (ice->akm[i].ops.set_rate_val)
  363. ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
  364. }
  365. }
  366. }
  367. /*
  368. * Interrupt handler
  369. */
  370. static irqreturn_t snd_ice1712_interrupt(int irq, void *dev_id)
  371. {
  372. struct snd_ice1712 *ice = dev_id;
  373. unsigned char status;
  374. int handled = 0;
  375. while (1) {
  376. status = inb(ICEREG(ice, IRQSTAT));
  377. if (status == 0)
  378. break;
  379. handled = 1;
  380. if (status & ICE1712_IRQ_MPU1) {
  381. if (ice->rmidi[0])
  382. snd_mpu401_uart_interrupt(irq, ice->rmidi[0]->private_data);
  383. outb(ICE1712_IRQ_MPU1, ICEREG(ice, IRQSTAT));
  384. status &= ~ICE1712_IRQ_MPU1;
  385. }
  386. if (status & ICE1712_IRQ_TIMER)
  387. outb(ICE1712_IRQ_TIMER, ICEREG(ice, IRQSTAT));
  388. if (status & ICE1712_IRQ_MPU2) {
  389. if (ice->rmidi[1])
  390. snd_mpu401_uart_interrupt(irq, ice->rmidi[1]->private_data);
  391. outb(ICE1712_IRQ_MPU2, ICEREG(ice, IRQSTAT));
  392. status &= ~ICE1712_IRQ_MPU2;
  393. }
  394. if (status & ICE1712_IRQ_PROPCM) {
  395. unsigned char mtstat = inb(ICEMT(ice, IRQ));
  396. if (mtstat & ICE1712_MULTI_PBKSTATUS) {
  397. if (ice->playback_pro_substream)
  398. snd_pcm_period_elapsed(ice->playback_pro_substream);
  399. outb(ICE1712_MULTI_PBKSTATUS, ICEMT(ice, IRQ));
  400. }
  401. if (mtstat & ICE1712_MULTI_CAPSTATUS) {
  402. if (ice->capture_pro_substream)
  403. snd_pcm_period_elapsed(ice->capture_pro_substream);
  404. outb(ICE1712_MULTI_CAPSTATUS, ICEMT(ice, IRQ));
  405. }
  406. }
  407. if (status & ICE1712_IRQ_FM)
  408. outb(ICE1712_IRQ_FM, ICEREG(ice, IRQSTAT));
  409. if (status & ICE1712_IRQ_PBKDS) {
  410. u32 idx;
  411. u16 pbkstatus;
  412. struct snd_pcm_substream *substream;
  413. pbkstatus = inw(ICEDS(ice, INTSTAT));
  414. /* dev_dbg(ice->card->dev, "pbkstatus = 0x%x\n", pbkstatus); */
  415. for (idx = 0; idx < 6; idx++) {
  416. if ((pbkstatus & (3 << (idx * 2))) == 0)
  417. continue;
  418. substream = ice->playback_con_substream_ds[idx];
  419. if (substream != NULL)
  420. snd_pcm_period_elapsed(substream);
  421. outw(3 << (idx * 2), ICEDS(ice, INTSTAT));
  422. }
  423. outb(ICE1712_IRQ_PBKDS, ICEREG(ice, IRQSTAT));
  424. }
  425. if (status & ICE1712_IRQ_CONCAP) {
  426. if (ice->capture_con_substream)
  427. snd_pcm_period_elapsed(ice->capture_con_substream);
  428. outb(ICE1712_IRQ_CONCAP, ICEREG(ice, IRQSTAT));
  429. }
  430. if (status & ICE1712_IRQ_CONPBK) {
  431. if (ice->playback_con_substream)
  432. snd_pcm_period_elapsed(ice->playback_con_substream);
  433. outb(ICE1712_IRQ_CONPBK, ICEREG(ice, IRQSTAT));
  434. }
  435. }
  436. return IRQ_RETVAL(handled);
  437. }
  438. /*
  439. * PCM part - misc
  440. */
  441. static int snd_ice1712_hw_params(struct snd_pcm_substream *substream,
  442. struct snd_pcm_hw_params *hw_params)
  443. {
  444. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  445. }
  446. static int snd_ice1712_hw_free(struct snd_pcm_substream *substream)
  447. {
  448. return snd_pcm_lib_free_pages(substream);
  449. }
  450. /*
  451. * PCM part - consumer I/O
  452. */
  453. static int snd_ice1712_playback_trigger(struct snd_pcm_substream *substream,
  454. int cmd)
  455. {
  456. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  457. int result = 0;
  458. u32 tmp;
  459. spin_lock(&ice->reg_lock);
  460. tmp = snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL);
  461. if (cmd == SNDRV_PCM_TRIGGER_START) {
  462. tmp |= 1;
  463. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  464. tmp &= ~1;
  465. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  466. tmp |= 2;
  467. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  468. tmp &= ~2;
  469. } else {
  470. result = -EINVAL;
  471. }
  472. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  473. spin_unlock(&ice->reg_lock);
  474. return result;
  475. }
  476. static int snd_ice1712_playback_ds_trigger(struct snd_pcm_substream *substream,
  477. int cmd)
  478. {
  479. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  480. int result = 0;
  481. u32 tmp;
  482. spin_lock(&ice->reg_lock);
  483. tmp = snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL);
  484. if (cmd == SNDRV_PCM_TRIGGER_START) {
  485. tmp |= 1;
  486. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  487. tmp &= ~1;
  488. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  489. tmp |= 2;
  490. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  491. tmp &= ~2;
  492. } else {
  493. result = -EINVAL;
  494. }
  495. snd_ice1712_ds_write(ice, substream->number * 2, ICE1712_DSC_CONTROL, tmp);
  496. spin_unlock(&ice->reg_lock);
  497. return result;
  498. }
  499. static int snd_ice1712_capture_trigger(struct snd_pcm_substream *substream,
  500. int cmd)
  501. {
  502. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  503. int result = 0;
  504. u8 tmp;
  505. spin_lock(&ice->reg_lock);
  506. tmp = snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL);
  507. if (cmd == SNDRV_PCM_TRIGGER_START) {
  508. tmp |= 1;
  509. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  510. tmp &= ~1;
  511. } else {
  512. result = -EINVAL;
  513. }
  514. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  515. spin_unlock(&ice->reg_lock);
  516. return result;
  517. }
  518. static int snd_ice1712_playback_prepare(struct snd_pcm_substream *substream)
  519. {
  520. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  521. struct snd_pcm_runtime *runtime = substream->runtime;
  522. u32 period_size, buf_size, rate, tmp;
  523. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  524. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  525. tmp = 0x0000;
  526. if (snd_pcm_format_width(runtime->format) == 16)
  527. tmp |= 0x10;
  528. if (runtime->channels == 2)
  529. tmp |= 0x08;
  530. rate = (runtime->rate * 8192) / 375;
  531. if (rate > 0x000fffff)
  532. rate = 0x000fffff;
  533. spin_lock_irq(&ice->reg_lock);
  534. outb(0, ice->ddma_port + 15);
  535. outb(ICE1712_DMA_MODE_WRITE | ICE1712_DMA_AUTOINIT, ice->ddma_port + 0x0b);
  536. outl(runtime->dma_addr, ice->ddma_port + 0);
  537. outw(buf_size, ice->ddma_port + 4);
  538. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_LO, rate & 0xff);
  539. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_MID, (rate >> 8) & 0xff);
  540. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_HI, (rate >> 16) & 0xff);
  541. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  542. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_LO, period_size & 0xff);
  543. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_HI, period_size >> 8);
  544. snd_ice1712_write(ice, ICE1712_IREG_PBK_LEFT, 0);
  545. snd_ice1712_write(ice, ICE1712_IREG_PBK_RIGHT, 0);
  546. spin_unlock_irq(&ice->reg_lock);
  547. return 0;
  548. }
  549. static int snd_ice1712_playback_ds_prepare(struct snd_pcm_substream *substream)
  550. {
  551. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  552. struct snd_pcm_runtime *runtime = substream->runtime;
  553. u32 period_size, buf_size, rate, tmp, chn;
  554. period_size = snd_pcm_lib_period_bytes(substream) - 1;
  555. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  556. tmp = 0x0064;
  557. if (snd_pcm_format_width(runtime->format) == 16)
  558. tmp &= ~0x04;
  559. if (runtime->channels == 2)
  560. tmp |= 0x08;
  561. rate = (runtime->rate * 8192) / 375;
  562. if (rate > 0x000fffff)
  563. rate = 0x000fffff;
  564. ice->playback_con_active_buf[substream->number] = 0;
  565. ice->playback_con_virt_addr[substream->number] = runtime->dma_addr;
  566. chn = substream->number * 2;
  567. spin_lock_irq(&ice->reg_lock);
  568. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR0, runtime->dma_addr);
  569. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT0, period_size);
  570. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR1, runtime->dma_addr + (runtime->periods > 1 ? period_size + 1 : 0));
  571. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT1, period_size);
  572. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_RATE, rate);
  573. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_VOLUME, 0);
  574. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_CONTROL, tmp);
  575. if (runtime->channels == 2) {
  576. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_RATE, rate);
  577. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_VOLUME, 0);
  578. }
  579. spin_unlock_irq(&ice->reg_lock);
  580. return 0;
  581. }
  582. static int snd_ice1712_capture_prepare(struct snd_pcm_substream *substream)
  583. {
  584. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  585. struct snd_pcm_runtime *runtime = substream->runtime;
  586. u32 period_size, buf_size;
  587. u8 tmp;
  588. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  589. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  590. tmp = 0x06;
  591. if (snd_pcm_format_width(runtime->format) == 16)
  592. tmp &= ~0x04;
  593. if (runtime->channels == 2)
  594. tmp &= ~0x02;
  595. spin_lock_irq(&ice->reg_lock);
  596. outl(ice->capture_con_virt_addr = runtime->dma_addr, ICEREG(ice, CONCAP_ADDR));
  597. outw(buf_size, ICEREG(ice, CONCAP_COUNT));
  598. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_HI, period_size >> 8);
  599. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_LO, period_size & 0xff);
  600. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  601. spin_unlock_irq(&ice->reg_lock);
  602. snd_ac97_set_rate(ice->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
  603. return 0;
  604. }
  605. static snd_pcm_uframes_t snd_ice1712_playback_pointer(struct snd_pcm_substream *substream)
  606. {
  607. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  608. struct snd_pcm_runtime *runtime = substream->runtime;
  609. size_t ptr;
  610. if (!(snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL) & 1))
  611. return 0;
  612. ptr = runtime->buffer_size - inw(ice->ddma_port + 4);
  613. ptr = bytes_to_frames(substream->runtime, ptr);
  614. if (ptr == runtime->buffer_size)
  615. ptr = 0;
  616. return ptr;
  617. }
  618. static snd_pcm_uframes_t snd_ice1712_playback_ds_pointer(struct snd_pcm_substream *substream)
  619. {
  620. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  621. u8 addr;
  622. size_t ptr;
  623. if (!(snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL) & 1))
  624. return 0;
  625. if (ice->playback_con_active_buf[substream->number])
  626. addr = ICE1712_DSC_ADDR1;
  627. else
  628. addr = ICE1712_DSC_ADDR0;
  629. ptr = snd_ice1712_ds_read(ice, substream->number * 2, addr) -
  630. ice->playback_con_virt_addr[substream->number];
  631. ptr = bytes_to_frames(substream->runtime, ptr);
  632. if (ptr == substream->runtime->buffer_size)
  633. ptr = 0;
  634. return ptr;
  635. }
  636. static snd_pcm_uframes_t snd_ice1712_capture_pointer(struct snd_pcm_substream *substream)
  637. {
  638. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  639. size_t ptr;
  640. if (!(snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL) & 1))
  641. return 0;
  642. ptr = inl(ICEREG(ice, CONCAP_ADDR)) - ice->capture_con_virt_addr;
  643. ptr = bytes_to_frames(substream->runtime, ptr);
  644. if (ptr == substream->runtime->buffer_size)
  645. ptr = 0;
  646. return ptr;
  647. }
  648. static const struct snd_pcm_hardware snd_ice1712_playback = {
  649. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  650. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  651. SNDRV_PCM_INFO_MMAP_VALID |
  652. SNDRV_PCM_INFO_PAUSE),
  653. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  654. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  655. .rate_min = 4000,
  656. .rate_max = 48000,
  657. .channels_min = 1,
  658. .channels_max = 2,
  659. .buffer_bytes_max = (64*1024),
  660. .period_bytes_min = 64,
  661. .period_bytes_max = (64*1024),
  662. .periods_min = 1,
  663. .periods_max = 1024,
  664. .fifo_size = 0,
  665. };
  666. static const struct snd_pcm_hardware snd_ice1712_playback_ds = {
  667. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  668. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  669. SNDRV_PCM_INFO_MMAP_VALID |
  670. SNDRV_PCM_INFO_PAUSE),
  671. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  672. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  673. .rate_min = 4000,
  674. .rate_max = 48000,
  675. .channels_min = 1,
  676. .channels_max = 2,
  677. .buffer_bytes_max = (128*1024),
  678. .period_bytes_min = 64,
  679. .period_bytes_max = (128*1024),
  680. .periods_min = 2,
  681. .periods_max = 2,
  682. .fifo_size = 0,
  683. };
  684. static const struct snd_pcm_hardware snd_ice1712_capture = {
  685. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  686. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  687. SNDRV_PCM_INFO_MMAP_VALID),
  688. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  689. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  690. .rate_min = 4000,
  691. .rate_max = 48000,
  692. .channels_min = 1,
  693. .channels_max = 2,
  694. .buffer_bytes_max = (64*1024),
  695. .period_bytes_min = 64,
  696. .period_bytes_max = (64*1024),
  697. .periods_min = 1,
  698. .periods_max = 1024,
  699. .fifo_size = 0,
  700. };
  701. static int snd_ice1712_playback_open(struct snd_pcm_substream *substream)
  702. {
  703. struct snd_pcm_runtime *runtime = substream->runtime;
  704. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  705. ice->playback_con_substream = substream;
  706. runtime->hw = snd_ice1712_playback;
  707. return 0;
  708. }
  709. static int snd_ice1712_playback_ds_open(struct snd_pcm_substream *substream)
  710. {
  711. struct snd_pcm_runtime *runtime = substream->runtime;
  712. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  713. u32 tmp;
  714. ice->playback_con_substream_ds[substream->number] = substream;
  715. runtime->hw = snd_ice1712_playback_ds;
  716. spin_lock_irq(&ice->reg_lock);
  717. tmp = inw(ICEDS(ice, INTMASK)) & ~(1 << (substream->number * 2));
  718. outw(tmp, ICEDS(ice, INTMASK));
  719. spin_unlock_irq(&ice->reg_lock);
  720. return 0;
  721. }
  722. static int snd_ice1712_capture_open(struct snd_pcm_substream *substream)
  723. {
  724. struct snd_pcm_runtime *runtime = substream->runtime;
  725. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  726. ice->capture_con_substream = substream;
  727. runtime->hw = snd_ice1712_capture;
  728. runtime->hw.rates = ice->ac97->rates[AC97_RATES_ADC];
  729. if (!(runtime->hw.rates & SNDRV_PCM_RATE_8000))
  730. runtime->hw.rate_min = 48000;
  731. return 0;
  732. }
  733. static int snd_ice1712_playback_close(struct snd_pcm_substream *substream)
  734. {
  735. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  736. ice->playback_con_substream = NULL;
  737. return 0;
  738. }
  739. static int snd_ice1712_playback_ds_close(struct snd_pcm_substream *substream)
  740. {
  741. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  742. u32 tmp;
  743. spin_lock_irq(&ice->reg_lock);
  744. tmp = inw(ICEDS(ice, INTMASK)) | (3 << (substream->number * 2));
  745. outw(tmp, ICEDS(ice, INTMASK));
  746. spin_unlock_irq(&ice->reg_lock);
  747. ice->playback_con_substream_ds[substream->number] = NULL;
  748. return 0;
  749. }
  750. static int snd_ice1712_capture_close(struct snd_pcm_substream *substream)
  751. {
  752. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  753. ice->capture_con_substream = NULL;
  754. return 0;
  755. }
  756. static struct snd_pcm_ops snd_ice1712_playback_ops = {
  757. .open = snd_ice1712_playback_open,
  758. .close = snd_ice1712_playback_close,
  759. .ioctl = snd_pcm_lib_ioctl,
  760. .hw_params = snd_ice1712_hw_params,
  761. .hw_free = snd_ice1712_hw_free,
  762. .prepare = snd_ice1712_playback_prepare,
  763. .trigger = snd_ice1712_playback_trigger,
  764. .pointer = snd_ice1712_playback_pointer,
  765. };
  766. static struct snd_pcm_ops snd_ice1712_playback_ds_ops = {
  767. .open = snd_ice1712_playback_ds_open,
  768. .close = snd_ice1712_playback_ds_close,
  769. .ioctl = snd_pcm_lib_ioctl,
  770. .hw_params = snd_ice1712_hw_params,
  771. .hw_free = snd_ice1712_hw_free,
  772. .prepare = snd_ice1712_playback_ds_prepare,
  773. .trigger = snd_ice1712_playback_ds_trigger,
  774. .pointer = snd_ice1712_playback_ds_pointer,
  775. };
  776. static struct snd_pcm_ops snd_ice1712_capture_ops = {
  777. .open = snd_ice1712_capture_open,
  778. .close = snd_ice1712_capture_close,
  779. .ioctl = snd_pcm_lib_ioctl,
  780. .hw_params = snd_ice1712_hw_params,
  781. .hw_free = snd_ice1712_hw_free,
  782. .prepare = snd_ice1712_capture_prepare,
  783. .trigger = snd_ice1712_capture_trigger,
  784. .pointer = snd_ice1712_capture_pointer,
  785. };
  786. static int snd_ice1712_pcm(struct snd_ice1712 *ice, int device, struct snd_pcm **rpcm)
  787. {
  788. struct snd_pcm *pcm;
  789. int err;
  790. if (rpcm)
  791. *rpcm = NULL;
  792. err = snd_pcm_new(ice->card, "ICE1712 consumer", device, 1, 1, &pcm);
  793. if (err < 0)
  794. return err;
  795. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ops);
  796. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_ops);
  797. pcm->private_data = ice;
  798. pcm->info_flags = 0;
  799. strcpy(pcm->name, "ICE1712 consumer");
  800. ice->pcm = pcm;
  801. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  802. snd_dma_pci_data(ice->pci), 64*1024, 64*1024);
  803. if (rpcm)
  804. *rpcm = pcm;
  805. dev_warn(ice->card->dev,
  806. "Consumer PCM code does not work well at the moment --jk\n");
  807. return 0;
  808. }
  809. static int snd_ice1712_pcm_ds(struct snd_ice1712 *ice, int device, struct snd_pcm **rpcm)
  810. {
  811. struct snd_pcm *pcm;
  812. int err;
  813. if (rpcm)
  814. *rpcm = NULL;
  815. err = snd_pcm_new(ice->card, "ICE1712 consumer (DS)", device, 6, 0, &pcm);
  816. if (err < 0)
  817. return err;
  818. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ds_ops);
  819. pcm->private_data = ice;
  820. pcm->info_flags = 0;
  821. strcpy(pcm->name, "ICE1712 consumer (DS)");
  822. ice->pcm_ds = pcm;
  823. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  824. snd_dma_pci_data(ice->pci), 64*1024, 128*1024);
  825. if (rpcm)
  826. *rpcm = pcm;
  827. return 0;
  828. }
  829. /*
  830. * PCM code - professional part (multitrack)
  831. */
  832. static unsigned int rates[] = { 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  833. 32000, 44100, 48000, 64000, 88200, 96000 };
  834. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  835. .count = ARRAY_SIZE(rates),
  836. .list = rates,
  837. .mask = 0,
  838. };
  839. static int snd_ice1712_pro_trigger(struct snd_pcm_substream *substream,
  840. int cmd)
  841. {
  842. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  843. switch (cmd) {
  844. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  845. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  846. {
  847. unsigned int what;
  848. unsigned int old;
  849. if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
  850. return -EINVAL;
  851. what = ICE1712_PLAYBACK_PAUSE;
  852. snd_pcm_trigger_done(substream, substream);
  853. spin_lock(&ice->reg_lock);
  854. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  855. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  856. old |= what;
  857. else
  858. old &= ~what;
  859. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  860. spin_unlock(&ice->reg_lock);
  861. break;
  862. }
  863. case SNDRV_PCM_TRIGGER_START:
  864. case SNDRV_PCM_TRIGGER_STOP:
  865. {
  866. unsigned int what = 0;
  867. unsigned int old;
  868. struct snd_pcm_substream *s;
  869. snd_pcm_group_for_each_entry(s, substream) {
  870. if (s == ice->playback_pro_substream) {
  871. what |= ICE1712_PLAYBACK_START;
  872. snd_pcm_trigger_done(s, substream);
  873. } else if (s == ice->capture_pro_substream) {
  874. what |= ICE1712_CAPTURE_START_SHADOW;
  875. snd_pcm_trigger_done(s, substream);
  876. }
  877. }
  878. spin_lock(&ice->reg_lock);
  879. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  880. if (cmd == SNDRV_PCM_TRIGGER_START)
  881. old |= what;
  882. else
  883. old &= ~what;
  884. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  885. spin_unlock(&ice->reg_lock);
  886. break;
  887. }
  888. default:
  889. return -EINVAL;
  890. }
  891. return 0;
  892. }
  893. /*
  894. */
  895. static void snd_ice1712_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate, int force)
  896. {
  897. unsigned long flags;
  898. unsigned char val, old;
  899. unsigned int i;
  900. switch (rate) {
  901. case 8000: val = 6; break;
  902. case 9600: val = 3; break;
  903. case 11025: val = 10; break;
  904. case 12000: val = 2; break;
  905. case 16000: val = 5; break;
  906. case 22050: val = 9; break;
  907. case 24000: val = 1; break;
  908. case 32000: val = 4; break;
  909. case 44100: val = 8; break;
  910. case 48000: val = 0; break;
  911. case 64000: val = 15; break;
  912. case 88200: val = 11; break;
  913. case 96000: val = 7; break;
  914. default:
  915. snd_BUG();
  916. val = 0;
  917. rate = 48000;
  918. break;
  919. }
  920. spin_lock_irqsave(&ice->reg_lock, flags);
  921. if (inb(ICEMT(ice, PLAYBACK_CONTROL)) & (ICE1712_CAPTURE_START_SHADOW|
  922. ICE1712_PLAYBACK_PAUSE|
  923. ICE1712_PLAYBACK_START)) {
  924. __out:
  925. spin_unlock_irqrestore(&ice->reg_lock, flags);
  926. return;
  927. }
  928. if (!force && is_pro_rate_locked(ice))
  929. goto __out;
  930. old = inb(ICEMT(ice, RATE));
  931. if (!force && old == val)
  932. goto __out;
  933. ice->cur_rate = rate;
  934. outb(val, ICEMT(ice, RATE));
  935. spin_unlock_irqrestore(&ice->reg_lock, flags);
  936. if (ice->gpio.set_pro_rate)
  937. ice->gpio.set_pro_rate(ice, rate);
  938. for (i = 0; i < ice->akm_codecs; i++) {
  939. if (ice->akm[i].ops.set_rate_val)
  940. ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
  941. }
  942. if (ice->spdif.ops.setup_rate)
  943. ice->spdif.ops.setup_rate(ice, rate);
  944. }
  945. static int snd_ice1712_playback_pro_prepare(struct snd_pcm_substream *substream)
  946. {
  947. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  948. ice->playback_pro_size = snd_pcm_lib_buffer_bytes(substream);
  949. spin_lock_irq(&ice->reg_lock);
  950. outl(substream->runtime->dma_addr, ICEMT(ice, PLAYBACK_ADDR));
  951. outw((ice->playback_pro_size >> 2) - 1, ICEMT(ice, PLAYBACK_SIZE));
  952. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, PLAYBACK_COUNT));
  953. spin_unlock_irq(&ice->reg_lock);
  954. return 0;
  955. }
  956. static int snd_ice1712_playback_pro_hw_params(struct snd_pcm_substream *substream,
  957. struct snd_pcm_hw_params *hw_params)
  958. {
  959. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  960. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  961. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  962. }
  963. static int snd_ice1712_capture_pro_prepare(struct snd_pcm_substream *substream)
  964. {
  965. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  966. ice->capture_pro_size = snd_pcm_lib_buffer_bytes(substream);
  967. spin_lock_irq(&ice->reg_lock);
  968. outl(substream->runtime->dma_addr, ICEMT(ice, CAPTURE_ADDR));
  969. outw((ice->capture_pro_size >> 2) - 1, ICEMT(ice, CAPTURE_SIZE));
  970. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, CAPTURE_COUNT));
  971. spin_unlock_irq(&ice->reg_lock);
  972. return 0;
  973. }
  974. static int snd_ice1712_capture_pro_hw_params(struct snd_pcm_substream *substream,
  975. struct snd_pcm_hw_params *hw_params)
  976. {
  977. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  978. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  979. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  980. }
  981. static snd_pcm_uframes_t snd_ice1712_playback_pro_pointer(struct snd_pcm_substream *substream)
  982. {
  983. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  984. size_t ptr;
  985. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_PLAYBACK_START))
  986. return 0;
  987. ptr = ice->playback_pro_size - (inw(ICEMT(ice, PLAYBACK_SIZE)) << 2);
  988. ptr = bytes_to_frames(substream->runtime, ptr);
  989. if (ptr == substream->runtime->buffer_size)
  990. ptr = 0;
  991. return ptr;
  992. }
  993. static snd_pcm_uframes_t snd_ice1712_capture_pro_pointer(struct snd_pcm_substream *substream)
  994. {
  995. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  996. size_t ptr;
  997. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_CAPTURE_START_SHADOW))
  998. return 0;
  999. ptr = ice->capture_pro_size - (inw(ICEMT(ice, CAPTURE_SIZE)) << 2);
  1000. ptr = bytes_to_frames(substream->runtime, ptr);
  1001. if (ptr == substream->runtime->buffer_size)
  1002. ptr = 0;
  1003. return ptr;
  1004. }
  1005. static const struct snd_pcm_hardware snd_ice1712_playback_pro = {
  1006. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1007. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1008. SNDRV_PCM_INFO_MMAP_VALID |
  1009. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  1010. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  1011. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  1012. .rate_min = 4000,
  1013. .rate_max = 96000,
  1014. .channels_min = 10,
  1015. .channels_max = 10,
  1016. .buffer_bytes_max = (256*1024),
  1017. .period_bytes_min = 10 * 4 * 2,
  1018. .period_bytes_max = 131040,
  1019. .periods_min = 1,
  1020. .periods_max = 1024,
  1021. .fifo_size = 0,
  1022. };
  1023. static const struct snd_pcm_hardware snd_ice1712_capture_pro = {
  1024. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1025. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1026. SNDRV_PCM_INFO_MMAP_VALID |
  1027. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  1028. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  1029. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  1030. .rate_min = 4000,
  1031. .rate_max = 96000,
  1032. .channels_min = 12,
  1033. .channels_max = 12,
  1034. .buffer_bytes_max = (256*1024),
  1035. .period_bytes_min = 12 * 4 * 2,
  1036. .period_bytes_max = 131040,
  1037. .periods_min = 1,
  1038. .periods_max = 1024,
  1039. .fifo_size = 0,
  1040. };
  1041. static int snd_ice1712_playback_pro_open(struct snd_pcm_substream *substream)
  1042. {
  1043. struct snd_pcm_runtime *runtime = substream->runtime;
  1044. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1045. ice->playback_pro_substream = substream;
  1046. runtime->hw = snd_ice1712_playback_pro;
  1047. snd_pcm_set_sync(substream);
  1048. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1049. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1050. if (is_pro_rate_locked(ice)) {
  1051. runtime->hw.rate_min = PRO_RATE_DEFAULT;
  1052. runtime->hw.rate_max = PRO_RATE_DEFAULT;
  1053. }
  1054. if (ice->spdif.ops.open)
  1055. ice->spdif.ops.open(ice, substream);
  1056. return 0;
  1057. }
  1058. static int snd_ice1712_capture_pro_open(struct snd_pcm_substream *substream)
  1059. {
  1060. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1061. struct snd_pcm_runtime *runtime = substream->runtime;
  1062. ice->capture_pro_substream = substream;
  1063. runtime->hw = snd_ice1712_capture_pro;
  1064. snd_pcm_set_sync(substream);
  1065. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1066. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1067. if (is_pro_rate_locked(ice)) {
  1068. runtime->hw.rate_min = PRO_RATE_DEFAULT;
  1069. runtime->hw.rate_max = PRO_RATE_DEFAULT;
  1070. }
  1071. return 0;
  1072. }
  1073. static int snd_ice1712_playback_pro_close(struct snd_pcm_substream *substream)
  1074. {
  1075. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1076. if (PRO_RATE_RESET)
  1077. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1078. ice->playback_pro_substream = NULL;
  1079. if (ice->spdif.ops.close)
  1080. ice->spdif.ops.close(ice, substream);
  1081. return 0;
  1082. }
  1083. static int snd_ice1712_capture_pro_close(struct snd_pcm_substream *substream)
  1084. {
  1085. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1086. if (PRO_RATE_RESET)
  1087. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1088. ice->capture_pro_substream = NULL;
  1089. return 0;
  1090. }
  1091. static struct snd_pcm_ops snd_ice1712_playback_pro_ops = {
  1092. .open = snd_ice1712_playback_pro_open,
  1093. .close = snd_ice1712_playback_pro_close,
  1094. .ioctl = snd_pcm_lib_ioctl,
  1095. .hw_params = snd_ice1712_playback_pro_hw_params,
  1096. .hw_free = snd_ice1712_hw_free,
  1097. .prepare = snd_ice1712_playback_pro_prepare,
  1098. .trigger = snd_ice1712_pro_trigger,
  1099. .pointer = snd_ice1712_playback_pro_pointer,
  1100. };
  1101. static struct snd_pcm_ops snd_ice1712_capture_pro_ops = {
  1102. .open = snd_ice1712_capture_pro_open,
  1103. .close = snd_ice1712_capture_pro_close,
  1104. .ioctl = snd_pcm_lib_ioctl,
  1105. .hw_params = snd_ice1712_capture_pro_hw_params,
  1106. .hw_free = snd_ice1712_hw_free,
  1107. .prepare = snd_ice1712_capture_pro_prepare,
  1108. .trigger = snd_ice1712_pro_trigger,
  1109. .pointer = snd_ice1712_capture_pro_pointer,
  1110. };
  1111. static int snd_ice1712_pcm_profi(struct snd_ice1712 *ice, int device, struct snd_pcm **rpcm)
  1112. {
  1113. struct snd_pcm *pcm;
  1114. int err;
  1115. if (rpcm)
  1116. *rpcm = NULL;
  1117. err = snd_pcm_new(ice->card, "ICE1712 multi", device, 1, 1, &pcm);
  1118. if (err < 0)
  1119. return err;
  1120. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_pro_ops);
  1121. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_pro_ops);
  1122. pcm->private_data = ice;
  1123. pcm->info_flags = 0;
  1124. strcpy(pcm->name, "ICE1712 multi");
  1125. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1126. snd_dma_pci_data(ice->pci), 256*1024, 256*1024);
  1127. ice->pcm_pro = pcm;
  1128. if (rpcm)
  1129. *rpcm = pcm;
  1130. if (ice->cs8427) {
  1131. /* assign channels to iec958 */
  1132. err = snd_cs8427_iec958_build(ice->cs8427,
  1133. pcm->streams[0].substream,
  1134. pcm->streams[1].substream);
  1135. if (err < 0)
  1136. return err;
  1137. }
  1138. err = snd_ice1712_build_pro_mixer(ice);
  1139. if (err < 0)
  1140. return err;
  1141. return 0;
  1142. }
  1143. /*
  1144. * Mixer section
  1145. */
  1146. static void snd_ice1712_update_volume(struct snd_ice1712 *ice, int index)
  1147. {
  1148. unsigned int vol = ice->pro_volumes[index];
  1149. unsigned short val = 0;
  1150. val |= (vol & 0x8000) == 0 ? (96 - (vol & 0x7f)) : 0x7f;
  1151. val |= ((vol & 0x80000000) == 0 ? (96 - ((vol >> 16) & 0x7f)) : 0x7f) << 8;
  1152. outb(index, ICEMT(ice, MONITOR_INDEX));
  1153. outw(val, ICEMT(ice, MONITOR_VOLUME));
  1154. }
  1155. #define snd_ice1712_pro_mixer_switch_info snd_ctl_boolean_stereo_info
  1156. static int snd_ice1712_pro_mixer_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1157. {
  1158. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1159. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1160. kcontrol->private_value;
  1161. spin_lock_irq(&ice->reg_lock);
  1162. ucontrol->value.integer.value[0] =
  1163. !((ice->pro_volumes[priv_idx] >> 15) & 1);
  1164. ucontrol->value.integer.value[1] =
  1165. !((ice->pro_volumes[priv_idx] >> 31) & 1);
  1166. spin_unlock_irq(&ice->reg_lock);
  1167. return 0;
  1168. }
  1169. static int snd_ice1712_pro_mixer_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1170. {
  1171. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1172. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1173. kcontrol->private_value;
  1174. unsigned int nval, change;
  1175. nval = (ucontrol->value.integer.value[0] ? 0 : 0x00008000) |
  1176. (ucontrol->value.integer.value[1] ? 0 : 0x80000000);
  1177. spin_lock_irq(&ice->reg_lock);
  1178. nval |= ice->pro_volumes[priv_idx] & ~0x80008000;
  1179. change = nval != ice->pro_volumes[priv_idx];
  1180. ice->pro_volumes[priv_idx] = nval;
  1181. snd_ice1712_update_volume(ice, priv_idx);
  1182. spin_unlock_irq(&ice->reg_lock);
  1183. return change;
  1184. }
  1185. static int snd_ice1712_pro_mixer_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1186. {
  1187. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1188. uinfo->count = 2;
  1189. uinfo->value.integer.min = 0;
  1190. uinfo->value.integer.max = 96;
  1191. return 0;
  1192. }
  1193. static int snd_ice1712_pro_mixer_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1194. {
  1195. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1196. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1197. kcontrol->private_value;
  1198. spin_lock_irq(&ice->reg_lock);
  1199. ucontrol->value.integer.value[0] =
  1200. (ice->pro_volumes[priv_idx] >> 0) & 127;
  1201. ucontrol->value.integer.value[1] =
  1202. (ice->pro_volumes[priv_idx] >> 16) & 127;
  1203. spin_unlock_irq(&ice->reg_lock);
  1204. return 0;
  1205. }
  1206. static int snd_ice1712_pro_mixer_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1207. {
  1208. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1209. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1210. kcontrol->private_value;
  1211. unsigned int nval, change;
  1212. nval = (ucontrol->value.integer.value[0] & 127) |
  1213. ((ucontrol->value.integer.value[1] & 127) << 16);
  1214. spin_lock_irq(&ice->reg_lock);
  1215. nval |= ice->pro_volumes[priv_idx] & ~0x007f007f;
  1216. change = nval != ice->pro_volumes[priv_idx];
  1217. ice->pro_volumes[priv_idx] = nval;
  1218. snd_ice1712_update_volume(ice, priv_idx);
  1219. spin_unlock_irq(&ice->reg_lock);
  1220. return change;
  1221. }
  1222. static const DECLARE_TLV_DB_SCALE(db_scale_playback, -14400, 150, 0);
  1223. static struct snd_kcontrol_new snd_ice1712_multi_playback_ctrls[] = {
  1224. {
  1225. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1226. .name = "Multi Playback Switch",
  1227. .info = snd_ice1712_pro_mixer_switch_info,
  1228. .get = snd_ice1712_pro_mixer_switch_get,
  1229. .put = snd_ice1712_pro_mixer_switch_put,
  1230. .private_value = 0,
  1231. .count = 10,
  1232. },
  1233. {
  1234. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1235. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1236. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1237. .name = "Multi Playback Volume",
  1238. .info = snd_ice1712_pro_mixer_volume_info,
  1239. .get = snd_ice1712_pro_mixer_volume_get,
  1240. .put = snd_ice1712_pro_mixer_volume_put,
  1241. .private_value = 0,
  1242. .count = 10,
  1243. .tlv = { .p = db_scale_playback }
  1244. },
  1245. };
  1246. static struct snd_kcontrol_new snd_ice1712_multi_capture_analog_switch = {
  1247. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1248. .name = "H/W Multi Capture Switch",
  1249. .info = snd_ice1712_pro_mixer_switch_info,
  1250. .get = snd_ice1712_pro_mixer_switch_get,
  1251. .put = snd_ice1712_pro_mixer_switch_put,
  1252. .private_value = 10,
  1253. };
  1254. static struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_switch = {
  1255. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1256. .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, SWITCH),
  1257. .info = snd_ice1712_pro_mixer_switch_info,
  1258. .get = snd_ice1712_pro_mixer_switch_get,
  1259. .put = snd_ice1712_pro_mixer_switch_put,
  1260. .private_value = 18,
  1261. .count = 2,
  1262. };
  1263. static struct snd_kcontrol_new snd_ice1712_multi_capture_analog_volume = {
  1264. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1265. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1266. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1267. .name = "H/W Multi Capture Volume",
  1268. .info = snd_ice1712_pro_mixer_volume_info,
  1269. .get = snd_ice1712_pro_mixer_volume_get,
  1270. .put = snd_ice1712_pro_mixer_volume_put,
  1271. .private_value = 10,
  1272. .tlv = { .p = db_scale_playback }
  1273. };
  1274. static struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_volume = {
  1275. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1276. .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, VOLUME),
  1277. .info = snd_ice1712_pro_mixer_volume_info,
  1278. .get = snd_ice1712_pro_mixer_volume_get,
  1279. .put = snd_ice1712_pro_mixer_volume_put,
  1280. .private_value = 18,
  1281. .count = 2,
  1282. };
  1283. static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice)
  1284. {
  1285. struct snd_card *card = ice->card;
  1286. unsigned int idx;
  1287. int err;
  1288. /* multi-channel mixer */
  1289. for (idx = 0; idx < ARRAY_SIZE(snd_ice1712_multi_playback_ctrls); idx++) {
  1290. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_playback_ctrls[idx], ice));
  1291. if (err < 0)
  1292. return err;
  1293. }
  1294. if (ice->num_total_adcs > 0) {
  1295. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_switch;
  1296. tmp.count = ice->num_total_adcs;
  1297. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1298. if (err < 0)
  1299. return err;
  1300. }
  1301. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_switch, ice));
  1302. if (err < 0)
  1303. return err;
  1304. if (ice->num_total_adcs > 0) {
  1305. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_volume;
  1306. tmp.count = ice->num_total_adcs;
  1307. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1308. if (err < 0)
  1309. return err;
  1310. }
  1311. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_volume, ice));
  1312. if (err < 0)
  1313. return err;
  1314. /* initialize volumes */
  1315. for (idx = 0; idx < 10; idx++) {
  1316. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1317. snd_ice1712_update_volume(ice, idx);
  1318. }
  1319. for (idx = 10; idx < 10 + ice->num_total_adcs; idx++) {
  1320. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1321. snd_ice1712_update_volume(ice, idx);
  1322. }
  1323. for (idx = 18; idx < 20; idx++) {
  1324. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1325. snd_ice1712_update_volume(ice, idx);
  1326. }
  1327. return 0;
  1328. }
  1329. static void snd_ice1712_mixer_free_ac97(struct snd_ac97 *ac97)
  1330. {
  1331. struct snd_ice1712 *ice = ac97->private_data;
  1332. ice->ac97 = NULL;
  1333. }
  1334. static int snd_ice1712_ac97_mixer(struct snd_ice1712 *ice)
  1335. {
  1336. int err, bus_num = 0;
  1337. struct snd_ac97_template ac97;
  1338. struct snd_ac97_bus *pbus;
  1339. static struct snd_ac97_bus_ops con_ops = {
  1340. .write = snd_ice1712_ac97_write,
  1341. .read = snd_ice1712_ac97_read,
  1342. };
  1343. static struct snd_ac97_bus_ops pro_ops = {
  1344. .write = snd_ice1712_pro_ac97_write,
  1345. .read = snd_ice1712_pro_ac97_read,
  1346. };
  1347. if (ice_has_con_ac97(ice)) {
  1348. err = snd_ac97_bus(ice->card, bus_num++, &con_ops, NULL, &pbus);
  1349. if (err < 0)
  1350. return err;
  1351. memset(&ac97, 0, sizeof(ac97));
  1352. ac97.private_data = ice;
  1353. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1354. err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
  1355. if (err < 0)
  1356. dev_warn(ice->card->dev,
  1357. "cannot initialize ac97 for consumer, skipped\n");
  1358. else {
  1359. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_digmix_route_ac97, ice));
  1360. if (err < 0)
  1361. return err;
  1362. return 0;
  1363. }
  1364. }
  1365. if (!(ice->eeprom.data[ICE_EEP1_ACLINK] & ICE1712_CFG_PRO_I2S)) {
  1366. err = snd_ac97_bus(ice->card, bus_num, &pro_ops, NULL, &pbus);
  1367. if (err < 0)
  1368. return err;
  1369. memset(&ac97, 0, sizeof(ac97));
  1370. ac97.private_data = ice;
  1371. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1372. err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
  1373. if (err < 0)
  1374. dev_warn(ice->card->dev,
  1375. "cannot initialize pro ac97, skipped\n");
  1376. else
  1377. return 0;
  1378. }
  1379. /* I2S mixer only */
  1380. strcat(ice->card->mixername, "ICE1712 - multitrack");
  1381. return 0;
  1382. }
  1383. /*
  1384. *
  1385. */
  1386. static inline unsigned int eeprom_double(struct snd_ice1712 *ice, int idx)
  1387. {
  1388. return (unsigned int)ice->eeprom.data[idx] | ((unsigned int)ice->eeprom.data[idx + 1] << 8);
  1389. }
  1390. static void snd_ice1712_proc_read(struct snd_info_entry *entry,
  1391. struct snd_info_buffer *buffer)
  1392. {
  1393. struct snd_ice1712 *ice = entry->private_data;
  1394. unsigned int idx;
  1395. snd_iprintf(buffer, "%s\n\n", ice->card->longname);
  1396. snd_iprintf(buffer, "EEPROM:\n");
  1397. snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
  1398. snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
  1399. snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
  1400. snd_iprintf(buffer, " Codec : 0x%x\n", ice->eeprom.data[ICE_EEP1_CODEC]);
  1401. snd_iprintf(buffer, " ACLink : 0x%x\n", ice->eeprom.data[ICE_EEP1_ACLINK]);
  1402. snd_iprintf(buffer, " I2S ID : 0x%x\n", ice->eeprom.data[ICE_EEP1_I2SID]);
  1403. snd_iprintf(buffer, " S/PDIF : 0x%x\n", ice->eeprom.data[ICE_EEP1_SPDIF]);
  1404. snd_iprintf(buffer, " GPIO mask : 0x%x\n", ice->eeprom.gpiomask);
  1405. snd_iprintf(buffer, " GPIO state : 0x%x\n", ice->eeprom.gpiostate);
  1406. snd_iprintf(buffer, " GPIO direction : 0x%x\n", ice->eeprom.gpiodir);
  1407. snd_iprintf(buffer, " AC'97 main : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_MAIN_LO));
  1408. snd_iprintf(buffer, " AC'97 pcm : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_PCM_LO));
  1409. snd_iprintf(buffer, " AC'97 record : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_REC_LO));
  1410. snd_iprintf(buffer, " AC'97 record src : 0x%x\n", ice->eeprom.data[ICE_EEP1_AC97_RECSRC]);
  1411. for (idx = 0; idx < 4; idx++)
  1412. snd_iprintf(buffer, " DAC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_DAC_ID + idx]);
  1413. for (idx = 0; idx < 4; idx++)
  1414. snd_iprintf(buffer, " ADC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_ADC_ID + idx]);
  1415. for (idx = 0x1c; idx < ice->eeprom.size; idx++)
  1416. snd_iprintf(buffer, " Extra #%02i : 0x%x\n", idx, ice->eeprom.data[idx]);
  1417. snd_iprintf(buffer, "\nRegisters:\n");
  1418. snd_iprintf(buffer, " PSDOUT03 : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_PSDOUT03)));
  1419. snd_iprintf(buffer, " CAPTURE : 0x%08x\n", inl(ICEMT(ice, ROUTE_CAPTURE)));
  1420. snd_iprintf(buffer, " SPDOUT : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_SPDOUT)));
  1421. snd_iprintf(buffer, " RATE : 0x%02x\n", (unsigned)inb(ICEMT(ice, RATE)));
  1422. snd_iprintf(buffer, " GPIO_DATA : 0x%02x\n", (unsigned)snd_ice1712_get_gpio_data(ice));
  1423. snd_iprintf(buffer, " GPIO_WRITE_MASK : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK));
  1424. snd_iprintf(buffer, " GPIO_DIRECTION : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION));
  1425. }
  1426. static void snd_ice1712_proc_init(struct snd_ice1712 *ice)
  1427. {
  1428. struct snd_info_entry *entry;
  1429. if (!snd_card_proc_new(ice->card, "ice1712", &entry))
  1430. snd_info_set_text_ops(entry, ice, snd_ice1712_proc_read);
  1431. }
  1432. /*
  1433. *
  1434. */
  1435. static int snd_ice1712_eeprom_info(struct snd_kcontrol *kcontrol,
  1436. struct snd_ctl_elem_info *uinfo)
  1437. {
  1438. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  1439. uinfo->count = sizeof(struct snd_ice1712_eeprom);
  1440. return 0;
  1441. }
  1442. static int snd_ice1712_eeprom_get(struct snd_kcontrol *kcontrol,
  1443. struct snd_ctl_elem_value *ucontrol)
  1444. {
  1445. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1446. memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
  1447. return 0;
  1448. }
  1449. static struct snd_kcontrol_new snd_ice1712_eeprom = {
  1450. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  1451. .name = "ICE1712 EEPROM",
  1452. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1453. .info = snd_ice1712_eeprom_info,
  1454. .get = snd_ice1712_eeprom_get
  1455. };
  1456. /*
  1457. */
  1458. static int snd_ice1712_spdif_info(struct snd_kcontrol *kcontrol,
  1459. struct snd_ctl_elem_info *uinfo)
  1460. {
  1461. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1462. uinfo->count = 1;
  1463. return 0;
  1464. }
  1465. static int snd_ice1712_spdif_default_get(struct snd_kcontrol *kcontrol,
  1466. struct snd_ctl_elem_value *ucontrol)
  1467. {
  1468. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1469. if (ice->spdif.ops.default_get)
  1470. ice->spdif.ops.default_get(ice, ucontrol);
  1471. return 0;
  1472. }
  1473. static int snd_ice1712_spdif_default_put(struct snd_kcontrol *kcontrol,
  1474. struct snd_ctl_elem_value *ucontrol)
  1475. {
  1476. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1477. if (ice->spdif.ops.default_put)
  1478. return ice->spdif.ops.default_put(ice, ucontrol);
  1479. return 0;
  1480. }
  1481. static struct snd_kcontrol_new snd_ice1712_spdif_default =
  1482. {
  1483. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1484. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  1485. .info = snd_ice1712_spdif_info,
  1486. .get = snd_ice1712_spdif_default_get,
  1487. .put = snd_ice1712_spdif_default_put
  1488. };
  1489. static int snd_ice1712_spdif_maskc_get(struct snd_kcontrol *kcontrol,
  1490. struct snd_ctl_elem_value *ucontrol)
  1491. {
  1492. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1493. if (ice->spdif.ops.default_get) {
  1494. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1495. IEC958_AES0_PROFESSIONAL |
  1496. IEC958_AES0_CON_NOT_COPYRIGHT |
  1497. IEC958_AES0_CON_EMPHASIS;
  1498. ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
  1499. IEC958_AES1_CON_CATEGORY;
  1500. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
  1501. } else {
  1502. ucontrol->value.iec958.status[0] = 0xff;
  1503. ucontrol->value.iec958.status[1] = 0xff;
  1504. ucontrol->value.iec958.status[2] = 0xff;
  1505. ucontrol->value.iec958.status[3] = 0xff;
  1506. ucontrol->value.iec958.status[4] = 0xff;
  1507. }
  1508. return 0;
  1509. }
  1510. static int snd_ice1712_spdif_maskp_get(struct snd_kcontrol *kcontrol,
  1511. struct snd_ctl_elem_value *ucontrol)
  1512. {
  1513. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1514. if (ice->spdif.ops.default_get) {
  1515. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1516. IEC958_AES0_PROFESSIONAL |
  1517. IEC958_AES0_PRO_FS |
  1518. IEC958_AES0_PRO_EMPHASIS;
  1519. ucontrol->value.iec958.status[1] = IEC958_AES1_PRO_MODE;
  1520. } else {
  1521. ucontrol->value.iec958.status[0] = 0xff;
  1522. ucontrol->value.iec958.status[1] = 0xff;
  1523. ucontrol->value.iec958.status[2] = 0xff;
  1524. ucontrol->value.iec958.status[3] = 0xff;
  1525. ucontrol->value.iec958.status[4] = 0xff;
  1526. }
  1527. return 0;
  1528. }
  1529. static struct snd_kcontrol_new snd_ice1712_spdif_maskc =
  1530. {
  1531. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1532. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1533. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
  1534. .info = snd_ice1712_spdif_info,
  1535. .get = snd_ice1712_spdif_maskc_get,
  1536. };
  1537. static struct snd_kcontrol_new snd_ice1712_spdif_maskp =
  1538. {
  1539. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1540. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1541. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
  1542. .info = snd_ice1712_spdif_info,
  1543. .get = snd_ice1712_spdif_maskp_get,
  1544. };
  1545. static int snd_ice1712_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1546. struct snd_ctl_elem_value *ucontrol)
  1547. {
  1548. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1549. if (ice->spdif.ops.stream_get)
  1550. ice->spdif.ops.stream_get(ice, ucontrol);
  1551. return 0;
  1552. }
  1553. static int snd_ice1712_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1554. struct snd_ctl_elem_value *ucontrol)
  1555. {
  1556. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1557. if (ice->spdif.ops.stream_put)
  1558. return ice->spdif.ops.stream_put(ice, ucontrol);
  1559. return 0;
  1560. }
  1561. static struct snd_kcontrol_new snd_ice1712_spdif_stream =
  1562. {
  1563. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1564. SNDRV_CTL_ELEM_ACCESS_INACTIVE),
  1565. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1566. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
  1567. .info = snd_ice1712_spdif_info,
  1568. .get = snd_ice1712_spdif_stream_get,
  1569. .put = snd_ice1712_spdif_stream_put
  1570. };
  1571. int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol,
  1572. struct snd_ctl_elem_value *ucontrol)
  1573. {
  1574. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1575. unsigned char mask = kcontrol->private_value & 0xff;
  1576. int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
  1577. snd_ice1712_save_gpio_status(ice);
  1578. ucontrol->value.integer.value[0] =
  1579. (snd_ice1712_gpio_read(ice) & mask ? 1 : 0) ^ invert;
  1580. snd_ice1712_restore_gpio_status(ice);
  1581. return 0;
  1582. }
  1583. int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
  1584. struct snd_ctl_elem_value *ucontrol)
  1585. {
  1586. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1587. unsigned char mask = kcontrol->private_value & 0xff;
  1588. int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
  1589. unsigned int val, nval;
  1590. if (kcontrol->private_value & (1 << 31))
  1591. return -EPERM;
  1592. nval = (ucontrol->value.integer.value[0] ? mask : 0) ^ invert;
  1593. snd_ice1712_save_gpio_status(ice);
  1594. val = snd_ice1712_gpio_read(ice);
  1595. nval |= val & ~mask;
  1596. if (val != nval)
  1597. snd_ice1712_gpio_write(ice, nval);
  1598. snd_ice1712_restore_gpio_status(ice);
  1599. return val != nval;
  1600. }
  1601. /*
  1602. * rate
  1603. */
  1604. static int snd_ice1712_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
  1605. struct snd_ctl_elem_info *uinfo)
  1606. {
  1607. static const char * const texts[] = {
  1608. "8000", /* 0: 6 */
  1609. "9600", /* 1: 3 */
  1610. "11025", /* 2: 10 */
  1611. "12000", /* 3: 2 */
  1612. "16000", /* 4: 5 */
  1613. "22050", /* 5: 9 */
  1614. "24000", /* 6: 1 */
  1615. "32000", /* 7: 4 */
  1616. "44100", /* 8: 8 */
  1617. "48000", /* 9: 0 */
  1618. "64000", /* 10: 15 */
  1619. "88200", /* 11: 11 */
  1620. "96000", /* 12: 7 */
  1621. "IEC958 Input", /* 13: -- */
  1622. };
  1623. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1624. uinfo->count = 1;
  1625. uinfo->value.enumerated.items = 14;
  1626. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1627. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1628. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1629. return 0;
  1630. }
  1631. static int snd_ice1712_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
  1632. struct snd_ctl_elem_value *ucontrol)
  1633. {
  1634. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1635. static const unsigned char xlate[16] = {
  1636. 9, 6, 3, 1, 7, 4, 0, 12, 8, 5, 2, 11, 255, 255, 255, 10
  1637. };
  1638. unsigned char val;
  1639. spin_lock_irq(&ice->reg_lock);
  1640. if (is_spdif_master(ice)) {
  1641. ucontrol->value.enumerated.item[0] = 13;
  1642. } else {
  1643. val = xlate[inb(ICEMT(ice, RATE)) & 15];
  1644. if (val == 255) {
  1645. snd_BUG();
  1646. val = 0;
  1647. }
  1648. ucontrol->value.enumerated.item[0] = val;
  1649. }
  1650. spin_unlock_irq(&ice->reg_lock);
  1651. return 0;
  1652. }
  1653. static int snd_ice1712_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
  1654. struct snd_ctl_elem_value *ucontrol)
  1655. {
  1656. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1657. static const unsigned int xrate[13] = {
  1658. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1659. 32000, 44100, 48000, 64000, 88200, 96000
  1660. };
  1661. unsigned char oval;
  1662. int change = 0;
  1663. spin_lock_irq(&ice->reg_lock);
  1664. oval = inb(ICEMT(ice, RATE));
  1665. if (ucontrol->value.enumerated.item[0] == 13) {
  1666. outb(oval | ICE1712_SPDIF_MASTER, ICEMT(ice, RATE));
  1667. } else {
  1668. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1669. spin_unlock_irq(&ice->reg_lock);
  1670. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 1);
  1671. spin_lock_irq(&ice->reg_lock);
  1672. }
  1673. change = inb(ICEMT(ice, RATE)) != oval;
  1674. spin_unlock_irq(&ice->reg_lock);
  1675. if ((oval & ICE1712_SPDIF_MASTER) !=
  1676. (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER))
  1677. snd_ice1712_set_input_clock_source(ice, is_spdif_master(ice));
  1678. return change;
  1679. }
  1680. static struct snd_kcontrol_new snd_ice1712_pro_internal_clock = {
  1681. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1682. .name = "Multi Track Internal Clock",
  1683. .info = snd_ice1712_pro_internal_clock_info,
  1684. .get = snd_ice1712_pro_internal_clock_get,
  1685. .put = snd_ice1712_pro_internal_clock_put
  1686. };
  1687. static int snd_ice1712_pro_internal_clock_default_info(struct snd_kcontrol *kcontrol,
  1688. struct snd_ctl_elem_info *uinfo)
  1689. {
  1690. static const char * const texts[] = {
  1691. "8000", /* 0: 6 */
  1692. "9600", /* 1: 3 */
  1693. "11025", /* 2: 10 */
  1694. "12000", /* 3: 2 */
  1695. "16000", /* 4: 5 */
  1696. "22050", /* 5: 9 */
  1697. "24000", /* 6: 1 */
  1698. "32000", /* 7: 4 */
  1699. "44100", /* 8: 8 */
  1700. "48000", /* 9: 0 */
  1701. "64000", /* 10: 15 */
  1702. "88200", /* 11: 11 */
  1703. "96000", /* 12: 7 */
  1704. /* "IEC958 Input", 13: -- */
  1705. };
  1706. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1707. uinfo->count = 1;
  1708. uinfo->value.enumerated.items = 13;
  1709. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1710. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1711. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1712. return 0;
  1713. }
  1714. static int snd_ice1712_pro_internal_clock_default_get(struct snd_kcontrol *kcontrol,
  1715. struct snd_ctl_elem_value *ucontrol)
  1716. {
  1717. int val;
  1718. static const unsigned int xrate[13] = {
  1719. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1720. 32000, 44100, 48000, 64000, 88200, 96000
  1721. };
  1722. for (val = 0; val < 13; val++) {
  1723. if (xrate[val] == PRO_RATE_DEFAULT)
  1724. break;
  1725. }
  1726. ucontrol->value.enumerated.item[0] = val;
  1727. return 0;
  1728. }
  1729. static int snd_ice1712_pro_internal_clock_default_put(struct snd_kcontrol *kcontrol,
  1730. struct snd_ctl_elem_value *ucontrol)
  1731. {
  1732. static const unsigned int xrate[13] = {
  1733. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1734. 32000, 44100, 48000, 64000, 88200, 96000
  1735. };
  1736. unsigned char oval;
  1737. int change = 0;
  1738. oval = PRO_RATE_DEFAULT;
  1739. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1740. change = PRO_RATE_DEFAULT != oval;
  1741. return change;
  1742. }
  1743. static struct snd_kcontrol_new snd_ice1712_pro_internal_clock_default = {
  1744. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1745. .name = "Multi Track Internal Clock Default",
  1746. .info = snd_ice1712_pro_internal_clock_default_info,
  1747. .get = snd_ice1712_pro_internal_clock_default_get,
  1748. .put = snd_ice1712_pro_internal_clock_default_put
  1749. };
  1750. #define snd_ice1712_pro_rate_locking_info snd_ctl_boolean_mono_info
  1751. static int snd_ice1712_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
  1752. struct snd_ctl_elem_value *ucontrol)
  1753. {
  1754. ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
  1755. return 0;
  1756. }
  1757. static int snd_ice1712_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
  1758. struct snd_ctl_elem_value *ucontrol)
  1759. {
  1760. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1761. int change = 0, nval;
  1762. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1763. spin_lock_irq(&ice->reg_lock);
  1764. change = PRO_RATE_LOCKED != nval;
  1765. PRO_RATE_LOCKED = nval;
  1766. spin_unlock_irq(&ice->reg_lock);
  1767. return change;
  1768. }
  1769. static struct snd_kcontrol_new snd_ice1712_pro_rate_locking = {
  1770. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1771. .name = "Multi Track Rate Locking",
  1772. .info = snd_ice1712_pro_rate_locking_info,
  1773. .get = snd_ice1712_pro_rate_locking_get,
  1774. .put = snd_ice1712_pro_rate_locking_put
  1775. };
  1776. #define snd_ice1712_pro_rate_reset_info snd_ctl_boolean_mono_info
  1777. static int snd_ice1712_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
  1778. struct snd_ctl_elem_value *ucontrol)
  1779. {
  1780. ucontrol->value.integer.value[0] = PRO_RATE_RESET;
  1781. return 0;
  1782. }
  1783. static int snd_ice1712_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
  1784. struct snd_ctl_elem_value *ucontrol)
  1785. {
  1786. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1787. int change = 0, nval;
  1788. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1789. spin_lock_irq(&ice->reg_lock);
  1790. change = PRO_RATE_RESET != nval;
  1791. PRO_RATE_RESET = nval;
  1792. spin_unlock_irq(&ice->reg_lock);
  1793. return change;
  1794. }
  1795. static struct snd_kcontrol_new snd_ice1712_pro_rate_reset = {
  1796. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1797. .name = "Multi Track Rate Reset",
  1798. .info = snd_ice1712_pro_rate_reset_info,
  1799. .get = snd_ice1712_pro_rate_reset_get,
  1800. .put = snd_ice1712_pro_rate_reset_put
  1801. };
  1802. /*
  1803. * routing
  1804. */
  1805. static int snd_ice1712_pro_route_info(struct snd_kcontrol *kcontrol,
  1806. struct snd_ctl_elem_info *uinfo)
  1807. {
  1808. static const char * const texts[] = {
  1809. "PCM Out", /* 0 */
  1810. "H/W In 0", "H/W In 1", "H/W In 2", "H/W In 3", /* 1-4 */
  1811. "H/W In 4", "H/W In 5", "H/W In 6", "H/W In 7", /* 5-8 */
  1812. "IEC958 In L", "IEC958 In R", /* 9-10 */
  1813. "Digital Mixer", /* 11 - optional */
  1814. };
  1815. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1816. uinfo->count = 1;
  1817. uinfo->value.enumerated.items =
  1818. snd_ctl_get_ioffidx(kcontrol, &uinfo->id) < 2 ? 12 : 11;
  1819. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1820. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1821. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1822. return 0;
  1823. }
  1824. static int snd_ice1712_pro_route_analog_get(struct snd_kcontrol *kcontrol,
  1825. struct snd_ctl_elem_value *ucontrol)
  1826. {
  1827. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1828. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1829. unsigned int val, cval;
  1830. spin_lock_irq(&ice->reg_lock);
  1831. val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1832. cval = inl(ICEMT(ice, ROUTE_CAPTURE));
  1833. spin_unlock_irq(&ice->reg_lock);
  1834. val >>= ((idx % 2) * 8) + ((idx / 2) * 2);
  1835. val &= 3;
  1836. cval >>= ((idx / 2) * 8) + ((idx % 2) * 4);
  1837. if (val == 1 && idx < 2)
  1838. ucontrol->value.enumerated.item[0] = 11;
  1839. else if (val == 2)
  1840. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1841. else if (val == 3)
  1842. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1843. else
  1844. ucontrol->value.enumerated.item[0] = 0;
  1845. return 0;
  1846. }
  1847. static int snd_ice1712_pro_route_analog_put(struct snd_kcontrol *kcontrol,
  1848. struct snd_ctl_elem_value *ucontrol)
  1849. {
  1850. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1851. int change, shift;
  1852. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1853. unsigned int val, old_val, nval;
  1854. /* update PSDOUT */
  1855. if (ucontrol->value.enumerated.item[0] >= 11)
  1856. nval = idx < 2 ? 1 : 0; /* dig mixer (or pcm) */
  1857. else if (ucontrol->value.enumerated.item[0] >= 9)
  1858. nval = 3; /* spdif in */
  1859. else if (ucontrol->value.enumerated.item[0] >= 1)
  1860. nval = 2; /* analog in */
  1861. else
  1862. nval = 0; /* pcm */
  1863. shift = ((idx % 2) * 8) + ((idx / 2) * 2);
  1864. spin_lock_irq(&ice->reg_lock);
  1865. val = old_val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1866. val &= ~(0x03 << shift);
  1867. val |= nval << shift;
  1868. change = val != old_val;
  1869. if (change)
  1870. outw(val, ICEMT(ice, ROUTE_PSDOUT03));
  1871. spin_unlock_irq(&ice->reg_lock);
  1872. if (nval < 2) /* dig mixer of pcm */
  1873. return change;
  1874. /* update CAPTURE */
  1875. spin_lock_irq(&ice->reg_lock);
  1876. val = old_val = inl(ICEMT(ice, ROUTE_CAPTURE));
  1877. shift = ((idx / 2) * 8) + ((idx % 2) * 4);
  1878. if (nval == 2) { /* analog in */
  1879. nval = ucontrol->value.enumerated.item[0] - 1;
  1880. val &= ~(0x07 << shift);
  1881. val |= nval << shift;
  1882. } else { /* spdif in */
  1883. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1884. val &= ~(0x08 << shift);
  1885. val |= nval << shift;
  1886. }
  1887. if (val != old_val) {
  1888. change = 1;
  1889. outl(val, ICEMT(ice, ROUTE_CAPTURE));
  1890. }
  1891. spin_unlock_irq(&ice->reg_lock);
  1892. return change;
  1893. }
  1894. static int snd_ice1712_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
  1895. struct snd_ctl_elem_value *ucontrol)
  1896. {
  1897. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1898. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1899. unsigned int val, cval;
  1900. val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1901. cval = (val >> (idx * 4 + 8)) & 0x0f;
  1902. val = (val >> (idx * 2)) & 0x03;
  1903. if (val == 1)
  1904. ucontrol->value.enumerated.item[0] = 11;
  1905. else if (val == 2)
  1906. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1907. else if (val == 3)
  1908. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1909. else
  1910. ucontrol->value.enumerated.item[0] = 0;
  1911. return 0;
  1912. }
  1913. static int snd_ice1712_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
  1914. struct snd_ctl_elem_value *ucontrol)
  1915. {
  1916. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1917. int change, shift;
  1918. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1919. unsigned int val, old_val, nval;
  1920. /* update SPDOUT */
  1921. spin_lock_irq(&ice->reg_lock);
  1922. val = old_val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1923. if (ucontrol->value.enumerated.item[0] >= 11)
  1924. nval = 1;
  1925. else if (ucontrol->value.enumerated.item[0] >= 9)
  1926. nval = 3;
  1927. else if (ucontrol->value.enumerated.item[0] >= 1)
  1928. nval = 2;
  1929. else
  1930. nval = 0;
  1931. shift = idx * 2;
  1932. val &= ~(0x03 << shift);
  1933. val |= nval << shift;
  1934. shift = idx * 4 + 8;
  1935. if (nval == 2) {
  1936. nval = ucontrol->value.enumerated.item[0] - 1;
  1937. val &= ~(0x07 << shift);
  1938. val |= nval << shift;
  1939. } else if (nval == 3) {
  1940. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1941. val &= ~(0x08 << shift);
  1942. val |= nval << shift;
  1943. }
  1944. change = val != old_val;
  1945. if (change)
  1946. outw(val, ICEMT(ice, ROUTE_SPDOUT));
  1947. spin_unlock_irq(&ice->reg_lock);
  1948. return change;
  1949. }
  1950. static struct snd_kcontrol_new snd_ice1712_mixer_pro_analog_route = {
  1951. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1952. .name = "H/W Playback Route",
  1953. .info = snd_ice1712_pro_route_info,
  1954. .get = snd_ice1712_pro_route_analog_get,
  1955. .put = snd_ice1712_pro_route_analog_put,
  1956. };
  1957. static struct snd_kcontrol_new snd_ice1712_mixer_pro_spdif_route = {
  1958. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1959. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
  1960. .info = snd_ice1712_pro_route_info,
  1961. .get = snd_ice1712_pro_route_spdif_get,
  1962. .put = snd_ice1712_pro_route_spdif_put,
  1963. .count = 2,
  1964. };
  1965. static int snd_ice1712_pro_volume_rate_info(struct snd_kcontrol *kcontrol,
  1966. struct snd_ctl_elem_info *uinfo)
  1967. {
  1968. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1969. uinfo->count = 1;
  1970. uinfo->value.integer.min = 0;
  1971. uinfo->value.integer.max = 255;
  1972. return 0;
  1973. }
  1974. static int snd_ice1712_pro_volume_rate_get(struct snd_kcontrol *kcontrol,
  1975. struct snd_ctl_elem_value *ucontrol)
  1976. {
  1977. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1978. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_RATE));
  1979. return 0;
  1980. }
  1981. static int snd_ice1712_pro_volume_rate_put(struct snd_kcontrol *kcontrol,
  1982. struct snd_ctl_elem_value *ucontrol)
  1983. {
  1984. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1985. int change;
  1986. spin_lock_irq(&ice->reg_lock);
  1987. change = inb(ICEMT(ice, MONITOR_RATE)) != ucontrol->value.integer.value[0];
  1988. outb(ucontrol->value.integer.value[0], ICEMT(ice, MONITOR_RATE));
  1989. spin_unlock_irq(&ice->reg_lock);
  1990. return change;
  1991. }
  1992. static struct snd_kcontrol_new snd_ice1712_mixer_pro_volume_rate = {
  1993. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1994. .name = "Multi Track Volume Rate",
  1995. .info = snd_ice1712_pro_volume_rate_info,
  1996. .get = snd_ice1712_pro_volume_rate_get,
  1997. .put = snd_ice1712_pro_volume_rate_put
  1998. };
  1999. static int snd_ice1712_pro_peak_info(struct snd_kcontrol *kcontrol,
  2000. struct snd_ctl_elem_info *uinfo)
  2001. {
  2002. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  2003. uinfo->count = 22;
  2004. uinfo->value.integer.min = 0;
  2005. uinfo->value.integer.max = 255;
  2006. return 0;
  2007. }
  2008. static int snd_ice1712_pro_peak_get(struct snd_kcontrol *kcontrol,
  2009. struct snd_ctl_elem_value *ucontrol)
  2010. {
  2011. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  2012. int idx;
  2013. spin_lock_irq(&ice->reg_lock);
  2014. for (idx = 0; idx < 22; idx++) {
  2015. outb(idx, ICEMT(ice, MONITOR_PEAKINDEX));
  2016. ucontrol->value.integer.value[idx] = inb(ICEMT(ice, MONITOR_PEAKDATA));
  2017. }
  2018. spin_unlock_irq(&ice->reg_lock);
  2019. return 0;
  2020. }
  2021. static struct snd_kcontrol_new snd_ice1712_mixer_pro_peak = {
  2022. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  2023. .name = "Multi Track Peak",
  2024. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  2025. .info = snd_ice1712_pro_peak_info,
  2026. .get = snd_ice1712_pro_peak_get
  2027. };
  2028. /*
  2029. *
  2030. */
  2031. /*
  2032. * list of available boards
  2033. */
  2034. static struct snd_ice1712_card_info *card_tables[] = {
  2035. snd_ice1712_hoontech_cards,
  2036. snd_ice1712_delta_cards,
  2037. snd_ice1712_ews_cards,
  2038. NULL,
  2039. };
  2040. static unsigned char snd_ice1712_read_i2c(struct snd_ice1712 *ice,
  2041. unsigned char dev,
  2042. unsigned char addr)
  2043. {
  2044. long t = 0x10000;
  2045. outb(addr, ICEREG(ice, I2C_BYTE_ADDR));
  2046. outb(dev & ~ICE1712_I2C_WRITE, ICEREG(ice, I2C_DEV_ADDR));
  2047. while (t-- > 0 && (inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_BUSY)) ;
  2048. return inb(ICEREG(ice, I2C_DATA));
  2049. }
  2050. static int snd_ice1712_read_eeprom(struct snd_ice1712 *ice,
  2051. const char *modelname)
  2052. {
  2053. int dev = 0xa0; /* EEPROM device address */
  2054. unsigned int i, size;
  2055. struct snd_ice1712_card_info * const *tbl, *c;
  2056. if (!modelname || !*modelname) {
  2057. ice->eeprom.subvendor = 0;
  2058. if ((inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_EEPROM) != 0)
  2059. ice->eeprom.subvendor = (snd_ice1712_read_i2c(ice, dev, 0x00) << 0) |
  2060. (snd_ice1712_read_i2c(ice, dev, 0x01) << 8) |
  2061. (snd_ice1712_read_i2c(ice, dev, 0x02) << 16) |
  2062. (snd_ice1712_read_i2c(ice, dev, 0x03) << 24);
  2063. if (ice->eeprom.subvendor == 0 ||
  2064. ice->eeprom.subvendor == (unsigned int)-1) {
  2065. /* invalid subvendor from EEPROM, try the PCI subststem ID instead */
  2066. u16 vendor, device;
  2067. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
  2068. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
  2069. ice->eeprom.subvendor = ((unsigned int)swab16(vendor) << 16) | swab16(device);
  2070. if (ice->eeprom.subvendor == 0 || ice->eeprom.subvendor == (unsigned int)-1) {
  2071. dev_err(ice->card->dev,
  2072. "No valid ID is found\n");
  2073. return -ENXIO;
  2074. }
  2075. }
  2076. }
  2077. for (tbl = card_tables; *tbl; tbl++) {
  2078. for (c = *tbl; c->subvendor; c++) {
  2079. if (modelname && c->model && !strcmp(modelname, c->model)) {
  2080. dev_info(ice->card->dev,
  2081. "Using board model %s\n", c->name);
  2082. ice->eeprom.subvendor = c->subvendor;
  2083. } else if (c->subvendor != ice->eeprom.subvendor)
  2084. continue;
  2085. if (!c->eeprom_size || !c->eeprom_data)
  2086. goto found;
  2087. /* if the EEPROM is given by the driver, use it */
  2088. dev_dbg(ice->card->dev, "using the defined eeprom..\n");
  2089. ice->eeprom.version = 1;
  2090. ice->eeprom.size = c->eeprom_size + 6;
  2091. memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
  2092. goto read_skipped;
  2093. }
  2094. }
  2095. dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
  2096. ice->eeprom.subvendor);
  2097. found:
  2098. ice->eeprom.size = snd_ice1712_read_i2c(ice, dev, 0x04);
  2099. if (ice->eeprom.size < 6)
  2100. ice->eeprom.size = 32; /* FIXME: any cards without the correct size? */
  2101. else if (ice->eeprom.size > 32) {
  2102. dev_err(ice->card->dev,
  2103. "invalid EEPROM (size = %i)\n", ice->eeprom.size);
  2104. return -EIO;
  2105. }
  2106. ice->eeprom.version = snd_ice1712_read_i2c(ice, dev, 0x05);
  2107. if (ice->eeprom.version != 1) {
  2108. dev_err(ice->card->dev, "invalid EEPROM version %i\n",
  2109. ice->eeprom.version);
  2110. /* return -EIO; */
  2111. }
  2112. size = ice->eeprom.size - 6;
  2113. for (i = 0; i < size; i++)
  2114. ice->eeprom.data[i] = snd_ice1712_read_i2c(ice, dev, i + 6);
  2115. read_skipped:
  2116. ice->eeprom.gpiomask = ice->eeprom.data[ICE_EEP1_GPIO_MASK];
  2117. ice->eeprom.gpiostate = ice->eeprom.data[ICE_EEP1_GPIO_STATE];
  2118. ice->eeprom.gpiodir = ice->eeprom.data[ICE_EEP1_GPIO_DIR];
  2119. return 0;
  2120. }
  2121. static int snd_ice1712_chip_init(struct snd_ice1712 *ice)
  2122. {
  2123. outb(ICE1712_RESET | ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2124. udelay(200);
  2125. outb(ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2126. udelay(200);
  2127. if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_DMX6FIRE &&
  2128. !ice->dxr_enable)
  2129. /* Set eeprom value to limit active ADCs and DACs to 6;
  2130. * Also disable AC97 as no hardware in standard 6fire card/box
  2131. * Note: DXR extensions are not currently supported
  2132. */
  2133. ice->eeprom.data[ICE_EEP1_CODEC] = 0x3a;
  2134. pci_write_config_byte(ice->pci, 0x60, ice->eeprom.data[ICE_EEP1_CODEC]);
  2135. pci_write_config_byte(ice->pci, 0x61, ice->eeprom.data[ICE_EEP1_ACLINK]);
  2136. pci_write_config_byte(ice->pci, 0x62, ice->eeprom.data[ICE_EEP1_I2SID]);
  2137. pci_write_config_byte(ice->pci, 0x63, ice->eeprom.data[ICE_EEP1_SPDIF]);
  2138. if (ice->eeprom.subvendor != ICE1712_SUBDEVICE_STDSP24) {
  2139. ice->gpio.write_mask = ice->eeprom.gpiomask;
  2140. ice->gpio.direction = ice->eeprom.gpiodir;
  2141. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
  2142. ice->eeprom.gpiomask);
  2143. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
  2144. ice->eeprom.gpiodir);
  2145. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2146. ice->eeprom.gpiostate);
  2147. } else {
  2148. ice->gpio.write_mask = 0xc0;
  2149. ice->gpio.direction = 0xff;
  2150. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, 0xc0);
  2151. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, 0xff);
  2152. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2153. ICE1712_STDSP24_CLOCK_BIT);
  2154. }
  2155. snd_ice1712_write(ice, ICE1712_IREG_PRO_POWERDOWN, 0);
  2156. if (!(ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) {
  2157. outb(ICE1712_AC97_WARM, ICEREG(ice, AC97_CMD));
  2158. udelay(100);
  2159. outb(0, ICEREG(ice, AC97_CMD));
  2160. udelay(200);
  2161. snd_ice1712_write(ice, ICE1712_IREG_CONSUMER_POWERDOWN, 0);
  2162. }
  2163. snd_ice1712_set_pro_rate(ice, 48000, 1);
  2164. /* unmask used interrupts */
  2165. outb(((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) == 0 ?
  2166. ICE1712_IRQ_MPU2 : 0) |
  2167. ((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97) ?
  2168. ICE1712_IRQ_PBKDS | ICE1712_IRQ_CONCAP | ICE1712_IRQ_CONPBK : 0),
  2169. ICEREG(ice, IRQMASK));
  2170. outb(0x00, ICEMT(ice, IRQ));
  2171. return 0;
  2172. }
  2173. int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice)
  2174. {
  2175. int err;
  2176. struct snd_kcontrol *kctl;
  2177. if (snd_BUG_ON(!ice->pcm_pro))
  2178. return -EIO;
  2179. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_default, ice));
  2180. if (err < 0)
  2181. return err;
  2182. kctl->id.device = ice->pcm_pro->device;
  2183. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskc, ice));
  2184. if (err < 0)
  2185. return err;
  2186. kctl->id.device = ice->pcm_pro->device;
  2187. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskp, ice));
  2188. if (err < 0)
  2189. return err;
  2190. kctl->id.device = ice->pcm_pro->device;
  2191. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_stream, ice));
  2192. if (err < 0)
  2193. return err;
  2194. kctl->id.device = ice->pcm_pro->device;
  2195. ice->spdif.stream_ctl = kctl;
  2196. return 0;
  2197. }
  2198. static int snd_ice1712_build_controls(struct snd_ice1712 *ice)
  2199. {
  2200. int err;
  2201. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_eeprom, ice));
  2202. if (err < 0)
  2203. return err;
  2204. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock, ice));
  2205. if (err < 0)
  2206. return err;
  2207. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock_default, ice));
  2208. if (err < 0)
  2209. return err;
  2210. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_locking, ice));
  2211. if (err < 0)
  2212. return err;
  2213. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_reset, ice));
  2214. if (err < 0)
  2215. return err;
  2216. if (ice->num_total_dacs > 0) {
  2217. struct snd_kcontrol_new tmp = snd_ice1712_mixer_pro_analog_route;
  2218. tmp.count = ice->num_total_dacs;
  2219. err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
  2220. if (err < 0)
  2221. return err;
  2222. }
  2223. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice));
  2224. if (err < 0)
  2225. return err;
  2226. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_volume_rate, ice));
  2227. if (err < 0)
  2228. return err;
  2229. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_peak, ice));
  2230. if (err < 0)
  2231. return err;
  2232. return 0;
  2233. }
  2234. static int snd_ice1712_free(struct snd_ice1712 *ice)
  2235. {
  2236. if (!ice->port)
  2237. goto __hw_end;
  2238. /* mask all interrupts */
  2239. outb(0xc0, ICEMT(ice, IRQ));
  2240. outb(0xff, ICEREG(ice, IRQMASK));
  2241. /* --- */
  2242. __hw_end:
  2243. if (ice->irq >= 0)
  2244. free_irq(ice->irq, ice);
  2245. if (ice->port)
  2246. pci_release_regions(ice->pci);
  2247. snd_ice1712_akm4xxx_free(ice);
  2248. pci_disable_device(ice->pci);
  2249. kfree(ice->spec);
  2250. kfree(ice);
  2251. return 0;
  2252. }
  2253. static int snd_ice1712_dev_free(struct snd_device *device)
  2254. {
  2255. struct snd_ice1712 *ice = device->device_data;
  2256. return snd_ice1712_free(ice);
  2257. }
  2258. static int snd_ice1712_create(struct snd_card *card,
  2259. struct pci_dev *pci,
  2260. const char *modelname,
  2261. int omni,
  2262. int cs8427_timeout,
  2263. int dxr_enable,
  2264. struct snd_ice1712 **r_ice1712)
  2265. {
  2266. struct snd_ice1712 *ice;
  2267. int err;
  2268. static struct snd_device_ops ops = {
  2269. .dev_free = snd_ice1712_dev_free,
  2270. };
  2271. *r_ice1712 = NULL;
  2272. /* enable PCI device */
  2273. err = pci_enable_device(pci);
  2274. if (err < 0)
  2275. return err;
  2276. /* check, if we can restrict PCI DMA transfers to 28 bits */
  2277. if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 ||
  2278. pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) {
  2279. dev_err(card->dev,
  2280. "architecture does not support 28bit PCI busmaster DMA\n");
  2281. pci_disable_device(pci);
  2282. return -ENXIO;
  2283. }
  2284. ice = kzalloc(sizeof(*ice), GFP_KERNEL);
  2285. if (ice == NULL) {
  2286. pci_disable_device(pci);
  2287. return -ENOMEM;
  2288. }
  2289. ice->omni = omni ? 1 : 0;
  2290. if (cs8427_timeout < 1)
  2291. cs8427_timeout = 1;
  2292. else if (cs8427_timeout > 1000)
  2293. cs8427_timeout = 1000;
  2294. ice->cs8427_timeout = cs8427_timeout;
  2295. ice->dxr_enable = dxr_enable;
  2296. spin_lock_init(&ice->reg_lock);
  2297. mutex_init(&ice->gpio_mutex);
  2298. mutex_init(&ice->i2c_mutex);
  2299. mutex_init(&ice->open_mutex);
  2300. ice->gpio.set_mask = snd_ice1712_set_gpio_mask;
  2301. ice->gpio.get_mask = snd_ice1712_get_gpio_mask;
  2302. ice->gpio.set_dir = snd_ice1712_set_gpio_dir;
  2303. ice->gpio.get_dir = snd_ice1712_get_gpio_dir;
  2304. ice->gpio.set_data = snd_ice1712_set_gpio_data;
  2305. ice->gpio.get_data = snd_ice1712_get_gpio_data;
  2306. ice->spdif.cs8403_bits =
  2307. ice->spdif.cs8403_stream_bits = (0x01 | /* consumer format */
  2308. 0x10 | /* no emphasis */
  2309. 0x20); /* PCM encoder/decoder */
  2310. ice->card = card;
  2311. ice->pci = pci;
  2312. ice->irq = -1;
  2313. pci_set_master(pci);
  2314. /* disable legacy emulation */
  2315. pci_write_config_word(ice->pci, 0x40, 0x807f);
  2316. pci_write_config_word(ice->pci, 0x42, 0x0006);
  2317. snd_ice1712_proc_init(ice);
  2318. synchronize_irq(pci->irq);
  2319. card->private_data = ice;
  2320. err = pci_request_regions(pci, "ICE1712");
  2321. if (err < 0) {
  2322. kfree(ice);
  2323. pci_disable_device(pci);
  2324. return err;
  2325. }
  2326. ice->port = pci_resource_start(pci, 0);
  2327. ice->ddma_port = pci_resource_start(pci, 1);
  2328. ice->dmapath_port = pci_resource_start(pci, 2);
  2329. ice->profi_port = pci_resource_start(pci, 3);
  2330. if (request_irq(pci->irq, snd_ice1712_interrupt, IRQF_SHARED,
  2331. KBUILD_MODNAME, ice)) {
  2332. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  2333. snd_ice1712_free(ice);
  2334. return -EIO;
  2335. }
  2336. ice->irq = pci->irq;
  2337. if (snd_ice1712_read_eeprom(ice, modelname) < 0) {
  2338. snd_ice1712_free(ice);
  2339. return -EIO;
  2340. }
  2341. if (snd_ice1712_chip_init(ice) < 0) {
  2342. snd_ice1712_free(ice);
  2343. return -EIO;
  2344. }
  2345. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
  2346. if (err < 0) {
  2347. snd_ice1712_free(ice);
  2348. return err;
  2349. }
  2350. *r_ice1712 = ice;
  2351. return 0;
  2352. }
  2353. /*
  2354. *
  2355. * Registration
  2356. *
  2357. */
  2358. static struct snd_ice1712_card_info no_matched;
  2359. static int snd_ice1712_probe(struct pci_dev *pci,
  2360. const struct pci_device_id *pci_id)
  2361. {
  2362. static int dev;
  2363. struct snd_card *card;
  2364. struct snd_ice1712 *ice;
  2365. int pcm_dev = 0, err;
  2366. struct snd_ice1712_card_info * const *tbl, *c;
  2367. if (dev >= SNDRV_CARDS)
  2368. return -ENODEV;
  2369. if (!enable[dev]) {
  2370. dev++;
  2371. return -ENOENT;
  2372. }
  2373. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  2374. 0, &card);
  2375. if (err < 0)
  2376. return err;
  2377. strcpy(card->driver, "ICE1712");
  2378. strcpy(card->shortname, "ICEnsemble ICE1712");
  2379. err = snd_ice1712_create(card, pci, model[dev], omni[dev],
  2380. cs8427_timeout[dev], dxr_enable[dev], &ice);
  2381. if (err < 0) {
  2382. snd_card_free(card);
  2383. return err;
  2384. }
  2385. for (tbl = card_tables; *tbl; tbl++) {
  2386. for (c = *tbl; c->subvendor; c++) {
  2387. if (c->subvendor == ice->eeprom.subvendor) {
  2388. ice->card_info = c;
  2389. strcpy(card->shortname, c->name);
  2390. if (c->driver) /* specific driver? */
  2391. strcpy(card->driver, c->driver);
  2392. if (c->chip_init) {
  2393. err = c->chip_init(ice);
  2394. if (err < 0) {
  2395. snd_card_free(card);
  2396. return err;
  2397. }
  2398. }
  2399. goto __found;
  2400. }
  2401. }
  2402. }
  2403. c = &no_matched;
  2404. __found:
  2405. err = snd_ice1712_pcm_profi(ice, pcm_dev++, NULL);
  2406. if (err < 0) {
  2407. snd_card_free(card);
  2408. return err;
  2409. }
  2410. if (ice_has_con_ac97(ice)) {
  2411. err = snd_ice1712_pcm(ice, pcm_dev++, NULL);
  2412. if (err < 0) {
  2413. snd_card_free(card);
  2414. return err;
  2415. }
  2416. }
  2417. err = snd_ice1712_ac97_mixer(ice);
  2418. if (err < 0) {
  2419. snd_card_free(card);
  2420. return err;
  2421. }
  2422. err = snd_ice1712_build_controls(ice);
  2423. if (err < 0) {
  2424. snd_card_free(card);
  2425. return err;
  2426. }
  2427. if (c->build_controls) {
  2428. err = c->build_controls(ice);
  2429. if (err < 0) {
  2430. snd_card_free(card);
  2431. return err;
  2432. }
  2433. }
  2434. if (ice_has_con_ac97(ice)) {
  2435. err = snd_ice1712_pcm_ds(ice, pcm_dev++, NULL);
  2436. if (err < 0) {
  2437. snd_card_free(card);
  2438. return err;
  2439. }
  2440. }
  2441. if (!c->no_mpu401) {
  2442. err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
  2443. ICEREG(ice, MPU1_CTRL),
  2444. c->mpu401_1_info_flags |
  2445. MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
  2446. -1, &ice->rmidi[0]);
  2447. if (err < 0) {
  2448. snd_card_free(card);
  2449. return err;
  2450. }
  2451. if (c->mpu401_1_name)
  2452. /* Preferred name available in card_info */
  2453. snprintf(ice->rmidi[0]->name,
  2454. sizeof(ice->rmidi[0]->name),
  2455. "%s %d", c->mpu401_1_name, card->number);
  2456. if (ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) {
  2457. /* 2nd port used */
  2458. err = snd_mpu401_uart_new(card, 1, MPU401_HW_ICE1712,
  2459. ICEREG(ice, MPU2_CTRL),
  2460. c->mpu401_2_info_flags |
  2461. MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
  2462. -1, &ice->rmidi[1]);
  2463. if (err < 0) {
  2464. snd_card_free(card);
  2465. return err;
  2466. }
  2467. if (c->mpu401_2_name)
  2468. /* Preferred name available in card_info */
  2469. snprintf(ice->rmidi[1]->name,
  2470. sizeof(ice->rmidi[1]->name),
  2471. "%s %d", c->mpu401_2_name,
  2472. card->number);
  2473. }
  2474. }
  2475. snd_ice1712_set_input_clock_source(ice, 0);
  2476. sprintf(card->longname, "%s at 0x%lx, irq %i",
  2477. card->shortname, ice->port, ice->irq);
  2478. err = snd_card_register(card);
  2479. if (err < 0) {
  2480. snd_card_free(card);
  2481. return err;
  2482. }
  2483. pci_set_drvdata(pci, card);
  2484. dev++;
  2485. return 0;
  2486. }
  2487. static void snd_ice1712_remove(struct pci_dev *pci)
  2488. {
  2489. struct snd_card *card = pci_get_drvdata(pci);
  2490. struct snd_ice1712 *ice = card->private_data;
  2491. if (ice->card_info && ice->card_info->chip_exit)
  2492. ice->card_info->chip_exit(ice);
  2493. snd_card_free(card);
  2494. }
  2495. #ifdef CONFIG_PM_SLEEP
  2496. static int snd_ice1712_suspend(struct device *dev)
  2497. {
  2498. struct pci_dev *pci = to_pci_dev(dev);
  2499. struct snd_card *card = dev_get_drvdata(dev);
  2500. struct snd_ice1712 *ice = card->private_data;
  2501. if (!ice->pm_suspend_enabled)
  2502. return 0;
  2503. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2504. snd_pcm_suspend_all(ice->pcm);
  2505. snd_pcm_suspend_all(ice->pcm_pro);
  2506. snd_pcm_suspend_all(ice->pcm_ds);
  2507. snd_ac97_suspend(ice->ac97);
  2508. spin_lock_irq(&ice->reg_lock);
  2509. ice->pm_saved_is_spdif_master = is_spdif_master(ice);
  2510. ice->pm_saved_spdif_ctrl = inw(ICEMT(ice, ROUTE_SPDOUT));
  2511. ice->pm_saved_route = inw(ICEMT(ice, ROUTE_PSDOUT03));
  2512. spin_unlock_irq(&ice->reg_lock);
  2513. if (ice->pm_suspend)
  2514. ice->pm_suspend(ice);
  2515. pci_disable_device(pci);
  2516. pci_save_state(pci);
  2517. pci_set_power_state(pci, PCI_D3hot);
  2518. return 0;
  2519. }
  2520. static int snd_ice1712_resume(struct device *dev)
  2521. {
  2522. struct pci_dev *pci = to_pci_dev(dev);
  2523. struct snd_card *card = dev_get_drvdata(dev);
  2524. struct snd_ice1712 *ice = card->private_data;
  2525. int rate;
  2526. if (!ice->pm_suspend_enabled)
  2527. return 0;
  2528. pci_set_power_state(pci, PCI_D0);
  2529. pci_restore_state(pci);
  2530. if (pci_enable_device(pci) < 0) {
  2531. snd_card_disconnect(card);
  2532. return -EIO;
  2533. }
  2534. pci_set_master(pci);
  2535. if (ice->cur_rate)
  2536. rate = ice->cur_rate;
  2537. else
  2538. rate = PRO_RATE_DEFAULT;
  2539. if (snd_ice1712_chip_init(ice) < 0) {
  2540. snd_card_disconnect(card);
  2541. return -EIO;
  2542. }
  2543. ice->cur_rate = rate;
  2544. if (ice->pm_resume)
  2545. ice->pm_resume(ice);
  2546. if (ice->pm_saved_is_spdif_master) {
  2547. /* switching to external clock via SPDIF */
  2548. spin_lock_irq(&ice->reg_lock);
  2549. outb(inb(ICEMT(ice, RATE)) | ICE1712_SPDIF_MASTER,
  2550. ICEMT(ice, RATE));
  2551. spin_unlock_irq(&ice->reg_lock);
  2552. snd_ice1712_set_input_clock_source(ice, 1);
  2553. } else {
  2554. /* internal on-card clock */
  2555. snd_ice1712_set_pro_rate(ice, rate, 1);
  2556. snd_ice1712_set_input_clock_source(ice, 0);
  2557. }
  2558. outw(ice->pm_saved_spdif_ctrl, ICEMT(ice, ROUTE_SPDOUT));
  2559. outw(ice->pm_saved_route, ICEMT(ice, ROUTE_PSDOUT03));
  2560. if (ice->ac97)
  2561. snd_ac97_resume(ice->ac97);
  2562. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2563. return 0;
  2564. }
  2565. static SIMPLE_DEV_PM_OPS(snd_ice1712_pm, snd_ice1712_suspend, snd_ice1712_resume);
  2566. #define SND_VT1712_PM_OPS &snd_ice1712_pm
  2567. #else
  2568. #define SND_VT1712_PM_OPS NULL
  2569. #endif /* CONFIG_PM_SLEEP */
  2570. static struct pci_driver ice1712_driver = {
  2571. .name = KBUILD_MODNAME,
  2572. .id_table = snd_ice1712_ids,
  2573. .probe = snd_ice1712_probe,
  2574. .remove = snd_ice1712_remove,
  2575. .driver = {
  2576. .pm = SND_VT1712_PM_OPS,
  2577. },
  2578. };
  2579. module_pci_driver(ice1712_driver);