mxc_w1.c 4.5 KB

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  1. /*
  2. * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
  3. * Copyright 2008 Luotao Fu, kernel@pengutronix.de
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/delay.h>
  16. #include <linux/io.h>
  17. #include <linux/module.h>
  18. #include <linux/platform_device.h>
  19. #include "../w1.h"
  20. #include "../w1_int.h"
  21. /* According to the mx27 Datasheet the reset procedure should take up to about
  22. * 1350us. We set the timeout to 500*100us = 50ms for sure */
  23. #define MXC_W1_RESET_TIMEOUT 500
  24. /*
  25. * MXC W1 Register offsets
  26. */
  27. #define MXC_W1_CONTROL 0x00
  28. # define MXC_W1_CONTROL_RDST BIT(3)
  29. # define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
  30. # define MXC_W1_CONTROL_PST BIT(6)
  31. # define MXC_W1_CONTROL_RPP BIT(7)
  32. #define MXC_W1_TIME_DIVIDER 0x02
  33. #define MXC_W1_RESET 0x04
  34. struct mxc_w1_device {
  35. void __iomem *regs;
  36. struct clk *clk;
  37. struct w1_bus_master bus_master;
  38. };
  39. /*
  40. * this is the low level routine to
  41. * reset the device on the One Wire interface
  42. * on the hardware
  43. */
  44. static u8 mxc_w1_ds2_reset_bus(void *data)
  45. {
  46. u8 reg_val;
  47. unsigned int timeout_cnt = 0;
  48. struct mxc_w1_device *dev = data;
  49. writeb(MXC_W1_CONTROL_RPP, (dev->regs + MXC_W1_CONTROL));
  50. while (1) {
  51. reg_val = readb(dev->regs + MXC_W1_CONTROL);
  52. if (!(reg_val & MXC_W1_CONTROL_RPP) ||
  53. timeout_cnt > MXC_W1_RESET_TIMEOUT)
  54. break;
  55. else
  56. timeout_cnt++;
  57. udelay(100);
  58. }
  59. return !(reg_val & MXC_W1_CONTROL_PST);
  60. }
  61. /*
  62. * this is the low level routine to read/write a bit on the One Wire
  63. * interface on the hardware. It does write 0 if parameter bit is set
  64. * to 0, otherwise a write 1/read.
  65. */
  66. static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit)
  67. {
  68. struct mxc_w1_device *mdev = data;
  69. void __iomem *ctrl_addr = mdev->regs + MXC_W1_CONTROL;
  70. unsigned int timeout_cnt = 400; /* Takes max. 120us according to
  71. * datasheet.
  72. */
  73. writeb(MXC_W1_CONTROL_WR(bit), ctrl_addr);
  74. while (timeout_cnt--) {
  75. if (!(readb(ctrl_addr) & MXC_W1_CONTROL_WR(bit)))
  76. break;
  77. udelay(1);
  78. }
  79. return !!(readb(ctrl_addr) & MXC_W1_CONTROL_RDST);
  80. }
  81. static int mxc_w1_probe(struct platform_device *pdev)
  82. {
  83. struct mxc_w1_device *mdev;
  84. unsigned long clkrate;
  85. struct resource *res;
  86. unsigned int clkdiv;
  87. int err;
  88. mdev = devm_kzalloc(&pdev->dev, sizeof(struct mxc_w1_device),
  89. GFP_KERNEL);
  90. if (!mdev)
  91. return -ENOMEM;
  92. mdev->clk = devm_clk_get(&pdev->dev, NULL);
  93. if (IS_ERR(mdev->clk))
  94. return PTR_ERR(mdev->clk);
  95. clkrate = clk_get_rate(mdev->clk);
  96. if (clkrate < 10000000)
  97. dev_warn(&pdev->dev,
  98. "Low clock frequency causes improper function\n");
  99. clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000);
  100. clkrate /= clkdiv;
  101. if ((clkrate < 980000) || (clkrate > 1020000))
  102. dev_warn(&pdev->dev,
  103. "Incorrect time base frequency %lu Hz\n", clkrate);
  104. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  105. mdev->regs = devm_ioremap_resource(&pdev->dev, res);
  106. if (IS_ERR(mdev->regs))
  107. return PTR_ERR(mdev->regs);
  108. err = clk_prepare_enable(mdev->clk);
  109. if (err)
  110. return err;
  111. writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER);
  112. mdev->bus_master.data = mdev;
  113. mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus;
  114. mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit;
  115. platform_set_drvdata(pdev, mdev);
  116. err = w1_add_master_device(&mdev->bus_master);
  117. if (err)
  118. clk_disable_unprepare(mdev->clk);
  119. return err;
  120. }
  121. /*
  122. * disassociate the w1 device from the driver
  123. */
  124. static int mxc_w1_remove(struct platform_device *pdev)
  125. {
  126. struct mxc_w1_device *mdev = platform_get_drvdata(pdev);
  127. w1_remove_master_device(&mdev->bus_master);
  128. clk_disable_unprepare(mdev->clk);
  129. return 0;
  130. }
  131. static struct of_device_id mxc_w1_dt_ids[] = {
  132. { .compatible = "fsl,imx21-owire" },
  133. { /* sentinel */ }
  134. };
  135. MODULE_DEVICE_TABLE(of, mxc_w1_dt_ids);
  136. static struct platform_driver mxc_w1_driver = {
  137. .driver = {
  138. .name = "mxc_w1",
  139. .owner = THIS_MODULE,
  140. .of_match_table = mxc_w1_dt_ids,
  141. },
  142. .probe = mxc_w1_probe,
  143. .remove = mxc_w1_remove,
  144. };
  145. module_platform_driver(mxc_w1_driver);
  146. MODULE_LICENSE("GPL");
  147. MODULE_AUTHOR("Freescale Semiconductors Inc");
  148. MODULE_DESCRIPTION("Driver for One-Wire on MXC");