ehci-tegra.c 15 KB

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  1. /*
  2. * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
  3. *
  4. * Copyright (C) 2010 Google, Inc.
  5. * Copyright (C) 2009 - 2013 NVIDIA Corporation
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. */
  18. #include <linux/clk.h>
  19. #include <linux/dma-mapping.h>
  20. #include <linux/err.h>
  21. #include <linux/gpio.h>
  22. #include <linux/io.h>
  23. #include <linux/irq.h>
  24. #include <linux/module.h>
  25. #include <linux/of.h>
  26. #include <linux/of_device.h>
  27. #include <linux/of_gpio.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/pm_runtime.h>
  30. #include <linux/reset.h>
  31. #include <linux/slab.h>
  32. #include <linux/usb/ehci_def.h>
  33. #include <linux/usb/tegra_usb_phy.h>
  34. #include <linux/usb.h>
  35. #include <linux/usb/hcd.h>
  36. #include <linux/usb/otg.h>
  37. #include "ehci.h"
  38. #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
  39. #define TEGRA_USB_DMA_ALIGN 32
  40. #define DRIVER_DESC "Tegra EHCI driver"
  41. #define DRV_NAME "tegra-ehci"
  42. static struct hc_driver __read_mostly tegra_ehci_hc_driver;
  43. struct tegra_ehci_soc_config {
  44. bool has_hostpc;
  45. };
  46. struct tegra_ehci_hcd {
  47. struct tegra_usb_phy *phy;
  48. struct clk *clk;
  49. struct reset_control *rst;
  50. int port_resuming;
  51. bool needs_double_reset;
  52. enum tegra_usb_phy_port_speed port_speed;
  53. };
  54. static int tegra_ehci_internal_port_reset(
  55. struct ehci_hcd *ehci,
  56. u32 __iomem *portsc_reg
  57. )
  58. {
  59. u32 temp;
  60. unsigned long flags;
  61. int retval = 0;
  62. int i, tries;
  63. u32 saved_usbintr;
  64. spin_lock_irqsave(&ehci->lock, flags);
  65. saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
  66. /* disable USB interrupt */
  67. ehci_writel(ehci, 0, &ehci->regs->intr_enable);
  68. spin_unlock_irqrestore(&ehci->lock, flags);
  69. /*
  70. * Here we have to do Port Reset at most twice for
  71. * Port Enable bit to be set.
  72. */
  73. for (i = 0; i < 2; i++) {
  74. temp = ehci_readl(ehci, portsc_reg);
  75. temp |= PORT_RESET;
  76. ehci_writel(ehci, temp, portsc_reg);
  77. mdelay(10);
  78. temp &= ~PORT_RESET;
  79. ehci_writel(ehci, temp, portsc_reg);
  80. mdelay(1);
  81. tries = 100;
  82. do {
  83. mdelay(1);
  84. /*
  85. * Up to this point, Port Enable bit is
  86. * expected to be set after 2 ms waiting.
  87. * USB1 usually takes extra 45 ms, for safety,
  88. * we take 100 ms as timeout.
  89. */
  90. temp = ehci_readl(ehci, portsc_reg);
  91. } while (!(temp & PORT_PE) && tries--);
  92. if (temp & PORT_PE)
  93. break;
  94. }
  95. if (i == 2)
  96. retval = -ETIMEDOUT;
  97. /*
  98. * Clear Connect Status Change bit if it's set.
  99. * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
  100. */
  101. if (temp & PORT_CSC)
  102. ehci_writel(ehci, PORT_CSC, portsc_reg);
  103. /*
  104. * Write to clear any interrupt status bits that might be set
  105. * during port reset.
  106. */
  107. temp = ehci_readl(ehci, &ehci->regs->status);
  108. ehci_writel(ehci, temp, &ehci->regs->status);
  109. /* restore original interrupt enable bits */
  110. ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
  111. return retval;
  112. }
  113. static int tegra_ehci_hub_control(
  114. struct usb_hcd *hcd,
  115. u16 typeReq,
  116. u16 wValue,
  117. u16 wIndex,
  118. char *buf,
  119. u16 wLength
  120. )
  121. {
  122. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  123. struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
  124. u32 __iomem *status_reg;
  125. u32 temp;
  126. unsigned long flags;
  127. int retval = 0;
  128. status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
  129. spin_lock_irqsave(&ehci->lock, flags);
  130. if (typeReq == GetPortStatus) {
  131. temp = ehci_readl(ehci, status_reg);
  132. if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
  133. /* Resume completed, re-enable disconnect detection */
  134. tegra->port_resuming = 0;
  135. tegra_usb_phy_postresume(hcd->phy);
  136. }
  137. }
  138. else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
  139. temp = ehci_readl(ehci, status_reg);
  140. if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
  141. retval = -EPIPE;
  142. goto done;
  143. }
  144. temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
  145. temp |= PORT_WKDISC_E | PORT_WKOC_E;
  146. ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
  147. /*
  148. * If a transaction is in progress, there may be a delay in
  149. * suspending the port. Poll until the port is suspended.
  150. */
  151. if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
  152. PORT_SUSPEND, 5000))
  153. pr_err("%s: timeout waiting for SUSPEND\n", __func__);
  154. set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
  155. goto done;
  156. }
  157. /* For USB1 port we need to issue Port Reset twice internally */
  158. if (tegra->needs_double_reset &&
  159. (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
  160. spin_unlock_irqrestore(&ehci->lock, flags);
  161. return tegra_ehci_internal_port_reset(ehci, status_reg);
  162. }
  163. /*
  164. * Tegra host controller will time the resume operation to clear the bit
  165. * when the port control state switches to HS or FS Idle. This behavior
  166. * is different from EHCI where the host controller driver is required
  167. * to set this bit to a zero after the resume duration is timed in the
  168. * driver.
  169. */
  170. else if (typeReq == ClearPortFeature &&
  171. wValue == USB_PORT_FEAT_SUSPEND) {
  172. temp = ehci_readl(ehci, status_reg);
  173. if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
  174. retval = -EPIPE;
  175. goto done;
  176. }
  177. if (!(temp & PORT_SUSPEND))
  178. goto done;
  179. /* Disable disconnect detection during port resume */
  180. tegra_usb_phy_preresume(hcd->phy);
  181. ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
  182. temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
  183. /* start resume signalling */
  184. ehci_writel(ehci, temp | PORT_RESUME, status_reg);
  185. set_bit(wIndex-1, &ehci->resuming_ports);
  186. spin_unlock_irqrestore(&ehci->lock, flags);
  187. msleep(20);
  188. spin_lock_irqsave(&ehci->lock, flags);
  189. /* Poll until the controller clears RESUME and SUSPEND */
  190. if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
  191. pr_err("%s: timeout waiting for RESUME\n", __func__);
  192. if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
  193. pr_err("%s: timeout waiting for SUSPEND\n", __func__);
  194. ehci->reset_done[wIndex-1] = 0;
  195. clear_bit(wIndex-1, &ehci->resuming_ports);
  196. tegra->port_resuming = 1;
  197. goto done;
  198. }
  199. spin_unlock_irqrestore(&ehci->lock, flags);
  200. /* Handle the hub control events here */
  201. return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
  202. done:
  203. spin_unlock_irqrestore(&ehci->lock, flags);
  204. return retval;
  205. }
  206. struct dma_aligned_buffer {
  207. void *kmalloc_ptr;
  208. void *old_xfer_buffer;
  209. u8 data[0];
  210. };
  211. static void free_dma_aligned_buffer(struct urb *urb)
  212. {
  213. struct dma_aligned_buffer *temp;
  214. if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
  215. return;
  216. temp = container_of(urb->transfer_buffer,
  217. struct dma_aligned_buffer, data);
  218. if (usb_urb_dir_in(urb))
  219. memcpy(temp->old_xfer_buffer, temp->data,
  220. urb->transfer_buffer_length);
  221. urb->transfer_buffer = temp->old_xfer_buffer;
  222. kfree(temp->kmalloc_ptr);
  223. urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
  224. }
  225. static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
  226. {
  227. struct dma_aligned_buffer *temp, *kmalloc_ptr;
  228. size_t kmalloc_size;
  229. if (urb->num_sgs || urb->sg ||
  230. urb->transfer_buffer_length == 0 ||
  231. !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
  232. return 0;
  233. /* Allocate a buffer with enough padding for alignment */
  234. kmalloc_size = urb->transfer_buffer_length +
  235. sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
  236. kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
  237. if (!kmalloc_ptr)
  238. return -ENOMEM;
  239. /* Position our struct dma_aligned_buffer such that data is aligned */
  240. temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
  241. temp->kmalloc_ptr = kmalloc_ptr;
  242. temp->old_xfer_buffer = urb->transfer_buffer;
  243. if (usb_urb_dir_out(urb))
  244. memcpy(temp->data, urb->transfer_buffer,
  245. urb->transfer_buffer_length);
  246. urb->transfer_buffer = temp->data;
  247. urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
  248. return 0;
  249. }
  250. static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
  251. gfp_t mem_flags)
  252. {
  253. int ret;
  254. ret = alloc_dma_aligned_buffer(urb, mem_flags);
  255. if (ret)
  256. return ret;
  257. ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
  258. if (ret)
  259. free_dma_aligned_buffer(urb);
  260. return ret;
  261. }
  262. static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
  263. {
  264. usb_hcd_unmap_urb_for_dma(hcd, urb);
  265. free_dma_aligned_buffer(urb);
  266. }
  267. static const struct tegra_ehci_soc_config tegra30_soc_config = {
  268. .has_hostpc = true,
  269. };
  270. static const struct tegra_ehci_soc_config tegra20_soc_config = {
  271. .has_hostpc = false,
  272. };
  273. static struct of_device_id tegra_ehci_of_match[] = {
  274. { .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
  275. { .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
  276. { },
  277. };
  278. static int tegra_ehci_probe(struct platform_device *pdev)
  279. {
  280. const struct of_device_id *match;
  281. const struct tegra_ehci_soc_config *soc_config;
  282. struct resource *res;
  283. struct usb_hcd *hcd;
  284. struct ehci_hcd *ehci;
  285. struct tegra_ehci_hcd *tegra;
  286. int err = 0;
  287. int irq;
  288. struct usb_phy *u_phy;
  289. match = of_match_device(tegra_ehci_of_match, &pdev->dev);
  290. if (!match) {
  291. dev_err(&pdev->dev, "Error: No device match found\n");
  292. return -ENODEV;
  293. }
  294. soc_config = match->data;
  295. /* Right now device-tree probed devices don't get dma_mask set.
  296. * Since shared usb code relies on it, set it here for now.
  297. * Once we have dma capability bindings this can go away.
  298. */
  299. err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  300. if (err)
  301. return err;
  302. hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
  303. dev_name(&pdev->dev));
  304. if (!hcd) {
  305. dev_err(&pdev->dev, "Unable to create HCD\n");
  306. return -ENOMEM;
  307. }
  308. platform_set_drvdata(pdev, hcd);
  309. ehci = hcd_to_ehci(hcd);
  310. tegra = (struct tegra_ehci_hcd *)ehci->priv;
  311. hcd->has_tt = 1;
  312. tegra->clk = devm_clk_get(&pdev->dev, NULL);
  313. if (IS_ERR(tegra->clk)) {
  314. dev_err(&pdev->dev, "Can't get ehci clock\n");
  315. err = PTR_ERR(tegra->clk);
  316. goto cleanup_hcd_create;
  317. }
  318. tegra->rst = devm_reset_control_get(&pdev->dev, "usb");
  319. if (IS_ERR(tegra->rst)) {
  320. dev_err(&pdev->dev, "Can't get ehci reset\n");
  321. err = PTR_ERR(tegra->rst);
  322. goto cleanup_hcd_create;
  323. }
  324. err = clk_prepare_enable(tegra->clk);
  325. if (err)
  326. goto cleanup_hcd_create;
  327. reset_control_assert(tegra->rst);
  328. udelay(1);
  329. reset_control_deassert(tegra->rst);
  330. u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
  331. if (IS_ERR(u_phy)) {
  332. err = PTR_ERR(u_phy);
  333. goto cleanup_clk_en;
  334. }
  335. hcd->phy = u_phy;
  336. tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
  337. "nvidia,needs-double-reset");
  338. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  339. if (!res) {
  340. dev_err(&pdev->dev, "Failed to get I/O memory\n");
  341. err = -ENXIO;
  342. goto cleanup_clk_en;
  343. }
  344. hcd->rsrc_start = res->start;
  345. hcd->rsrc_len = resource_size(res);
  346. hcd->regs = devm_ioremap_resource(&pdev->dev, res);
  347. if (IS_ERR(hcd->regs)) {
  348. err = PTR_ERR(hcd->regs);
  349. goto cleanup_clk_en;
  350. }
  351. ehci->caps = hcd->regs + 0x100;
  352. ehci->has_hostpc = soc_config->has_hostpc;
  353. err = usb_phy_init(hcd->phy);
  354. if (err) {
  355. dev_err(&pdev->dev, "Failed to initialize phy\n");
  356. goto cleanup_clk_en;
  357. }
  358. u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
  359. GFP_KERNEL);
  360. if (!u_phy->otg) {
  361. dev_err(&pdev->dev, "Failed to alloc memory for otg\n");
  362. err = -ENOMEM;
  363. goto cleanup_phy;
  364. }
  365. u_phy->otg->host = hcd_to_bus(hcd);
  366. err = usb_phy_set_suspend(hcd->phy, 0);
  367. if (err) {
  368. dev_err(&pdev->dev, "Failed to power on the phy\n");
  369. goto cleanup_phy;
  370. }
  371. irq = platform_get_irq(pdev, 0);
  372. if (!irq) {
  373. dev_err(&pdev->dev, "Failed to get IRQ\n");
  374. err = -ENODEV;
  375. goto cleanup_phy;
  376. }
  377. otg_set_host(u_phy->otg, &hcd->self);
  378. err = usb_add_hcd(hcd, irq, IRQF_SHARED);
  379. if (err) {
  380. dev_err(&pdev->dev, "Failed to add USB HCD\n");
  381. goto cleanup_otg_set_host;
  382. }
  383. device_wakeup_enable(hcd->self.controller);
  384. return err;
  385. cleanup_otg_set_host:
  386. otg_set_host(u_phy->otg, NULL);
  387. cleanup_phy:
  388. usb_phy_shutdown(hcd->phy);
  389. cleanup_clk_en:
  390. clk_disable_unprepare(tegra->clk);
  391. cleanup_hcd_create:
  392. usb_put_hcd(hcd);
  393. return err;
  394. }
  395. static int tegra_ehci_remove(struct platform_device *pdev)
  396. {
  397. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  398. struct tegra_ehci_hcd *tegra =
  399. (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
  400. otg_set_host(hcd->phy->otg, NULL);
  401. usb_phy_shutdown(hcd->phy);
  402. usb_remove_hcd(hcd);
  403. usb_put_hcd(hcd);
  404. clk_disable_unprepare(tegra->clk);
  405. return 0;
  406. }
  407. static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
  408. {
  409. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  410. if (hcd->driver->shutdown)
  411. hcd->driver->shutdown(hcd);
  412. }
  413. static struct platform_driver tegra_ehci_driver = {
  414. .probe = tegra_ehci_probe,
  415. .remove = tegra_ehci_remove,
  416. .shutdown = tegra_ehci_hcd_shutdown,
  417. .driver = {
  418. .name = DRV_NAME,
  419. .of_match_table = tegra_ehci_of_match,
  420. }
  421. };
  422. static int tegra_ehci_reset(struct usb_hcd *hcd)
  423. {
  424. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  425. int retval;
  426. int txfifothresh;
  427. retval = ehci_setup(hcd);
  428. if (retval)
  429. return retval;
  430. /*
  431. * We should really pull this value out of tegra_ehci_soc_config, but
  432. * to avoid needing access to it, make use of the fact that Tegra20 is
  433. * the only one so far that needs a value of 10, and Tegra20 is the
  434. * only one which doesn't set has_hostpc.
  435. */
  436. txfifothresh = ehci->has_hostpc ? 0x10 : 10;
  437. ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning);
  438. return 0;
  439. }
  440. static const struct ehci_driver_overrides tegra_overrides __initconst = {
  441. .extra_priv_size = sizeof(struct tegra_ehci_hcd),
  442. .reset = tegra_ehci_reset,
  443. };
  444. static int __init ehci_tegra_init(void)
  445. {
  446. if (usb_disabled())
  447. return -ENODEV;
  448. pr_info(DRV_NAME ": " DRIVER_DESC "\n");
  449. ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
  450. /*
  451. * The Tegra HW has some unusual quirks, which require Tegra-specific
  452. * workarounds. We override certain hc_driver functions here to
  453. * achieve that. We explicitly do not enhance ehci_driver_overrides to
  454. * allow this more easily, since this is an unusual case, and we don't
  455. * want to encourage others to override these functions by making it
  456. * too easy.
  457. */
  458. tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
  459. tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
  460. tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
  461. return platform_driver_register(&tegra_ehci_driver);
  462. }
  463. module_init(ehci_tegra_init);
  464. static void __exit ehci_tegra_cleanup(void)
  465. {
  466. platform_driver_unregister(&tegra_ehci_driver);
  467. }
  468. module_exit(ehci_tegra_cleanup);
  469. MODULE_DESCRIPTION(DRIVER_DESC);
  470. MODULE_LICENSE("GPL");
  471. MODULE_ALIAS("platform:" DRV_NAME);
  472. MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);