ehci-fsl.c 19 KB

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  1. /*
  2. * Copyright 2005-2009 MontaVista Software, Inc.
  3. * Copyright 2008,2012 Freescale Semiconductor, Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  13. * for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software Foundation,
  17. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. *
  19. * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
  20. * by Hunter Wu.
  21. * Power Management support by Dave Liu <daveliu@freescale.com>,
  22. * Jerry Huang <Chang-Ming.Huang@freescale.com> and
  23. * Anton Vorontsov <avorontsov@ru.mvista.com>.
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/types.h>
  27. #include <linux/delay.h>
  28. #include <linux/pm.h>
  29. #include <linux/err.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/fsl_devices.h>
  32. #include "ehci-fsl.h"
  33. /* configure so an HC device and id are always provided */
  34. /* always called with process context; sleeping is OK */
  35. /**
  36. * usb_hcd_fsl_probe - initialize FSL-based HCDs
  37. * @drvier: Driver to be used for this HCD
  38. * @pdev: USB Host Controller being probed
  39. * Context: !in_interrupt()
  40. *
  41. * Allocates basic resources for this USB host controller.
  42. *
  43. */
  44. static int usb_hcd_fsl_probe(const struct hc_driver *driver,
  45. struct platform_device *pdev)
  46. {
  47. struct fsl_usb2_platform_data *pdata;
  48. struct usb_hcd *hcd;
  49. struct resource *res;
  50. int irq;
  51. int retval;
  52. pr_debug("initializing FSL-SOC USB Controller\n");
  53. /* Need platform data for setup */
  54. pdata = dev_get_platdata(&pdev->dev);
  55. if (!pdata) {
  56. dev_err(&pdev->dev,
  57. "No platform data for %s.\n", dev_name(&pdev->dev));
  58. return -ENODEV;
  59. }
  60. /*
  61. * This is a host mode driver, verify that we're supposed to be
  62. * in host mode.
  63. */
  64. if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  65. (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
  66. (pdata->operating_mode == FSL_USB2_DR_OTG))) {
  67. dev_err(&pdev->dev,
  68. "Non Host Mode configured for %s. Wrong driver linked.\n",
  69. dev_name(&pdev->dev));
  70. return -ENODEV;
  71. }
  72. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  73. if (!res) {
  74. dev_err(&pdev->dev,
  75. "Found HC with no IRQ. Check %s setup!\n",
  76. dev_name(&pdev->dev));
  77. return -ENODEV;
  78. }
  79. irq = res->start;
  80. hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
  81. if (!hcd) {
  82. retval = -ENOMEM;
  83. goto err1;
  84. }
  85. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  86. if (!res) {
  87. dev_err(&pdev->dev,
  88. "Found HC with no register addr. Check %s setup!\n",
  89. dev_name(&pdev->dev));
  90. retval = -ENODEV;
  91. goto err2;
  92. }
  93. hcd->rsrc_start = res->start;
  94. hcd->rsrc_len = resource_size(res);
  95. hcd->regs = devm_ioremap_resource(&pdev->dev, res);
  96. if (IS_ERR(hcd->regs)) {
  97. retval = PTR_ERR(hcd->regs);
  98. goto err2;
  99. }
  100. pdata->regs = hcd->regs;
  101. if (pdata->power_budget)
  102. hcd->power_budget = pdata->power_budget;
  103. /*
  104. * do platform specific init: check the clock, grab/config pins, etc.
  105. */
  106. if (pdata->init && pdata->init(pdev)) {
  107. retval = -ENODEV;
  108. goto err2;
  109. }
  110. /* Enable USB controller, 83xx or 8536 */
  111. if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
  112. setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
  113. /* Don't need to set host mode here. It will be done by tdi_reset() */
  114. retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
  115. if (retval != 0)
  116. goto err2;
  117. device_wakeup_enable(hcd->self.controller);
  118. #ifdef CONFIG_USB_OTG
  119. if (pdata->operating_mode == FSL_USB2_DR_OTG) {
  120. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  121. hcd->phy = usb_get_phy(USB_PHY_TYPE_USB2);
  122. dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
  123. hcd, ehci, hcd->phy);
  124. if (!IS_ERR_OR_NULL(hcd->phy)) {
  125. retval = otg_set_host(hcd->phy->otg,
  126. &ehci_to_hcd(ehci)->self);
  127. if (retval) {
  128. usb_put_phy(hcd->phy);
  129. goto err2;
  130. }
  131. } else {
  132. dev_err(&pdev->dev, "can't find phy\n");
  133. retval = -ENODEV;
  134. goto err2;
  135. }
  136. }
  137. #endif
  138. return retval;
  139. err2:
  140. usb_put_hcd(hcd);
  141. err1:
  142. dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
  143. if (pdata->exit)
  144. pdata->exit(pdev);
  145. return retval;
  146. }
  147. /* may be called without controller electrically present */
  148. /* may be called with controller, bus, and devices active */
  149. /**
  150. * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs
  151. * @dev: USB Host Controller being removed
  152. * Context: !in_interrupt()
  153. *
  154. * Reverses the effect of usb_hcd_fsl_probe().
  155. *
  156. */
  157. static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
  158. struct platform_device *pdev)
  159. {
  160. struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
  161. if (!IS_ERR_OR_NULL(hcd->phy)) {
  162. otg_set_host(hcd->phy->otg, NULL);
  163. usb_put_phy(hcd->phy);
  164. }
  165. usb_remove_hcd(hcd);
  166. /*
  167. * do platform specific un-initialization:
  168. * release iomux pins, disable clock, etc.
  169. */
  170. if (pdata->exit)
  171. pdata->exit(pdev);
  172. usb_put_hcd(hcd);
  173. }
  174. static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
  175. enum fsl_usb2_phy_modes phy_mode,
  176. unsigned int port_offset)
  177. {
  178. u32 portsc;
  179. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  180. void __iomem *non_ehci = hcd->regs;
  181. struct device *dev = hcd->self.controller;
  182. struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
  183. if (pdata->controller_ver < 0) {
  184. dev_warn(hcd->self.controller, "Could not get controller version\n");
  185. return -ENODEV;
  186. }
  187. portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
  188. portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
  189. switch (phy_mode) {
  190. case FSL_USB2_PHY_ULPI:
  191. if (pdata->have_sysif_regs && pdata->controller_ver) {
  192. /* controller version 1.6 or above */
  193. clrbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
  194. setbits32(non_ehci + FSL_SOC_USB_CTRL,
  195. ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
  196. }
  197. portsc |= PORT_PTS_ULPI;
  198. break;
  199. case FSL_USB2_PHY_SERIAL:
  200. portsc |= PORT_PTS_SERIAL;
  201. break;
  202. case FSL_USB2_PHY_UTMI_WIDE:
  203. portsc |= PORT_PTS_PTW;
  204. /* fall through */
  205. case FSL_USB2_PHY_UTMI:
  206. if (pdata->have_sysif_regs && pdata->controller_ver) {
  207. /* controller version 1.6 or above */
  208. setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
  209. mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
  210. become stable - 10ms*/
  211. }
  212. /* enable UTMI PHY */
  213. if (pdata->have_sysif_regs)
  214. setbits32(non_ehci + FSL_SOC_USB_CTRL,
  215. CTRL_UTMI_PHY_EN);
  216. portsc |= PORT_PTS_UTMI;
  217. break;
  218. case FSL_USB2_PHY_NONE:
  219. break;
  220. }
  221. if (pdata->have_sysif_regs &&
  222. pdata->controller_ver > FSL_USB_VER_1_6 &&
  223. (phy_mode == FSL_USB2_PHY_ULPI)) {
  224. /* check PHY_CLK_VALID to get phy clk valid */
  225. if (!(spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
  226. PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0) ||
  227. in_be32(non_ehci + FSL_SOC_USB_PRICTRL))) {
  228. dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
  229. return -EINVAL;
  230. }
  231. }
  232. ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
  233. if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
  234. setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
  235. return 0;
  236. }
  237. static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
  238. {
  239. struct usb_hcd *hcd = ehci_to_hcd(ehci);
  240. struct fsl_usb2_platform_data *pdata;
  241. void __iomem *non_ehci = hcd->regs;
  242. pdata = dev_get_platdata(hcd->self.controller);
  243. if (pdata->have_sysif_regs) {
  244. /*
  245. * Turn on cache snooping hardware, since some PowerPC platforms
  246. * wholly rely on hardware to deal with cache coherent
  247. */
  248. /* Setup Snooping for all the 4GB space */
  249. /* SNOOP1 starts from 0x0, size 2G */
  250. out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB);
  251. /* SNOOP2 starts from 0x80000000, size 2G */
  252. out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
  253. }
  254. if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  255. (pdata->operating_mode == FSL_USB2_DR_OTG))
  256. if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
  257. return -EINVAL;
  258. if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
  259. unsigned int chip, rev, svr;
  260. svr = mfspr(SPRN_SVR);
  261. chip = svr >> 16;
  262. rev = (svr >> 4) & 0xf;
  263. /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
  264. if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
  265. ehci->has_fsl_port_bug = 1;
  266. if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
  267. if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
  268. return -EINVAL;
  269. if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
  270. if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
  271. return -EINVAL;
  272. }
  273. if (pdata->have_sysif_regs) {
  274. #ifdef CONFIG_FSL_SOC_BOOKE
  275. out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
  276. out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080);
  277. #else
  278. out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c);
  279. out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040);
  280. #endif
  281. out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
  282. }
  283. return 0;
  284. }
  285. /* called after powerup, by probe or system-pm "wakeup" */
  286. static int ehci_fsl_reinit(struct ehci_hcd *ehci)
  287. {
  288. if (ehci_fsl_usb_setup(ehci))
  289. return -EINVAL;
  290. return 0;
  291. }
  292. /* called during probe() after chip reset completes */
  293. static int ehci_fsl_setup(struct usb_hcd *hcd)
  294. {
  295. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  296. int retval;
  297. struct fsl_usb2_platform_data *pdata;
  298. struct device *dev;
  299. dev = hcd->self.controller;
  300. pdata = dev_get_platdata(hcd->self.controller);
  301. ehci->big_endian_desc = pdata->big_endian_desc;
  302. ehci->big_endian_mmio = pdata->big_endian_mmio;
  303. /* EHCI registers start at offset 0x100 */
  304. ehci->caps = hcd->regs + 0x100;
  305. #ifdef CONFIG_PPC_83xx
  306. /*
  307. * Deal with MPC834X that need port power to be cycled after the power
  308. * fault condition is removed. Otherwise the state machine does not
  309. * reflect PORTSC[CSC] correctly.
  310. */
  311. ehci->need_oc_pp_cycle = 1;
  312. #endif
  313. hcd->has_tt = 1;
  314. retval = ehci_setup(hcd);
  315. if (retval)
  316. return retval;
  317. if (of_device_is_compatible(dev->parent->of_node,
  318. "fsl,mpc5121-usb2-dr")) {
  319. /*
  320. * set SBUSCFG:AHBBRST so that control msgs don't
  321. * fail when doing heavy PATA writes.
  322. */
  323. ehci_writel(ehci, SBUSCFG_INCR8,
  324. hcd->regs + FSL_SOC_USB_SBUSCFG);
  325. }
  326. retval = ehci_fsl_reinit(ehci);
  327. return retval;
  328. }
  329. struct ehci_fsl {
  330. struct ehci_hcd ehci;
  331. #ifdef CONFIG_PM
  332. /* Saved USB PHY settings, need to restore after deep sleep. */
  333. u32 usb_ctrl;
  334. #endif
  335. };
  336. #ifdef CONFIG_PM
  337. #ifdef CONFIG_PPC_MPC512x
  338. static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
  339. {
  340. struct usb_hcd *hcd = dev_get_drvdata(dev);
  341. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  342. struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
  343. u32 tmp;
  344. #ifdef CONFIG_DYNAMIC_DEBUG
  345. u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
  346. mode &= USBMODE_CM_MASK;
  347. tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
  348. dev_dbg(dev, "suspend=%d already_suspended=%d "
  349. "mode=%d usbcmd %08x\n", pdata->suspended,
  350. pdata->already_suspended, mode, tmp);
  351. #endif
  352. /*
  353. * If the controller is already suspended, then this must be a
  354. * PM suspend. Remember this fact, so that we will leave the
  355. * controller suspended at PM resume time.
  356. */
  357. if (pdata->suspended) {
  358. dev_dbg(dev, "already suspended, leaving early\n");
  359. pdata->already_suspended = 1;
  360. return 0;
  361. }
  362. dev_dbg(dev, "suspending...\n");
  363. ehci->rh_state = EHCI_RH_SUSPENDED;
  364. dev->power.power_state = PMSG_SUSPEND;
  365. /* ignore non-host interrupts */
  366. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  367. /* stop the controller */
  368. tmp = ehci_readl(ehci, &ehci->regs->command);
  369. tmp &= ~CMD_RUN;
  370. ehci_writel(ehci, tmp, &ehci->regs->command);
  371. /* save EHCI registers */
  372. pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
  373. pdata->pm_command &= ~CMD_RUN;
  374. pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
  375. pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
  376. pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
  377. pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
  378. pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
  379. pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
  380. pdata->pm_configured_flag =
  381. ehci_readl(ehci, &ehci->regs->configured_flag);
  382. pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
  383. pdata->pm_usbgenctrl = ehci_readl(ehci,
  384. hcd->regs + FSL_SOC_USB_USBGENCTRL);
  385. /* clear the W1C bits */
  386. pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
  387. pdata->suspended = 1;
  388. /* clear PP to cut power to the port */
  389. tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
  390. tmp &= ~PORT_POWER;
  391. ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
  392. return 0;
  393. }
  394. static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
  395. {
  396. struct usb_hcd *hcd = dev_get_drvdata(dev);
  397. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  398. struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
  399. u32 tmp;
  400. dev_dbg(dev, "suspend=%d already_suspended=%d\n",
  401. pdata->suspended, pdata->already_suspended);
  402. /*
  403. * If the controller was already suspended at suspend time,
  404. * then don't resume it now.
  405. */
  406. if (pdata->already_suspended) {
  407. dev_dbg(dev, "already suspended, leaving early\n");
  408. pdata->already_suspended = 0;
  409. return 0;
  410. }
  411. if (!pdata->suspended) {
  412. dev_dbg(dev, "not suspended, leaving early\n");
  413. return 0;
  414. }
  415. pdata->suspended = 0;
  416. dev_dbg(dev, "resuming...\n");
  417. /* set host mode */
  418. tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
  419. ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
  420. ehci_writel(ehci, pdata->pm_usbgenctrl,
  421. hcd->regs + FSL_SOC_USB_USBGENCTRL);
  422. ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
  423. hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
  424. ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
  425. /* restore EHCI registers */
  426. ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
  427. ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
  428. ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
  429. ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
  430. ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
  431. ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
  432. ehci_writel(ehci, pdata->pm_configured_flag,
  433. &ehci->regs->configured_flag);
  434. ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
  435. set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  436. ehci->rh_state = EHCI_RH_RUNNING;
  437. dev->power.power_state = PMSG_ON;
  438. tmp = ehci_readl(ehci, &ehci->regs->command);
  439. tmp |= CMD_RUN;
  440. ehci_writel(ehci, tmp, &ehci->regs->command);
  441. usb_hcd_resume_root_hub(hcd);
  442. return 0;
  443. }
  444. #else
  445. static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
  446. {
  447. return 0;
  448. }
  449. static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
  450. {
  451. return 0;
  452. }
  453. #endif /* CONFIG_PPC_MPC512x */
  454. static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
  455. {
  456. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  457. return container_of(ehci, struct ehci_fsl, ehci);
  458. }
  459. static int ehci_fsl_drv_suspend(struct device *dev)
  460. {
  461. struct usb_hcd *hcd = dev_get_drvdata(dev);
  462. struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  463. void __iomem *non_ehci = hcd->regs;
  464. if (of_device_is_compatible(dev->parent->of_node,
  465. "fsl,mpc5121-usb2-dr")) {
  466. return ehci_fsl_mpc512x_drv_suspend(dev);
  467. }
  468. ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
  469. device_may_wakeup(dev));
  470. if (!fsl_deep_sleep())
  471. return 0;
  472. ehci_fsl->usb_ctrl = in_be32(non_ehci + FSL_SOC_USB_CTRL);
  473. return 0;
  474. }
  475. static int ehci_fsl_drv_resume(struct device *dev)
  476. {
  477. struct usb_hcd *hcd = dev_get_drvdata(dev);
  478. struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  479. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  480. void __iomem *non_ehci = hcd->regs;
  481. if (of_device_is_compatible(dev->parent->of_node,
  482. "fsl,mpc5121-usb2-dr")) {
  483. return ehci_fsl_mpc512x_drv_resume(dev);
  484. }
  485. ehci_prepare_ports_for_controller_resume(ehci);
  486. if (!fsl_deep_sleep())
  487. return 0;
  488. usb_root_hub_lost_power(hcd->self.root_hub);
  489. /* Restore USB PHY settings and enable the controller. */
  490. out_be32(non_ehci + FSL_SOC_USB_CTRL, ehci_fsl->usb_ctrl);
  491. ehci_reset(ehci);
  492. ehci_fsl_reinit(ehci);
  493. return 0;
  494. }
  495. static int ehci_fsl_drv_restore(struct device *dev)
  496. {
  497. struct usb_hcd *hcd = dev_get_drvdata(dev);
  498. usb_root_hub_lost_power(hcd->self.root_hub);
  499. return 0;
  500. }
  501. static struct dev_pm_ops ehci_fsl_pm_ops = {
  502. .suspend = ehci_fsl_drv_suspend,
  503. .resume = ehci_fsl_drv_resume,
  504. .restore = ehci_fsl_drv_restore,
  505. };
  506. #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
  507. #else
  508. #define EHCI_FSL_PM_OPS NULL
  509. #endif /* CONFIG_PM */
  510. #ifdef CONFIG_USB_OTG
  511. static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
  512. {
  513. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  514. u32 status;
  515. if (!port)
  516. return -EINVAL;
  517. port--;
  518. /* start port reset before HNP protocol time out */
  519. status = readl(&ehci->regs->port_status[port]);
  520. if (!(status & PORT_CONNECT))
  521. return -ENODEV;
  522. /* khubd will finish the reset later */
  523. if (ehci_is_TDI(ehci)) {
  524. writel(PORT_RESET |
  525. (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
  526. &ehci->regs->port_status[port]);
  527. } else {
  528. writel(PORT_RESET, &ehci->regs->port_status[port]);
  529. }
  530. return 0;
  531. }
  532. #else
  533. #define ehci_start_port_reset NULL
  534. #endif /* CONFIG_USB_OTG */
  535. static const struct hc_driver ehci_fsl_hc_driver = {
  536. .description = hcd_name,
  537. .product_desc = "Freescale On-Chip EHCI Host Controller",
  538. .hcd_priv_size = sizeof(struct ehci_fsl),
  539. /*
  540. * generic hardware linkage
  541. */
  542. .irq = ehci_irq,
  543. .flags = HCD_USB2 | HCD_MEMORY | HCD_BH,
  544. /*
  545. * basic lifecycle operations
  546. */
  547. .reset = ehci_fsl_setup,
  548. .start = ehci_run,
  549. .stop = ehci_stop,
  550. .shutdown = ehci_shutdown,
  551. /*
  552. * managing i/o requests and associated device resources
  553. */
  554. .urb_enqueue = ehci_urb_enqueue,
  555. .urb_dequeue = ehci_urb_dequeue,
  556. .endpoint_disable = ehci_endpoint_disable,
  557. .endpoint_reset = ehci_endpoint_reset,
  558. /*
  559. * scheduling support
  560. */
  561. .get_frame_number = ehci_get_frame,
  562. /*
  563. * root hub support
  564. */
  565. .hub_status_data = ehci_hub_status_data,
  566. .hub_control = ehci_hub_control,
  567. .bus_suspend = ehci_bus_suspend,
  568. .bus_resume = ehci_bus_resume,
  569. .start_port_reset = ehci_start_port_reset,
  570. .relinquish_port = ehci_relinquish_port,
  571. .port_handed_over = ehci_port_handed_over,
  572. .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
  573. };
  574. static int ehci_fsl_drv_probe(struct platform_device *pdev)
  575. {
  576. if (usb_disabled())
  577. return -ENODEV;
  578. /* FIXME we only want one one probe() not two */
  579. return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev);
  580. }
  581. static int ehci_fsl_drv_remove(struct platform_device *pdev)
  582. {
  583. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  584. /* FIXME we only want one one remove() not two */
  585. usb_hcd_fsl_remove(hcd, pdev);
  586. return 0;
  587. }
  588. MODULE_ALIAS("platform:fsl-ehci");
  589. static struct platform_driver ehci_fsl_driver = {
  590. .probe = ehci_fsl_drv_probe,
  591. .remove = ehci_fsl_drv_remove,
  592. .shutdown = usb_hcd_platform_shutdown,
  593. .driver = {
  594. .name = "fsl-ehci",
  595. .owner = THIS_MODULE,
  596. .pm = EHCI_FSL_PM_OPS,
  597. },
  598. };