udc.c 45 KB

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  1. /*
  2. * udc.c - ChipIdea UDC driver
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/device.h>
  14. #include <linux/dmapool.h>
  15. #include <linux/err.h>
  16. #include <linux/irqreturn.h>
  17. #include <linux/kernel.h>
  18. #include <linux/slab.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/usb/ch9.h>
  21. #include <linux/usb/gadget.h>
  22. #include <linux/usb/otg-fsm.h>
  23. #include <linux/usb/chipidea.h>
  24. #include "ci.h"
  25. #include "udc.h"
  26. #include "bits.h"
  27. #include "debug.h"
  28. #include "otg.h"
  29. #include "otg_fsm.h"
  30. /* control endpoint description */
  31. static const struct usb_endpoint_descriptor
  32. ctrl_endpt_out_desc = {
  33. .bLength = USB_DT_ENDPOINT_SIZE,
  34. .bDescriptorType = USB_DT_ENDPOINT,
  35. .bEndpointAddress = USB_DIR_OUT,
  36. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  37. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  38. };
  39. static const struct usb_endpoint_descriptor
  40. ctrl_endpt_in_desc = {
  41. .bLength = USB_DT_ENDPOINT_SIZE,
  42. .bDescriptorType = USB_DT_ENDPOINT,
  43. .bEndpointAddress = USB_DIR_IN,
  44. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  45. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  46. };
  47. /**
  48. * hw_ep_bit: calculates the bit number
  49. * @num: endpoint number
  50. * @dir: endpoint direction
  51. *
  52. * This function returns bit number
  53. */
  54. static inline int hw_ep_bit(int num, int dir)
  55. {
  56. return num + (dir ? 16 : 0);
  57. }
  58. static inline int ep_to_bit(struct ci_hdrc *ci, int n)
  59. {
  60. int fill = 16 - ci->hw_ep_max / 2;
  61. if (n >= ci->hw_ep_max / 2)
  62. n += fill;
  63. return n;
  64. }
  65. /**
  66. * hw_device_state: enables/disables interrupts (execute without interruption)
  67. * @dma: 0 => disable, !0 => enable and set dma engine
  68. *
  69. * This function returns an error code
  70. */
  71. static int hw_device_state(struct ci_hdrc *ci, u32 dma)
  72. {
  73. if (dma) {
  74. hw_write(ci, OP_ENDPTLISTADDR, ~0, dma);
  75. /* interrupt, error, port change, reset, sleep/suspend */
  76. hw_write(ci, OP_USBINTR, ~0,
  77. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  78. hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  79. } else {
  80. hw_write(ci, OP_USBINTR, ~0, 0);
  81. hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
  82. }
  83. return 0;
  84. }
  85. /**
  86. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  87. * @num: endpoint number
  88. * @dir: endpoint direction
  89. *
  90. * This function returns an error code
  91. */
  92. static int hw_ep_flush(struct ci_hdrc *ci, int num, int dir)
  93. {
  94. int n = hw_ep_bit(num, dir);
  95. do {
  96. /* flush any pending transfer */
  97. hw_write(ci, OP_ENDPTFLUSH, ~0, BIT(n));
  98. while (hw_read(ci, OP_ENDPTFLUSH, BIT(n)))
  99. cpu_relax();
  100. } while (hw_read(ci, OP_ENDPTSTAT, BIT(n)));
  101. return 0;
  102. }
  103. /**
  104. * hw_ep_disable: disables endpoint (execute without interruption)
  105. * @num: endpoint number
  106. * @dir: endpoint direction
  107. *
  108. * This function returns an error code
  109. */
  110. static int hw_ep_disable(struct ci_hdrc *ci, int num, int dir)
  111. {
  112. hw_ep_flush(ci, num, dir);
  113. hw_write(ci, OP_ENDPTCTRL + num,
  114. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  115. return 0;
  116. }
  117. /**
  118. * hw_ep_enable: enables endpoint (execute without interruption)
  119. * @num: endpoint number
  120. * @dir: endpoint direction
  121. * @type: endpoint type
  122. *
  123. * This function returns an error code
  124. */
  125. static int hw_ep_enable(struct ci_hdrc *ci, int num, int dir, int type)
  126. {
  127. u32 mask, data;
  128. if (dir) {
  129. mask = ENDPTCTRL_TXT; /* type */
  130. data = type << __ffs(mask);
  131. mask |= ENDPTCTRL_TXS; /* unstall */
  132. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  133. data |= ENDPTCTRL_TXR;
  134. mask |= ENDPTCTRL_TXE; /* enable */
  135. data |= ENDPTCTRL_TXE;
  136. } else {
  137. mask = ENDPTCTRL_RXT; /* type */
  138. data = type << __ffs(mask);
  139. mask |= ENDPTCTRL_RXS; /* unstall */
  140. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  141. data |= ENDPTCTRL_RXR;
  142. mask |= ENDPTCTRL_RXE; /* enable */
  143. data |= ENDPTCTRL_RXE;
  144. }
  145. hw_write(ci, OP_ENDPTCTRL + num, mask, data);
  146. return 0;
  147. }
  148. /**
  149. * hw_ep_get_halt: return endpoint halt status
  150. * @num: endpoint number
  151. * @dir: endpoint direction
  152. *
  153. * This function returns 1 if endpoint halted
  154. */
  155. static int hw_ep_get_halt(struct ci_hdrc *ci, int num, int dir)
  156. {
  157. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  158. return hw_read(ci, OP_ENDPTCTRL + num, mask) ? 1 : 0;
  159. }
  160. /**
  161. * hw_ep_prime: primes endpoint (execute without interruption)
  162. * @num: endpoint number
  163. * @dir: endpoint direction
  164. * @is_ctrl: true if control endpoint
  165. *
  166. * This function returns an error code
  167. */
  168. static int hw_ep_prime(struct ci_hdrc *ci, int num, int dir, int is_ctrl)
  169. {
  170. int n = hw_ep_bit(num, dir);
  171. if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num)))
  172. return -EAGAIN;
  173. hw_write(ci, OP_ENDPTPRIME, ~0, BIT(n));
  174. while (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
  175. cpu_relax();
  176. if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num)))
  177. return -EAGAIN;
  178. /* status shoult be tested according with manual but it doesn't work */
  179. return 0;
  180. }
  181. /**
  182. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  183. * without interruption)
  184. * @num: endpoint number
  185. * @dir: endpoint direction
  186. * @value: true => stall, false => unstall
  187. *
  188. * This function returns an error code
  189. */
  190. static int hw_ep_set_halt(struct ci_hdrc *ci, int num, int dir, int value)
  191. {
  192. if (value != 0 && value != 1)
  193. return -EINVAL;
  194. do {
  195. enum ci_hw_regs reg = OP_ENDPTCTRL + num;
  196. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  197. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  198. /* data toggle - reserved for EP0 but it's in ESS */
  199. hw_write(ci, reg, mask_xs|mask_xr,
  200. value ? mask_xs : mask_xr);
  201. } while (value != hw_ep_get_halt(ci, num, dir));
  202. return 0;
  203. }
  204. /**
  205. * hw_is_port_high_speed: test if port is high speed
  206. *
  207. * This function returns true if high speed port
  208. */
  209. static int hw_port_is_high_speed(struct ci_hdrc *ci)
  210. {
  211. return ci->hw_bank.lpm ? hw_read(ci, OP_DEVLC, DEVLC_PSPD) :
  212. hw_read(ci, OP_PORTSC, PORTSC_HSP);
  213. }
  214. /**
  215. * hw_test_and_clear_complete: test & clear complete status (execute without
  216. * interruption)
  217. * @n: endpoint number
  218. *
  219. * This function returns complete status
  220. */
  221. static int hw_test_and_clear_complete(struct ci_hdrc *ci, int n)
  222. {
  223. n = ep_to_bit(ci, n);
  224. return hw_test_and_clear(ci, OP_ENDPTCOMPLETE, BIT(n));
  225. }
  226. /**
  227. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  228. * without interruption)
  229. *
  230. * This function returns active interrutps
  231. */
  232. static u32 hw_test_and_clear_intr_active(struct ci_hdrc *ci)
  233. {
  234. u32 reg = hw_read_intr_status(ci) & hw_read_intr_enable(ci);
  235. hw_write(ci, OP_USBSTS, ~0, reg);
  236. return reg;
  237. }
  238. /**
  239. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  240. * interruption)
  241. *
  242. * This function returns guard value
  243. */
  244. static int hw_test_and_clear_setup_guard(struct ci_hdrc *ci)
  245. {
  246. return hw_test_and_write(ci, OP_USBCMD, USBCMD_SUTW, 0);
  247. }
  248. /**
  249. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  250. * interruption)
  251. *
  252. * This function returns guard value
  253. */
  254. static int hw_test_and_set_setup_guard(struct ci_hdrc *ci)
  255. {
  256. return hw_test_and_write(ci, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  257. }
  258. /**
  259. * hw_usb_set_address: configures USB address (execute without interruption)
  260. * @value: new USB address
  261. *
  262. * This function explicitly sets the address, without the "USBADRA" (advance)
  263. * feature, which is not supported by older versions of the controller.
  264. */
  265. static void hw_usb_set_address(struct ci_hdrc *ci, u8 value)
  266. {
  267. hw_write(ci, OP_DEVICEADDR, DEVICEADDR_USBADR,
  268. value << __ffs(DEVICEADDR_USBADR));
  269. }
  270. /**
  271. * hw_usb_reset: restart device after a bus reset (execute without
  272. * interruption)
  273. *
  274. * This function returns an error code
  275. */
  276. static int hw_usb_reset(struct ci_hdrc *ci)
  277. {
  278. hw_usb_set_address(ci, 0);
  279. /* ESS flushes only at end?!? */
  280. hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
  281. /* clear setup token semaphores */
  282. hw_write(ci, OP_ENDPTSETUPSTAT, 0, 0);
  283. /* clear complete status */
  284. hw_write(ci, OP_ENDPTCOMPLETE, 0, 0);
  285. /* wait until all bits cleared */
  286. while (hw_read(ci, OP_ENDPTPRIME, ~0))
  287. udelay(10); /* not RTOS friendly */
  288. /* reset all endpoints ? */
  289. /* reset internal status and wait for further instructions
  290. no need to verify the port reset status (ESS does it) */
  291. return 0;
  292. }
  293. /******************************************************************************
  294. * UTIL block
  295. *****************************************************************************/
  296. static int add_td_to_list(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq,
  297. unsigned length)
  298. {
  299. int i;
  300. u32 temp;
  301. struct td_node *lastnode, *node = kzalloc(sizeof(struct td_node),
  302. GFP_ATOMIC);
  303. if (node == NULL)
  304. return -ENOMEM;
  305. node->ptr = dma_pool_alloc(hwep->td_pool, GFP_ATOMIC,
  306. &node->dma);
  307. if (node->ptr == NULL) {
  308. kfree(node);
  309. return -ENOMEM;
  310. }
  311. memset(node->ptr, 0, sizeof(struct ci_hw_td));
  312. node->ptr->token = cpu_to_le32(length << __ffs(TD_TOTAL_BYTES));
  313. node->ptr->token &= cpu_to_le32(TD_TOTAL_BYTES);
  314. node->ptr->token |= cpu_to_le32(TD_STATUS_ACTIVE);
  315. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == TX) {
  316. u32 mul = hwreq->req.length / hwep->ep.maxpacket;
  317. if (hwreq->req.length == 0
  318. || hwreq->req.length % hwep->ep.maxpacket)
  319. mul++;
  320. node->ptr->token |= mul << __ffs(TD_MULTO);
  321. }
  322. temp = (u32) (hwreq->req.dma + hwreq->req.actual);
  323. if (length) {
  324. node->ptr->page[0] = cpu_to_le32(temp);
  325. for (i = 1; i < TD_PAGE_COUNT; i++) {
  326. u32 page = temp + i * CI_HDRC_PAGE_SIZE;
  327. page &= ~TD_RESERVED_MASK;
  328. node->ptr->page[i] = cpu_to_le32(page);
  329. }
  330. }
  331. hwreq->req.actual += length;
  332. if (!list_empty(&hwreq->tds)) {
  333. /* get the last entry */
  334. lastnode = list_entry(hwreq->tds.prev,
  335. struct td_node, td);
  336. lastnode->ptr->next = cpu_to_le32(node->dma);
  337. }
  338. INIT_LIST_HEAD(&node->td);
  339. list_add_tail(&node->td, &hwreq->tds);
  340. return 0;
  341. }
  342. /**
  343. * _usb_addr: calculates endpoint address from direction & number
  344. * @ep: endpoint
  345. */
  346. static inline u8 _usb_addr(struct ci_hw_ep *ep)
  347. {
  348. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  349. }
  350. /**
  351. * _hardware_queue: configures a request at hardware level
  352. * @gadget: gadget
  353. * @hwep: endpoint
  354. *
  355. * This function returns an error code
  356. */
  357. static int _hardware_enqueue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
  358. {
  359. struct ci_hdrc *ci = hwep->ci;
  360. int ret = 0;
  361. unsigned rest = hwreq->req.length;
  362. int pages = TD_PAGE_COUNT;
  363. struct td_node *firstnode, *lastnode;
  364. /* don't queue twice */
  365. if (hwreq->req.status == -EALREADY)
  366. return -EALREADY;
  367. hwreq->req.status = -EALREADY;
  368. ret = usb_gadget_map_request(&ci->gadget, &hwreq->req, hwep->dir);
  369. if (ret)
  370. return ret;
  371. /*
  372. * The first buffer could be not page aligned.
  373. * In that case we have to span into one extra td.
  374. */
  375. if (hwreq->req.dma % PAGE_SIZE)
  376. pages--;
  377. if (rest == 0)
  378. add_td_to_list(hwep, hwreq, 0);
  379. while (rest > 0) {
  380. unsigned count = min(hwreq->req.length - hwreq->req.actual,
  381. (unsigned)(pages * CI_HDRC_PAGE_SIZE));
  382. add_td_to_list(hwep, hwreq, count);
  383. rest -= count;
  384. }
  385. if (hwreq->req.zero && hwreq->req.length
  386. && (hwreq->req.length % hwep->ep.maxpacket == 0))
  387. add_td_to_list(hwep, hwreq, 0);
  388. firstnode = list_first_entry(&hwreq->tds, struct td_node, td);
  389. lastnode = list_entry(hwreq->tds.prev,
  390. struct td_node, td);
  391. lastnode->ptr->next = cpu_to_le32(TD_TERMINATE);
  392. if (!hwreq->req.no_interrupt)
  393. lastnode->ptr->token |= cpu_to_le32(TD_IOC);
  394. wmb();
  395. hwreq->req.actual = 0;
  396. if (!list_empty(&hwep->qh.queue)) {
  397. struct ci_hw_req *hwreqprev;
  398. int n = hw_ep_bit(hwep->num, hwep->dir);
  399. int tmp_stat;
  400. struct td_node *prevlastnode;
  401. u32 next = firstnode->dma & TD_ADDR_MASK;
  402. hwreqprev = list_entry(hwep->qh.queue.prev,
  403. struct ci_hw_req, queue);
  404. prevlastnode = list_entry(hwreqprev->tds.prev,
  405. struct td_node, td);
  406. prevlastnode->ptr->next = cpu_to_le32(next);
  407. wmb();
  408. if (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
  409. goto done;
  410. do {
  411. hw_write(ci, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  412. tmp_stat = hw_read(ci, OP_ENDPTSTAT, BIT(n));
  413. } while (!hw_read(ci, OP_USBCMD, USBCMD_ATDTW));
  414. hw_write(ci, OP_USBCMD, USBCMD_ATDTW, 0);
  415. if (tmp_stat)
  416. goto done;
  417. }
  418. /* QH configuration */
  419. hwep->qh.ptr->td.next = cpu_to_le32(firstnode->dma);
  420. hwep->qh.ptr->td.token &=
  421. cpu_to_le32(~(TD_STATUS_HALTED|TD_STATUS_ACTIVE));
  422. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == RX) {
  423. u32 mul = hwreq->req.length / hwep->ep.maxpacket;
  424. if (hwreq->req.length == 0
  425. || hwreq->req.length % hwep->ep.maxpacket)
  426. mul++;
  427. hwep->qh.ptr->cap |= mul << __ffs(QH_MULT);
  428. }
  429. wmb(); /* synchronize before ep prime */
  430. ret = hw_ep_prime(ci, hwep->num, hwep->dir,
  431. hwep->type == USB_ENDPOINT_XFER_CONTROL);
  432. done:
  433. return ret;
  434. }
  435. /*
  436. * free_pending_td: remove a pending request for the endpoint
  437. * @hwep: endpoint
  438. */
  439. static void free_pending_td(struct ci_hw_ep *hwep)
  440. {
  441. struct td_node *pending = hwep->pending_td;
  442. dma_pool_free(hwep->td_pool, pending->ptr, pending->dma);
  443. hwep->pending_td = NULL;
  444. kfree(pending);
  445. }
  446. /**
  447. * _hardware_dequeue: handles a request at hardware level
  448. * @gadget: gadget
  449. * @hwep: endpoint
  450. *
  451. * This function returns an error code
  452. */
  453. static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
  454. {
  455. u32 tmptoken;
  456. struct td_node *node, *tmpnode;
  457. unsigned remaining_length;
  458. unsigned actual = hwreq->req.length;
  459. if (hwreq->req.status != -EALREADY)
  460. return -EINVAL;
  461. hwreq->req.status = 0;
  462. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  463. tmptoken = le32_to_cpu(node->ptr->token);
  464. if ((TD_STATUS_ACTIVE & tmptoken) != 0) {
  465. hwreq->req.status = -EALREADY;
  466. return -EBUSY;
  467. }
  468. remaining_length = (tmptoken & TD_TOTAL_BYTES);
  469. remaining_length >>= __ffs(TD_TOTAL_BYTES);
  470. actual -= remaining_length;
  471. hwreq->req.status = tmptoken & TD_STATUS;
  472. if ((TD_STATUS_HALTED & hwreq->req.status)) {
  473. hwreq->req.status = -EPIPE;
  474. break;
  475. } else if ((TD_STATUS_DT_ERR & hwreq->req.status)) {
  476. hwreq->req.status = -EPROTO;
  477. break;
  478. } else if ((TD_STATUS_TR_ERR & hwreq->req.status)) {
  479. hwreq->req.status = -EILSEQ;
  480. break;
  481. }
  482. if (remaining_length) {
  483. if (hwep->dir) {
  484. hwreq->req.status = -EPROTO;
  485. break;
  486. }
  487. }
  488. /*
  489. * As the hardware could still address the freed td
  490. * which will run the udc unusable, the cleanup of the
  491. * td has to be delayed by one.
  492. */
  493. if (hwep->pending_td)
  494. free_pending_td(hwep);
  495. hwep->pending_td = node;
  496. list_del_init(&node->td);
  497. }
  498. usb_gadget_unmap_request(&hwep->ci->gadget, &hwreq->req, hwep->dir);
  499. hwreq->req.actual += actual;
  500. if (hwreq->req.status)
  501. return hwreq->req.status;
  502. return hwreq->req.actual;
  503. }
  504. /**
  505. * _ep_nuke: dequeues all endpoint requests
  506. * @hwep: endpoint
  507. *
  508. * This function returns an error code
  509. * Caller must hold lock
  510. */
  511. static int _ep_nuke(struct ci_hw_ep *hwep)
  512. __releases(hwep->lock)
  513. __acquires(hwep->lock)
  514. {
  515. struct td_node *node, *tmpnode;
  516. if (hwep == NULL)
  517. return -EINVAL;
  518. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  519. while (!list_empty(&hwep->qh.queue)) {
  520. /* pop oldest request */
  521. struct ci_hw_req *hwreq = list_entry(hwep->qh.queue.next,
  522. struct ci_hw_req, queue);
  523. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  524. dma_pool_free(hwep->td_pool, node->ptr, node->dma);
  525. list_del_init(&node->td);
  526. node->ptr = NULL;
  527. kfree(node);
  528. }
  529. list_del_init(&hwreq->queue);
  530. hwreq->req.status = -ESHUTDOWN;
  531. if (hwreq->req.complete != NULL) {
  532. spin_unlock(hwep->lock);
  533. hwreq->req.complete(&hwep->ep, &hwreq->req);
  534. spin_lock(hwep->lock);
  535. }
  536. }
  537. if (hwep->pending_td)
  538. free_pending_td(hwep);
  539. return 0;
  540. }
  541. /**
  542. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  543. * @gadget: gadget
  544. *
  545. * This function returns an error code
  546. */
  547. static int _gadget_stop_activity(struct usb_gadget *gadget)
  548. {
  549. struct usb_ep *ep;
  550. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  551. unsigned long flags;
  552. spin_lock_irqsave(&ci->lock, flags);
  553. ci->gadget.speed = USB_SPEED_UNKNOWN;
  554. ci->remote_wakeup = 0;
  555. ci->suspended = 0;
  556. spin_unlock_irqrestore(&ci->lock, flags);
  557. /* flush all endpoints */
  558. gadget_for_each_ep(ep, gadget) {
  559. usb_ep_fifo_flush(ep);
  560. }
  561. usb_ep_fifo_flush(&ci->ep0out->ep);
  562. usb_ep_fifo_flush(&ci->ep0in->ep);
  563. /* make sure to disable all endpoints */
  564. gadget_for_each_ep(ep, gadget) {
  565. usb_ep_disable(ep);
  566. }
  567. if (ci->status != NULL) {
  568. usb_ep_free_request(&ci->ep0in->ep, ci->status);
  569. ci->status = NULL;
  570. }
  571. return 0;
  572. }
  573. /******************************************************************************
  574. * ISR block
  575. *****************************************************************************/
  576. /**
  577. * isr_reset_handler: USB reset interrupt handler
  578. * @ci: UDC device
  579. *
  580. * This function resets USB engine after a bus reset occurred
  581. */
  582. static void isr_reset_handler(struct ci_hdrc *ci)
  583. __releases(ci->lock)
  584. __acquires(ci->lock)
  585. {
  586. int retval;
  587. spin_unlock(&ci->lock);
  588. if (ci->gadget.speed != USB_SPEED_UNKNOWN) {
  589. if (ci->driver)
  590. ci->driver->disconnect(&ci->gadget);
  591. }
  592. retval = _gadget_stop_activity(&ci->gadget);
  593. if (retval)
  594. goto done;
  595. retval = hw_usb_reset(ci);
  596. if (retval)
  597. goto done;
  598. ci->status = usb_ep_alloc_request(&ci->ep0in->ep, GFP_ATOMIC);
  599. if (ci->status == NULL)
  600. retval = -ENOMEM;
  601. usb_gadget_set_state(&ci->gadget, USB_STATE_DEFAULT);
  602. done:
  603. spin_lock(&ci->lock);
  604. if (retval)
  605. dev_err(ci->dev, "error: %i\n", retval);
  606. }
  607. /**
  608. * isr_get_status_complete: get_status request complete function
  609. * @ep: endpoint
  610. * @req: request handled
  611. *
  612. * Caller must release lock
  613. */
  614. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  615. {
  616. if (ep == NULL || req == NULL)
  617. return;
  618. kfree(req->buf);
  619. usb_ep_free_request(ep, req);
  620. }
  621. /**
  622. * _ep_queue: queues (submits) an I/O request to an endpoint
  623. *
  624. * Caller must hold lock
  625. */
  626. static int _ep_queue(struct usb_ep *ep, struct usb_request *req,
  627. gfp_t __maybe_unused gfp_flags)
  628. {
  629. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  630. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  631. struct ci_hdrc *ci = hwep->ci;
  632. int retval = 0;
  633. if (ep == NULL || req == NULL || hwep->ep.desc == NULL)
  634. return -EINVAL;
  635. if (hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  636. if (req->length)
  637. hwep = (ci->ep0_dir == RX) ?
  638. ci->ep0out : ci->ep0in;
  639. if (!list_empty(&hwep->qh.queue)) {
  640. _ep_nuke(hwep);
  641. retval = -EOVERFLOW;
  642. dev_warn(hwep->ci->dev, "endpoint ctrl %X nuked\n",
  643. _usb_addr(hwep));
  644. }
  645. }
  646. if (usb_endpoint_xfer_isoc(hwep->ep.desc) &&
  647. hwreq->req.length > (1 + hwep->ep.mult) * hwep->ep.maxpacket) {
  648. dev_err(hwep->ci->dev, "request length too big for isochronous\n");
  649. return -EMSGSIZE;
  650. }
  651. /* first nuke then test link, e.g. previous status has not sent */
  652. if (!list_empty(&hwreq->queue)) {
  653. dev_err(hwep->ci->dev, "request already in queue\n");
  654. return -EBUSY;
  655. }
  656. /* push request */
  657. hwreq->req.status = -EINPROGRESS;
  658. hwreq->req.actual = 0;
  659. retval = _hardware_enqueue(hwep, hwreq);
  660. if (retval == -EALREADY)
  661. retval = 0;
  662. if (!retval)
  663. list_add_tail(&hwreq->queue, &hwep->qh.queue);
  664. return retval;
  665. }
  666. /**
  667. * isr_get_status_response: get_status request response
  668. * @ci: ci struct
  669. * @setup: setup request packet
  670. *
  671. * This function returns an error code
  672. */
  673. static int isr_get_status_response(struct ci_hdrc *ci,
  674. struct usb_ctrlrequest *setup)
  675. __releases(hwep->lock)
  676. __acquires(hwep->lock)
  677. {
  678. struct ci_hw_ep *hwep = ci->ep0in;
  679. struct usb_request *req = NULL;
  680. gfp_t gfp_flags = GFP_ATOMIC;
  681. int dir, num, retval;
  682. if (hwep == NULL || setup == NULL)
  683. return -EINVAL;
  684. spin_unlock(hwep->lock);
  685. req = usb_ep_alloc_request(&hwep->ep, gfp_flags);
  686. spin_lock(hwep->lock);
  687. if (req == NULL)
  688. return -ENOMEM;
  689. req->complete = isr_get_status_complete;
  690. req->length = 2;
  691. req->buf = kzalloc(req->length, gfp_flags);
  692. if (req->buf == NULL) {
  693. retval = -ENOMEM;
  694. goto err_free_req;
  695. }
  696. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  697. /* Assume that device is bus powered for now. */
  698. *(u16 *)req->buf = ci->remote_wakeup << 1;
  699. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  700. == USB_RECIP_ENDPOINT) {
  701. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  702. TX : RX;
  703. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  704. *(u16 *)req->buf = hw_ep_get_halt(ci, num, dir);
  705. }
  706. /* else do nothing; reserved for future use */
  707. retval = _ep_queue(&hwep->ep, req, gfp_flags);
  708. if (retval)
  709. goto err_free_buf;
  710. return 0;
  711. err_free_buf:
  712. kfree(req->buf);
  713. err_free_req:
  714. spin_unlock(hwep->lock);
  715. usb_ep_free_request(&hwep->ep, req);
  716. spin_lock(hwep->lock);
  717. return retval;
  718. }
  719. /**
  720. * isr_setup_status_complete: setup_status request complete function
  721. * @ep: endpoint
  722. * @req: request handled
  723. *
  724. * Caller must release lock. Put the port in test mode if test mode
  725. * feature is selected.
  726. */
  727. static void
  728. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  729. {
  730. struct ci_hdrc *ci = req->context;
  731. unsigned long flags;
  732. if (ci->setaddr) {
  733. hw_usb_set_address(ci, ci->address);
  734. ci->setaddr = false;
  735. if (ci->address)
  736. usb_gadget_set_state(&ci->gadget, USB_STATE_ADDRESS);
  737. }
  738. spin_lock_irqsave(&ci->lock, flags);
  739. if (ci->test_mode)
  740. hw_port_test_set(ci, ci->test_mode);
  741. spin_unlock_irqrestore(&ci->lock, flags);
  742. }
  743. /**
  744. * isr_setup_status_phase: queues the status phase of a setup transation
  745. * @ci: ci struct
  746. *
  747. * This function returns an error code
  748. */
  749. static int isr_setup_status_phase(struct ci_hdrc *ci)
  750. {
  751. int retval;
  752. struct ci_hw_ep *hwep;
  753. hwep = (ci->ep0_dir == TX) ? ci->ep0out : ci->ep0in;
  754. ci->status->context = ci;
  755. ci->status->complete = isr_setup_status_complete;
  756. retval = _ep_queue(&hwep->ep, ci->status, GFP_ATOMIC);
  757. return retval;
  758. }
  759. /**
  760. * isr_tr_complete_low: transaction complete low level handler
  761. * @hwep: endpoint
  762. *
  763. * This function returns an error code
  764. * Caller must hold lock
  765. */
  766. static int isr_tr_complete_low(struct ci_hw_ep *hwep)
  767. __releases(hwep->lock)
  768. __acquires(hwep->lock)
  769. {
  770. struct ci_hw_req *hwreq, *hwreqtemp;
  771. struct ci_hw_ep *hweptemp = hwep;
  772. int retval = 0;
  773. list_for_each_entry_safe(hwreq, hwreqtemp, &hwep->qh.queue,
  774. queue) {
  775. retval = _hardware_dequeue(hwep, hwreq);
  776. if (retval < 0)
  777. break;
  778. list_del_init(&hwreq->queue);
  779. if (hwreq->req.complete != NULL) {
  780. spin_unlock(hwep->lock);
  781. if ((hwep->type == USB_ENDPOINT_XFER_CONTROL) &&
  782. hwreq->req.length)
  783. hweptemp = hwep->ci->ep0in;
  784. hwreq->req.complete(&hweptemp->ep, &hwreq->req);
  785. spin_lock(hwep->lock);
  786. }
  787. }
  788. if (retval == -EBUSY)
  789. retval = 0;
  790. return retval;
  791. }
  792. /**
  793. * isr_setup_packet_handler: setup packet handler
  794. * @ci: UDC descriptor
  795. *
  796. * This function handles setup packet
  797. */
  798. static void isr_setup_packet_handler(struct ci_hdrc *ci)
  799. __releases(ci->lock)
  800. __acquires(ci->lock)
  801. {
  802. struct ci_hw_ep *hwep = &ci->ci_hw_ep[0];
  803. struct usb_ctrlrequest req;
  804. int type, num, dir, err = -EINVAL;
  805. u8 tmode = 0;
  806. /*
  807. * Flush data and handshake transactions of previous
  808. * setup packet.
  809. */
  810. _ep_nuke(ci->ep0out);
  811. _ep_nuke(ci->ep0in);
  812. /* read_setup_packet */
  813. do {
  814. hw_test_and_set_setup_guard(ci);
  815. memcpy(&req, &hwep->qh.ptr->setup, sizeof(req));
  816. } while (!hw_test_and_clear_setup_guard(ci));
  817. type = req.bRequestType;
  818. ci->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  819. switch (req.bRequest) {
  820. case USB_REQ_CLEAR_FEATURE:
  821. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  822. le16_to_cpu(req.wValue) ==
  823. USB_ENDPOINT_HALT) {
  824. if (req.wLength != 0)
  825. break;
  826. num = le16_to_cpu(req.wIndex);
  827. dir = num & USB_ENDPOINT_DIR_MASK;
  828. num &= USB_ENDPOINT_NUMBER_MASK;
  829. if (dir) /* TX */
  830. num += ci->hw_ep_max / 2;
  831. if (!ci->ci_hw_ep[num].wedge) {
  832. spin_unlock(&ci->lock);
  833. err = usb_ep_clear_halt(
  834. &ci->ci_hw_ep[num].ep);
  835. spin_lock(&ci->lock);
  836. if (err)
  837. break;
  838. }
  839. err = isr_setup_status_phase(ci);
  840. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  841. le16_to_cpu(req.wValue) ==
  842. USB_DEVICE_REMOTE_WAKEUP) {
  843. if (req.wLength != 0)
  844. break;
  845. ci->remote_wakeup = 0;
  846. err = isr_setup_status_phase(ci);
  847. } else {
  848. goto delegate;
  849. }
  850. break;
  851. case USB_REQ_GET_STATUS:
  852. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  853. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  854. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  855. goto delegate;
  856. if (le16_to_cpu(req.wLength) != 2 ||
  857. le16_to_cpu(req.wValue) != 0)
  858. break;
  859. err = isr_get_status_response(ci, &req);
  860. break;
  861. case USB_REQ_SET_ADDRESS:
  862. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  863. goto delegate;
  864. if (le16_to_cpu(req.wLength) != 0 ||
  865. le16_to_cpu(req.wIndex) != 0)
  866. break;
  867. ci->address = (u8)le16_to_cpu(req.wValue);
  868. ci->setaddr = true;
  869. err = isr_setup_status_phase(ci);
  870. break;
  871. case USB_REQ_SET_FEATURE:
  872. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  873. le16_to_cpu(req.wValue) ==
  874. USB_ENDPOINT_HALT) {
  875. if (req.wLength != 0)
  876. break;
  877. num = le16_to_cpu(req.wIndex);
  878. dir = num & USB_ENDPOINT_DIR_MASK;
  879. num &= USB_ENDPOINT_NUMBER_MASK;
  880. if (dir) /* TX */
  881. num += ci->hw_ep_max / 2;
  882. spin_unlock(&ci->lock);
  883. err = usb_ep_set_halt(&ci->ci_hw_ep[num].ep);
  884. spin_lock(&ci->lock);
  885. if (!err)
  886. isr_setup_status_phase(ci);
  887. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  888. if (req.wLength != 0)
  889. break;
  890. switch (le16_to_cpu(req.wValue)) {
  891. case USB_DEVICE_REMOTE_WAKEUP:
  892. ci->remote_wakeup = 1;
  893. err = isr_setup_status_phase(ci);
  894. break;
  895. case USB_DEVICE_TEST_MODE:
  896. tmode = le16_to_cpu(req.wIndex) >> 8;
  897. switch (tmode) {
  898. case TEST_J:
  899. case TEST_K:
  900. case TEST_SE0_NAK:
  901. case TEST_PACKET:
  902. case TEST_FORCE_EN:
  903. ci->test_mode = tmode;
  904. err = isr_setup_status_phase(
  905. ci);
  906. break;
  907. default:
  908. break;
  909. }
  910. break;
  911. case USB_DEVICE_B_HNP_ENABLE:
  912. if (ci_otg_is_fsm_mode(ci)) {
  913. ci->gadget.b_hnp_enable = 1;
  914. err = isr_setup_status_phase(
  915. ci);
  916. }
  917. break;
  918. default:
  919. goto delegate;
  920. }
  921. } else {
  922. goto delegate;
  923. }
  924. break;
  925. default:
  926. delegate:
  927. if (req.wLength == 0) /* no data phase */
  928. ci->ep0_dir = TX;
  929. spin_unlock(&ci->lock);
  930. err = ci->driver->setup(&ci->gadget, &req);
  931. spin_lock(&ci->lock);
  932. break;
  933. }
  934. if (err < 0) {
  935. spin_unlock(&ci->lock);
  936. if (usb_ep_set_halt(&hwep->ep))
  937. dev_err(ci->dev, "error: ep_set_halt\n");
  938. spin_lock(&ci->lock);
  939. }
  940. }
  941. /**
  942. * isr_tr_complete_handler: transaction complete interrupt handler
  943. * @ci: UDC descriptor
  944. *
  945. * This function handles traffic events
  946. */
  947. static void isr_tr_complete_handler(struct ci_hdrc *ci)
  948. __releases(ci->lock)
  949. __acquires(ci->lock)
  950. {
  951. unsigned i;
  952. int err;
  953. for (i = 0; i < ci->hw_ep_max; i++) {
  954. struct ci_hw_ep *hwep = &ci->ci_hw_ep[i];
  955. if (hwep->ep.desc == NULL)
  956. continue; /* not configured */
  957. if (hw_test_and_clear_complete(ci, i)) {
  958. err = isr_tr_complete_low(hwep);
  959. if (hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  960. if (err > 0) /* needs status phase */
  961. err = isr_setup_status_phase(ci);
  962. if (err < 0) {
  963. spin_unlock(&ci->lock);
  964. if (usb_ep_set_halt(&hwep->ep))
  965. dev_err(ci->dev,
  966. "error: ep_set_halt\n");
  967. spin_lock(&ci->lock);
  968. }
  969. }
  970. }
  971. /* Only handle setup packet below */
  972. if (i == 0 &&
  973. hw_test_and_clear(ci, OP_ENDPTSETUPSTAT, BIT(0)))
  974. isr_setup_packet_handler(ci);
  975. }
  976. }
  977. /******************************************************************************
  978. * ENDPT block
  979. *****************************************************************************/
  980. /**
  981. * ep_enable: configure endpoint, making it usable
  982. *
  983. * Check usb_ep_enable() at "usb_gadget.h" for details
  984. */
  985. static int ep_enable(struct usb_ep *ep,
  986. const struct usb_endpoint_descriptor *desc)
  987. {
  988. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  989. int retval = 0;
  990. unsigned long flags;
  991. u32 cap = 0;
  992. if (ep == NULL || desc == NULL)
  993. return -EINVAL;
  994. spin_lock_irqsave(hwep->lock, flags);
  995. /* only internal SW should enable ctrl endpts */
  996. hwep->ep.desc = desc;
  997. if (!list_empty(&hwep->qh.queue))
  998. dev_warn(hwep->ci->dev, "enabling a non-empty endpoint!\n");
  999. hwep->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1000. hwep->num = usb_endpoint_num(desc);
  1001. hwep->type = usb_endpoint_type(desc);
  1002. hwep->ep.maxpacket = usb_endpoint_maxp(desc) & 0x07ff;
  1003. hwep->ep.mult = QH_ISO_MULT(usb_endpoint_maxp(desc));
  1004. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  1005. cap |= QH_IOS;
  1006. cap |= QH_ZLT;
  1007. cap |= (hwep->ep.maxpacket << __ffs(QH_MAX_PKT)) & QH_MAX_PKT;
  1008. /*
  1009. * For ISO-TX, we set mult at QH as the largest value, and use
  1010. * MultO at TD as real mult value.
  1011. */
  1012. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == TX)
  1013. cap |= 3 << __ffs(QH_MULT);
  1014. hwep->qh.ptr->cap = cpu_to_le32(cap);
  1015. hwep->qh.ptr->td.next |= cpu_to_le32(TD_TERMINATE); /* needed? */
  1016. if (hwep->num != 0 && hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  1017. dev_err(hwep->ci->dev, "Set control xfer at non-ep0\n");
  1018. retval = -EINVAL;
  1019. }
  1020. /*
  1021. * Enable endpoints in the HW other than ep0 as ep0
  1022. * is always enabled
  1023. */
  1024. if (hwep->num)
  1025. retval |= hw_ep_enable(hwep->ci, hwep->num, hwep->dir,
  1026. hwep->type);
  1027. spin_unlock_irqrestore(hwep->lock, flags);
  1028. return retval;
  1029. }
  1030. /**
  1031. * ep_disable: endpoint is no longer usable
  1032. *
  1033. * Check usb_ep_disable() at "usb_gadget.h" for details
  1034. */
  1035. static int ep_disable(struct usb_ep *ep)
  1036. {
  1037. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1038. int direction, retval = 0;
  1039. unsigned long flags;
  1040. if (ep == NULL)
  1041. return -EINVAL;
  1042. else if (hwep->ep.desc == NULL)
  1043. return -EBUSY;
  1044. spin_lock_irqsave(hwep->lock, flags);
  1045. /* only internal SW should disable ctrl endpts */
  1046. direction = hwep->dir;
  1047. do {
  1048. retval |= _ep_nuke(hwep);
  1049. retval |= hw_ep_disable(hwep->ci, hwep->num, hwep->dir);
  1050. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  1051. hwep->dir = (hwep->dir == TX) ? RX : TX;
  1052. } while (hwep->dir != direction);
  1053. hwep->ep.desc = NULL;
  1054. spin_unlock_irqrestore(hwep->lock, flags);
  1055. return retval;
  1056. }
  1057. /**
  1058. * ep_alloc_request: allocate a request object to use with this endpoint
  1059. *
  1060. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1061. */
  1062. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1063. {
  1064. struct ci_hw_req *hwreq = NULL;
  1065. if (ep == NULL)
  1066. return NULL;
  1067. hwreq = kzalloc(sizeof(struct ci_hw_req), gfp_flags);
  1068. if (hwreq != NULL) {
  1069. INIT_LIST_HEAD(&hwreq->queue);
  1070. INIT_LIST_HEAD(&hwreq->tds);
  1071. }
  1072. return (hwreq == NULL) ? NULL : &hwreq->req;
  1073. }
  1074. /**
  1075. * ep_free_request: frees a request object
  1076. *
  1077. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1078. */
  1079. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1080. {
  1081. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1082. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  1083. struct td_node *node, *tmpnode;
  1084. unsigned long flags;
  1085. if (ep == NULL || req == NULL) {
  1086. return;
  1087. } else if (!list_empty(&hwreq->queue)) {
  1088. dev_err(hwep->ci->dev, "freeing queued request\n");
  1089. return;
  1090. }
  1091. spin_lock_irqsave(hwep->lock, flags);
  1092. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  1093. dma_pool_free(hwep->td_pool, node->ptr, node->dma);
  1094. list_del_init(&node->td);
  1095. node->ptr = NULL;
  1096. kfree(node);
  1097. }
  1098. kfree(hwreq);
  1099. spin_unlock_irqrestore(hwep->lock, flags);
  1100. }
  1101. /**
  1102. * ep_queue: queues (submits) an I/O request to an endpoint
  1103. *
  1104. * Check usb_ep_queue()* at usb_gadget.h" for details
  1105. */
  1106. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1107. gfp_t __maybe_unused gfp_flags)
  1108. {
  1109. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1110. int retval = 0;
  1111. unsigned long flags;
  1112. if (ep == NULL || req == NULL || hwep->ep.desc == NULL)
  1113. return -EINVAL;
  1114. spin_lock_irqsave(hwep->lock, flags);
  1115. retval = _ep_queue(ep, req, gfp_flags);
  1116. spin_unlock_irqrestore(hwep->lock, flags);
  1117. return retval;
  1118. }
  1119. /**
  1120. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  1121. *
  1122. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  1123. */
  1124. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  1125. {
  1126. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1127. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  1128. unsigned long flags;
  1129. struct td_node *node, *tmpnode;
  1130. if (ep == NULL || req == NULL || hwreq->req.status != -EALREADY ||
  1131. hwep->ep.desc == NULL || list_empty(&hwreq->queue) ||
  1132. list_empty(&hwep->qh.queue))
  1133. return -EINVAL;
  1134. spin_lock_irqsave(hwep->lock, flags);
  1135. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  1136. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  1137. dma_pool_free(hwep->td_pool, node->ptr, node->dma);
  1138. list_del(&node->td);
  1139. kfree(node);
  1140. }
  1141. /* pop request */
  1142. list_del_init(&hwreq->queue);
  1143. usb_gadget_unmap_request(&hwep->ci->gadget, req, hwep->dir);
  1144. req->status = -ECONNRESET;
  1145. if (hwreq->req.complete != NULL) {
  1146. spin_unlock(hwep->lock);
  1147. hwreq->req.complete(&hwep->ep, &hwreq->req);
  1148. spin_lock(hwep->lock);
  1149. }
  1150. spin_unlock_irqrestore(hwep->lock, flags);
  1151. return 0;
  1152. }
  1153. /**
  1154. * ep_set_halt: sets the endpoint halt feature
  1155. *
  1156. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  1157. */
  1158. static int ep_set_halt(struct usb_ep *ep, int value)
  1159. {
  1160. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1161. int direction, retval = 0;
  1162. unsigned long flags;
  1163. if (ep == NULL || hwep->ep.desc == NULL)
  1164. return -EINVAL;
  1165. if (usb_endpoint_xfer_isoc(hwep->ep.desc))
  1166. return -EOPNOTSUPP;
  1167. spin_lock_irqsave(hwep->lock, flags);
  1168. #ifndef STALL_IN
  1169. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  1170. if (value && hwep->type == USB_ENDPOINT_XFER_BULK && hwep->dir == TX &&
  1171. !list_empty(&hwep->qh.queue)) {
  1172. spin_unlock_irqrestore(hwep->lock, flags);
  1173. return -EAGAIN;
  1174. }
  1175. #endif
  1176. direction = hwep->dir;
  1177. do {
  1178. retval |= hw_ep_set_halt(hwep->ci, hwep->num, hwep->dir, value);
  1179. if (!value)
  1180. hwep->wedge = 0;
  1181. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  1182. hwep->dir = (hwep->dir == TX) ? RX : TX;
  1183. } while (hwep->dir != direction);
  1184. spin_unlock_irqrestore(hwep->lock, flags);
  1185. return retval;
  1186. }
  1187. /**
  1188. * ep_set_wedge: sets the halt feature and ignores clear requests
  1189. *
  1190. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  1191. */
  1192. static int ep_set_wedge(struct usb_ep *ep)
  1193. {
  1194. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1195. unsigned long flags;
  1196. if (ep == NULL || hwep->ep.desc == NULL)
  1197. return -EINVAL;
  1198. spin_lock_irqsave(hwep->lock, flags);
  1199. hwep->wedge = 1;
  1200. spin_unlock_irqrestore(hwep->lock, flags);
  1201. return usb_ep_set_halt(ep);
  1202. }
  1203. /**
  1204. * ep_fifo_flush: flushes contents of a fifo
  1205. *
  1206. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  1207. */
  1208. static void ep_fifo_flush(struct usb_ep *ep)
  1209. {
  1210. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1211. unsigned long flags;
  1212. if (ep == NULL) {
  1213. dev_err(hwep->ci->dev, "%02X: -EINVAL\n", _usb_addr(hwep));
  1214. return;
  1215. }
  1216. spin_lock_irqsave(hwep->lock, flags);
  1217. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  1218. spin_unlock_irqrestore(hwep->lock, flags);
  1219. }
  1220. /**
  1221. * Endpoint-specific part of the API to the USB controller hardware
  1222. * Check "usb_gadget.h" for details
  1223. */
  1224. static const struct usb_ep_ops usb_ep_ops = {
  1225. .enable = ep_enable,
  1226. .disable = ep_disable,
  1227. .alloc_request = ep_alloc_request,
  1228. .free_request = ep_free_request,
  1229. .queue = ep_queue,
  1230. .dequeue = ep_dequeue,
  1231. .set_halt = ep_set_halt,
  1232. .set_wedge = ep_set_wedge,
  1233. .fifo_flush = ep_fifo_flush,
  1234. };
  1235. /******************************************************************************
  1236. * GADGET block
  1237. *****************************************************************************/
  1238. static int ci_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
  1239. {
  1240. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1241. unsigned long flags;
  1242. int gadget_ready = 0;
  1243. spin_lock_irqsave(&ci->lock, flags);
  1244. ci->vbus_active = is_active;
  1245. if (ci->driver)
  1246. gadget_ready = 1;
  1247. spin_unlock_irqrestore(&ci->lock, flags);
  1248. if (gadget_ready) {
  1249. if (is_active) {
  1250. pm_runtime_get_sync(&_gadget->dev);
  1251. hw_device_reset(ci, USBMODE_CM_DC);
  1252. hw_device_state(ci, ci->ep0out->qh.dma);
  1253. usb_gadget_set_state(_gadget, USB_STATE_POWERED);
  1254. } else {
  1255. if (ci->driver)
  1256. ci->driver->disconnect(&ci->gadget);
  1257. hw_device_state(ci, 0);
  1258. if (ci->platdata->notify_event)
  1259. ci->platdata->notify_event(ci,
  1260. CI_HDRC_CONTROLLER_STOPPED_EVENT);
  1261. _gadget_stop_activity(&ci->gadget);
  1262. pm_runtime_put_sync(&_gadget->dev);
  1263. usb_gadget_set_state(_gadget, USB_STATE_NOTATTACHED);
  1264. }
  1265. }
  1266. return 0;
  1267. }
  1268. static int ci_udc_wakeup(struct usb_gadget *_gadget)
  1269. {
  1270. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1271. unsigned long flags;
  1272. int ret = 0;
  1273. spin_lock_irqsave(&ci->lock, flags);
  1274. if (!ci->remote_wakeup) {
  1275. ret = -EOPNOTSUPP;
  1276. goto out;
  1277. }
  1278. if (!hw_read(ci, OP_PORTSC, PORTSC_SUSP)) {
  1279. ret = -EINVAL;
  1280. goto out;
  1281. }
  1282. hw_write(ci, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  1283. out:
  1284. spin_unlock_irqrestore(&ci->lock, flags);
  1285. return ret;
  1286. }
  1287. static int ci_udc_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1288. {
  1289. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1290. if (ci->transceiver)
  1291. return usb_phy_set_power(ci->transceiver, ma);
  1292. return -ENOTSUPP;
  1293. }
  1294. /* Change Data+ pullup status
  1295. * this func is used by usb_gadget_connect/disconnet
  1296. */
  1297. static int ci_udc_pullup(struct usb_gadget *_gadget, int is_on)
  1298. {
  1299. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1300. if (!ci->vbus_active)
  1301. return -EOPNOTSUPP;
  1302. if (is_on)
  1303. hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  1304. else
  1305. hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
  1306. return 0;
  1307. }
  1308. static int ci_udc_start(struct usb_gadget *gadget,
  1309. struct usb_gadget_driver *driver);
  1310. static int ci_udc_stop(struct usb_gadget *gadget,
  1311. struct usb_gadget_driver *driver);
  1312. /**
  1313. * Device operations part of the API to the USB controller hardware,
  1314. * which don't involve endpoints (or i/o)
  1315. * Check "usb_gadget.h" for details
  1316. */
  1317. static const struct usb_gadget_ops usb_gadget_ops = {
  1318. .vbus_session = ci_udc_vbus_session,
  1319. .wakeup = ci_udc_wakeup,
  1320. .pullup = ci_udc_pullup,
  1321. .vbus_draw = ci_udc_vbus_draw,
  1322. .udc_start = ci_udc_start,
  1323. .udc_stop = ci_udc_stop,
  1324. };
  1325. static int init_eps(struct ci_hdrc *ci)
  1326. {
  1327. int retval = 0, i, j;
  1328. for (i = 0; i < ci->hw_ep_max/2; i++)
  1329. for (j = RX; j <= TX; j++) {
  1330. int k = i + j * ci->hw_ep_max/2;
  1331. struct ci_hw_ep *hwep = &ci->ci_hw_ep[k];
  1332. scnprintf(hwep->name, sizeof(hwep->name), "ep%i%s", i,
  1333. (j == TX) ? "in" : "out");
  1334. hwep->ci = ci;
  1335. hwep->lock = &ci->lock;
  1336. hwep->td_pool = ci->td_pool;
  1337. hwep->ep.name = hwep->name;
  1338. hwep->ep.ops = &usb_ep_ops;
  1339. /*
  1340. * for ep0: maxP defined in desc, for other
  1341. * eps, maxP is set by epautoconfig() called
  1342. * by gadget layer
  1343. */
  1344. usb_ep_set_maxpacket_limit(&hwep->ep, (unsigned short)~0);
  1345. INIT_LIST_HEAD(&hwep->qh.queue);
  1346. hwep->qh.ptr = dma_pool_alloc(ci->qh_pool, GFP_KERNEL,
  1347. &hwep->qh.dma);
  1348. if (hwep->qh.ptr == NULL)
  1349. retval = -ENOMEM;
  1350. else
  1351. memset(hwep->qh.ptr, 0, sizeof(*hwep->qh.ptr));
  1352. /*
  1353. * set up shorthands for ep0 out and in endpoints,
  1354. * don't add to gadget's ep_list
  1355. */
  1356. if (i == 0) {
  1357. if (j == RX)
  1358. ci->ep0out = hwep;
  1359. else
  1360. ci->ep0in = hwep;
  1361. usb_ep_set_maxpacket_limit(&hwep->ep, CTRL_PAYLOAD_MAX);
  1362. continue;
  1363. }
  1364. list_add_tail(&hwep->ep.ep_list, &ci->gadget.ep_list);
  1365. }
  1366. return retval;
  1367. }
  1368. static void destroy_eps(struct ci_hdrc *ci)
  1369. {
  1370. int i;
  1371. for (i = 0; i < ci->hw_ep_max; i++) {
  1372. struct ci_hw_ep *hwep = &ci->ci_hw_ep[i];
  1373. if (hwep->pending_td)
  1374. free_pending_td(hwep);
  1375. dma_pool_free(ci->qh_pool, hwep->qh.ptr, hwep->qh.dma);
  1376. }
  1377. }
  1378. /**
  1379. * ci_udc_start: register a gadget driver
  1380. * @gadget: our gadget
  1381. * @driver: the driver being registered
  1382. *
  1383. * Interrupts are enabled here.
  1384. */
  1385. static int ci_udc_start(struct usb_gadget *gadget,
  1386. struct usb_gadget_driver *driver)
  1387. {
  1388. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  1389. unsigned long flags;
  1390. int retval = -ENOMEM;
  1391. if (driver->disconnect == NULL)
  1392. return -EINVAL;
  1393. ci->ep0out->ep.desc = &ctrl_endpt_out_desc;
  1394. retval = usb_ep_enable(&ci->ep0out->ep);
  1395. if (retval)
  1396. return retval;
  1397. ci->ep0in->ep.desc = &ctrl_endpt_in_desc;
  1398. retval = usb_ep_enable(&ci->ep0in->ep);
  1399. if (retval)
  1400. return retval;
  1401. ci->driver = driver;
  1402. /* Start otg fsm for B-device */
  1403. if (ci_otg_is_fsm_mode(ci) && ci->fsm.id) {
  1404. ci_hdrc_otg_fsm_start(ci);
  1405. return retval;
  1406. }
  1407. pm_runtime_get_sync(&ci->gadget.dev);
  1408. if (ci->vbus_active) {
  1409. spin_lock_irqsave(&ci->lock, flags);
  1410. hw_device_reset(ci, USBMODE_CM_DC);
  1411. } else {
  1412. pm_runtime_put_sync(&ci->gadget.dev);
  1413. return retval;
  1414. }
  1415. retval = hw_device_state(ci, ci->ep0out->qh.dma);
  1416. spin_unlock_irqrestore(&ci->lock, flags);
  1417. if (retval)
  1418. pm_runtime_put_sync(&ci->gadget.dev);
  1419. return retval;
  1420. }
  1421. /**
  1422. * ci_udc_stop: unregister a gadget driver
  1423. */
  1424. static int ci_udc_stop(struct usb_gadget *gadget,
  1425. struct usb_gadget_driver *driver)
  1426. {
  1427. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  1428. unsigned long flags;
  1429. spin_lock_irqsave(&ci->lock, flags);
  1430. if (ci->vbus_active) {
  1431. hw_device_state(ci, 0);
  1432. if (ci->platdata->notify_event)
  1433. ci->platdata->notify_event(ci,
  1434. CI_HDRC_CONTROLLER_STOPPED_EVENT);
  1435. spin_unlock_irqrestore(&ci->lock, flags);
  1436. _gadget_stop_activity(&ci->gadget);
  1437. spin_lock_irqsave(&ci->lock, flags);
  1438. pm_runtime_put(&ci->gadget.dev);
  1439. }
  1440. ci->driver = NULL;
  1441. spin_unlock_irqrestore(&ci->lock, flags);
  1442. return 0;
  1443. }
  1444. /******************************************************************************
  1445. * BUS block
  1446. *****************************************************************************/
  1447. /**
  1448. * udc_irq: ci interrupt handler
  1449. *
  1450. * This function returns IRQ_HANDLED if the IRQ has been handled
  1451. * It locks access to registers
  1452. */
  1453. static irqreturn_t udc_irq(struct ci_hdrc *ci)
  1454. {
  1455. irqreturn_t retval;
  1456. u32 intr;
  1457. if (ci == NULL)
  1458. return IRQ_HANDLED;
  1459. spin_lock(&ci->lock);
  1460. if (ci->platdata->flags & CI_HDRC_REGS_SHARED) {
  1461. if (hw_read(ci, OP_USBMODE, USBMODE_CM) !=
  1462. USBMODE_CM_DC) {
  1463. spin_unlock(&ci->lock);
  1464. return IRQ_NONE;
  1465. }
  1466. }
  1467. intr = hw_test_and_clear_intr_active(ci);
  1468. if (intr) {
  1469. /* order defines priority - do NOT change it */
  1470. if (USBi_URI & intr)
  1471. isr_reset_handler(ci);
  1472. if (USBi_PCI & intr) {
  1473. ci->gadget.speed = hw_port_is_high_speed(ci) ?
  1474. USB_SPEED_HIGH : USB_SPEED_FULL;
  1475. if (ci->suspended && ci->driver->resume) {
  1476. spin_unlock(&ci->lock);
  1477. ci->driver->resume(&ci->gadget);
  1478. spin_lock(&ci->lock);
  1479. ci->suspended = 0;
  1480. }
  1481. }
  1482. if (USBi_UI & intr)
  1483. isr_tr_complete_handler(ci);
  1484. if (USBi_SLI & intr) {
  1485. if (ci->gadget.speed != USB_SPEED_UNKNOWN &&
  1486. ci->driver->suspend) {
  1487. ci->suspended = 1;
  1488. spin_unlock(&ci->lock);
  1489. ci->driver->suspend(&ci->gadget);
  1490. usb_gadget_set_state(&ci->gadget,
  1491. USB_STATE_SUSPENDED);
  1492. spin_lock(&ci->lock);
  1493. }
  1494. }
  1495. retval = IRQ_HANDLED;
  1496. } else {
  1497. retval = IRQ_NONE;
  1498. }
  1499. spin_unlock(&ci->lock);
  1500. return retval;
  1501. }
  1502. /**
  1503. * udc_start: initialize gadget role
  1504. * @ci: chipidea controller
  1505. */
  1506. static int udc_start(struct ci_hdrc *ci)
  1507. {
  1508. struct device *dev = ci->dev;
  1509. int retval = 0;
  1510. spin_lock_init(&ci->lock);
  1511. ci->gadget.ops = &usb_gadget_ops;
  1512. ci->gadget.speed = USB_SPEED_UNKNOWN;
  1513. ci->gadget.max_speed = USB_SPEED_HIGH;
  1514. ci->gadget.is_otg = ci->is_otg ? 1 : 0;
  1515. ci->gadget.name = ci->platdata->name;
  1516. INIT_LIST_HEAD(&ci->gadget.ep_list);
  1517. /* alloc resources */
  1518. ci->qh_pool = dma_pool_create("ci_hw_qh", dev,
  1519. sizeof(struct ci_hw_qh),
  1520. 64, CI_HDRC_PAGE_SIZE);
  1521. if (ci->qh_pool == NULL)
  1522. return -ENOMEM;
  1523. ci->td_pool = dma_pool_create("ci_hw_td", dev,
  1524. sizeof(struct ci_hw_td),
  1525. 64, CI_HDRC_PAGE_SIZE);
  1526. if (ci->td_pool == NULL) {
  1527. retval = -ENOMEM;
  1528. goto free_qh_pool;
  1529. }
  1530. retval = init_eps(ci);
  1531. if (retval)
  1532. goto free_pools;
  1533. ci->gadget.ep0 = &ci->ep0in->ep;
  1534. retval = usb_add_gadget_udc(dev, &ci->gadget);
  1535. if (retval)
  1536. goto destroy_eps;
  1537. pm_runtime_no_callbacks(&ci->gadget.dev);
  1538. pm_runtime_enable(&ci->gadget.dev);
  1539. return retval;
  1540. destroy_eps:
  1541. destroy_eps(ci);
  1542. free_pools:
  1543. dma_pool_destroy(ci->td_pool);
  1544. free_qh_pool:
  1545. dma_pool_destroy(ci->qh_pool);
  1546. return retval;
  1547. }
  1548. /**
  1549. * ci_hdrc_gadget_destroy: parent remove must call this to remove UDC
  1550. *
  1551. * No interrupts active, the IRQ has been released
  1552. */
  1553. void ci_hdrc_gadget_destroy(struct ci_hdrc *ci)
  1554. {
  1555. if (!ci->roles[CI_ROLE_GADGET])
  1556. return;
  1557. usb_del_gadget_udc(&ci->gadget);
  1558. destroy_eps(ci);
  1559. dma_pool_destroy(ci->td_pool);
  1560. dma_pool_destroy(ci->qh_pool);
  1561. }
  1562. static int udc_id_switch_for_device(struct ci_hdrc *ci)
  1563. {
  1564. if (ci->is_otg)
  1565. /* Clear and enable BSV irq */
  1566. hw_write_otgsc(ci, OTGSC_BSVIS | OTGSC_BSVIE,
  1567. OTGSC_BSVIS | OTGSC_BSVIE);
  1568. return 0;
  1569. }
  1570. static void udc_id_switch_for_host(struct ci_hdrc *ci)
  1571. {
  1572. /*
  1573. * host doesn't care B_SESSION_VALID event
  1574. * so clear and disbale BSV irq
  1575. */
  1576. if (ci->is_otg)
  1577. hw_write_otgsc(ci, OTGSC_BSVIE | OTGSC_BSVIS, OTGSC_BSVIS);
  1578. }
  1579. /**
  1580. * ci_hdrc_gadget_init - initialize device related bits
  1581. * ci: the controller
  1582. *
  1583. * This function initializes the gadget, if the device is "device capable".
  1584. */
  1585. int ci_hdrc_gadget_init(struct ci_hdrc *ci)
  1586. {
  1587. struct ci_role_driver *rdrv;
  1588. if (!hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DC))
  1589. return -ENXIO;
  1590. rdrv = devm_kzalloc(ci->dev, sizeof(struct ci_role_driver), GFP_KERNEL);
  1591. if (!rdrv)
  1592. return -ENOMEM;
  1593. rdrv->start = udc_id_switch_for_device;
  1594. rdrv->stop = udc_id_switch_for_host;
  1595. rdrv->irq = udc_irq;
  1596. rdrv->name = "gadget";
  1597. ci->roles[CI_ROLE_GADGET] = rdrv;
  1598. return udc_start(ci);
  1599. }