qeth_core_main.c 160 KB

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  1. /*
  2. * Copyright IBM Corp. 2007, 2009
  3. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  4. * Frank Pavlic <fpavlic@de.ibm.com>,
  5. * Thomas Spatzier <tspat@de.ibm.com>,
  6. * Frank Blaschka <frank.blaschka@de.ibm.com>
  7. */
  8. #define KMSG_COMPONENT "qeth"
  9. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ip.h>
  16. #include <linux/tcp.h>
  17. #include <linux/mii.h>
  18. #include <linux/kthread.h>
  19. #include <linux/slab.h>
  20. #include <net/iucv/af_iucv.h>
  21. #include <net/dsfield.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/chpid.h>
  24. #include <asm/io.h>
  25. #include <asm/sysinfo.h>
  26. #include <asm/compat.h>
  27. #include "qeth_core.h"
  28. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  29. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  30. /* N P A M L V H */
  31. [QETH_DBF_SETUP] = {"qeth_setup",
  32. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  33. [QETH_DBF_MSG] = {"qeth_msg", 8, 1, 11 * sizeof(long), 3,
  34. &debug_sprintf_view, NULL},
  35. [QETH_DBF_CTRL] = {"qeth_control",
  36. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  37. };
  38. EXPORT_SYMBOL_GPL(qeth_dbf);
  39. struct qeth_card_list_struct qeth_core_card_list;
  40. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  41. struct kmem_cache *qeth_core_header_cache;
  42. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  43. static struct kmem_cache *qeth_qdio_outbuf_cache;
  44. static struct device *qeth_core_root_dev;
  45. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  46. static struct lock_class_key qdio_out_skb_queue_key;
  47. static struct mutex qeth_mod_mutex;
  48. static void qeth_send_control_data_cb(struct qeth_channel *,
  49. struct qeth_cmd_buffer *);
  50. static int qeth_issue_next_read(struct qeth_card *);
  51. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  52. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  53. static void qeth_free_buffer_pool(struct qeth_card *);
  54. static int qeth_qdio_establish(struct qeth_card *);
  55. static void qeth_free_qdio_buffers(struct qeth_card *);
  56. static void qeth_notify_skbs(struct qeth_qdio_out_q *queue,
  57. struct qeth_qdio_out_buffer *buf,
  58. enum iucv_tx_notify notification);
  59. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf);
  60. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  61. struct qeth_qdio_out_buffer *buf,
  62. enum qeth_qdio_buffer_states newbufstate);
  63. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *, int);
  64. struct workqueue_struct *qeth_wq;
  65. EXPORT_SYMBOL_GPL(qeth_wq);
  66. static void qeth_close_dev_handler(struct work_struct *work)
  67. {
  68. struct qeth_card *card;
  69. card = container_of(work, struct qeth_card, close_dev_work);
  70. QETH_CARD_TEXT(card, 2, "cldevhdl");
  71. rtnl_lock();
  72. dev_close(card->dev);
  73. rtnl_unlock();
  74. ccwgroup_set_offline(card->gdev);
  75. }
  76. void qeth_close_dev(struct qeth_card *card)
  77. {
  78. QETH_CARD_TEXT(card, 2, "cldevsubm");
  79. queue_work(qeth_wq, &card->close_dev_work);
  80. }
  81. EXPORT_SYMBOL_GPL(qeth_close_dev);
  82. static inline const char *qeth_get_cardname(struct qeth_card *card)
  83. {
  84. if (card->info.guestlan) {
  85. switch (card->info.type) {
  86. case QETH_CARD_TYPE_OSD:
  87. return " Virtual NIC QDIO";
  88. case QETH_CARD_TYPE_IQD:
  89. return " Virtual NIC Hiper";
  90. case QETH_CARD_TYPE_OSM:
  91. return " Virtual NIC QDIO - OSM";
  92. case QETH_CARD_TYPE_OSX:
  93. return " Virtual NIC QDIO - OSX";
  94. default:
  95. return " unknown";
  96. }
  97. } else {
  98. switch (card->info.type) {
  99. case QETH_CARD_TYPE_OSD:
  100. return " OSD Express";
  101. case QETH_CARD_TYPE_IQD:
  102. return " HiperSockets";
  103. case QETH_CARD_TYPE_OSN:
  104. return " OSN QDIO";
  105. case QETH_CARD_TYPE_OSM:
  106. return " OSM QDIO";
  107. case QETH_CARD_TYPE_OSX:
  108. return " OSX QDIO";
  109. default:
  110. return " unknown";
  111. }
  112. }
  113. return " n/a";
  114. }
  115. /* max length to be returned: 14 */
  116. const char *qeth_get_cardname_short(struct qeth_card *card)
  117. {
  118. if (card->info.guestlan) {
  119. switch (card->info.type) {
  120. case QETH_CARD_TYPE_OSD:
  121. return "Virt.NIC QDIO";
  122. case QETH_CARD_TYPE_IQD:
  123. return "Virt.NIC Hiper";
  124. case QETH_CARD_TYPE_OSM:
  125. return "Virt.NIC OSM";
  126. case QETH_CARD_TYPE_OSX:
  127. return "Virt.NIC OSX";
  128. default:
  129. return "unknown";
  130. }
  131. } else {
  132. switch (card->info.type) {
  133. case QETH_CARD_TYPE_OSD:
  134. switch (card->info.link_type) {
  135. case QETH_LINK_TYPE_FAST_ETH:
  136. return "OSD_100";
  137. case QETH_LINK_TYPE_HSTR:
  138. return "HSTR";
  139. case QETH_LINK_TYPE_GBIT_ETH:
  140. return "OSD_1000";
  141. case QETH_LINK_TYPE_10GBIT_ETH:
  142. return "OSD_10GIG";
  143. case QETH_LINK_TYPE_LANE_ETH100:
  144. return "OSD_FE_LANE";
  145. case QETH_LINK_TYPE_LANE_TR:
  146. return "OSD_TR_LANE";
  147. case QETH_LINK_TYPE_LANE_ETH1000:
  148. return "OSD_GbE_LANE";
  149. case QETH_LINK_TYPE_LANE:
  150. return "OSD_ATM_LANE";
  151. default:
  152. return "OSD_Express";
  153. }
  154. case QETH_CARD_TYPE_IQD:
  155. return "HiperSockets";
  156. case QETH_CARD_TYPE_OSN:
  157. return "OSN";
  158. case QETH_CARD_TYPE_OSM:
  159. return "OSM_1000";
  160. case QETH_CARD_TYPE_OSX:
  161. return "OSX_10GIG";
  162. default:
  163. return "unknown";
  164. }
  165. }
  166. return "n/a";
  167. }
  168. void qeth_set_recovery_task(struct qeth_card *card)
  169. {
  170. card->recovery_task = current;
  171. }
  172. EXPORT_SYMBOL_GPL(qeth_set_recovery_task);
  173. void qeth_clear_recovery_task(struct qeth_card *card)
  174. {
  175. card->recovery_task = NULL;
  176. }
  177. EXPORT_SYMBOL_GPL(qeth_clear_recovery_task);
  178. static bool qeth_is_recovery_task(const struct qeth_card *card)
  179. {
  180. return card->recovery_task == current;
  181. }
  182. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  183. int clear_start_mask)
  184. {
  185. unsigned long flags;
  186. spin_lock_irqsave(&card->thread_mask_lock, flags);
  187. card->thread_allowed_mask = threads;
  188. if (clear_start_mask)
  189. card->thread_start_mask &= threads;
  190. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  191. wake_up(&card->wait_q);
  192. }
  193. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  194. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  195. {
  196. unsigned long flags;
  197. int rc = 0;
  198. spin_lock_irqsave(&card->thread_mask_lock, flags);
  199. rc = (card->thread_running_mask & threads);
  200. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  201. return rc;
  202. }
  203. EXPORT_SYMBOL_GPL(qeth_threads_running);
  204. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  205. {
  206. if (qeth_is_recovery_task(card))
  207. return 0;
  208. return wait_event_interruptible(card->wait_q,
  209. qeth_threads_running(card, threads) == 0);
  210. }
  211. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  212. void qeth_clear_working_pool_list(struct qeth_card *card)
  213. {
  214. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  215. QETH_CARD_TEXT(card, 5, "clwrklst");
  216. list_for_each_entry_safe(pool_entry, tmp,
  217. &card->qdio.in_buf_pool.entry_list, list){
  218. list_del(&pool_entry->list);
  219. }
  220. }
  221. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  222. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  223. {
  224. struct qeth_buffer_pool_entry *pool_entry;
  225. void *ptr;
  226. int i, j;
  227. QETH_CARD_TEXT(card, 5, "alocpool");
  228. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  229. pool_entry = kzalloc(sizeof(*pool_entry), GFP_KERNEL);
  230. if (!pool_entry) {
  231. qeth_free_buffer_pool(card);
  232. return -ENOMEM;
  233. }
  234. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  235. ptr = (void *) __get_free_page(GFP_KERNEL);
  236. if (!ptr) {
  237. while (j > 0)
  238. free_page((unsigned long)
  239. pool_entry->elements[--j]);
  240. kfree(pool_entry);
  241. qeth_free_buffer_pool(card);
  242. return -ENOMEM;
  243. }
  244. pool_entry->elements[j] = ptr;
  245. }
  246. list_add(&pool_entry->init_list,
  247. &card->qdio.init_pool.entry_list);
  248. }
  249. return 0;
  250. }
  251. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  252. {
  253. QETH_CARD_TEXT(card, 2, "realcbp");
  254. if ((card->state != CARD_STATE_DOWN) &&
  255. (card->state != CARD_STATE_RECOVER))
  256. return -EPERM;
  257. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  258. qeth_clear_working_pool_list(card);
  259. qeth_free_buffer_pool(card);
  260. card->qdio.in_buf_pool.buf_count = bufcnt;
  261. card->qdio.init_pool.buf_count = bufcnt;
  262. return qeth_alloc_buffer_pool(card);
  263. }
  264. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  265. static inline int qeth_cq_init(struct qeth_card *card)
  266. {
  267. int rc;
  268. if (card->options.cq == QETH_CQ_ENABLED) {
  269. QETH_DBF_TEXT(SETUP, 2, "cqinit");
  270. memset(card->qdio.c_q->qdio_bufs, 0,
  271. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  272. card->qdio.c_q->next_buf_to_init = 127;
  273. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT,
  274. card->qdio.no_in_queues - 1, 0,
  275. 127);
  276. if (rc) {
  277. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  278. goto out;
  279. }
  280. }
  281. rc = 0;
  282. out:
  283. return rc;
  284. }
  285. static inline int qeth_alloc_cq(struct qeth_card *card)
  286. {
  287. int rc;
  288. if (card->options.cq == QETH_CQ_ENABLED) {
  289. int i;
  290. struct qdio_outbuf_state *outbuf_states;
  291. QETH_DBF_TEXT(SETUP, 2, "cqon");
  292. card->qdio.c_q = kzalloc(sizeof(struct qeth_qdio_q),
  293. GFP_KERNEL);
  294. if (!card->qdio.c_q) {
  295. rc = -1;
  296. goto kmsg_out;
  297. }
  298. QETH_DBF_HEX(SETUP, 2, &card->qdio.c_q, sizeof(void *));
  299. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  300. card->qdio.c_q->bufs[i].buffer =
  301. &card->qdio.c_q->qdio_bufs[i];
  302. }
  303. card->qdio.no_in_queues = 2;
  304. card->qdio.out_bufstates =
  305. kzalloc(card->qdio.no_out_queues *
  306. QDIO_MAX_BUFFERS_PER_Q *
  307. sizeof(struct qdio_outbuf_state), GFP_KERNEL);
  308. outbuf_states = card->qdio.out_bufstates;
  309. if (outbuf_states == NULL) {
  310. rc = -1;
  311. goto free_cq_out;
  312. }
  313. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  314. card->qdio.out_qs[i]->bufstates = outbuf_states;
  315. outbuf_states += QDIO_MAX_BUFFERS_PER_Q;
  316. }
  317. } else {
  318. QETH_DBF_TEXT(SETUP, 2, "nocq");
  319. card->qdio.c_q = NULL;
  320. card->qdio.no_in_queues = 1;
  321. }
  322. QETH_DBF_TEXT_(SETUP, 2, "iqc%d", card->qdio.no_in_queues);
  323. rc = 0;
  324. out:
  325. return rc;
  326. free_cq_out:
  327. kfree(card->qdio.c_q);
  328. card->qdio.c_q = NULL;
  329. kmsg_out:
  330. dev_err(&card->gdev->dev, "Failed to create completion queue\n");
  331. goto out;
  332. }
  333. static inline void qeth_free_cq(struct qeth_card *card)
  334. {
  335. if (card->qdio.c_q) {
  336. --card->qdio.no_in_queues;
  337. kfree(card->qdio.c_q);
  338. card->qdio.c_q = NULL;
  339. }
  340. kfree(card->qdio.out_bufstates);
  341. card->qdio.out_bufstates = NULL;
  342. }
  343. static inline enum iucv_tx_notify qeth_compute_cq_notification(int sbalf15,
  344. int delayed) {
  345. enum iucv_tx_notify n;
  346. switch (sbalf15) {
  347. case 0:
  348. n = delayed ? TX_NOTIFY_DELAYED_OK : TX_NOTIFY_OK;
  349. break;
  350. case 4:
  351. case 16:
  352. case 17:
  353. case 18:
  354. n = delayed ? TX_NOTIFY_DELAYED_UNREACHABLE :
  355. TX_NOTIFY_UNREACHABLE;
  356. break;
  357. default:
  358. n = delayed ? TX_NOTIFY_DELAYED_GENERALERROR :
  359. TX_NOTIFY_GENERALERROR;
  360. break;
  361. }
  362. return n;
  363. }
  364. static inline void qeth_cleanup_handled_pending(struct qeth_qdio_out_q *q,
  365. int bidx, int forced_cleanup)
  366. {
  367. if (q->card->options.cq != QETH_CQ_ENABLED)
  368. return;
  369. if (q->bufs[bidx]->next_pending != NULL) {
  370. struct qeth_qdio_out_buffer *head = q->bufs[bidx];
  371. struct qeth_qdio_out_buffer *c = q->bufs[bidx]->next_pending;
  372. while (c) {
  373. if (forced_cleanup ||
  374. atomic_read(&c->state) ==
  375. QETH_QDIO_BUF_HANDLED_DELAYED) {
  376. struct qeth_qdio_out_buffer *f = c;
  377. QETH_CARD_TEXT(f->q->card, 5, "fp");
  378. QETH_CARD_TEXT_(f->q->card, 5, "%lx", (long) f);
  379. /* release here to avoid interleaving between
  380. outbound tasklet and inbound tasklet
  381. regarding notifications and lifecycle */
  382. qeth_release_skbs(c);
  383. c = f->next_pending;
  384. WARN_ON_ONCE(head->next_pending != f);
  385. head->next_pending = c;
  386. kmem_cache_free(qeth_qdio_outbuf_cache, f);
  387. } else {
  388. head = c;
  389. c = c->next_pending;
  390. }
  391. }
  392. }
  393. if (forced_cleanup && (atomic_read(&(q->bufs[bidx]->state)) ==
  394. QETH_QDIO_BUF_HANDLED_DELAYED)) {
  395. /* for recovery situations */
  396. q->bufs[bidx]->aob = q->bufstates[bidx].aob;
  397. qeth_init_qdio_out_buf(q, bidx);
  398. QETH_CARD_TEXT(q->card, 2, "clprecov");
  399. }
  400. }
  401. static inline void qeth_qdio_handle_aob(struct qeth_card *card,
  402. unsigned long phys_aob_addr) {
  403. struct qaob *aob;
  404. struct qeth_qdio_out_buffer *buffer;
  405. enum iucv_tx_notify notification;
  406. aob = (struct qaob *) phys_to_virt(phys_aob_addr);
  407. QETH_CARD_TEXT(card, 5, "haob");
  408. QETH_CARD_TEXT_(card, 5, "%lx", phys_aob_addr);
  409. buffer = (struct qeth_qdio_out_buffer *) aob->user1;
  410. QETH_CARD_TEXT_(card, 5, "%lx", aob->user1);
  411. if (atomic_cmpxchg(&buffer->state, QETH_QDIO_BUF_PRIMED,
  412. QETH_QDIO_BUF_IN_CQ) == QETH_QDIO_BUF_PRIMED) {
  413. notification = TX_NOTIFY_OK;
  414. } else {
  415. WARN_ON_ONCE(atomic_read(&buffer->state) !=
  416. QETH_QDIO_BUF_PENDING);
  417. atomic_set(&buffer->state, QETH_QDIO_BUF_IN_CQ);
  418. notification = TX_NOTIFY_DELAYED_OK;
  419. }
  420. if (aob->aorc != 0) {
  421. QETH_CARD_TEXT_(card, 2, "aorc%02X", aob->aorc);
  422. notification = qeth_compute_cq_notification(aob->aorc, 1);
  423. }
  424. qeth_notify_skbs(buffer->q, buffer, notification);
  425. buffer->aob = NULL;
  426. qeth_clear_output_buffer(buffer->q, buffer,
  427. QETH_QDIO_BUF_HANDLED_DELAYED);
  428. /* from here on: do not touch buffer anymore */
  429. qdio_release_aob(aob);
  430. }
  431. static inline int qeth_is_cq(struct qeth_card *card, unsigned int queue)
  432. {
  433. return card->options.cq == QETH_CQ_ENABLED &&
  434. card->qdio.c_q != NULL &&
  435. queue != 0 &&
  436. queue == card->qdio.no_in_queues - 1;
  437. }
  438. static int qeth_issue_next_read(struct qeth_card *card)
  439. {
  440. int rc;
  441. struct qeth_cmd_buffer *iob;
  442. QETH_CARD_TEXT(card, 5, "issnxrd");
  443. if (card->read.state != CH_STATE_UP)
  444. return -EIO;
  445. iob = qeth_get_buffer(&card->read);
  446. if (!iob) {
  447. dev_warn(&card->gdev->dev, "The qeth device driver "
  448. "failed to recover an error on the device\n");
  449. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  450. "available\n", dev_name(&card->gdev->dev));
  451. return -ENOMEM;
  452. }
  453. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  454. QETH_CARD_TEXT(card, 6, "noirqpnd");
  455. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  456. (addr_t) iob, 0, 0);
  457. if (rc) {
  458. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  459. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  460. atomic_set(&card->read.irq_pending, 0);
  461. card->read_or_write_problem = 1;
  462. qeth_schedule_recovery(card);
  463. wake_up(&card->wait_q);
  464. }
  465. return rc;
  466. }
  467. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  468. {
  469. struct qeth_reply *reply;
  470. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  471. if (reply) {
  472. atomic_set(&reply->refcnt, 1);
  473. atomic_set(&reply->received, 0);
  474. reply->card = card;
  475. }
  476. return reply;
  477. }
  478. static void qeth_get_reply(struct qeth_reply *reply)
  479. {
  480. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  481. atomic_inc(&reply->refcnt);
  482. }
  483. static void qeth_put_reply(struct qeth_reply *reply)
  484. {
  485. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  486. if (atomic_dec_and_test(&reply->refcnt))
  487. kfree(reply);
  488. }
  489. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  490. struct qeth_card *card)
  491. {
  492. char *ipa_name;
  493. int com = cmd->hdr.command;
  494. ipa_name = qeth_get_ipa_cmd_name(com);
  495. if (rc)
  496. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s/%s returned "
  497. "x%X \"%s\"\n",
  498. ipa_name, com, dev_name(&card->gdev->dev),
  499. QETH_CARD_IFNAME(card), rc,
  500. qeth_get_ipa_msg(rc));
  501. else
  502. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s/%s succeeded\n",
  503. ipa_name, com, dev_name(&card->gdev->dev),
  504. QETH_CARD_IFNAME(card));
  505. }
  506. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  507. struct qeth_cmd_buffer *iob)
  508. {
  509. struct qeth_ipa_cmd *cmd = NULL;
  510. QETH_CARD_TEXT(card, 5, "chkipad");
  511. if (IS_IPA(iob->data)) {
  512. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  513. if (IS_IPA_REPLY(cmd)) {
  514. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  515. cmd->hdr.command != IPA_CMD_DELCCID &&
  516. cmd->hdr.command != IPA_CMD_MODCCID &&
  517. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  518. qeth_issue_ipa_msg(cmd,
  519. cmd->hdr.return_code, card);
  520. return cmd;
  521. } else {
  522. switch (cmd->hdr.command) {
  523. case IPA_CMD_STOPLAN:
  524. if (cmd->hdr.return_code ==
  525. IPA_RC_VEPA_TO_VEB_TRANSITION) {
  526. dev_err(&card->gdev->dev,
  527. "Interface %s is down because the "
  528. "adjacent port is no longer in "
  529. "reflective relay mode\n",
  530. QETH_CARD_IFNAME(card));
  531. qeth_close_dev(card);
  532. } else {
  533. dev_warn(&card->gdev->dev,
  534. "The link for interface %s on CHPID"
  535. " 0x%X failed\n",
  536. QETH_CARD_IFNAME(card),
  537. card->info.chpid);
  538. qeth_issue_ipa_msg(cmd,
  539. cmd->hdr.return_code, card);
  540. }
  541. card->lan_online = 0;
  542. if (card->dev && netif_carrier_ok(card->dev))
  543. netif_carrier_off(card->dev);
  544. return NULL;
  545. case IPA_CMD_STARTLAN:
  546. dev_info(&card->gdev->dev,
  547. "The link for %s on CHPID 0x%X has"
  548. " been restored\n",
  549. QETH_CARD_IFNAME(card),
  550. card->info.chpid);
  551. netif_carrier_on(card->dev);
  552. card->lan_online = 1;
  553. if (card->info.hwtrap)
  554. card->info.hwtrap = 2;
  555. qeth_schedule_recovery(card);
  556. return NULL;
  557. case IPA_CMD_SETBRIDGEPORT:
  558. case IPA_CMD_ADDRESS_CHANGE_NOTIF:
  559. if (card->discipline->control_event_handler
  560. (card, cmd))
  561. return cmd;
  562. else
  563. return NULL;
  564. case IPA_CMD_MODCCID:
  565. return cmd;
  566. case IPA_CMD_REGISTER_LOCAL_ADDR:
  567. QETH_CARD_TEXT(card, 3, "irla");
  568. break;
  569. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  570. QETH_CARD_TEXT(card, 3, "urla");
  571. break;
  572. default:
  573. QETH_DBF_MESSAGE(2, "Received data is IPA "
  574. "but not a reply!\n");
  575. break;
  576. }
  577. }
  578. }
  579. return cmd;
  580. }
  581. void qeth_clear_ipacmd_list(struct qeth_card *card)
  582. {
  583. struct qeth_reply *reply, *r;
  584. unsigned long flags;
  585. QETH_CARD_TEXT(card, 4, "clipalst");
  586. spin_lock_irqsave(&card->lock, flags);
  587. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  588. qeth_get_reply(reply);
  589. reply->rc = -EIO;
  590. atomic_inc(&reply->received);
  591. list_del_init(&reply->list);
  592. wake_up(&reply->wait_q);
  593. qeth_put_reply(reply);
  594. }
  595. spin_unlock_irqrestore(&card->lock, flags);
  596. atomic_set(&card->write.irq_pending, 0);
  597. }
  598. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  599. static int qeth_check_idx_response(struct qeth_card *card,
  600. unsigned char *buffer)
  601. {
  602. if (!buffer)
  603. return 0;
  604. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  605. if ((buffer[2] & 0xc0) == 0xc0) {
  606. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  607. "with cause code 0x%02x%s\n",
  608. buffer[4],
  609. ((buffer[4] == 0x22) ?
  610. " -- try another portname" : ""));
  611. QETH_CARD_TEXT(card, 2, "ckidxres");
  612. QETH_CARD_TEXT(card, 2, " idxterm");
  613. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  614. if (buffer[4] == 0xf6) {
  615. dev_err(&card->gdev->dev,
  616. "The qeth device is not configured "
  617. "for the OSI layer required by z/VM\n");
  618. return -EPERM;
  619. }
  620. return -EIO;
  621. }
  622. return 0;
  623. }
  624. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  625. __u32 len)
  626. {
  627. struct qeth_card *card;
  628. card = CARD_FROM_CDEV(channel->ccwdev);
  629. QETH_CARD_TEXT(card, 4, "setupccw");
  630. if (channel == &card->read)
  631. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  632. else
  633. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  634. channel->ccw.count = len;
  635. channel->ccw.cda = (__u32) __pa(iob);
  636. }
  637. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  638. {
  639. __u8 index;
  640. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  641. index = channel->io_buf_no;
  642. do {
  643. if (channel->iob[index].state == BUF_STATE_FREE) {
  644. channel->iob[index].state = BUF_STATE_LOCKED;
  645. channel->io_buf_no = (channel->io_buf_no + 1) %
  646. QETH_CMD_BUFFER_NO;
  647. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  648. return channel->iob + index;
  649. }
  650. index = (index + 1) % QETH_CMD_BUFFER_NO;
  651. } while (index != channel->io_buf_no);
  652. return NULL;
  653. }
  654. void qeth_release_buffer(struct qeth_channel *channel,
  655. struct qeth_cmd_buffer *iob)
  656. {
  657. unsigned long flags;
  658. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  659. spin_lock_irqsave(&channel->iob_lock, flags);
  660. memset(iob->data, 0, QETH_BUFSIZE);
  661. iob->state = BUF_STATE_FREE;
  662. iob->callback = qeth_send_control_data_cb;
  663. iob->rc = 0;
  664. spin_unlock_irqrestore(&channel->iob_lock, flags);
  665. wake_up(&channel->wait_q);
  666. }
  667. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  668. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  669. {
  670. struct qeth_cmd_buffer *buffer = NULL;
  671. unsigned long flags;
  672. spin_lock_irqsave(&channel->iob_lock, flags);
  673. buffer = __qeth_get_buffer(channel);
  674. spin_unlock_irqrestore(&channel->iob_lock, flags);
  675. return buffer;
  676. }
  677. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  678. {
  679. struct qeth_cmd_buffer *buffer;
  680. wait_event(channel->wait_q,
  681. ((buffer = qeth_get_buffer(channel)) != NULL));
  682. return buffer;
  683. }
  684. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  685. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  686. {
  687. int cnt;
  688. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  689. qeth_release_buffer(channel, &channel->iob[cnt]);
  690. channel->buf_no = 0;
  691. channel->io_buf_no = 0;
  692. }
  693. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  694. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  695. struct qeth_cmd_buffer *iob)
  696. {
  697. struct qeth_card *card;
  698. struct qeth_reply *reply, *r;
  699. struct qeth_ipa_cmd *cmd;
  700. unsigned long flags;
  701. int keep_reply;
  702. int rc = 0;
  703. card = CARD_FROM_CDEV(channel->ccwdev);
  704. QETH_CARD_TEXT(card, 4, "sndctlcb");
  705. rc = qeth_check_idx_response(card, iob->data);
  706. switch (rc) {
  707. case 0:
  708. break;
  709. case -EIO:
  710. qeth_clear_ipacmd_list(card);
  711. qeth_schedule_recovery(card);
  712. /* fall through */
  713. default:
  714. goto out;
  715. }
  716. cmd = qeth_check_ipa_data(card, iob);
  717. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  718. goto out;
  719. /*in case of OSN : check if cmd is set */
  720. if (card->info.type == QETH_CARD_TYPE_OSN &&
  721. cmd &&
  722. cmd->hdr.command != IPA_CMD_STARTLAN &&
  723. card->osn_info.assist_cb != NULL) {
  724. card->osn_info.assist_cb(card->dev, cmd);
  725. goto out;
  726. }
  727. spin_lock_irqsave(&card->lock, flags);
  728. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  729. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  730. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  731. qeth_get_reply(reply);
  732. list_del_init(&reply->list);
  733. spin_unlock_irqrestore(&card->lock, flags);
  734. keep_reply = 0;
  735. if (reply->callback != NULL) {
  736. if (cmd) {
  737. reply->offset = (__u16)((char *)cmd -
  738. (char *)iob->data);
  739. keep_reply = reply->callback(card,
  740. reply,
  741. (unsigned long)cmd);
  742. } else
  743. keep_reply = reply->callback(card,
  744. reply,
  745. (unsigned long)iob);
  746. }
  747. if (cmd)
  748. reply->rc = (u16) cmd->hdr.return_code;
  749. else if (iob->rc)
  750. reply->rc = iob->rc;
  751. if (keep_reply) {
  752. spin_lock_irqsave(&card->lock, flags);
  753. list_add_tail(&reply->list,
  754. &card->cmd_waiter_list);
  755. spin_unlock_irqrestore(&card->lock, flags);
  756. } else {
  757. atomic_inc(&reply->received);
  758. wake_up(&reply->wait_q);
  759. }
  760. qeth_put_reply(reply);
  761. goto out;
  762. }
  763. }
  764. spin_unlock_irqrestore(&card->lock, flags);
  765. out:
  766. memcpy(&card->seqno.pdu_hdr_ack,
  767. QETH_PDU_HEADER_SEQ_NO(iob->data),
  768. QETH_SEQ_NO_LENGTH);
  769. qeth_release_buffer(channel, iob);
  770. }
  771. static int qeth_setup_channel(struct qeth_channel *channel)
  772. {
  773. int cnt;
  774. QETH_DBF_TEXT(SETUP, 2, "setupch");
  775. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  776. channel->iob[cnt].data =
  777. kzalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  778. if (channel->iob[cnt].data == NULL)
  779. break;
  780. channel->iob[cnt].state = BUF_STATE_FREE;
  781. channel->iob[cnt].channel = channel;
  782. channel->iob[cnt].callback = qeth_send_control_data_cb;
  783. channel->iob[cnt].rc = 0;
  784. }
  785. if (cnt < QETH_CMD_BUFFER_NO) {
  786. while (cnt-- > 0)
  787. kfree(channel->iob[cnt].data);
  788. return -ENOMEM;
  789. }
  790. channel->buf_no = 0;
  791. channel->io_buf_no = 0;
  792. atomic_set(&channel->irq_pending, 0);
  793. spin_lock_init(&channel->iob_lock);
  794. init_waitqueue_head(&channel->wait_q);
  795. return 0;
  796. }
  797. static int qeth_set_thread_start_bit(struct qeth_card *card,
  798. unsigned long thread)
  799. {
  800. unsigned long flags;
  801. spin_lock_irqsave(&card->thread_mask_lock, flags);
  802. if (!(card->thread_allowed_mask & thread) ||
  803. (card->thread_start_mask & thread)) {
  804. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  805. return -EPERM;
  806. }
  807. card->thread_start_mask |= thread;
  808. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  809. return 0;
  810. }
  811. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  812. {
  813. unsigned long flags;
  814. spin_lock_irqsave(&card->thread_mask_lock, flags);
  815. card->thread_start_mask &= ~thread;
  816. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  817. wake_up(&card->wait_q);
  818. }
  819. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  820. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  821. {
  822. unsigned long flags;
  823. spin_lock_irqsave(&card->thread_mask_lock, flags);
  824. card->thread_running_mask &= ~thread;
  825. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  826. wake_up(&card->wait_q);
  827. }
  828. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  829. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  830. {
  831. unsigned long flags;
  832. int rc = 0;
  833. spin_lock_irqsave(&card->thread_mask_lock, flags);
  834. if (card->thread_start_mask & thread) {
  835. if ((card->thread_allowed_mask & thread) &&
  836. !(card->thread_running_mask & thread)) {
  837. rc = 1;
  838. card->thread_start_mask &= ~thread;
  839. card->thread_running_mask |= thread;
  840. } else
  841. rc = -EPERM;
  842. }
  843. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  844. return rc;
  845. }
  846. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  847. {
  848. int rc = 0;
  849. wait_event(card->wait_q,
  850. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  851. return rc;
  852. }
  853. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  854. void qeth_schedule_recovery(struct qeth_card *card)
  855. {
  856. QETH_CARD_TEXT(card, 2, "startrec");
  857. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  858. schedule_work(&card->kernel_thread_starter);
  859. }
  860. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  861. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  862. {
  863. int dstat, cstat;
  864. char *sense;
  865. struct qeth_card *card;
  866. sense = (char *) irb->ecw;
  867. cstat = irb->scsw.cmd.cstat;
  868. dstat = irb->scsw.cmd.dstat;
  869. card = CARD_FROM_CDEV(cdev);
  870. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  871. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  872. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  873. QETH_CARD_TEXT(card, 2, "CGENCHK");
  874. dev_warn(&cdev->dev, "The qeth device driver "
  875. "failed to recover an error on the device\n");
  876. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  877. dev_name(&cdev->dev), dstat, cstat);
  878. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  879. 16, 1, irb, 64, 1);
  880. return 1;
  881. }
  882. if (dstat & DEV_STAT_UNIT_CHECK) {
  883. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  884. SENSE_RESETTING_EVENT_FLAG) {
  885. QETH_CARD_TEXT(card, 2, "REVIND");
  886. return 1;
  887. }
  888. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  889. SENSE_COMMAND_REJECT_FLAG) {
  890. QETH_CARD_TEXT(card, 2, "CMDREJi");
  891. return 1;
  892. }
  893. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  894. QETH_CARD_TEXT(card, 2, "AFFE");
  895. return 1;
  896. }
  897. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  898. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  899. return 0;
  900. }
  901. QETH_CARD_TEXT(card, 2, "DGENCHK");
  902. return 1;
  903. }
  904. return 0;
  905. }
  906. static long __qeth_check_irb_error(struct ccw_device *cdev,
  907. unsigned long intparm, struct irb *irb)
  908. {
  909. struct qeth_card *card;
  910. card = CARD_FROM_CDEV(cdev);
  911. if (!card || !IS_ERR(irb))
  912. return 0;
  913. switch (PTR_ERR(irb)) {
  914. case -EIO:
  915. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  916. dev_name(&cdev->dev));
  917. QETH_CARD_TEXT(card, 2, "ckirberr");
  918. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  919. break;
  920. case -ETIMEDOUT:
  921. dev_warn(&cdev->dev, "A hardware operation timed out"
  922. " on the device\n");
  923. QETH_CARD_TEXT(card, 2, "ckirberr");
  924. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  925. if (intparm == QETH_RCD_PARM) {
  926. if (card->data.ccwdev == cdev) {
  927. card->data.state = CH_STATE_DOWN;
  928. wake_up(&card->wait_q);
  929. }
  930. }
  931. break;
  932. default:
  933. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  934. dev_name(&cdev->dev), PTR_ERR(irb));
  935. QETH_CARD_TEXT(card, 2, "ckirberr");
  936. QETH_CARD_TEXT(card, 2, " rc???");
  937. }
  938. return PTR_ERR(irb);
  939. }
  940. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  941. struct irb *irb)
  942. {
  943. int rc;
  944. int cstat, dstat;
  945. struct qeth_cmd_buffer *buffer;
  946. struct qeth_channel *channel;
  947. struct qeth_card *card;
  948. struct qeth_cmd_buffer *iob;
  949. __u8 index;
  950. if (__qeth_check_irb_error(cdev, intparm, irb))
  951. return;
  952. cstat = irb->scsw.cmd.cstat;
  953. dstat = irb->scsw.cmd.dstat;
  954. card = CARD_FROM_CDEV(cdev);
  955. if (!card)
  956. return;
  957. QETH_CARD_TEXT(card, 5, "irq");
  958. if (card->read.ccwdev == cdev) {
  959. channel = &card->read;
  960. QETH_CARD_TEXT(card, 5, "read");
  961. } else if (card->write.ccwdev == cdev) {
  962. channel = &card->write;
  963. QETH_CARD_TEXT(card, 5, "write");
  964. } else {
  965. channel = &card->data;
  966. QETH_CARD_TEXT(card, 5, "data");
  967. }
  968. atomic_set(&channel->irq_pending, 0);
  969. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  970. channel->state = CH_STATE_STOPPED;
  971. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  972. channel->state = CH_STATE_HALTED;
  973. /*let's wake up immediately on data channel*/
  974. if ((channel == &card->data) && (intparm != 0) &&
  975. (intparm != QETH_RCD_PARM))
  976. goto out;
  977. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  978. QETH_CARD_TEXT(card, 6, "clrchpar");
  979. /* we don't have to handle this further */
  980. intparm = 0;
  981. }
  982. if (intparm == QETH_HALT_CHANNEL_PARM) {
  983. QETH_CARD_TEXT(card, 6, "hltchpar");
  984. /* we don't have to handle this further */
  985. intparm = 0;
  986. }
  987. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  988. (dstat & DEV_STAT_UNIT_CHECK) ||
  989. (cstat)) {
  990. if (irb->esw.esw0.erw.cons) {
  991. dev_warn(&channel->ccwdev->dev,
  992. "The qeth device driver failed to recover "
  993. "an error on the device\n");
  994. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  995. "0x%X dstat 0x%X\n",
  996. dev_name(&channel->ccwdev->dev), cstat, dstat);
  997. print_hex_dump(KERN_WARNING, "qeth: irb ",
  998. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  999. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  1000. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  1001. }
  1002. if (intparm == QETH_RCD_PARM) {
  1003. channel->state = CH_STATE_DOWN;
  1004. goto out;
  1005. }
  1006. rc = qeth_get_problem(cdev, irb);
  1007. if (rc) {
  1008. qeth_clear_ipacmd_list(card);
  1009. qeth_schedule_recovery(card);
  1010. goto out;
  1011. }
  1012. }
  1013. if (intparm == QETH_RCD_PARM) {
  1014. channel->state = CH_STATE_RCD_DONE;
  1015. goto out;
  1016. }
  1017. if (intparm) {
  1018. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  1019. buffer->state = BUF_STATE_PROCESSED;
  1020. }
  1021. if (channel == &card->data)
  1022. return;
  1023. if (channel == &card->read &&
  1024. channel->state == CH_STATE_UP)
  1025. qeth_issue_next_read(card);
  1026. iob = channel->iob;
  1027. index = channel->buf_no;
  1028. while (iob[index].state == BUF_STATE_PROCESSED) {
  1029. if (iob[index].callback != NULL)
  1030. iob[index].callback(channel, iob + index);
  1031. index = (index + 1) % QETH_CMD_BUFFER_NO;
  1032. }
  1033. channel->buf_no = index;
  1034. out:
  1035. wake_up(&card->wait_q);
  1036. return;
  1037. }
  1038. static void qeth_notify_skbs(struct qeth_qdio_out_q *q,
  1039. struct qeth_qdio_out_buffer *buf,
  1040. enum iucv_tx_notify notification)
  1041. {
  1042. struct sk_buff *skb;
  1043. if (skb_queue_empty(&buf->skb_list))
  1044. goto out;
  1045. skb = skb_peek(&buf->skb_list);
  1046. while (skb) {
  1047. QETH_CARD_TEXT_(q->card, 5, "skbn%d", notification);
  1048. QETH_CARD_TEXT_(q->card, 5, "%lx", (long) skb);
  1049. if (skb->protocol == ETH_P_AF_IUCV) {
  1050. if (skb->sk) {
  1051. struct iucv_sock *iucv = iucv_sk(skb->sk);
  1052. iucv->sk_txnotify(skb, notification);
  1053. }
  1054. }
  1055. if (skb_queue_is_last(&buf->skb_list, skb))
  1056. skb = NULL;
  1057. else
  1058. skb = skb_queue_next(&buf->skb_list, skb);
  1059. }
  1060. out:
  1061. return;
  1062. }
  1063. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf)
  1064. {
  1065. struct sk_buff *skb;
  1066. struct iucv_sock *iucv;
  1067. int notify_general_error = 0;
  1068. if (atomic_read(&buf->state) == QETH_QDIO_BUF_PENDING)
  1069. notify_general_error = 1;
  1070. /* release may never happen from within CQ tasklet scope */
  1071. WARN_ON_ONCE(atomic_read(&buf->state) == QETH_QDIO_BUF_IN_CQ);
  1072. skb = skb_dequeue(&buf->skb_list);
  1073. while (skb) {
  1074. QETH_CARD_TEXT(buf->q->card, 5, "skbr");
  1075. QETH_CARD_TEXT_(buf->q->card, 5, "%lx", (long) skb);
  1076. if (notify_general_error && skb->protocol == ETH_P_AF_IUCV) {
  1077. if (skb->sk) {
  1078. iucv = iucv_sk(skb->sk);
  1079. iucv->sk_txnotify(skb, TX_NOTIFY_GENERALERROR);
  1080. }
  1081. }
  1082. atomic_dec(&skb->users);
  1083. dev_kfree_skb_any(skb);
  1084. skb = skb_dequeue(&buf->skb_list);
  1085. }
  1086. }
  1087. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  1088. struct qeth_qdio_out_buffer *buf,
  1089. enum qeth_qdio_buffer_states newbufstate)
  1090. {
  1091. int i;
  1092. /* is PCI flag set on buffer? */
  1093. if (buf->buffer->element[0].sflags & SBAL_SFLAGS0_PCI_REQ)
  1094. atomic_dec(&queue->set_pci_flags_count);
  1095. if (newbufstate == QETH_QDIO_BUF_EMPTY) {
  1096. qeth_release_skbs(buf);
  1097. }
  1098. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  1099. if (buf->buffer->element[i].addr && buf->is_header[i])
  1100. kmem_cache_free(qeth_core_header_cache,
  1101. buf->buffer->element[i].addr);
  1102. buf->is_header[i] = 0;
  1103. buf->buffer->element[i].length = 0;
  1104. buf->buffer->element[i].addr = NULL;
  1105. buf->buffer->element[i].eflags = 0;
  1106. buf->buffer->element[i].sflags = 0;
  1107. }
  1108. buf->buffer->element[15].eflags = 0;
  1109. buf->buffer->element[15].sflags = 0;
  1110. buf->next_element_to_fill = 0;
  1111. atomic_set(&buf->state, newbufstate);
  1112. }
  1113. static void qeth_clear_outq_buffers(struct qeth_qdio_out_q *q, int free)
  1114. {
  1115. int j;
  1116. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1117. if (!q->bufs[j])
  1118. continue;
  1119. qeth_cleanup_handled_pending(q, j, 1);
  1120. qeth_clear_output_buffer(q, q->bufs[j], QETH_QDIO_BUF_EMPTY);
  1121. if (free) {
  1122. kmem_cache_free(qeth_qdio_outbuf_cache, q->bufs[j]);
  1123. q->bufs[j] = NULL;
  1124. }
  1125. }
  1126. }
  1127. void qeth_clear_qdio_buffers(struct qeth_card *card)
  1128. {
  1129. int i;
  1130. QETH_CARD_TEXT(card, 2, "clearqdbf");
  1131. /* clear outbound buffers to free skbs */
  1132. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1133. if (card->qdio.out_qs[i]) {
  1134. qeth_clear_outq_buffers(card->qdio.out_qs[i], 0);
  1135. }
  1136. }
  1137. }
  1138. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  1139. static void qeth_free_buffer_pool(struct qeth_card *card)
  1140. {
  1141. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  1142. int i = 0;
  1143. list_for_each_entry_safe(pool_entry, tmp,
  1144. &card->qdio.init_pool.entry_list, init_list){
  1145. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  1146. free_page((unsigned long)pool_entry->elements[i]);
  1147. list_del(&pool_entry->init_list);
  1148. kfree(pool_entry);
  1149. }
  1150. }
  1151. static void qeth_free_qdio_buffers(struct qeth_card *card)
  1152. {
  1153. int i, j;
  1154. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  1155. QETH_QDIO_UNINITIALIZED)
  1156. return;
  1157. qeth_free_cq(card);
  1158. cancel_delayed_work_sync(&card->buffer_reclaim_work);
  1159. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1160. if (card->qdio.in_q->bufs[j].rx_skb)
  1161. dev_kfree_skb_any(card->qdio.in_q->bufs[j].rx_skb);
  1162. }
  1163. kfree(card->qdio.in_q);
  1164. card->qdio.in_q = NULL;
  1165. /* inbound buffer pool */
  1166. qeth_free_buffer_pool(card);
  1167. /* free outbound qdio_qs */
  1168. if (card->qdio.out_qs) {
  1169. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1170. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  1171. kfree(card->qdio.out_qs[i]);
  1172. }
  1173. kfree(card->qdio.out_qs);
  1174. card->qdio.out_qs = NULL;
  1175. }
  1176. }
  1177. static void qeth_clean_channel(struct qeth_channel *channel)
  1178. {
  1179. int cnt;
  1180. QETH_DBF_TEXT(SETUP, 2, "freech");
  1181. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  1182. kfree(channel->iob[cnt].data);
  1183. }
  1184. static void qeth_set_single_write_queues(struct qeth_card *card)
  1185. {
  1186. if ((atomic_read(&card->qdio.state) != QETH_QDIO_UNINITIALIZED) &&
  1187. (card->qdio.no_out_queues == 4))
  1188. qeth_free_qdio_buffers(card);
  1189. card->qdio.no_out_queues = 1;
  1190. if (card->qdio.default_out_queue != 0)
  1191. dev_info(&card->gdev->dev, "Priority Queueing not supported\n");
  1192. card->qdio.default_out_queue = 0;
  1193. }
  1194. static void qeth_set_multiple_write_queues(struct qeth_card *card)
  1195. {
  1196. if ((atomic_read(&card->qdio.state) != QETH_QDIO_UNINITIALIZED) &&
  1197. (card->qdio.no_out_queues == 1)) {
  1198. qeth_free_qdio_buffers(card);
  1199. card->qdio.default_out_queue = 2;
  1200. }
  1201. card->qdio.no_out_queues = 4;
  1202. }
  1203. static void qeth_update_from_chp_desc(struct qeth_card *card)
  1204. {
  1205. struct ccw_device *ccwdev;
  1206. struct channel_path_desc *chp_dsc;
  1207. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  1208. ccwdev = card->data.ccwdev;
  1209. chp_dsc = ccw_device_get_chp_desc(ccwdev, 0);
  1210. if (!chp_dsc)
  1211. goto out;
  1212. card->info.func_level = 0x4100 + chp_dsc->desc;
  1213. if (card->info.type == QETH_CARD_TYPE_IQD)
  1214. goto out;
  1215. /* CHPP field bit 6 == 1 -> single queue */
  1216. if ((chp_dsc->chpp & 0x02) == 0x02)
  1217. qeth_set_single_write_queues(card);
  1218. else
  1219. qeth_set_multiple_write_queues(card);
  1220. out:
  1221. kfree(chp_dsc);
  1222. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  1223. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  1224. }
  1225. static void qeth_init_qdio_info(struct qeth_card *card)
  1226. {
  1227. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  1228. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1229. /* inbound */
  1230. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1231. if (card->info.type == QETH_CARD_TYPE_IQD)
  1232. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_HSDEFAULT;
  1233. else
  1234. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  1235. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  1236. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  1237. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  1238. }
  1239. static void qeth_set_intial_options(struct qeth_card *card)
  1240. {
  1241. card->options.route4.type = NO_ROUTER;
  1242. card->options.route6.type = NO_ROUTER;
  1243. card->options.fake_broadcast = 0;
  1244. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  1245. card->options.performance_stats = 0;
  1246. card->options.rx_sg_cb = QETH_RX_SG_CB;
  1247. card->options.isolation = ISOLATION_MODE_NONE;
  1248. card->options.cq = QETH_CQ_DISABLED;
  1249. }
  1250. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  1251. {
  1252. unsigned long flags;
  1253. int rc = 0;
  1254. spin_lock_irqsave(&card->thread_mask_lock, flags);
  1255. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  1256. (u8) card->thread_start_mask,
  1257. (u8) card->thread_allowed_mask,
  1258. (u8) card->thread_running_mask);
  1259. rc = (card->thread_start_mask & thread);
  1260. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  1261. return rc;
  1262. }
  1263. static void qeth_start_kernel_thread(struct work_struct *work)
  1264. {
  1265. struct task_struct *ts;
  1266. struct qeth_card *card = container_of(work, struct qeth_card,
  1267. kernel_thread_starter);
  1268. QETH_CARD_TEXT(card , 2, "strthrd");
  1269. if (card->read.state != CH_STATE_UP &&
  1270. card->write.state != CH_STATE_UP)
  1271. return;
  1272. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD)) {
  1273. ts = kthread_run(card->discipline->recover, (void *)card,
  1274. "qeth_recover");
  1275. if (IS_ERR(ts)) {
  1276. qeth_clear_thread_start_bit(card, QETH_RECOVER_THREAD);
  1277. qeth_clear_thread_running_bit(card,
  1278. QETH_RECOVER_THREAD);
  1279. }
  1280. }
  1281. }
  1282. static int qeth_setup_card(struct qeth_card *card)
  1283. {
  1284. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  1285. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1286. card->read.state = CH_STATE_DOWN;
  1287. card->write.state = CH_STATE_DOWN;
  1288. card->data.state = CH_STATE_DOWN;
  1289. card->state = CARD_STATE_DOWN;
  1290. card->lan_online = 0;
  1291. card->read_or_write_problem = 0;
  1292. card->dev = NULL;
  1293. spin_lock_init(&card->vlanlock);
  1294. spin_lock_init(&card->mclock);
  1295. spin_lock_init(&card->lock);
  1296. spin_lock_init(&card->ip_lock);
  1297. spin_lock_init(&card->thread_mask_lock);
  1298. mutex_init(&card->conf_mutex);
  1299. mutex_init(&card->discipline_mutex);
  1300. card->thread_start_mask = 0;
  1301. card->thread_allowed_mask = 0;
  1302. card->thread_running_mask = 0;
  1303. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1304. INIT_LIST_HEAD(&card->ip_list);
  1305. INIT_LIST_HEAD(card->ip_tbd_list);
  1306. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1307. init_waitqueue_head(&card->wait_q);
  1308. /* initial options */
  1309. qeth_set_intial_options(card);
  1310. /* IP address takeover */
  1311. INIT_LIST_HEAD(&card->ipato.entries);
  1312. card->ipato.enabled = 0;
  1313. card->ipato.invert4 = 0;
  1314. card->ipato.invert6 = 0;
  1315. /* init QDIO stuff */
  1316. qeth_init_qdio_info(card);
  1317. INIT_DELAYED_WORK(&card->buffer_reclaim_work, qeth_buffer_reclaim_work);
  1318. INIT_WORK(&card->close_dev_work, qeth_close_dev_handler);
  1319. return 0;
  1320. }
  1321. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1322. {
  1323. struct qeth_card *card = container_of(slr, struct qeth_card,
  1324. qeth_service_level);
  1325. if (card->info.mcl_level[0])
  1326. seq_printf(m, "qeth: %s firmware level %s\n",
  1327. CARD_BUS_ID(card), card->info.mcl_level);
  1328. }
  1329. static struct qeth_card *qeth_alloc_card(void)
  1330. {
  1331. struct qeth_card *card;
  1332. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1333. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1334. if (!card)
  1335. goto out;
  1336. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1337. card->ip_tbd_list = kzalloc(sizeof(struct list_head), GFP_KERNEL);
  1338. if (!card->ip_tbd_list) {
  1339. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1340. goto out_card;
  1341. }
  1342. if (qeth_setup_channel(&card->read))
  1343. goto out_ip;
  1344. if (qeth_setup_channel(&card->write))
  1345. goto out_channel;
  1346. card->options.layer2 = -1;
  1347. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1348. register_service_level(&card->qeth_service_level);
  1349. return card;
  1350. out_channel:
  1351. qeth_clean_channel(&card->read);
  1352. out_ip:
  1353. kfree(card->ip_tbd_list);
  1354. out_card:
  1355. kfree(card);
  1356. out:
  1357. return NULL;
  1358. }
  1359. static int qeth_determine_card_type(struct qeth_card *card)
  1360. {
  1361. int i = 0;
  1362. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1363. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1364. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1365. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1366. if ((CARD_RDEV(card)->id.dev_type ==
  1367. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1368. (CARD_RDEV(card)->id.dev_model ==
  1369. known_devices[i][QETH_DEV_MODEL_IND])) {
  1370. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1371. card->qdio.no_out_queues =
  1372. known_devices[i][QETH_QUEUE_NO_IND];
  1373. card->qdio.no_in_queues = 1;
  1374. card->info.is_multicast_different =
  1375. known_devices[i][QETH_MULTICAST_IND];
  1376. qeth_update_from_chp_desc(card);
  1377. return 0;
  1378. }
  1379. i++;
  1380. }
  1381. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1382. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1383. "unknown type\n");
  1384. return -ENOENT;
  1385. }
  1386. static int qeth_clear_channel(struct qeth_channel *channel)
  1387. {
  1388. unsigned long flags;
  1389. struct qeth_card *card;
  1390. int rc;
  1391. card = CARD_FROM_CDEV(channel->ccwdev);
  1392. QETH_CARD_TEXT(card, 3, "clearch");
  1393. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1394. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1395. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1396. if (rc)
  1397. return rc;
  1398. rc = wait_event_interruptible_timeout(card->wait_q,
  1399. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1400. if (rc == -ERESTARTSYS)
  1401. return rc;
  1402. if (channel->state != CH_STATE_STOPPED)
  1403. return -ETIME;
  1404. channel->state = CH_STATE_DOWN;
  1405. return 0;
  1406. }
  1407. static int qeth_halt_channel(struct qeth_channel *channel)
  1408. {
  1409. unsigned long flags;
  1410. struct qeth_card *card;
  1411. int rc;
  1412. card = CARD_FROM_CDEV(channel->ccwdev);
  1413. QETH_CARD_TEXT(card, 3, "haltch");
  1414. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1415. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1416. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1417. if (rc)
  1418. return rc;
  1419. rc = wait_event_interruptible_timeout(card->wait_q,
  1420. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1421. if (rc == -ERESTARTSYS)
  1422. return rc;
  1423. if (channel->state != CH_STATE_HALTED)
  1424. return -ETIME;
  1425. return 0;
  1426. }
  1427. static int qeth_halt_channels(struct qeth_card *card)
  1428. {
  1429. int rc1 = 0, rc2 = 0, rc3 = 0;
  1430. QETH_CARD_TEXT(card, 3, "haltchs");
  1431. rc1 = qeth_halt_channel(&card->read);
  1432. rc2 = qeth_halt_channel(&card->write);
  1433. rc3 = qeth_halt_channel(&card->data);
  1434. if (rc1)
  1435. return rc1;
  1436. if (rc2)
  1437. return rc2;
  1438. return rc3;
  1439. }
  1440. static int qeth_clear_channels(struct qeth_card *card)
  1441. {
  1442. int rc1 = 0, rc2 = 0, rc3 = 0;
  1443. QETH_CARD_TEXT(card, 3, "clearchs");
  1444. rc1 = qeth_clear_channel(&card->read);
  1445. rc2 = qeth_clear_channel(&card->write);
  1446. rc3 = qeth_clear_channel(&card->data);
  1447. if (rc1)
  1448. return rc1;
  1449. if (rc2)
  1450. return rc2;
  1451. return rc3;
  1452. }
  1453. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1454. {
  1455. int rc = 0;
  1456. QETH_CARD_TEXT(card, 3, "clhacrd");
  1457. if (halt)
  1458. rc = qeth_halt_channels(card);
  1459. if (rc)
  1460. return rc;
  1461. return qeth_clear_channels(card);
  1462. }
  1463. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1464. {
  1465. int rc = 0;
  1466. QETH_CARD_TEXT(card, 3, "qdioclr");
  1467. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1468. QETH_QDIO_CLEANING)) {
  1469. case QETH_QDIO_ESTABLISHED:
  1470. if (card->info.type == QETH_CARD_TYPE_IQD)
  1471. rc = qdio_shutdown(CARD_DDEV(card),
  1472. QDIO_FLAG_CLEANUP_USING_HALT);
  1473. else
  1474. rc = qdio_shutdown(CARD_DDEV(card),
  1475. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1476. if (rc)
  1477. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1478. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1479. break;
  1480. case QETH_QDIO_CLEANING:
  1481. return rc;
  1482. default:
  1483. break;
  1484. }
  1485. rc = qeth_clear_halt_card(card, use_halt);
  1486. if (rc)
  1487. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1488. card->state = CARD_STATE_DOWN;
  1489. return rc;
  1490. }
  1491. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1492. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1493. int *length)
  1494. {
  1495. struct ciw *ciw;
  1496. char *rcd_buf;
  1497. int ret;
  1498. struct qeth_channel *channel = &card->data;
  1499. unsigned long flags;
  1500. /*
  1501. * scan for RCD command in extended SenseID data
  1502. */
  1503. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1504. if (!ciw || ciw->cmd == 0)
  1505. return -EOPNOTSUPP;
  1506. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1507. if (!rcd_buf)
  1508. return -ENOMEM;
  1509. channel->ccw.cmd_code = ciw->cmd;
  1510. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1511. channel->ccw.count = ciw->count;
  1512. channel->ccw.flags = CCW_FLAG_SLI;
  1513. channel->state = CH_STATE_RCD;
  1514. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1515. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1516. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1517. QETH_RCD_TIMEOUT);
  1518. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1519. if (!ret)
  1520. wait_event(card->wait_q,
  1521. (channel->state == CH_STATE_RCD_DONE ||
  1522. channel->state == CH_STATE_DOWN));
  1523. if (channel->state == CH_STATE_DOWN)
  1524. ret = -EIO;
  1525. else
  1526. channel->state = CH_STATE_DOWN;
  1527. if (ret) {
  1528. kfree(rcd_buf);
  1529. *buffer = NULL;
  1530. *length = 0;
  1531. } else {
  1532. *length = ciw->count;
  1533. *buffer = rcd_buf;
  1534. }
  1535. return ret;
  1536. }
  1537. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1538. {
  1539. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1540. card->info.chpid = prcd[30];
  1541. card->info.unit_addr2 = prcd[31];
  1542. card->info.cula = prcd[63];
  1543. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1544. (prcd[0x11] == _ascebc['M']));
  1545. }
  1546. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1547. {
  1548. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1549. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 &&
  1550. prcd[76] >= 0xF1 && prcd[76] <= 0xF4) {
  1551. card->info.blkt.time_total = 0;
  1552. card->info.blkt.inter_packet = 0;
  1553. card->info.blkt.inter_packet_jumbo = 0;
  1554. } else {
  1555. card->info.blkt.time_total = 250;
  1556. card->info.blkt.inter_packet = 5;
  1557. card->info.blkt.inter_packet_jumbo = 15;
  1558. }
  1559. }
  1560. static void qeth_init_tokens(struct qeth_card *card)
  1561. {
  1562. card->token.issuer_rm_w = 0x00010103UL;
  1563. card->token.cm_filter_w = 0x00010108UL;
  1564. card->token.cm_connection_w = 0x0001010aUL;
  1565. card->token.ulp_filter_w = 0x0001010bUL;
  1566. card->token.ulp_connection_w = 0x0001010dUL;
  1567. }
  1568. static void qeth_init_func_level(struct qeth_card *card)
  1569. {
  1570. switch (card->info.type) {
  1571. case QETH_CARD_TYPE_IQD:
  1572. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1573. break;
  1574. case QETH_CARD_TYPE_OSD:
  1575. case QETH_CARD_TYPE_OSN:
  1576. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1577. break;
  1578. default:
  1579. break;
  1580. }
  1581. }
  1582. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1583. void (*idx_reply_cb)(struct qeth_channel *,
  1584. struct qeth_cmd_buffer *))
  1585. {
  1586. struct qeth_cmd_buffer *iob;
  1587. unsigned long flags;
  1588. int rc;
  1589. struct qeth_card *card;
  1590. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1591. card = CARD_FROM_CDEV(channel->ccwdev);
  1592. iob = qeth_get_buffer(channel);
  1593. iob->callback = idx_reply_cb;
  1594. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1595. channel->ccw.count = QETH_BUFSIZE;
  1596. channel->ccw.cda = (__u32) __pa(iob->data);
  1597. wait_event(card->wait_q,
  1598. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1599. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1600. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1601. rc = ccw_device_start(channel->ccwdev,
  1602. &channel->ccw, (addr_t) iob, 0, 0);
  1603. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1604. if (rc) {
  1605. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1606. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1607. atomic_set(&channel->irq_pending, 0);
  1608. wake_up(&card->wait_q);
  1609. return rc;
  1610. }
  1611. rc = wait_event_interruptible_timeout(card->wait_q,
  1612. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1613. if (rc == -ERESTARTSYS)
  1614. return rc;
  1615. if (channel->state != CH_STATE_UP) {
  1616. rc = -ETIME;
  1617. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1618. qeth_clear_cmd_buffers(channel);
  1619. } else
  1620. rc = 0;
  1621. return rc;
  1622. }
  1623. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1624. void (*idx_reply_cb)(struct qeth_channel *,
  1625. struct qeth_cmd_buffer *))
  1626. {
  1627. struct qeth_card *card;
  1628. struct qeth_cmd_buffer *iob;
  1629. unsigned long flags;
  1630. __u16 temp;
  1631. __u8 tmp;
  1632. int rc;
  1633. struct ccw_dev_id temp_devid;
  1634. card = CARD_FROM_CDEV(channel->ccwdev);
  1635. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1636. iob = qeth_get_buffer(channel);
  1637. iob->callback = idx_reply_cb;
  1638. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1639. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1640. channel->ccw.cda = (__u32) __pa(iob->data);
  1641. if (channel == &card->write) {
  1642. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1643. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1644. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1645. card->seqno.trans_hdr++;
  1646. } else {
  1647. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1648. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1649. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1650. }
  1651. tmp = ((__u8)card->info.portno) | 0x80;
  1652. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1653. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1654. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1655. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1656. &card->info.func_level, sizeof(__u16));
  1657. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1658. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1659. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1660. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1661. wait_event(card->wait_q,
  1662. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1663. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1664. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1665. rc = ccw_device_start(channel->ccwdev,
  1666. &channel->ccw, (addr_t) iob, 0, 0);
  1667. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1668. if (rc) {
  1669. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1670. rc);
  1671. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1672. atomic_set(&channel->irq_pending, 0);
  1673. wake_up(&card->wait_q);
  1674. return rc;
  1675. }
  1676. rc = wait_event_interruptible_timeout(card->wait_q,
  1677. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1678. if (rc == -ERESTARTSYS)
  1679. return rc;
  1680. if (channel->state != CH_STATE_ACTIVATING) {
  1681. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1682. " failed to recover an error on the device\n");
  1683. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1684. dev_name(&channel->ccwdev->dev));
  1685. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1686. qeth_clear_cmd_buffers(channel);
  1687. return -ETIME;
  1688. }
  1689. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1690. }
  1691. static int qeth_peer_func_level(int level)
  1692. {
  1693. if ((level & 0xff) == 8)
  1694. return (level & 0xff) + 0x400;
  1695. if (((level >> 8) & 3) == 1)
  1696. return (level & 0xff) + 0x200;
  1697. return level;
  1698. }
  1699. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1700. struct qeth_cmd_buffer *iob)
  1701. {
  1702. struct qeth_card *card;
  1703. __u16 temp;
  1704. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1705. if (channel->state == CH_STATE_DOWN) {
  1706. channel->state = CH_STATE_ACTIVATING;
  1707. goto out;
  1708. }
  1709. card = CARD_FROM_CDEV(channel->ccwdev);
  1710. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1711. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1712. dev_err(&card->write.ccwdev->dev,
  1713. "The adapter is used exclusively by another "
  1714. "host\n");
  1715. else
  1716. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1717. " negative reply\n",
  1718. dev_name(&card->write.ccwdev->dev));
  1719. goto out;
  1720. }
  1721. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1722. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1723. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1724. "function level mismatch (sent: 0x%x, received: "
  1725. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1726. card->info.func_level, temp);
  1727. goto out;
  1728. }
  1729. channel->state = CH_STATE_UP;
  1730. out:
  1731. qeth_release_buffer(channel, iob);
  1732. }
  1733. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1734. struct qeth_cmd_buffer *iob)
  1735. {
  1736. struct qeth_card *card;
  1737. __u16 temp;
  1738. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1739. if (channel->state == CH_STATE_DOWN) {
  1740. channel->state = CH_STATE_ACTIVATING;
  1741. goto out;
  1742. }
  1743. card = CARD_FROM_CDEV(channel->ccwdev);
  1744. if (qeth_check_idx_response(card, iob->data))
  1745. goto out;
  1746. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1747. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1748. case QETH_IDX_ACT_ERR_EXCL:
  1749. dev_err(&card->write.ccwdev->dev,
  1750. "The adapter is used exclusively by another "
  1751. "host\n");
  1752. break;
  1753. case QETH_IDX_ACT_ERR_AUTH:
  1754. case QETH_IDX_ACT_ERR_AUTH_USER:
  1755. dev_err(&card->read.ccwdev->dev,
  1756. "Setting the device online failed because of "
  1757. "insufficient authorization\n");
  1758. break;
  1759. default:
  1760. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1761. " negative reply\n",
  1762. dev_name(&card->read.ccwdev->dev));
  1763. }
  1764. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1765. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1766. goto out;
  1767. }
  1768. /**
  1769. * * temporary fix for microcode bug
  1770. * * to revert it,replace OR by AND
  1771. * */
  1772. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1773. (card->info.type == QETH_CARD_TYPE_OSD))
  1774. card->info.portname_required = 1;
  1775. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1776. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1777. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1778. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1779. dev_name(&card->read.ccwdev->dev),
  1780. card->info.func_level, temp);
  1781. goto out;
  1782. }
  1783. memcpy(&card->token.issuer_rm_r,
  1784. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1785. QETH_MPC_TOKEN_LENGTH);
  1786. memcpy(&card->info.mcl_level[0],
  1787. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1788. channel->state = CH_STATE_UP;
  1789. out:
  1790. qeth_release_buffer(channel, iob);
  1791. }
  1792. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1793. struct qeth_cmd_buffer *iob)
  1794. {
  1795. qeth_setup_ccw(&card->write, iob->data, len);
  1796. iob->callback = qeth_release_buffer;
  1797. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1798. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1799. card->seqno.trans_hdr++;
  1800. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1801. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1802. card->seqno.pdu_hdr++;
  1803. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1804. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1805. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1806. }
  1807. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1808. int qeth_send_control_data(struct qeth_card *card, int len,
  1809. struct qeth_cmd_buffer *iob,
  1810. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1811. unsigned long),
  1812. void *reply_param)
  1813. {
  1814. int rc;
  1815. unsigned long flags;
  1816. struct qeth_reply *reply = NULL;
  1817. unsigned long timeout, event_timeout;
  1818. struct qeth_ipa_cmd *cmd;
  1819. QETH_CARD_TEXT(card, 2, "sendctl");
  1820. if (card->read_or_write_problem) {
  1821. qeth_release_buffer(iob->channel, iob);
  1822. return -EIO;
  1823. }
  1824. reply = qeth_alloc_reply(card);
  1825. if (!reply) {
  1826. return -ENOMEM;
  1827. }
  1828. reply->callback = reply_cb;
  1829. reply->param = reply_param;
  1830. if (card->state == CARD_STATE_DOWN)
  1831. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1832. else
  1833. reply->seqno = card->seqno.ipa++;
  1834. init_waitqueue_head(&reply->wait_q);
  1835. spin_lock_irqsave(&card->lock, flags);
  1836. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1837. spin_unlock_irqrestore(&card->lock, flags);
  1838. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1839. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1840. qeth_prepare_control_data(card, len, iob);
  1841. if (IS_IPA(iob->data))
  1842. event_timeout = QETH_IPA_TIMEOUT;
  1843. else
  1844. event_timeout = QETH_TIMEOUT;
  1845. timeout = jiffies + event_timeout;
  1846. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1847. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1848. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1849. (addr_t) iob, 0, 0);
  1850. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1851. if (rc) {
  1852. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1853. "ccw_device_start rc = %i\n",
  1854. dev_name(&card->write.ccwdev->dev), rc);
  1855. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1856. spin_lock_irqsave(&card->lock, flags);
  1857. list_del_init(&reply->list);
  1858. qeth_put_reply(reply);
  1859. spin_unlock_irqrestore(&card->lock, flags);
  1860. qeth_release_buffer(iob->channel, iob);
  1861. atomic_set(&card->write.irq_pending, 0);
  1862. wake_up(&card->wait_q);
  1863. return rc;
  1864. }
  1865. /* we have only one long running ipassist, since we can ensure
  1866. process context of this command we can sleep */
  1867. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1868. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1869. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1870. if (!wait_event_timeout(reply->wait_q,
  1871. atomic_read(&reply->received), event_timeout))
  1872. goto time_err;
  1873. } else {
  1874. while (!atomic_read(&reply->received)) {
  1875. if (time_after(jiffies, timeout))
  1876. goto time_err;
  1877. cpu_relax();
  1878. }
  1879. }
  1880. if (reply->rc == -EIO)
  1881. goto error;
  1882. rc = reply->rc;
  1883. qeth_put_reply(reply);
  1884. return rc;
  1885. time_err:
  1886. reply->rc = -ETIME;
  1887. spin_lock_irqsave(&reply->card->lock, flags);
  1888. list_del_init(&reply->list);
  1889. spin_unlock_irqrestore(&reply->card->lock, flags);
  1890. atomic_inc(&reply->received);
  1891. error:
  1892. atomic_set(&card->write.irq_pending, 0);
  1893. qeth_release_buffer(iob->channel, iob);
  1894. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1895. rc = reply->rc;
  1896. qeth_put_reply(reply);
  1897. return rc;
  1898. }
  1899. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1900. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1901. unsigned long data)
  1902. {
  1903. struct qeth_cmd_buffer *iob;
  1904. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1905. iob = (struct qeth_cmd_buffer *) data;
  1906. memcpy(&card->token.cm_filter_r,
  1907. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1908. QETH_MPC_TOKEN_LENGTH);
  1909. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1910. return 0;
  1911. }
  1912. static int qeth_cm_enable(struct qeth_card *card)
  1913. {
  1914. int rc;
  1915. struct qeth_cmd_buffer *iob;
  1916. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1917. iob = qeth_wait_for_buffer(&card->write);
  1918. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1919. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1920. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1921. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1922. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1923. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1924. qeth_cm_enable_cb, NULL);
  1925. return rc;
  1926. }
  1927. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1928. unsigned long data)
  1929. {
  1930. struct qeth_cmd_buffer *iob;
  1931. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1932. iob = (struct qeth_cmd_buffer *) data;
  1933. memcpy(&card->token.cm_connection_r,
  1934. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1935. QETH_MPC_TOKEN_LENGTH);
  1936. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1937. return 0;
  1938. }
  1939. static int qeth_cm_setup(struct qeth_card *card)
  1940. {
  1941. int rc;
  1942. struct qeth_cmd_buffer *iob;
  1943. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1944. iob = qeth_wait_for_buffer(&card->write);
  1945. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1946. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1947. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1948. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1949. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1950. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1951. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1952. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1953. qeth_cm_setup_cb, NULL);
  1954. return rc;
  1955. }
  1956. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1957. {
  1958. switch (card->info.type) {
  1959. case QETH_CARD_TYPE_UNKNOWN:
  1960. return 1500;
  1961. case QETH_CARD_TYPE_IQD:
  1962. return card->info.max_mtu;
  1963. case QETH_CARD_TYPE_OSD:
  1964. switch (card->info.link_type) {
  1965. case QETH_LINK_TYPE_HSTR:
  1966. case QETH_LINK_TYPE_LANE_TR:
  1967. return 2000;
  1968. default:
  1969. return card->options.layer2 ? 1500 : 1492;
  1970. }
  1971. case QETH_CARD_TYPE_OSM:
  1972. case QETH_CARD_TYPE_OSX:
  1973. return card->options.layer2 ? 1500 : 1492;
  1974. default:
  1975. return 1500;
  1976. }
  1977. }
  1978. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1979. {
  1980. switch (framesize) {
  1981. case 0x4000:
  1982. return 8192;
  1983. case 0x6000:
  1984. return 16384;
  1985. case 0xa000:
  1986. return 32768;
  1987. case 0xffff:
  1988. return 57344;
  1989. default:
  1990. return 0;
  1991. }
  1992. }
  1993. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1994. {
  1995. switch (card->info.type) {
  1996. case QETH_CARD_TYPE_OSD:
  1997. case QETH_CARD_TYPE_OSM:
  1998. case QETH_CARD_TYPE_OSX:
  1999. case QETH_CARD_TYPE_IQD:
  2000. return ((mtu >= 576) &&
  2001. (mtu <= card->info.max_mtu));
  2002. case QETH_CARD_TYPE_OSN:
  2003. case QETH_CARD_TYPE_UNKNOWN:
  2004. default:
  2005. return 1;
  2006. }
  2007. }
  2008. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  2009. unsigned long data)
  2010. {
  2011. __u16 mtu, framesize;
  2012. __u16 len;
  2013. __u8 link_type;
  2014. struct qeth_cmd_buffer *iob;
  2015. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  2016. iob = (struct qeth_cmd_buffer *) data;
  2017. memcpy(&card->token.ulp_filter_r,
  2018. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  2019. QETH_MPC_TOKEN_LENGTH);
  2020. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2021. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  2022. mtu = qeth_get_mtu_outof_framesize(framesize);
  2023. if (!mtu) {
  2024. iob->rc = -EINVAL;
  2025. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2026. return 0;
  2027. }
  2028. if (card->info.initial_mtu && (card->info.initial_mtu != mtu)) {
  2029. /* frame size has changed */
  2030. if (card->dev &&
  2031. ((card->dev->mtu == card->info.initial_mtu) ||
  2032. (card->dev->mtu > mtu)))
  2033. card->dev->mtu = mtu;
  2034. qeth_free_qdio_buffers(card);
  2035. }
  2036. card->info.initial_mtu = mtu;
  2037. card->info.max_mtu = mtu;
  2038. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  2039. } else {
  2040. card->info.max_mtu = *(__u16 *)QETH_ULP_ENABLE_RESP_MAX_MTU(
  2041. iob->data);
  2042. card->info.initial_mtu = min(card->info.max_mtu,
  2043. qeth_get_initial_mtu_for_card(card));
  2044. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  2045. }
  2046. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  2047. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  2048. memcpy(&link_type,
  2049. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  2050. card->info.link_type = link_type;
  2051. } else
  2052. card->info.link_type = 0;
  2053. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  2054. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2055. return 0;
  2056. }
  2057. static int qeth_ulp_enable(struct qeth_card *card)
  2058. {
  2059. int rc;
  2060. char prot_type;
  2061. struct qeth_cmd_buffer *iob;
  2062. /*FIXME: trace view callbacks*/
  2063. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  2064. iob = qeth_wait_for_buffer(&card->write);
  2065. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  2066. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  2067. (__u8) card->info.portno;
  2068. if (card->options.layer2)
  2069. if (card->info.type == QETH_CARD_TYPE_OSN)
  2070. prot_type = QETH_PROT_OSN2;
  2071. else
  2072. prot_type = QETH_PROT_LAYER2;
  2073. else
  2074. prot_type = QETH_PROT_TCPIP;
  2075. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  2076. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  2077. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2078. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  2079. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  2080. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  2081. card->info.portname, 9);
  2082. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  2083. qeth_ulp_enable_cb, NULL);
  2084. return rc;
  2085. }
  2086. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  2087. unsigned long data)
  2088. {
  2089. struct qeth_cmd_buffer *iob;
  2090. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  2091. iob = (struct qeth_cmd_buffer *) data;
  2092. memcpy(&card->token.ulp_connection_r,
  2093. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2094. QETH_MPC_TOKEN_LENGTH);
  2095. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2096. 3)) {
  2097. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  2098. dev_err(&card->gdev->dev, "A connection could not be "
  2099. "established because of an OLM limit\n");
  2100. iob->rc = -EMLINK;
  2101. }
  2102. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2103. return 0;
  2104. }
  2105. static int qeth_ulp_setup(struct qeth_card *card)
  2106. {
  2107. int rc;
  2108. __u16 temp;
  2109. struct qeth_cmd_buffer *iob;
  2110. struct ccw_dev_id dev_id;
  2111. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  2112. iob = qeth_wait_for_buffer(&card->write);
  2113. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  2114. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  2115. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2116. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  2117. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  2118. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  2119. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  2120. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  2121. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  2122. temp = (card->info.cula << 8) + card->info.unit_addr2;
  2123. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  2124. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  2125. qeth_ulp_setup_cb, NULL);
  2126. return rc;
  2127. }
  2128. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *q, int bidx)
  2129. {
  2130. int rc;
  2131. struct qeth_qdio_out_buffer *newbuf;
  2132. rc = 0;
  2133. newbuf = kmem_cache_zalloc(qeth_qdio_outbuf_cache, GFP_ATOMIC);
  2134. if (!newbuf) {
  2135. rc = -ENOMEM;
  2136. goto out;
  2137. }
  2138. newbuf->buffer = &q->qdio_bufs[bidx];
  2139. skb_queue_head_init(&newbuf->skb_list);
  2140. lockdep_set_class(&newbuf->skb_list.lock, &qdio_out_skb_queue_key);
  2141. newbuf->q = q;
  2142. newbuf->aob = NULL;
  2143. newbuf->next_pending = q->bufs[bidx];
  2144. atomic_set(&newbuf->state, QETH_QDIO_BUF_EMPTY);
  2145. q->bufs[bidx] = newbuf;
  2146. if (q->bufstates) {
  2147. q->bufstates[bidx].user = newbuf;
  2148. QETH_CARD_TEXT_(q->card, 2, "nbs%d", bidx);
  2149. QETH_CARD_TEXT_(q->card, 2, "%lx", (long) newbuf);
  2150. QETH_CARD_TEXT_(q->card, 2, "%lx",
  2151. (long) newbuf->next_pending);
  2152. }
  2153. out:
  2154. return rc;
  2155. }
  2156. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  2157. {
  2158. int i, j;
  2159. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  2160. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  2161. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  2162. return 0;
  2163. card->qdio.in_q = kzalloc(sizeof(struct qeth_qdio_q),
  2164. GFP_KERNEL);
  2165. if (!card->qdio.in_q)
  2166. goto out_nomem;
  2167. QETH_DBF_TEXT(SETUP, 2, "inq");
  2168. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  2169. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  2170. /* give inbound qeth_qdio_buffers their qdio_buffers */
  2171. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  2172. card->qdio.in_q->bufs[i].buffer =
  2173. &card->qdio.in_q->qdio_bufs[i];
  2174. card->qdio.in_q->bufs[i].rx_skb = NULL;
  2175. }
  2176. /* inbound buffer pool */
  2177. if (qeth_alloc_buffer_pool(card))
  2178. goto out_freeinq;
  2179. /* outbound */
  2180. card->qdio.out_qs =
  2181. kzalloc(card->qdio.no_out_queues *
  2182. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  2183. if (!card->qdio.out_qs)
  2184. goto out_freepool;
  2185. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2186. card->qdio.out_qs[i] = kzalloc(sizeof(struct qeth_qdio_out_q),
  2187. GFP_KERNEL);
  2188. if (!card->qdio.out_qs[i])
  2189. goto out_freeoutq;
  2190. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  2191. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  2192. card->qdio.out_qs[i]->queue_no = i;
  2193. /* give outbound qeth_qdio_buffers their qdio_buffers */
  2194. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2195. WARN_ON(card->qdio.out_qs[i]->bufs[j] != NULL);
  2196. if (qeth_init_qdio_out_buf(card->qdio.out_qs[i], j))
  2197. goto out_freeoutqbufs;
  2198. }
  2199. }
  2200. /* completion */
  2201. if (qeth_alloc_cq(card))
  2202. goto out_freeoutq;
  2203. return 0;
  2204. out_freeoutqbufs:
  2205. while (j > 0) {
  2206. --j;
  2207. kmem_cache_free(qeth_qdio_outbuf_cache,
  2208. card->qdio.out_qs[i]->bufs[j]);
  2209. card->qdio.out_qs[i]->bufs[j] = NULL;
  2210. }
  2211. out_freeoutq:
  2212. while (i > 0) {
  2213. kfree(card->qdio.out_qs[--i]);
  2214. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  2215. }
  2216. kfree(card->qdio.out_qs);
  2217. card->qdio.out_qs = NULL;
  2218. out_freepool:
  2219. qeth_free_buffer_pool(card);
  2220. out_freeinq:
  2221. kfree(card->qdio.in_q);
  2222. card->qdio.in_q = NULL;
  2223. out_nomem:
  2224. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  2225. return -ENOMEM;
  2226. }
  2227. static void qeth_create_qib_param_field(struct qeth_card *card,
  2228. char *param_field)
  2229. {
  2230. param_field[0] = _ascebc['P'];
  2231. param_field[1] = _ascebc['C'];
  2232. param_field[2] = _ascebc['I'];
  2233. param_field[3] = _ascebc['T'];
  2234. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  2235. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  2236. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  2237. }
  2238. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  2239. char *param_field)
  2240. {
  2241. param_field[16] = _ascebc['B'];
  2242. param_field[17] = _ascebc['L'];
  2243. param_field[18] = _ascebc['K'];
  2244. param_field[19] = _ascebc['T'];
  2245. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  2246. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  2247. *((unsigned int *) (&param_field[28])) =
  2248. card->info.blkt.inter_packet_jumbo;
  2249. }
  2250. static int qeth_qdio_activate(struct qeth_card *card)
  2251. {
  2252. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  2253. return qdio_activate(CARD_DDEV(card));
  2254. }
  2255. static int qeth_dm_act(struct qeth_card *card)
  2256. {
  2257. int rc;
  2258. struct qeth_cmd_buffer *iob;
  2259. QETH_DBF_TEXT(SETUP, 2, "dmact");
  2260. iob = qeth_wait_for_buffer(&card->write);
  2261. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  2262. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  2263. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2264. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  2265. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2266. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  2267. return rc;
  2268. }
  2269. static int qeth_mpc_initialize(struct qeth_card *card)
  2270. {
  2271. int rc;
  2272. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  2273. rc = qeth_issue_next_read(card);
  2274. if (rc) {
  2275. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2276. return rc;
  2277. }
  2278. rc = qeth_cm_enable(card);
  2279. if (rc) {
  2280. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  2281. goto out_qdio;
  2282. }
  2283. rc = qeth_cm_setup(card);
  2284. if (rc) {
  2285. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  2286. goto out_qdio;
  2287. }
  2288. rc = qeth_ulp_enable(card);
  2289. if (rc) {
  2290. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  2291. goto out_qdio;
  2292. }
  2293. rc = qeth_ulp_setup(card);
  2294. if (rc) {
  2295. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2296. goto out_qdio;
  2297. }
  2298. rc = qeth_alloc_qdio_buffers(card);
  2299. if (rc) {
  2300. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2301. goto out_qdio;
  2302. }
  2303. rc = qeth_qdio_establish(card);
  2304. if (rc) {
  2305. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  2306. qeth_free_qdio_buffers(card);
  2307. goto out_qdio;
  2308. }
  2309. rc = qeth_qdio_activate(card);
  2310. if (rc) {
  2311. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  2312. goto out_qdio;
  2313. }
  2314. rc = qeth_dm_act(card);
  2315. if (rc) {
  2316. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  2317. goto out_qdio;
  2318. }
  2319. return 0;
  2320. out_qdio:
  2321. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  2322. qdio_free(CARD_DDEV(card));
  2323. return rc;
  2324. }
  2325. static void qeth_print_status_with_portname(struct qeth_card *card)
  2326. {
  2327. char dbf_text[15];
  2328. int i;
  2329. sprintf(dbf_text, "%s", card->info.portname + 1);
  2330. for (i = 0; i < 8; i++)
  2331. dbf_text[i] =
  2332. (char) _ebcasc[(__u8) dbf_text[i]];
  2333. dbf_text[8] = 0;
  2334. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  2335. "with link type %s (portname: %s)\n",
  2336. qeth_get_cardname(card),
  2337. (card->info.mcl_level[0]) ? " (level: " : "",
  2338. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2339. (card->info.mcl_level[0]) ? ")" : "",
  2340. qeth_get_cardname_short(card),
  2341. dbf_text);
  2342. }
  2343. static void qeth_print_status_no_portname(struct qeth_card *card)
  2344. {
  2345. if (card->info.portname[0])
  2346. dev_info(&card->gdev->dev, "Device is a%s "
  2347. "card%s%s%s\nwith link type %s "
  2348. "(no portname needed by interface).\n",
  2349. qeth_get_cardname(card),
  2350. (card->info.mcl_level[0]) ? " (level: " : "",
  2351. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2352. (card->info.mcl_level[0]) ? ")" : "",
  2353. qeth_get_cardname_short(card));
  2354. else
  2355. dev_info(&card->gdev->dev, "Device is a%s "
  2356. "card%s%s%s\nwith link type %s.\n",
  2357. qeth_get_cardname(card),
  2358. (card->info.mcl_level[0]) ? " (level: " : "",
  2359. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2360. (card->info.mcl_level[0]) ? ")" : "",
  2361. qeth_get_cardname_short(card));
  2362. }
  2363. void qeth_print_status_message(struct qeth_card *card)
  2364. {
  2365. switch (card->info.type) {
  2366. case QETH_CARD_TYPE_OSD:
  2367. case QETH_CARD_TYPE_OSM:
  2368. case QETH_CARD_TYPE_OSX:
  2369. /* VM will use a non-zero first character
  2370. * to indicate a HiperSockets like reporting
  2371. * of the level OSA sets the first character to zero
  2372. * */
  2373. if (!card->info.mcl_level[0]) {
  2374. sprintf(card->info.mcl_level, "%02x%02x",
  2375. card->info.mcl_level[2],
  2376. card->info.mcl_level[3]);
  2377. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2378. break;
  2379. }
  2380. /* fallthrough */
  2381. case QETH_CARD_TYPE_IQD:
  2382. if ((card->info.guestlan) ||
  2383. (card->info.mcl_level[0] & 0x80)) {
  2384. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2385. card->info.mcl_level[0]];
  2386. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2387. card->info.mcl_level[1]];
  2388. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2389. card->info.mcl_level[2]];
  2390. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2391. card->info.mcl_level[3]];
  2392. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2393. }
  2394. break;
  2395. default:
  2396. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2397. }
  2398. if (card->info.portname_required)
  2399. qeth_print_status_with_portname(card);
  2400. else
  2401. qeth_print_status_no_portname(card);
  2402. }
  2403. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2404. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2405. {
  2406. struct qeth_buffer_pool_entry *entry;
  2407. QETH_CARD_TEXT(card, 5, "inwrklst");
  2408. list_for_each_entry(entry,
  2409. &card->qdio.init_pool.entry_list, init_list) {
  2410. qeth_put_buffer_pool_entry(card, entry);
  2411. }
  2412. }
  2413. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2414. struct qeth_card *card)
  2415. {
  2416. struct list_head *plh;
  2417. struct qeth_buffer_pool_entry *entry;
  2418. int i, free;
  2419. struct page *page;
  2420. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2421. return NULL;
  2422. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2423. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2424. free = 1;
  2425. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2426. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2427. free = 0;
  2428. break;
  2429. }
  2430. }
  2431. if (free) {
  2432. list_del_init(&entry->list);
  2433. return entry;
  2434. }
  2435. }
  2436. /* no free buffer in pool so take first one and swap pages */
  2437. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2438. struct qeth_buffer_pool_entry, list);
  2439. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2440. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2441. page = alloc_page(GFP_ATOMIC);
  2442. if (!page) {
  2443. return NULL;
  2444. } else {
  2445. free_page((unsigned long)entry->elements[i]);
  2446. entry->elements[i] = page_address(page);
  2447. if (card->options.performance_stats)
  2448. card->perf_stats.sg_alloc_page_rx++;
  2449. }
  2450. }
  2451. }
  2452. list_del_init(&entry->list);
  2453. return entry;
  2454. }
  2455. static int qeth_init_input_buffer(struct qeth_card *card,
  2456. struct qeth_qdio_buffer *buf)
  2457. {
  2458. struct qeth_buffer_pool_entry *pool_entry;
  2459. int i;
  2460. if ((card->options.cq == QETH_CQ_ENABLED) && (!buf->rx_skb)) {
  2461. buf->rx_skb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  2462. if (!buf->rx_skb)
  2463. return 1;
  2464. }
  2465. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2466. if (!pool_entry)
  2467. return 1;
  2468. /*
  2469. * since the buffer is accessed only from the input_tasklet
  2470. * there shouldn't be a need to synchronize; also, since we use
  2471. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2472. * buffers
  2473. */
  2474. buf->pool_entry = pool_entry;
  2475. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2476. buf->buffer->element[i].length = PAGE_SIZE;
  2477. buf->buffer->element[i].addr = pool_entry->elements[i];
  2478. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2479. buf->buffer->element[i].eflags = SBAL_EFLAGS_LAST_ENTRY;
  2480. else
  2481. buf->buffer->element[i].eflags = 0;
  2482. buf->buffer->element[i].sflags = 0;
  2483. }
  2484. return 0;
  2485. }
  2486. int qeth_init_qdio_queues(struct qeth_card *card)
  2487. {
  2488. int i, j;
  2489. int rc;
  2490. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2491. /* inbound queue */
  2492. memset(card->qdio.in_q->qdio_bufs, 0,
  2493. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2494. qeth_initialize_working_pool_list(card);
  2495. /*give only as many buffers to hardware as we have buffer pool entries*/
  2496. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2497. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2498. card->qdio.in_q->next_buf_to_init =
  2499. card->qdio.in_buf_pool.buf_count - 1;
  2500. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2501. card->qdio.in_buf_pool.buf_count - 1);
  2502. if (rc) {
  2503. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2504. return rc;
  2505. }
  2506. /* completion */
  2507. rc = qeth_cq_init(card);
  2508. if (rc) {
  2509. return rc;
  2510. }
  2511. /* outbound queue */
  2512. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2513. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2514. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2515. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2516. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2517. card->qdio.out_qs[i]->bufs[j],
  2518. QETH_QDIO_BUF_EMPTY);
  2519. }
  2520. card->qdio.out_qs[i]->card = card;
  2521. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2522. card->qdio.out_qs[i]->do_pack = 0;
  2523. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2524. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2525. atomic_set(&card->qdio.out_qs[i]->state,
  2526. QETH_OUT_Q_UNLOCKED);
  2527. }
  2528. return 0;
  2529. }
  2530. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2531. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2532. {
  2533. switch (link_type) {
  2534. case QETH_LINK_TYPE_HSTR:
  2535. return 2;
  2536. default:
  2537. return 1;
  2538. }
  2539. }
  2540. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2541. struct qeth_ipa_cmd *cmd, __u8 command,
  2542. enum qeth_prot_versions prot)
  2543. {
  2544. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2545. cmd->hdr.command = command;
  2546. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2547. cmd->hdr.seqno = card->seqno.ipa;
  2548. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2549. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2550. if (card->options.layer2)
  2551. cmd->hdr.prim_version_no = 2;
  2552. else
  2553. cmd->hdr.prim_version_no = 1;
  2554. cmd->hdr.param_count = 1;
  2555. cmd->hdr.prot_version = prot;
  2556. cmd->hdr.ipa_supported = 0;
  2557. cmd->hdr.ipa_enabled = 0;
  2558. }
  2559. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2560. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2561. {
  2562. struct qeth_cmd_buffer *iob;
  2563. struct qeth_ipa_cmd *cmd;
  2564. iob = qeth_wait_for_buffer(&card->write);
  2565. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2566. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2567. return iob;
  2568. }
  2569. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2570. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2571. char prot_type)
  2572. {
  2573. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2574. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2575. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2576. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2577. }
  2578. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2579. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2580. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2581. unsigned long),
  2582. void *reply_param)
  2583. {
  2584. int rc;
  2585. char prot_type;
  2586. QETH_CARD_TEXT(card, 4, "sendipa");
  2587. if (card->options.layer2)
  2588. if (card->info.type == QETH_CARD_TYPE_OSN)
  2589. prot_type = QETH_PROT_OSN2;
  2590. else
  2591. prot_type = QETH_PROT_LAYER2;
  2592. else
  2593. prot_type = QETH_PROT_TCPIP;
  2594. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2595. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2596. iob, reply_cb, reply_param);
  2597. if (rc == -ETIME) {
  2598. qeth_clear_ipacmd_list(card);
  2599. qeth_schedule_recovery(card);
  2600. }
  2601. return rc;
  2602. }
  2603. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2604. int qeth_send_startlan(struct qeth_card *card)
  2605. {
  2606. int rc;
  2607. struct qeth_cmd_buffer *iob;
  2608. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2609. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);
  2610. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2611. return rc;
  2612. }
  2613. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2614. static int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2615. struct qeth_reply *reply, unsigned long data)
  2616. {
  2617. struct qeth_ipa_cmd *cmd;
  2618. QETH_CARD_TEXT(card, 4, "defadpcb");
  2619. cmd = (struct qeth_ipa_cmd *) data;
  2620. if (cmd->hdr.return_code == 0)
  2621. cmd->hdr.return_code =
  2622. cmd->data.setadapterparms.hdr.return_code;
  2623. return 0;
  2624. }
  2625. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2626. struct qeth_reply *reply, unsigned long data)
  2627. {
  2628. struct qeth_ipa_cmd *cmd;
  2629. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2630. cmd = (struct qeth_ipa_cmd *) data;
  2631. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2632. card->info.link_type =
  2633. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2634. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2635. }
  2636. card->options.adp.supported_funcs =
  2637. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2638. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2639. }
  2640. static struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2641. __u32 command, __u32 cmdlen)
  2642. {
  2643. struct qeth_cmd_buffer *iob;
  2644. struct qeth_ipa_cmd *cmd;
  2645. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2646. QETH_PROT_IPV4);
  2647. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2648. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2649. cmd->data.setadapterparms.hdr.command_code = command;
  2650. cmd->data.setadapterparms.hdr.used_total = 1;
  2651. cmd->data.setadapterparms.hdr.seq_no = 1;
  2652. return iob;
  2653. }
  2654. int qeth_query_setadapterparms(struct qeth_card *card)
  2655. {
  2656. int rc;
  2657. struct qeth_cmd_buffer *iob;
  2658. QETH_CARD_TEXT(card, 3, "queryadp");
  2659. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2660. sizeof(struct qeth_ipacmd_setadpparms));
  2661. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2662. return rc;
  2663. }
  2664. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2665. static int qeth_query_ipassists_cb(struct qeth_card *card,
  2666. struct qeth_reply *reply, unsigned long data)
  2667. {
  2668. struct qeth_ipa_cmd *cmd;
  2669. QETH_DBF_TEXT(SETUP, 2, "qipasscb");
  2670. cmd = (struct qeth_ipa_cmd *) data;
  2671. switch (cmd->hdr.return_code) {
  2672. case IPA_RC_NOTSUPP:
  2673. case IPA_RC_L2_UNSUPPORTED_CMD:
  2674. QETH_DBF_TEXT(SETUP, 2, "ipaunsup");
  2675. card->options.ipa4.supported_funcs |= IPA_SETADAPTERPARMS;
  2676. card->options.ipa6.supported_funcs |= IPA_SETADAPTERPARMS;
  2677. return -0;
  2678. default:
  2679. if (cmd->hdr.return_code) {
  2680. QETH_DBF_MESSAGE(1, "%s IPA_CMD_QIPASSIST: Unhandled "
  2681. "rc=%d\n",
  2682. dev_name(&card->gdev->dev),
  2683. cmd->hdr.return_code);
  2684. return 0;
  2685. }
  2686. }
  2687. if (cmd->hdr.prot_version == QETH_PROT_IPV4) {
  2688. card->options.ipa4.supported_funcs = cmd->hdr.ipa_supported;
  2689. card->options.ipa4.enabled_funcs = cmd->hdr.ipa_enabled;
  2690. } else if (cmd->hdr.prot_version == QETH_PROT_IPV6) {
  2691. card->options.ipa6.supported_funcs = cmd->hdr.ipa_supported;
  2692. card->options.ipa6.enabled_funcs = cmd->hdr.ipa_enabled;
  2693. } else
  2694. QETH_DBF_MESSAGE(1, "%s IPA_CMD_QIPASSIST: Flawed LIC detected"
  2695. "\n", dev_name(&card->gdev->dev));
  2696. return 0;
  2697. }
  2698. int qeth_query_ipassists(struct qeth_card *card, enum qeth_prot_versions prot)
  2699. {
  2700. int rc;
  2701. struct qeth_cmd_buffer *iob;
  2702. QETH_DBF_TEXT_(SETUP, 2, "qipassi%i", prot);
  2703. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_QIPASSIST, prot);
  2704. rc = qeth_send_ipa_cmd(card, iob, qeth_query_ipassists_cb, NULL);
  2705. return rc;
  2706. }
  2707. EXPORT_SYMBOL_GPL(qeth_query_ipassists);
  2708. static int qeth_query_setdiagass_cb(struct qeth_card *card,
  2709. struct qeth_reply *reply, unsigned long data)
  2710. {
  2711. struct qeth_ipa_cmd *cmd;
  2712. __u16 rc;
  2713. cmd = (struct qeth_ipa_cmd *)data;
  2714. rc = cmd->hdr.return_code;
  2715. if (rc)
  2716. QETH_CARD_TEXT_(card, 2, "diagq:%x", rc);
  2717. else
  2718. card->info.diagass_support = cmd->data.diagass.ext;
  2719. return 0;
  2720. }
  2721. static int qeth_query_setdiagass(struct qeth_card *card)
  2722. {
  2723. struct qeth_cmd_buffer *iob;
  2724. struct qeth_ipa_cmd *cmd;
  2725. QETH_DBF_TEXT(SETUP, 2, "qdiagass");
  2726. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2727. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2728. cmd->data.diagass.subcmd_len = 16;
  2729. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_QUERY;
  2730. return qeth_send_ipa_cmd(card, iob, qeth_query_setdiagass_cb, NULL);
  2731. }
  2732. static void qeth_get_trap_id(struct qeth_card *card, struct qeth_trap_id *tid)
  2733. {
  2734. unsigned long info = get_zeroed_page(GFP_KERNEL);
  2735. struct sysinfo_2_2_2 *info222 = (struct sysinfo_2_2_2 *)info;
  2736. struct sysinfo_3_2_2 *info322 = (struct sysinfo_3_2_2 *)info;
  2737. struct ccw_dev_id ccwid;
  2738. int level;
  2739. tid->chpid = card->info.chpid;
  2740. ccw_device_get_id(CARD_RDEV(card), &ccwid);
  2741. tid->ssid = ccwid.ssid;
  2742. tid->devno = ccwid.devno;
  2743. if (!info)
  2744. return;
  2745. level = stsi(NULL, 0, 0, 0);
  2746. if ((level >= 2) && (stsi(info222, 2, 2, 2) == 0))
  2747. tid->lparnr = info222->lpar_number;
  2748. if ((level >= 3) && (stsi(info322, 3, 2, 2) == 0)) {
  2749. EBCASC(info322->vm[0].name, sizeof(info322->vm[0].name));
  2750. memcpy(tid->vmname, info322->vm[0].name, sizeof(tid->vmname));
  2751. }
  2752. free_page(info);
  2753. return;
  2754. }
  2755. static int qeth_hw_trap_cb(struct qeth_card *card,
  2756. struct qeth_reply *reply, unsigned long data)
  2757. {
  2758. struct qeth_ipa_cmd *cmd;
  2759. __u16 rc;
  2760. cmd = (struct qeth_ipa_cmd *)data;
  2761. rc = cmd->hdr.return_code;
  2762. if (rc)
  2763. QETH_CARD_TEXT_(card, 2, "trapc:%x", rc);
  2764. return 0;
  2765. }
  2766. int qeth_hw_trap(struct qeth_card *card, enum qeth_diags_trap_action action)
  2767. {
  2768. struct qeth_cmd_buffer *iob;
  2769. struct qeth_ipa_cmd *cmd;
  2770. QETH_DBF_TEXT(SETUP, 2, "diagtrap");
  2771. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2772. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2773. cmd->data.diagass.subcmd_len = 80;
  2774. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_TRAP;
  2775. cmd->data.diagass.type = 1;
  2776. cmd->data.diagass.action = action;
  2777. switch (action) {
  2778. case QETH_DIAGS_TRAP_ARM:
  2779. cmd->data.diagass.options = 0x0003;
  2780. cmd->data.diagass.ext = 0x00010000 +
  2781. sizeof(struct qeth_trap_id);
  2782. qeth_get_trap_id(card,
  2783. (struct qeth_trap_id *)cmd->data.diagass.cdata);
  2784. break;
  2785. case QETH_DIAGS_TRAP_DISARM:
  2786. cmd->data.diagass.options = 0x0001;
  2787. break;
  2788. case QETH_DIAGS_TRAP_CAPTURE:
  2789. break;
  2790. }
  2791. return qeth_send_ipa_cmd(card, iob, qeth_hw_trap_cb, NULL);
  2792. }
  2793. EXPORT_SYMBOL_GPL(qeth_hw_trap);
  2794. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2795. unsigned int qdio_error, const char *dbftext)
  2796. {
  2797. if (qdio_error) {
  2798. QETH_CARD_TEXT(card, 2, dbftext);
  2799. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2800. buf->element[15].sflags);
  2801. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2802. buf->element[14].sflags);
  2803. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2804. if ((buf->element[15].sflags) == 0x12) {
  2805. card->stats.rx_dropped++;
  2806. return 0;
  2807. } else
  2808. return 1;
  2809. }
  2810. return 0;
  2811. }
  2812. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2813. void qeth_buffer_reclaim_work(struct work_struct *work)
  2814. {
  2815. struct qeth_card *card = container_of(work, struct qeth_card,
  2816. buffer_reclaim_work.work);
  2817. QETH_CARD_TEXT_(card, 2, "brw:%x", card->reclaim_index);
  2818. qeth_queue_input_buffer(card, card->reclaim_index);
  2819. }
  2820. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2821. {
  2822. struct qeth_qdio_q *queue = card->qdio.in_q;
  2823. struct list_head *lh;
  2824. int count;
  2825. int i;
  2826. int rc;
  2827. int newcount = 0;
  2828. count = (index < queue->next_buf_to_init)?
  2829. card->qdio.in_buf_pool.buf_count -
  2830. (queue->next_buf_to_init - index) :
  2831. card->qdio.in_buf_pool.buf_count -
  2832. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2833. /* only requeue at a certain threshold to avoid SIGAs */
  2834. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2835. for (i = queue->next_buf_to_init;
  2836. i < queue->next_buf_to_init + count; ++i) {
  2837. if (qeth_init_input_buffer(card,
  2838. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2839. break;
  2840. } else {
  2841. newcount++;
  2842. }
  2843. }
  2844. if (newcount < count) {
  2845. /* we are in memory shortage so we switch back to
  2846. traditional skb allocation and drop packages */
  2847. atomic_set(&card->force_alloc_skb, 3);
  2848. count = newcount;
  2849. } else {
  2850. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2851. }
  2852. if (!count) {
  2853. i = 0;
  2854. list_for_each(lh, &card->qdio.in_buf_pool.entry_list)
  2855. i++;
  2856. if (i == card->qdio.in_buf_pool.buf_count) {
  2857. QETH_CARD_TEXT(card, 2, "qsarbw");
  2858. card->reclaim_index = index;
  2859. schedule_delayed_work(
  2860. &card->buffer_reclaim_work,
  2861. QETH_RECLAIM_WORK_TIME);
  2862. }
  2863. return;
  2864. }
  2865. /*
  2866. * according to old code it should be avoided to requeue all
  2867. * 128 buffers in order to benefit from PCI avoidance.
  2868. * this function keeps at least one buffer (the buffer at
  2869. * 'index') un-requeued -> this buffer is the first buffer that
  2870. * will be requeued the next time
  2871. */
  2872. if (card->options.performance_stats) {
  2873. card->perf_stats.inbound_do_qdio_cnt++;
  2874. card->perf_stats.inbound_do_qdio_start_time =
  2875. qeth_get_micros();
  2876. }
  2877. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2878. queue->next_buf_to_init, count);
  2879. if (card->options.performance_stats)
  2880. card->perf_stats.inbound_do_qdio_time +=
  2881. qeth_get_micros() -
  2882. card->perf_stats.inbound_do_qdio_start_time;
  2883. if (rc) {
  2884. QETH_CARD_TEXT(card, 2, "qinberr");
  2885. }
  2886. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2887. QDIO_MAX_BUFFERS_PER_Q;
  2888. }
  2889. }
  2890. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2891. static int qeth_handle_send_error(struct qeth_card *card,
  2892. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2893. {
  2894. int sbalf15 = buffer->buffer->element[15].sflags;
  2895. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2896. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2897. if (sbalf15 == 0) {
  2898. qdio_err = 0;
  2899. } else {
  2900. qdio_err = 1;
  2901. }
  2902. }
  2903. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2904. if (!qdio_err)
  2905. return QETH_SEND_ERROR_NONE;
  2906. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2907. return QETH_SEND_ERROR_RETRY;
  2908. QETH_CARD_TEXT(card, 1, "lnkfail");
  2909. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2910. (u16)qdio_err, (u8)sbalf15);
  2911. return QETH_SEND_ERROR_LINK_FAILURE;
  2912. }
  2913. /*
  2914. * Switched to packing state if the number of used buffers on a queue
  2915. * reaches a certain limit.
  2916. */
  2917. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2918. {
  2919. if (!queue->do_pack) {
  2920. if (atomic_read(&queue->used_buffers)
  2921. >= QETH_HIGH_WATERMARK_PACK){
  2922. /* switch non-PACKING -> PACKING */
  2923. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2924. if (queue->card->options.performance_stats)
  2925. queue->card->perf_stats.sc_dp_p++;
  2926. queue->do_pack = 1;
  2927. }
  2928. }
  2929. }
  2930. /*
  2931. * Switches from packing to non-packing mode. If there is a packing
  2932. * buffer on the queue this buffer will be prepared to be flushed.
  2933. * In that case 1 is returned to inform the caller. If no buffer
  2934. * has to be flushed, zero is returned.
  2935. */
  2936. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2937. {
  2938. struct qeth_qdio_out_buffer *buffer;
  2939. int flush_count = 0;
  2940. if (queue->do_pack) {
  2941. if (atomic_read(&queue->used_buffers)
  2942. <= QETH_LOW_WATERMARK_PACK) {
  2943. /* switch PACKING -> non-PACKING */
  2944. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2945. if (queue->card->options.performance_stats)
  2946. queue->card->perf_stats.sc_p_dp++;
  2947. queue->do_pack = 0;
  2948. /* flush packing buffers */
  2949. buffer = queue->bufs[queue->next_buf_to_fill];
  2950. if ((atomic_read(&buffer->state) ==
  2951. QETH_QDIO_BUF_EMPTY) &&
  2952. (buffer->next_element_to_fill > 0)) {
  2953. atomic_set(&buffer->state,
  2954. QETH_QDIO_BUF_PRIMED);
  2955. flush_count++;
  2956. queue->next_buf_to_fill =
  2957. (queue->next_buf_to_fill + 1) %
  2958. QDIO_MAX_BUFFERS_PER_Q;
  2959. }
  2960. }
  2961. }
  2962. return flush_count;
  2963. }
  2964. /*
  2965. * Called to flush a packing buffer if no more pci flags are on the queue.
  2966. * Checks if there is a packing buffer and prepares it to be flushed.
  2967. * In that case returns 1, otherwise zero.
  2968. */
  2969. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2970. {
  2971. struct qeth_qdio_out_buffer *buffer;
  2972. buffer = queue->bufs[queue->next_buf_to_fill];
  2973. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2974. (buffer->next_element_to_fill > 0)) {
  2975. /* it's a packing buffer */
  2976. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2977. queue->next_buf_to_fill =
  2978. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2979. return 1;
  2980. }
  2981. return 0;
  2982. }
  2983. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2984. int count)
  2985. {
  2986. struct qeth_qdio_out_buffer *buf;
  2987. int rc;
  2988. int i;
  2989. unsigned int qdio_flags;
  2990. for (i = index; i < index + count; ++i) {
  2991. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  2992. buf = queue->bufs[bidx];
  2993. buf->buffer->element[buf->next_element_to_fill - 1].eflags |=
  2994. SBAL_EFLAGS_LAST_ENTRY;
  2995. if (queue->bufstates)
  2996. queue->bufstates[bidx].user = buf;
  2997. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2998. continue;
  2999. if (!queue->do_pack) {
  3000. if ((atomic_read(&queue->used_buffers) >=
  3001. (QETH_HIGH_WATERMARK_PACK -
  3002. QETH_WATERMARK_PACK_FUZZ)) &&
  3003. !atomic_read(&queue->set_pci_flags_count)) {
  3004. /* it's likely that we'll go to packing
  3005. * mode soon */
  3006. atomic_inc(&queue->set_pci_flags_count);
  3007. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  3008. }
  3009. } else {
  3010. if (!atomic_read(&queue->set_pci_flags_count)) {
  3011. /*
  3012. * there's no outstanding PCI any more, so we
  3013. * have to request a PCI to be sure the the PCI
  3014. * will wake at some time in the future then we
  3015. * can flush packed buffers that might still be
  3016. * hanging around, which can happen if no
  3017. * further send was requested by the stack
  3018. */
  3019. atomic_inc(&queue->set_pci_flags_count);
  3020. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  3021. }
  3022. }
  3023. }
  3024. queue->card->dev->trans_start = jiffies;
  3025. if (queue->card->options.performance_stats) {
  3026. queue->card->perf_stats.outbound_do_qdio_cnt++;
  3027. queue->card->perf_stats.outbound_do_qdio_start_time =
  3028. qeth_get_micros();
  3029. }
  3030. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  3031. if (atomic_read(&queue->set_pci_flags_count))
  3032. qdio_flags |= QDIO_FLAG_PCI_OUT;
  3033. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  3034. queue->queue_no, index, count);
  3035. if (queue->card->options.performance_stats)
  3036. queue->card->perf_stats.outbound_do_qdio_time +=
  3037. qeth_get_micros() -
  3038. queue->card->perf_stats.outbound_do_qdio_start_time;
  3039. atomic_add(count, &queue->used_buffers);
  3040. if (rc) {
  3041. queue->card->stats.tx_errors += count;
  3042. /* ignore temporary SIGA errors without busy condition */
  3043. if (rc == -ENOBUFS)
  3044. return;
  3045. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  3046. QETH_CARD_TEXT_(queue->card, 2, " q%d", queue->queue_no);
  3047. QETH_CARD_TEXT_(queue->card, 2, " idx%d", index);
  3048. QETH_CARD_TEXT_(queue->card, 2, " c%d", count);
  3049. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  3050. /* this must not happen under normal circumstances. if it
  3051. * happens something is really wrong -> recover */
  3052. qeth_schedule_recovery(queue->card);
  3053. return;
  3054. }
  3055. if (queue->card->options.performance_stats)
  3056. queue->card->perf_stats.bufs_sent += count;
  3057. }
  3058. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  3059. {
  3060. int index;
  3061. int flush_cnt = 0;
  3062. int q_was_packing = 0;
  3063. /*
  3064. * check if weed have to switch to non-packing mode or if
  3065. * we have to get a pci flag out on the queue
  3066. */
  3067. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  3068. !atomic_read(&queue->set_pci_flags_count)) {
  3069. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  3070. QETH_OUT_Q_UNLOCKED) {
  3071. /*
  3072. * If we get in here, there was no action in
  3073. * do_send_packet. So, we check if there is a
  3074. * packing buffer to be flushed here.
  3075. */
  3076. netif_stop_queue(queue->card->dev);
  3077. index = queue->next_buf_to_fill;
  3078. q_was_packing = queue->do_pack;
  3079. /* queue->do_pack may change */
  3080. barrier();
  3081. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  3082. if (!flush_cnt &&
  3083. !atomic_read(&queue->set_pci_flags_count))
  3084. flush_cnt +=
  3085. qeth_flush_buffers_on_no_pci(queue);
  3086. if (queue->card->options.performance_stats &&
  3087. q_was_packing)
  3088. queue->card->perf_stats.bufs_sent_pack +=
  3089. flush_cnt;
  3090. if (flush_cnt)
  3091. qeth_flush_buffers(queue, index, flush_cnt);
  3092. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3093. }
  3094. }
  3095. }
  3096. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  3097. unsigned long card_ptr)
  3098. {
  3099. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3100. if (card->dev && (card->dev->flags & IFF_UP))
  3101. napi_schedule(&card->napi);
  3102. }
  3103. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  3104. int qeth_configure_cq(struct qeth_card *card, enum qeth_cq cq)
  3105. {
  3106. int rc;
  3107. if (card->options.cq == QETH_CQ_NOTAVAILABLE) {
  3108. rc = -1;
  3109. goto out;
  3110. } else {
  3111. if (card->options.cq == cq) {
  3112. rc = 0;
  3113. goto out;
  3114. }
  3115. if (card->state != CARD_STATE_DOWN &&
  3116. card->state != CARD_STATE_RECOVER) {
  3117. rc = -1;
  3118. goto out;
  3119. }
  3120. qeth_free_qdio_buffers(card);
  3121. card->options.cq = cq;
  3122. rc = 0;
  3123. }
  3124. out:
  3125. return rc;
  3126. }
  3127. EXPORT_SYMBOL_GPL(qeth_configure_cq);
  3128. static void qeth_qdio_cq_handler(struct qeth_card *card,
  3129. unsigned int qdio_err,
  3130. unsigned int queue, int first_element, int count) {
  3131. struct qeth_qdio_q *cq = card->qdio.c_q;
  3132. int i;
  3133. int rc;
  3134. if (!qeth_is_cq(card, queue))
  3135. goto out;
  3136. QETH_CARD_TEXT_(card, 5, "qcqhe%d", first_element);
  3137. QETH_CARD_TEXT_(card, 5, "qcqhc%d", count);
  3138. QETH_CARD_TEXT_(card, 5, "qcqherr%d", qdio_err);
  3139. if (qdio_err) {
  3140. netif_stop_queue(card->dev);
  3141. qeth_schedule_recovery(card);
  3142. goto out;
  3143. }
  3144. if (card->options.performance_stats) {
  3145. card->perf_stats.cq_cnt++;
  3146. card->perf_stats.cq_start_time = qeth_get_micros();
  3147. }
  3148. for (i = first_element; i < first_element + count; ++i) {
  3149. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3150. struct qdio_buffer *buffer = &cq->qdio_bufs[bidx];
  3151. int e;
  3152. e = 0;
  3153. while (buffer->element[e].addr) {
  3154. unsigned long phys_aob_addr;
  3155. phys_aob_addr = (unsigned long) buffer->element[e].addr;
  3156. qeth_qdio_handle_aob(card, phys_aob_addr);
  3157. buffer->element[e].addr = NULL;
  3158. buffer->element[e].eflags = 0;
  3159. buffer->element[e].sflags = 0;
  3160. buffer->element[e].length = 0;
  3161. ++e;
  3162. }
  3163. buffer->element[15].eflags = 0;
  3164. buffer->element[15].sflags = 0;
  3165. }
  3166. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, queue,
  3167. card->qdio.c_q->next_buf_to_init,
  3168. count);
  3169. if (rc) {
  3170. dev_warn(&card->gdev->dev,
  3171. "QDIO reported an error, rc=%i\n", rc);
  3172. QETH_CARD_TEXT(card, 2, "qcqherr");
  3173. }
  3174. card->qdio.c_q->next_buf_to_init = (card->qdio.c_q->next_buf_to_init
  3175. + count) % QDIO_MAX_BUFFERS_PER_Q;
  3176. netif_wake_queue(card->dev);
  3177. if (card->options.performance_stats) {
  3178. int delta_t = qeth_get_micros();
  3179. delta_t -= card->perf_stats.cq_start_time;
  3180. card->perf_stats.cq_time += delta_t;
  3181. }
  3182. out:
  3183. return;
  3184. }
  3185. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  3186. unsigned int queue, int first_elem, int count,
  3187. unsigned long card_ptr)
  3188. {
  3189. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3190. QETH_CARD_TEXT_(card, 2, "qihq%d", queue);
  3191. QETH_CARD_TEXT_(card, 2, "qiec%d", qdio_err);
  3192. if (qeth_is_cq(card, queue))
  3193. qeth_qdio_cq_handler(card, qdio_err, queue, first_elem, count);
  3194. else if (qdio_err)
  3195. qeth_schedule_recovery(card);
  3196. }
  3197. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  3198. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  3199. unsigned int qdio_error, int __queue, int first_element,
  3200. int count, unsigned long card_ptr)
  3201. {
  3202. struct qeth_card *card = (struct qeth_card *) card_ptr;
  3203. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  3204. struct qeth_qdio_out_buffer *buffer;
  3205. int i;
  3206. QETH_CARD_TEXT(card, 6, "qdouhdl");
  3207. if (qdio_error & QDIO_ERROR_FATAL) {
  3208. QETH_CARD_TEXT(card, 2, "achkcond");
  3209. netif_stop_queue(card->dev);
  3210. qeth_schedule_recovery(card);
  3211. return;
  3212. }
  3213. if (card->options.performance_stats) {
  3214. card->perf_stats.outbound_handler_cnt++;
  3215. card->perf_stats.outbound_handler_start_time =
  3216. qeth_get_micros();
  3217. }
  3218. for (i = first_element; i < (first_element + count); ++i) {
  3219. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3220. buffer = queue->bufs[bidx];
  3221. qeth_handle_send_error(card, buffer, qdio_error);
  3222. if (queue->bufstates &&
  3223. (queue->bufstates[bidx].flags &
  3224. QDIO_OUTBUF_STATE_FLAG_PENDING) != 0) {
  3225. WARN_ON_ONCE(card->options.cq != QETH_CQ_ENABLED);
  3226. if (atomic_cmpxchg(&buffer->state,
  3227. QETH_QDIO_BUF_PRIMED,
  3228. QETH_QDIO_BUF_PENDING) ==
  3229. QETH_QDIO_BUF_PRIMED) {
  3230. qeth_notify_skbs(queue, buffer,
  3231. TX_NOTIFY_PENDING);
  3232. }
  3233. buffer->aob = queue->bufstates[bidx].aob;
  3234. QETH_CARD_TEXT_(queue->card, 5, "pel%d", bidx);
  3235. QETH_CARD_TEXT(queue->card, 5, "aob");
  3236. QETH_CARD_TEXT_(queue->card, 5, "%lx",
  3237. virt_to_phys(buffer->aob));
  3238. if (qeth_init_qdio_out_buf(queue, bidx)) {
  3239. QETH_CARD_TEXT(card, 2, "outofbuf");
  3240. qeth_schedule_recovery(card);
  3241. }
  3242. } else {
  3243. if (card->options.cq == QETH_CQ_ENABLED) {
  3244. enum iucv_tx_notify n;
  3245. n = qeth_compute_cq_notification(
  3246. buffer->buffer->element[15].sflags, 0);
  3247. qeth_notify_skbs(queue, buffer, n);
  3248. }
  3249. qeth_clear_output_buffer(queue, buffer,
  3250. QETH_QDIO_BUF_EMPTY);
  3251. }
  3252. qeth_cleanup_handled_pending(queue, bidx, 0);
  3253. }
  3254. atomic_sub(count, &queue->used_buffers);
  3255. /* check if we need to do something on this outbound queue */
  3256. if (card->info.type != QETH_CARD_TYPE_IQD)
  3257. qeth_check_outbound_queue(queue);
  3258. netif_wake_queue(queue->card->dev);
  3259. if (card->options.performance_stats)
  3260. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  3261. card->perf_stats.outbound_handler_start_time;
  3262. }
  3263. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  3264. /**
  3265. * Note: Function assumes that we have 4 outbound queues.
  3266. */
  3267. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  3268. int ipv, int cast_type)
  3269. {
  3270. __be16 *tci;
  3271. u8 tos;
  3272. if (cast_type && card->info.is_multicast_different)
  3273. return card->info.is_multicast_different &
  3274. (card->qdio.no_out_queues - 1);
  3275. switch (card->qdio.do_prio_queueing) {
  3276. case QETH_PRIO_Q_ING_TOS:
  3277. case QETH_PRIO_Q_ING_PREC:
  3278. switch (ipv) {
  3279. case 4:
  3280. tos = ipv4_get_dsfield(ip_hdr(skb));
  3281. break;
  3282. case 6:
  3283. tos = ipv6_get_dsfield(ipv6_hdr(skb));
  3284. break;
  3285. default:
  3286. return card->qdio.default_out_queue;
  3287. }
  3288. if (card->qdio.do_prio_queueing == QETH_PRIO_Q_ING_PREC)
  3289. return ~tos >> 6 & 3;
  3290. if (tos & IPTOS_MINCOST)
  3291. return 3;
  3292. if (tos & IPTOS_RELIABILITY)
  3293. return 2;
  3294. if (tos & IPTOS_THROUGHPUT)
  3295. return 1;
  3296. if (tos & IPTOS_LOWDELAY)
  3297. return 0;
  3298. break;
  3299. case QETH_PRIO_Q_ING_SKB:
  3300. if (skb->priority > 5)
  3301. return 0;
  3302. return ~skb->priority >> 1 & 3;
  3303. case QETH_PRIO_Q_ING_VLAN:
  3304. tci = &((struct ethhdr *)skb->data)->h_proto;
  3305. if (*tci == ETH_P_8021Q)
  3306. return ~*(tci + 1) >> (VLAN_PRIO_SHIFT + 1) & 3;
  3307. break;
  3308. default:
  3309. break;
  3310. }
  3311. return card->qdio.default_out_queue;
  3312. }
  3313. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  3314. int qeth_get_elements_for_frags(struct sk_buff *skb)
  3315. {
  3316. int cnt, length, e, elements = 0;
  3317. struct skb_frag_struct *frag;
  3318. char *data;
  3319. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  3320. frag = &skb_shinfo(skb)->frags[cnt];
  3321. data = (char *)page_to_phys(skb_frag_page(frag)) +
  3322. frag->page_offset;
  3323. length = frag->size;
  3324. e = PFN_UP((unsigned long)data + length - 1) -
  3325. PFN_DOWN((unsigned long)data);
  3326. elements += e;
  3327. }
  3328. return elements;
  3329. }
  3330. EXPORT_SYMBOL_GPL(qeth_get_elements_for_frags);
  3331. int qeth_get_elements_no(struct qeth_card *card,
  3332. struct sk_buff *skb, int elems)
  3333. {
  3334. int dlen = skb->len - skb->data_len;
  3335. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  3336. PFN_DOWN((unsigned long)skb->data);
  3337. elements_needed += qeth_get_elements_for_frags(skb);
  3338. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  3339. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  3340. "(Number=%d / Length=%d). Discarded.\n",
  3341. (elements_needed+elems), skb->len);
  3342. return 0;
  3343. }
  3344. return elements_needed;
  3345. }
  3346. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  3347. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, struct qeth_hdr **hdr, int len)
  3348. {
  3349. int hroom, inpage, rest;
  3350. if (((unsigned long)skb->data & PAGE_MASK) !=
  3351. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  3352. hroom = skb_headroom(skb);
  3353. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  3354. rest = len - inpage;
  3355. if (rest > hroom)
  3356. return 1;
  3357. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  3358. skb->data -= rest;
  3359. skb->tail -= rest;
  3360. *hdr = (struct qeth_hdr *)skb->data;
  3361. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  3362. }
  3363. return 0;
  3364. }
  3365. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  3366. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  3367. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  3368. int offset)
  3369. {
  3370. int length = skb->len - skb->data_len;
  3371. int length_here;
  3372. int element;
  3373. char *data;
  3374. int first_lap, cnt;
  3375. struct skb_frag_struct *frag;
  3376. element = *next_element_to_fill;
  3377. data = skb->data;
  3378. first_lap = (is_tso == 0 ? 1 : 0);
  3379. if (offset >= 0) {
  3380. data = skb->data + offset;
  3381. length -= offset;
  3382. first_lap = 0;
  3383. }
  3384. while (length > 0) {
  3385. /* length_here is the remaining amount of data in this page */
  3386. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  3387. if (length < length_here)
  3388. length_here = length;
  3389. buffer->element[element].addr = data;
  3390. buffer->element[element].length = length_here;
  3391. length -= length_here;
  3392. if (!length) {
  3393. if (first_lap)
  3394. if (skb_shinfo(skb)->nr_frags)
  3395. buffer->element[element].eflags =
  3396. SBAL_EFLAGS_FIRST_FRAG;
  3397. else
  3398. buffer->element[element].eflags = 0;
  3399. else
  3400. buffer->element[element].eflags =
  3401. SBAL_EFLAGS_MIDDLE_FRAG;
  3402. } else {
  3403. if (first_lap)
  3404. buffer->element[element].eflags =
  3405. SBAL_EFLAGS_FIRST_FRAG;
  3406. else
  3407. buffer->element[element].eflags =
  3408. SBAL_EFLAGS_MIDDLE_FRAG;
  3409. }
  3410. data += length_here;
  3411. element++;
  3412. first_lap = 0;
  3413. }
  3414. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  3415. frag = &skb_shinfo(skb)->frags[cnt];
  3416. data = (char *)page_to_phys(skb_frag_page(frag)) +
  3417. frag->page_offset;
  3418. length = frag->size;
  3419. while (length > 0) {
  3420. length_here = PAGE_SIZE -
  3421. ((unsigned long) data % PAGE_SIZE);
  3422. if (length < length_here)
  3423. length_here = length;
  3424. buffer->element[element].addr = data;
  3425. buffer->element[element].length = length_here;
  3426. buffer->element[element].eflags =
  3427. SBAL_EFLAGS_MIDDLE_FRAG;
  3428. length -= length_here;
  3429. data += length_here;
  3430. element++;
  3431. }
  3432. }
  3433. if (buffer->element[element - 1].eflags)
  3434. buffer->element[element - 1].eflags = SBAL_EFLAGS_LAST_FRAG;
  3435. *next_element_to_fill = element;
  3436. }
  3437. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  3438. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  3439. struct qeth_hdr *hdr, int offset, int hd_len)
  3440. {
  3441. struct qdio_buffer *buffer;
  3442. int flush_cnt = 0, hdr_len, large_send = 0;
  3443. buffer = buf->buffer;
  3444. atomic_inc(&skb->users);
  3445. skb_queue_tail(&buf->skb_list, skb);
  3446. /*check first on TSO ....*/
  3447. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  3448. int element = buf->next_element_to_fill;
  3449. hdr_len = sizeof(struct qeth_hdr_tso) +
  3450. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  3451. /*fill first buffer entry only with header information */
  3452. buffer->element[element].addr = skb->data;
  3453. buffer->element[element].length = hdr_len;
  3454. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3455. buf->next_element_to_fill++;
  3456. skb->data += hdr_len;
  3457. skb->len -= hdr_len;
  3458. large_send = 1;
  3459. }
  3460. if (offset >= 0) {
  3461. int element = buf->next_element_to_fill;
  3462. buffer->element[element].addr = hdr;
  3463. buffer->element[element].length = sizeof(struct qeth_hdr) +
  3464. hd_len;
  3465. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3466. buf->is_header[element] = 1;
  3467. buf->next_element_to_fill++;
  3468. }
  3469. __qeth_fill_buffer(skb, buffer, large_send,
  3470. (int *)&buf->next_element_to_fill, offset);
  3471. if (!queue->do_pack) {
  3472. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  3473. /* set state to PRIMED -> will be flushed */
  3474. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3475. flush_cnt = 1;
  3476. } else {
  3477. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  3478. if (queue->card->options.performance_stats)
  3479. queue->card->perf_stats.skbs_sent_pack++;
  3480. if (buf->next_element_to_fill >=
  3481. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  3482. /*
  3483. * packed buffer if full -> set state PRIMED
  3484. * -> will be flushed
  3485. */
  3486. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3487. flush_cnt = 1;
  3488. }
  3489. }
  3490. return flush_cnt;
  3491. }
  3492. int qeth_do_send_packet_fast(struct qeth_card *card,
  3493. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  3494. struct qeth_hdr *hdr, int elements_needed,
  3495. int offset, int hd_len)
  3496. {
  3497. struct qeth_qdio_out_buffer *buffer;
  3498. int index;
  3499. /* spin until we get the queue ... */
  3500. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3501. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3502. /* ... now we've got the queue */
  3503. index = queue->next_buf_to_fill;
  3504. buffer = queue->bufs[queue->next_buf_to_fill];
  3505. /*
  3506. * check if buffer is empty to make sure that we do not 'overtake'
  3507. * ourselves and try to fill a buffer that is already primed
  3508. */
  3509. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  3510. goto out;
  3511. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  3512. QDIO_MAX_BUFFERS_PER_Q;
  3513. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3514. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  3515. qeth_flush_buffers(queue, index, 1);
  3516. return 0;
  3517. out:
  3518. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3519. return -EBUSY;
  3520. }
  3521. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  3522. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  3523. struct sk_buff *skb, struct qeth_hdr *hdr,
  3524. int elements_needed)
  3525. {
  3526. struct qeth_qdio_out_buffer *buffer;
  3527. int start_index;
  3528. int flush_count = 0;
  3529. int do_pack = 0;
  3530. int tmp;
  3531. int rc = 0;
  3532. /* spin until we get the queue ... */
  3533. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3534. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3535. start_index = queue->next_buf_to_fill;
  3536. buffer = queue->bufs[queue->next_buf_to_fill];
  3537. /*
  3538. * check if buffer is empty to make sure that we do not 'overtake'
  3539. * ourselves and try to fill a buffer that is already primed
  3540. */
  3541. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  3542. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3543. return -EBUSY;
  3544. }
  3545. /* check if we need to switch packing state of this queue */
  3546. qeth_switch_to_packing_if_needed(queue);
  3547. if (queue->do_pack) {
  3548. do_pack = 1;
  3549. /* does packet fit in current buffer? */
  3550. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  3551. buffer->next_element_to_fill) < elements_needed) {
  3552. /* ... no -> set state PRIMED */
  3553. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  3554. flush_count++;
  3555. queue->next_buf_to_fill =
  3556. (queue->next_buf_to_fill + 1) %
  3557. QDIO_MAX_BUFFERS_PER_Q;
  3558. buffer = queue->bufs[queue->next_buf_to_fill];
  3559. /* we did a step forward, so check buffer state
  3560. * again */
  3561. if (atomic_read(&buffer->state) !=
  3562. QETH_QDIO_BUF_EMPTY) {
  3563. qeth_flush_buffers(queue, start_index,
  3564. flush_count);
  3565. atomic_set(&queue->state,
  3566. QETH_OUT_Q_UNLOCKED);
  3567. return -EBUSY;
  3568. }
  3569. }
  3570. }
  3571. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  3572. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  3573. QDIO_MAX_BUFFERS_PER_Q;
  3574. flush_count += tmp;
  3575. if (flush_count)
  3576. qeth_flush_buffers(queue, start_index, flush_count);
  3577. else if (!atomic_read(&queue->set_pci_flags_count))
  3578. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  3579. /*
  3580. * queue->state will go from LOCKED -> UNLOCKED or from
  3581. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  3582. * (switch packing state or flush buffer to get another pci flag out).
  3583. * In that case we will enter this loop
  3584. */
  3585. while (atomic_dec_return(&queue->state)) {
  3586. flush_count = 0;
  3587. start_index = queue->next_buf_to_fill;
  3588. /* check if we can go back to non-packing state */
  3589. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3590. /*
  3591. * check if we need to flush a packing buffer to get a pci
  3592. * flag out on the queue
  3593. */
  3594. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3595. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3596. if (flush_count)
  3597. qeth_flush_buffers(queue, start_index, flush_count);
  3598. }
  3599. /* at this point the queue is UNLOCKED again */
  3600. if (queue->card->options.performance_stats && do_pack)
  3601. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3602. return rc;
  3603. }
  3604. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3605. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3606. struct qeth_reply *reply, unsigned long data)
  3607. {
  3608. struct qeth_ipa_cmd *cmd;
  3609. struct qeth_ipacmd_setadpparms *setparms;
  3610. QETH_CARD_TEXT(card, 4, "prmadpcb");
  3611. cmd = (struct qeth_ipa_cmd *) data;
  3612. setparms = &(cmd->data.setadapterparms);
  3613. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3614. if (cmd->hdr.return_code) {
  3615. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3616. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3617. }
  3618. card->info.promisc_mode = setparms->data.mode;
  3619. return 0;
  3620. }
  3621. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3622. {
  3623. enum qeth_ipa_promisc_modes mode;
  3624. struct net_device *dev = card->dev;
  3625. struct qeth_cmd_buffer *iob;
  3626. struct qeth_ipa_cmd *cmd;
  3627. QETH_CARD_TEXT(card, 4, "setprom");
  3628. if (((dev->flags & IFF_PROMISC) &&
  3629. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3630. (!(dev->flags & IFF_PROMISC) &&
  3631. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3632. return;
  3633. mode = SET_PROMISC_MODE_OFF;
  3634. if (dev->flags & IFF_PROMISC)
  3635. mode = SET_PROMISC_MODE_ON;
  3636. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  3637. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3638. sizeof(struct qeth_ipacmd_setadpparms));
  3639. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3640. cmd->data.setadapterparms.data.mode = mode;
  3641. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3642. }
  3643. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3644. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3645. {
  3646. struct qeth_card *card;
  3647. char dbf_text[15];
  3648. card = dev->ml_priv;
  3649. QETH_CARD_TEXT(card, 4, "chgmtu");
  3650. sprintf(dbf_text, "%8x", new_mtu);
  3651. QETH_CARD_TEXT(card, 4, dbf_text);
  3652. if (new_mtu < 64)
  3653. return -EINVAL;
  3654. if (new_mtu > 65535)
  3655. return -EINVAL;
  3656. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3657. (!qeth_mtu_is_valid(card, new_mtu)))
  3658. return -EINVAL;
  3659. dev->mtu = new_mtu;
  3660. return 0;
  3661. }
  3662. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3663. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3664. {
  3665. struct qeth_card *card;
  3666. card = dev->ml_priv;
  3667. QETH_CARD_TEXT(card, 5, "getstat");
  3668. return &card->stats;
  3669. }
  3670. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3671. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3672. struct qeth_reply *reply, unsigned long data)
  3673. {
  3674. struct qeth_ipa_cmd *cmd;
  3675. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3676. cmd = (struct qeth_ipa_cmd *) data;
  3677. if (!card->options.layer2 ||
  3678. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3679. memcpy(card->dev->dev_addr,
  3680. &cmd->data.setadapterparms.data.change_addr.addr,
  3681. OSA_ADDR_LEN);
  3682. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3683. }
  3684. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3685. return 0;
  3686. }
  3687. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3688. {
  3689. int rc;
  3690. struct qeth_cmd_buffer *iob;
  3691. struct qeth_ipa_cmd *cmd;
  3692. QETH_CARD_TEXT(card, 4, "chgmac");
  3693. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3694. sizeof(struct qeth_ipacmd_setadpparms));
  3695. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3696. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3697. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3698. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3699. card->dev->dev_addr, OSA_ADDR_LEN);
  3700. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3701. NULL);
  3702. return rc;
  3703. }
  3704. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3705. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3706. struct qeth_reply *reply, unsigned long data)
  3707. {
  3708. struct qeth_ipa_cmd *cmd;
  3709. struct qeth_set_access_ctrl *access_ctrl_req;
  3710. int fallback = *(int *)reply->param;
  3711. QETH_CARD_TEXT(card, 4, "setaccb");
  3712. cmd = (struct qeth_ipa_cmd *) data;
  3713. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3714. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3715. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3716. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3717. cmd->data.setadapterparms.hdr.return_code);
  3718. if (cmd->data.setadapterparms.hdr.return_code !=
  3719. SET_ACCESS_CTRL_RC_SUCCESS)
  3720. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3721. card->gdev->dev.kobj.name,
  3722. access_ctrl_req->subcmd_code,
  3723. cmd->data.setadapterparms.hdr.return_code);
  3724. switch (cmd->data.setadapterparms.hdr.return_code) {
  3725. case SET_ACCESS_CTRL_RC_SUCCESS:
  3726. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3727. dev_info(&card->gdev->dev,
  3728. "QDIO data connection isolation is deactivated\n");
  3729. } else {
  3730. dev_info(&card->gdev->dev,
  3731. "QDIO data connection isolation is activated\n");
  3732. }
  3733. break;
  3734. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3735. QETH_DBF_MESSAGE(2, "%s QDIO data connection isolation already "
  3736. "deactivated\n", dev_name(&card->gdev->dev));
  3737. if (fallback)
  3738. card->options.isolation = card->options.prev_isolation;
  3739. break;
  3740. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3741. QETH_DBF_MESSAGE(2, "%s QDIO data connection isolation already"
  3742. " activated\n", dev_name(&card->gdev->dev));
  3743. if (fallback)
  3744. card->options.isolation = card->options.prev_isolation;
  3745. break;
  3746. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3747. dev_err(&card->gdev->dev, "Adapter does not "
  3748. "support QDIO data connection isolation\n");
  3749. break;
  3750. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3751. dev_err(&card->gdev->dev,
  3752. "Adapter is dedicated. "
  3753. "QDIO data connection isolation not supported\n");
  3754. if (fallback)
  3755. card->options.isolation = card->options.prev_isolation;
  3756. break;
  3757. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3758. dev_err(&card->gdev->dev,
  3759. "TSO does not permit QDIO data connection isolation\n");
  3760. if (fallback)
  3761. card->options.isolation = card->options.prev_isolation;
  3762. break;
  3763. case SET_ACCESS_CTRL_RC_REFLREL_UNSUPPORTED:
  3764. dev_err(&card->gdev->dev, "The adjacent switch port does not "
  3765. "support reflective relay mode\n");
  3766. if (fallback)
  3767. card->options.isolation = card->options.prev_isolation;
  3768. break;
  3769. case SET_ACCESS_CTRL_RC_REFLREL_FAILED:
  3770. dev_err(&card->gdev->dev, "The reflective relay mode cannot be "
  3771. "enabled at the adjacent switch port");
  3772. if (fallback)
  3773. card->options.isolation = card->options.prev_isolation;
  3774. break;
  3775. case SET_ACCESS_CTRL_RC_REFLREL_DEACT_FAILED:
  3776. dev_warn(&card->gdev->dev, "Turning off reflective relay mode "
  3777. "at the adjacent switch failed\n");
  3778. break;
  3779. default:
  3780. /* this should never happen */
  3781. if (fallback)
  3782. card->options.isolation = card->options.prev_isolation;
  3783. break;
  3784. }
  3785. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3786. return 0;
  3787. }
  3788. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3789. enum qeth_ipa_isolation_modes isolation, int fallback)
  3790. {
  3791. int rc;
  3792. struct qeth_cmd_buffer *iob;
  3793. struct qeth_ipa_cmd *cmd;
  3794. struct qeth_set_access_ctrl *access_ctrl_req;
  3795. QETH_CARD_TEXT(card, 4, "setacctl");
  3796. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3797. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3798. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3799. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3800. sizeof(struct qeth_set_access_ctrl));
  3801. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3802. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3803. access_ctrl_req->subcmd_code = isolation;
  3804. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3805. &fallback);
  3806. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3807. return rc;
  3808. }
  3809. int qeth_set_access_ctrl_online(struct qeth_card *card, int fallback)
  3810. {
  3811. int rc = 0;
  3812. QETH_CARD_TEXT(card, 4, "setactlo");
  3813. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3814. card->info.type == QETH_CARD_TYPE_OSX) &&
  3815. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3816. rc = qeth_setadpparms_set_access_ctrl(card,
  3817. card->options.isolation, fallback);
  3818. if (rc) {
  3819. QETH_DBF_MESSAGE(3,
  3820. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3821. card->gdev->dev.kobj.name,
  3822. rc);
  3823. rc = -EOPNOTSUPP;
  3824. }
  3825. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3826. card->options.isolation = ISOLATION_MODE_NONE;
  3827. dev_err(&card->gdev->dev, "Adapter does not "
  3828. "support QDIO data connection isolation\n");
  3829. rc = -EOPNOTSUPP;
  3830. }
  3831. return rc;
  3832. }
  3833. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3834. void qeth_tx_timeout(struct net_device *dev)
  3835. {
  3836. struct qeth_card *card;
  3837. card = dev->ml_priv;
  3838. QETH_CARD_TEXT(card, 4, "txtimeo");
  3839. card->stats.tx_errors++;
  3840. qeth_schedule_recovery(card);
  3841. }
  3842. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3843. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3844. {
  3845. struct qeth_card *card = dev->ml_priv;
  3846. int rc = 0;
  3847. switch (regnum) {
  3848. case MII_BMCR: /* Basic mode control register */
  3849. rc = BMCR_FULLDPLX;
  3850. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3851. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3852. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3853. rc |= BMCR_SPEED100;
  3854. break;
  3855. case MII_BMSR: /* Basic mode status register */
  3856. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3857. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3858. BMSR_100BASE4;
  3859. break;
  3860. case MII_PHYSID1: /* PHYS ID 1 */
  3861. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3862. dev->dev_addr[2];
  3863. rc = (rc >> 5) & 0xFFFF;
  3864. break;
  3865. case MII_PHYSID2: /* PHYS ID 2 */
  3866. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3867. break;
  3868. case MII_ADVERTISE: /* Advertisement control reg */
  3869. rc = ADVERTISE_ALL;
  3870. break;
  3871. case MII_LPA: /* Link partner ability reg */
  3872. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3873. LPA_100BASE4 | LPA_LPACK;
  3874. break;
  3875. case MII_EXPANSION: /* Expansion register */
  3876. break;
  3877. case MII_DCOUNTER: /* disconnect counter */
  3878. break;
  3879. case MII_FCSCOUNTER: /* false carrier counter */
  3880. break;
  3881. case MII_NWAYTEST: /* N-way auto-neg test register */
  3882. break;
  3883. case MII_RERRCOUNTER: /* rx error counter */
  3884. rc = card->stats.rx_errors;
  3885. break;
  3886. case MII_SREVISION: /* silicon revision */
  3887. break;
  3888. case MII_RESV1: /* reserved 1 */
  3889. break;
  3890. case MII_LBRERROR: /* loopback, rx, bypass error */
  3891. break;
  3892. case MII_PHYADDR: /* physical address */
  3893. break;
  3894. case MII_RESV2: /* reserved 2 */
  3895. break;
  3896. case MII_TPISTATUS: /* TPI status for 10mbps */
  3897. break;
  3898. case MII_NCONFIG: /* network interface config */
  3899. break;
  3900. default:
  3901. break;
  3902. }
  3903. return rc;
  3904. }
  3905. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3906. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3907. struct qeth_cmd_buffer *iob, int len,
  3908. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3909. unsigned long),
  3910. void *reply_param)
  3911. {
  3912. u16 s1, s2;
  3913. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3914. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3915. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3916. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3917. /* adjust PDU length fields in IPA_PDU_HEADER */
  3918. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3919. s2 = (u32) len;
  3920. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3921. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3922. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3923. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3924. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3925. reply_cb, reply_param);
  3926. }
  3927. static int qeth_snmp_command_cb(struct qeth_card *card,
  3928. struct qeth_reply *reply, unsigned long sdata)
  3929. {
  3930. struct qeth_ipa_cmd *cmd;
  3931. struct qeth_arp_query_info *qinfo;
  3932. struct qeth_snmp_cmd *snmp;
  3933. unsigned char *data;
  3934. __u16 data_len;
  3935. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3936. cmd = (struct qeth_ipa_cmd *) sdata;
  3937. data = (unsigned char *)((char *)cmd - reply->offset);
  3938. qinfo = (struct qeth_arp_query_info *) reply->param;
  3939. snmp = &cmd->data.setadapterparms.data.snmp;
  3940. if (cmd->hdr.return_code) {
  3941. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3942. return 0;
  3943. }
  3944. if (cmd->data.setadapterparms.hdr.return_code) {
  3945. cmd->hdr.return_code =
  3946. cmd->data.setadapterparms.hdr.return_code;
  3947. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3948. return 0;
  3949. }
  3950. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3951. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3952. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3953. else
  3954. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3955. /* check if there is enough room in userspace */
  3956. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3957. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3958. cmd->hdr.return_code = IPA_RC_ENOMEM;
  3959. return 0;
  3960. }
  3961. QETH_CARD_TEXT_(card, 4, "snore%i",
  3962. cmd->data.setadapterparms.hdr.used_total);
  3963. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3964. cmd->data.setadapterparms.hdr.seq_no);
  3965. /*copy entries to user buffer*/
  3966. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3967. memcpy(qinfo->udata + qinfo->udata_offset,
  3968. (char *)snmp,
  3969. data_len + offsetof(struct qeth_snmp_cmd, data));
  3970. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3971. } else {
  3972. memcpy(qinfo->udata + qinfo->udata_offset,
  3973. (char *)&snmp->request, data_len);
  3974. }
  3975. qinfo->udata_offset += data_len;
  3976. /* check if all replies received ... */
  3977. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3978. cmd->data.setadapterparms.hdr.used_total);
  3979. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3980. cmd->data.setadapterparms.hdr.seq_no);
  3981. if (cmd->data.setadapterparms.hdr.seq_no <
  3982. cmd->data.setadapterparms.hdr.used_total)
  3983. return 1;
  3984. return 0;
  3985. }
  3986. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3987. {
  3988. struct qeth_cmd_buffer *iob;
  3989. struct qeth_ipa_cmd *cmd;
  3990. struct qeth_snmp_ureq *ureq;
  3991. unsigned int req_len;
  3992. struct qeth_arp_query_info qinfo = {0, };
  3993. int rc = 0;
  3994. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3995. if (card->info.guestlan)
  3996. return -EOPNOTSUPP;
  3997. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3998. (!card->options.layer2)) {
  3999. return -EOPNOTSUPP;
  4000. }
  4001. /* skip 4 bytes (data_len struct member) to get req_len */
  4002. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  4003. return -EFAULT;
  4004. if (req_len > (QETH_BUFSIZE - IPA_PDU_HEADER_SIZE -
  4005. sizeof(struct qeth_ipacmd_hdr) -
  4006. sizeof(struct qeth_ipacmd_setadpparms_hdr)))
  4007. return -EINVAL;
  4008. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  4009. if (IS_ERR(ureq)) {
  4010. QETH_CARD_TEXT(card, 2, "snmpnome");
  4011. return PTR_ERR(ureq);
  4012. }
  4013. qinfo.udata_len = ureq->hdr.data_len;
  4014. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  4015. if (!qinfo.udata) {
  4016. kfree(ureq);
  4017. return -ENOMEM;
  4018. }
  4019. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  4020. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  4021. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  4022. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  4023. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  4024. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  4025. qeth_snmp_command_cb, (void *)&qinfo);
  4026. if (rc)
  4027. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  4028. QETH_CARD_IFNAME(card), rc);
  4029. else {
  4030. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  4031. rc = -EFAULT;
  4032. }
  4033. kfree(ureq);
  4034. kfree(qinfo.udata);
  4035. return rc;
  4036. }
  4037. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  4038. static int qeth_setadpparms_query_oat_cb(struct qeth_card *card,
  4039. struct qeth_reply *reply, unsigned long data)
  4040. {
  4041. struct qeth_ipa_cmd *cmd;
  4042. struct qeth_qoat_priv *priv;
  4043. char *resdata;
  4044. int resdatalen;
  4045. QETH_CARD_TEXT(card, 3, "qoatcb");
  4046. cmd = (struct qeth_ipa_cmd *)data;
  4047. priv = (struct qeth_qoat_priv *)reply->param;
  4048. resdatalen = cmd->data.setadapterparms.hdr.cmdlength;
  4049. resdata = (char *)data + 28;
  4050. if (resdatalen > (priv->buffer_len - priv->response_len)) {
  4051. cmd->hdr.return_code = IPA_RC_FFFF;
  4052. return 0;
  4053. }
  4054. memcpy((priv->buffer + priv->response_len), resdata,
  4055. resdatalen);
  4056. priv->response_len += resdatalen;
  4057. if (cmd->data.setadapterparms.hdr.seq_no <
  4058. cmd->data.setadapterparms.hdr.used_total)
  4059. return 1;
  4060. return 0;
  4061. }
  4062. int qeth_query_oat_command(struct qeth_card *card, char __user *udata)
  4063. {
  4064. int rc = 0;
  4065. struct qeth_cmd_buffer *iob;
  4066. struct qeth_ipa_cmd *cmd;
  4067. struct qeth_query_oat *oat_req;
  4068. struct qeth_query_oat_data oat_data;
  4069. struct qeth_qoat_priv priv;
  4070. void __user *tmp;
  4071. QETH_CARD_TEXT(card, 3, "qoatcmd");
  4072. if (!qeth_adp_supported(card, IPA_SETADP_QUERY_OAT)) {
  4073. rc = -EOPNOTSUPP;
  4074. goto out;
  4075. }
  4076. if (copy_from_user(&oat_data, udata,
  4077. sizeof(struct qeth_query_oat_data))) {
  4078. rc = -EFAULT;
  4079. goto out;
  4080. }
  4081. priv.buffer_len = oat_data.buffer_len;
  4082. priv.response_len = 0;
  4083. priv.buffer = kzalloc(oat_data.buffer_len, GFP_KERNEL);
  4084. if (!priv.buffer) {
  4085. rc = -ENOMEM;
  4086. goto out;
  4087. }
  4088. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_OAT,
  4089. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  4090. sizeof(struct qeth_query_oat));
  4091. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  4092. oat_req = &cmd->data.setadapterparms.data.query_oat;
  4093. oat_req->subcmd_code = oat_data.command;
  4094. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_query_oat_cb,
  4095. &priv);
  4096. if (!rc) {
  4097. if (is_compat_task())
  4098. tmp = compat_ptr(oat_data.ptr);
  4099. else
  4100. tmp = (void __user *)(unsigned long)oat_data.ptr;
  4101. if (copy_to_user(tmp, priv.buffer,
  4102. priv.response_len)) {
  4103. rc = -EFAULT;
  4104. goto out_free;
  4105. }
  4106. oat_data.response_len = priv.response_len;
  4107. if (copy_to_user(udata, &oat_data,
  4108. sizeof(struct qeth_query_oat_data)))
  4109. rc = -EFAULT;
  4110. } else
  4111. if (rc == IPA_RC_FFFF)
  4112. rc = -EFAULT;
  4113. out_free:
  4114. kfree(priv.buffer);
  4115. out:
  4116. return rc;
  4117. }
  4118. EXPORT_SYMBOL_GPL(qeth_query_oat_command);
  4119. static int qeth_query_card_info_cb(struct qeth_card *card,
  4120. struct qeth_reply *reply, unsigned long data)
  4121. {
  4122. struct qeth_ipa_cmd *cmd;
  4123. struct qeth_query_card_info *card_info;
  4124. struct carrier_info *carrier_info;
  4125. QETH_CARD_TEXT(card, 2, "qcrdincb");
  4126. carrier_info = (struct carrier_info *)reply->param;
  4127. cmd = (struct qeth_ipa_cmd *)data;
  4128. card_info = &cmd->data.setadapterparms.data.card_info;
  4129. if (cmd->data.setadapterparms.hdr.return_code == 0) {
  4130. carrier_info->card_type = card_info->card_type;
  4131. carrier_info->port_mode = card_info->port_mode;
  4132. carrier_info->port_speed = card_info->port_speed;
  4133. }
  4134. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  4135. return 0;
  4136. }
  4137. int qeth_query_card_info(struct qeth_card *card,
  4138. struct carrier_info *carrier_info)
  4139. {
  4140. struct qeth_cmd_buffer *iob;
  4141. QETH_CARD_TEXT(card, 2, "qcrdinfo");
  4142. if (!qeth_adp_supported(card, IPA_SETADP_QUERY_CARD_INFO))
  4143. return -EOPNOTSUPP;
  4144. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_CARD_INFO,
  4145. sizeof(struct qeth_ipacmd_setadpparms_hdr));
  4146. return qeth_send_ipa_cmd(card, iob, qeth_query_card_info_cb,
  4147. (void *)carrier_info);
  4148. }
  4149. EXPORT_SYMBOL_GPL(qeth_query_card_info);
  4150. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  4151. {
  4152. switch (card->info.type) {
  4153. case QETH_CARD_TYPE_IQD:
  4154. return 2;
  4155. default:
  4156. return 0;
  4157. }
  4158. }
  4159. static void qeth_determine_capabilities(struct qeth_card *card)
  4160. {
  4161. int rc;
  4162. int length;
  4163. char *prcd;
  4164. struct ccw_device *ddev;
  4165. int ddev_offline = 0;
  4166. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  4167. ddev = CARD_DDEV(card);
  4168. if (!ddev->online) {
  4169. ddev_offline = 1;
  4170. rc = ccw_device_set_online(ddev);
  4171. if (rc) {
  4172. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4173. goto out;
  4174. }
  4175. }
  4176. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  4177. if (rc) {
  4178. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  4179. dev_name(&card->gdev->dev), rc);
  4180. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4181. goto out_offline;
  4182. }
  4183. qeth_configure_unitaddr(card, prcd);
  4184. if (ddev_offline)
  4185. qeth_configure_blkt_default(card, prcd);
  4186. kfree(prcd);
  4187. rc = qdio_get_ssqd_desc(ddev, &card->ssqd);
  4188. if (rc)
  4189. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  4190. QETH_DBF_TEXT_(SETUP, 2, "qfmt%d", card->ssqd.qfmt);
  4191. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac1);
  4192. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac3);
  4193. QETH_DBF_TEXT_(SETUP, 2, "icnt%d", card->ssqd.icnt);
  4194. if (!((card->ssqd.qfmt != QDIO_IQDIO_QFMT) ||
  4195. ((card->ssqd.qdioac1 & CHSC_AC1_INITIATE_INPUTQ) == 0) ||
  4196. ((card->ssqd.qdioac3 & CHSC_AC3_FORMAT2_CQ_AVAILABLE) == 0))) {
  4197. dev_info(&card->gdev->dev,
  4198. "Completion Queueing supported\n");
  4199. } else {
  4200. card->options.cq = QETH_CQ_NOTAVAILABLE;
  4201. }
  4202. out_offline:
  4203. if (ddev_offline == 1)
  4204. ccw_device_set_offline(ddev);
  4205. out:
  4206. return;
  4207. }
  4208. static inline void qeth_qdio_establish_cq(struct qeth_card *card,
  4209. struct qdio_buffer **in_sbal_ptrs,
  4210. void (**queue_start_poll) (struct ccw_device *, int, unsigned long)) {
  4211. int i;
  4212. if (card->options.cq == QETH_CQ_ENABLED) {
  4213. int offset = QDIO_MAX_BUFFERS_PER_Q *
  4214. (card->qdio.no_in_queues - 1);
  4215. i = QDIO_MAX_BUFFERS_PER_Q * (card->qdio.no_in_queues - 1);
  4216. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4217. in_sbal_ptrs[offset + i] = (struct qdio_buffer *)
  4218. virt_to_phys(card->qdio.c_q->bufs[i].buffer);
  4219. }
  4220. queue_start_poll[card->qdio.no_in_queues - 1] = NULL;
  4221. }
  4222. }
  4223. static int qeth_qdio_establish(struct qeth_card *card)
  4224. {
  4225. struct qdio_initialize init_data;
  4226. char *qib_param_field;
  4227. struct qdio_buffer **in_sbal_ptrs;
  4228. void (**queue_start_poll) (struct ccw_device *, int, unsigned long);
  4229. struct qdio_buffer **out_sbal_ptrs;
  4230. int i, j, k;
  4231. int rc = 0;
  4232. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  4233. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  4234. GFP_KERNEL);
  4235. if (!qib_param_field) {
  4236. rc = -ENOMEM;
  4237. goto out_free_nothing;
  4238. }
  4239. qeth_create_qib_param_field(card, qib_param_field);
  4240. qeth_create_qib_param_field_blkt(card, qib_param_field);
  4241. in_sbal_ptrs = kzalloc(card->qdio.no_in_queues *
  4242. QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  4243. GFP_KERNEL);
  4244. if (!in_sbal_ptrs) {
  4245. rc = -ENOMEM;
  4246. goto out_free_qib_param;
  4247. }
  4248. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4249. in_sbal_ptrs[i] = (struct qdio_buffer *)
  4250. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  4251. }
  4252. queue_start_poll = kzalloc(sizeof(void *) * card->qdio.no_in_queues,
  4253. GFP_KERNEL);
  4254. if (!queue_start_poll) {
  4255. rc = -ENOMEM;
  4256. goto out_free_in_sbals;
  4257. }
  4258. for (i = 0; i < card->qdio.no_in_queues; ++i)
  4259. queue_start_poll[i] = card->discipline->start_poll;
  4260. qeth_qdio_establish_cq(card, in_sbal_ptrs, queue_start_poll);
  4261. out_sbal_ptrs =
  4262. kzalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  4263. sizeof(void *), GFP_KERNEL);
  4264. if (!out_sbal_ptrs) {
  4265. rc = -ENOMEM;
  4266. goto out_free_queue_start_poll;
  4267. }
  4268. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  4269. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  4270. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  4271. card->qdio.out_qs[i]->bufs[j]->buffer);
  4272. }
  4273. memset(&init_data, 0, sizeof(struct qdio_initialize));
  4274. init_data.cdev = CARD_DDEV(card);
  4275. init_data.q_format = qeth_get_qdio_q_format(card);
  4276. init_data.qib_param_field_format = 0;
  4277. init_data.qib_param_field = qib_param_field;
  4278. init_data.no_input_qs = card->qdio.no_in_queues;
  4279. init_data.no_output_qs = card->qdio.no_out_queues;
  4280. init_data.input_handler = card->discipline->input_handler;
  4281. init_data.output_handler = card->discipline->output_handler;
  4282. init_data.queue_start_poll_array = queue_start_poll;
  4283. init_data.int_parm = (unsigned long) card;
  4284. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  4285. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  4286. init_data.output_sbal_state_array = card->qdio.out_bufstates;
  4287. init_data.scan_threshold =
  4288. (card->info.type == QETH_CARD_TYPE_IQD) ? 1 : 32;
  4289. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  4290. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  4291. rc = qdio_allocate(&init_data);
  4292. if (rc) {
  4293. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4294. goto out;
  4295. }
  4296. rc = qdio_establish(&init_data);
  4297. if (rc) {
  4298. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4299. qdio_free(CARD_DDEV(card));
  4300. }
  4301. }
  4302. switch (card->options.cq) {
  4303. case QETH_CQ_ENABLED:
  4304. dev_info(&card->gdev->dev, "Completion Queue support enabled");
  4305. break;
  4306. case QETH_CQ_DISABLED:
  4307. dev_info(&card->gdev->dev, "Completion Queue support disabled");
  4308. break;
  4309. default:
  4310. break;
  4311. }
  4312. out:
  4313. kfree(out_sbal_ptrs);
  4314. out_free_queue_start_poll:
  4315. kfree(queue_start_poll);
  4316. out_free_in_sbals:
  4317. kfree(in_sbal_ptrs);
  4318. out_free_qib_param:
  4319. kfree(qib_param_field);
  4320. out_free_nothing:
  4321. return rc;
  4322. }
  4323. static void qeth_core_free_card(struct qeth_card *card)
  4324. {
  4325. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  4326. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  4327. qeth_clean_channel(&card->read);
  4328. qeth_clean_channel(&card->write);
  4329. if (card->dev)
  4330. free_netdev(card->dev);
  4331. kfree(card->ip_tbd_list);
  4332. qeth_free_qdio_buffers(card);
  4333. unregister_service_level(&card->qeth_service_level);
  4334. kfree(card);
  4335. }
  4336. void qeth_trace_features(struct qeth_card *card)
  4337. {
  4338. QETH_CARD_TEXT(card, 2, "features");
  4339. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa4.supported_funcs);
  4340. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa4.enabled_funcs);
  4341. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa6.supported_funcs);
  4342. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa6.enabled_funcs);
  4343. QETH_CARD_TEXT_(card, 2, "%x", card->options.adp.supported_funcs);
  4344. QETH_CARD_TEXT_(card, 2, "%x", card->options.adp.enabled_funcs);
  4345. QETH_CARD_TEXT_(card, 2, "%x", card->info.diagass_support);
  4346. }
  4347. EXPORT_SYMBOL_GPL(qeth_trace_features);
  4348. static struct ccw_device_id qeth_ids[] = {
  4349. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  4350. .driver_info = QETH_CARD_TYPE_OSD},
  4351. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  4352. .driver_info = QETH_CARD_TYPE_IQD},
  4353. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  4354. .driver_info = QETH_CARD_TYPE_OSN},
  4355. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  4356. .driver_info = QETH_CARD_TYPE_OSM},
  4357. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  4358. .driver_info = QETH_CARD_TYPE_OSX},
  4359. {},
  4360. };
  4361. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  4362. static struct ccw_driver qeth_ccw_driver = {
  4363. .driver = {
  4364. .owner = THIS_MODULE,
  4365. .name = "qeth",
  4366. },
  4367. .ids = qeth_ids,
  4368. .probe = ccwgroup_probe_ccwdev,
  4369. .remove = ccwgroup_remove_ccwdev,
  4370. };
  4371. int qeth_core_hardsetup_card(struct qeth_card *card)
  4372. {
  4373. int retries = 3;
  4374. int rc;
  4375. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  4376. atomic_set(&card->force_alloc_skb, 0);
  4377. qeth_update_from_chp_desc(card);
  4378. retry:
  4379. if (retries < 3)
  4380. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  4381. dev_name(&card->gdev->dev));
  4382. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  4383. ccw_device_set_offline(CARD_DDEV(card));
  4384. ccw_device_set_offline(CARD_WDEV(card));
  4385. ccw_device_set_offline(CARD_RDEV(card));
  4386. qdio_free(CARD_DDEV(card));
  4387. rc = ccw_device_set_online(CARD_RDEV(card));
  4388. if (rc)
  4389. goto retriable;
  4390. rc = ccw_device_set_online(CARD_WDEV(card));
  4391. if (rc)
  4392. goto retriable;
  4393. rc = ccw_device_set_online(CARD_DDEV(card));
  4394. if (rc)
  4395. goto retriable;
  4396. retriable:
  4397. if (rc == -ERESTARTSYS) {
  4398. QETH_DBF_TEXT(SETUP, 2, "break1");
  4399. return rc;
  4400. } else if (rc) {
  4401. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  4402. if (--retries < 0)
  4403. goto out;
  4404. else
  4405. goto retry;
  4406. }
  4407. qeth_determine_capabilities(card);
  4408. qeth_init_tokens(card);
  4409. qeth_init_func_level(card);
  4410. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  4411. if (rc == -ERESTARTSYS) {
  4412. QETH_DBF_TEXT(SETUP, 2, "break2");
  4413. return rc;
  4414. } else if (rc) {
  4415. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4416. if (--retries < 0)
  4417. goto out;
  4418. else
  4419. goto retry;
  4420. }
  4421. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  4422. if (rc == -ERESTARTSYS) {
  4423. QETH_DBF_TEXT(SETUP, 2, "break3");
  4424. return rc;
  4425. } else if (rc) {
  4426. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  4427. if (--retries < 0)
  4428. goto out;
  4429. else
  4430. goto retry;
  4431. }
  4432. card->read_or_write_problem = 0;
  4433. rc = qeth_mpc_initialize(card);
  4434. if (rc) {
  4435. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4436. goto out;
  4437. }
  4438. card->options.ipa4.supported_funcs = 0;
  4439. card->options.adp.supported_funcs = 0;
  4440. card->options.sbp.supported_funcs = 0;
  4441. card->info.diagass_support = 0;
  4442. qeth_query_ipassists(card, QETH_PROT_IPV4);
  4443. if (qeth_is_supported(card, IPA_SETADAPTERPARMS))
  4444. qeth_query_setadapterparms(card);
  4445. if (qeth_adp_supported(card, IPA_SETADP_SET_DIAG_ASSIST))
  4446. qeth_query_setdiagass(card);
  4447. return 0;
  4448. out:
  4449. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  4450. "an error on the device\n");
  4451. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  4452. dev_name(&card->gdev->dev), rc);
  4453. return rc;
  4454. }
  4455. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  4456. static inline int qeth_create_skb_frag(struct qeth_qdio_buffer *qethbuffer,
  4457. struct qdio_buffer_element *element,
  4458. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  4459. {
  4460. struct page *page = virt_to_page(element->addr);
  4461. if (*pskb == NULL) {
  4462. if (qethbuffer->rx_skb) {
  4463. /* only if qeth_card.options.cq == QETH_CQ_ENABLED */
  4464. *pskb = qethbuffer->rx_skb;
  4465. qethbuffer->rx_skb = NULL;
  4466. } else {
  4467. *pskb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  4468. if (!(*pskb))
  4469. return -ENOMEM;
  4470. }
  4471. skb_reserve(*pskb, ETH_HLEN);
  4472. if (data_len <= QETH_RX_PULL_LEN) {
  4473. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  4474. data_len);
  4475. } else {
  4476. get_page(page);
  4477. memcpy(skb_put(*pskb, QETH_RX_PULL_LEN),
  4478. element->addr + offset, QETH_RX_PULL_LEN);
  4479. skb_fill_page_desc(*pskb, *pfrag, page,
  4480. offset + QETH_RX_PULL_LEN,
  4481. data_len - QETH_RX_PULL_LEN);
  4482. (*pskb)->data_len += data_len - QETH_RX_PULL_LEN;
  4483. (*pskb)->len += data_len - QETH_RX_PULL_LEN;
  4484. (*pskb)->truesize += data_len - QETH_RX_PULL_LEN;
  4485. (*pfrag)++;
  4486. }
  4487. } else {
  4488. get_page(page);
  4489. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  4490. (*pskb)->data_len += data_len;
  4491. (*pskb)->len += data_len;
  4492. (*pskb)->truesize += data_len;
  4493. (*pfrag)++;
  4494. }
  4495. return 0;
  4496. }
  4497. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  4498. struct qeth_qdio_buffer *qethbuffer,
  4499. struct qdio_buffer_element **__element, int *__offset,
  4500. struct qeth_hdr **hdr)
  4501. {
  4502. struct qdio_buffer_element *element = *__element;
  4503. struct qdio_buffer *buffer = qethbuffer->buffer;
  4504. int offset = *__offset;
  4505. struct sk_buff *skb = NULL;
  4506. int skb_len = 0;
  4507. void *data_ptr;
  4508. int data_len;
  4509. int headroom = 0;
  4510. int use_rx_sg = 0;
  4511. int frag = 0;
  4512. /* qeth_hdr must not cross element boundaries */
  4513. if (element->length < offset + sizeof(struct qeth_hdr)) {
  4514. if (qeth_is_last_sbale(element))
  4515. return NULL;
  4516. element++;
  4517. offset = 0;
  4518. if (element->length < sizeof(struct qeth_hdr))
  4519. return NULL;
  4520. }
  4521. *hdr = element->addr + offset;
  4522. offset += sizeof(struct qeth_hdr);
  4523. switch ((*hdr)->hdr.l2.id) {
  4524. case QETH_HEADER_TYPE_LAYER2:
  4525. skb_len = (*hdr)->hdr.l2.pkt_length;
  4526. break;
  4527. case QETH_HEADER_TYPE_LAYER3:
  4528. skb_len = (*hdr)->hdr.l3.length;
  4529. headroom = ETH_HLEN;
  4530. break;
  4531. case QETH_HEADER_TYPE_OSN:
  4532. skb_len = (*hdr)->hdr.osn.pdu_length;
  4533. headroom = sizeof(struct qeth_hdr);
  4534. break;
  4535. default:
  4536. break;
  4537. }
  4538. if (!skb_len)
  4539. return NULL;
  4540. if (((skb_len >= card->options.rx_sg_cb) &&
  4541. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  4542. (!atomic_read(&card->force_alloc_skb))) ||
  4543. (card->options.cq == QETH_CQ_ENABLED)) {
  4544. use_rx_sg = 1;
  4545. } else {
  4546. skb = dev_alloc_skb(skb_len + headroom);
  4547. if (!skb)
  4548. goto no_mem;
  4549. if (headroom)
  4550. skb_reserve(skb, headroom);
  4551. }
  4552. data_ptr = element->addr + offset;
  4553. while (skb_len) {
  4554. data_len = min(skb_len, (int)(element->length - offset));
  4555. if (data_len) {
  4556. if (use_rx_sg) {
  4557. if (qeth_create_skb_frag(qethbuffer, element,
  4558. &skb, offset, &frag, data_len))
  4559. goto no_mem;
  4560. } else {
  4561. memcpy(skb_put(skb, data_len), data_ptr,
  4562. data_len);
  4563. }
  4564. }
  4565. skb_len -= data_len;
  4566. if (skb_len) {
  4567. if (qeth_is_last_sbale(element)) {
  4568. QETH_CARD_TEXT(card, 4, "unexeob");
  4569. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  4570. dev_kfree_skb_any(skb);
  4571. card->stats.rx_errors++;
  4572. return NULL;
  4573. }
  4574. element++;
  4575. offset = 0;
  4576. data_ptr = element->addr;
  4577. } else {
  4578. offset += data_len;
  4579. }
  4580. }
  4581. *__element = element;
  4582. *__offset = offset;
  4583. if (use_rx_sg && card->options.performance_stats) {
  4584. card->perf_stats.sg_skbs_rx++;
  4585. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  4586. }
  4587. return skb;
  4588. no_mem:
  4589. if (net_ratelimit()) {
  4590. QETH_CARD_TEXT(card, 2, "noskbmem");
  4591. }
  4592. card->stats.rx_dropped++;
  4593. return NULL;
  4594. }
  4595. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  4596. static void qeth_unregister_dbf_views(void)
  4597. {
  4598. int x;
  4599. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4600. debug_unregister(qeth_dbf[x].id);
  4601. qeth_dbf[x].id = NULL;
  4602. }
  4603. }
  4604. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  4605. {
  4606. char dbf_txt_buf[32];
  4607. va_list args;
  4608. if (!debug_level_enabled(id, level))
  4609. return;
  4610. va_start(args, fmt);
  4611. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  4612. va_end(args);
  4613. debug_text_event(id, level, dbf_txt_buf);
  4614. }
  4615. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  4616. static int qeth_register_dbf_views(void)
  4617. {
  4618. int ret;
  4619. int x;
  4620. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4621. /* register the areas */
  4622. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  4623. qeth_dbf[x].pages,
  4624. qeth_dbf[x].areas,
  4625. qeth_dbf[x].len);
  4626. if (qeth_dbf[x].id == NULL) {
  4627. qeth_unregister_dbf_views();
  4628. return -ENOMEM;
  4629. }
  4630. /* register a view */
  4631. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  4632. if (ret) {
  4633. qeth_unregister_dbf_views();
  4634. return ret;
  4635. }
  4636. /* set a passing level */
  4637. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  4638. }
  4639. return 0;
  4640. }
  4641. int qeth_core_load_discipline(struct qeth_card *card,
  4642. enum qeth_discipline_id discipline)
  4643. {
  4644. int rc = 0;
  4645. mutex_lock(&qeth_mod_mutex);
  4646. switch (discipline) {
  4647. case QETH_DISCIPLINE_LAYER3:
  4648. card->discipline = try_then_request_module(
  4649. symbol_get(qeth_l3_discipline), "qeth_l3");
  4650. break;
  4651. case QETH_DISCIPLINE_LAYER2:
  4652. card->discipline = try_then_request_module(
  4653. symbol_get(qeth_l2_discipline), "qeth_l2");
  4654. break;
  4655. }
  4656. if (!card->discipline) {
  4657. dev_err(&card->gdev->dev, "There is no kernel module to "
  4658. "support discipline %d\n", discipline);
  4659. rc = -EINVAL;
  4660. }
  4661. mutex_unlock(&qeth_mod_mutex);
  4662. return rc;
  4663. }
  4664. void qeth_core_free_discipline(struct qeth_card *card)
  4665. {
  4666. if (card->options.layer2)
  4667. symbol_put(qeth_l2_discipline);
  4668. else
  4669. symbol_put(qeth_l3_discipline);
  4670. card->discipline = NULL;
  4671. }
  4672. static const struct device_type qeth_generic_devtype = {
  4673. .name = "qeth_generic",
  4674. .groups = qeth_generic_attr_groups,
  4675. };
  4676. static const struct device_type qeth_osn_devtype = {
  4677. .name = "qeth_osn",
  4678. .groups = qeth_osn_attr_groups,
  4679. };
  4680. #define DBF_NAME_LEN 20
  4681. struct qeth_dbf_entry {
  4682. char dbf_name[DBF_NAME_LEN];
  4683. debug_info_t *dbf_info;
  4684. struct list_head dbf_list;
  4685. };
  4686. static LIST_HEAD(qeth_dbf_list);
  4687. static DEFINE_MUTEX(qeth_dbf_list_mutex);
  4688. static debug_info_t *qeth_get_dbf_entry(char *name)
  4689. {
  4690. struct qeth_dbf_entry *entry;
  4691. debug_info_t *rc = NULL;
  4692. mutex_lock(&qeth_dbf_list_mutex);
  4693. list_for_each_entry(entry, &qeth_dbf_list, dbf_list) {
  4694. if (strcmp(entry->dbf_name, name) == 0) {
  4695. rc = entry->dbf_info;
  4696. break;
  4697. }
  4698. }
  4699. mutex_unlock(&qeth_dbf_list_mutex);
  4700. return rc;
  4701. }
  4702. static int qeth_add_dbf_entry(struct qeth_card *card, char *name)
  4703. {
  4704. struct qeth_dbf_entry *new_entry;
  4705. card->debug = debug_register(name, 2, 1, 8);
  4706. if (!card->debug) {
  4707. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  4708. goto err;
  4709. }
  4710. if (debug_register_view(card->debug, &debug_hex_ascii_view))
  4711. goto err_dbg;
  4712. new_entry = kzalloc(sizeof(struct qeth_dbf_entry), GFP_KERNEL);
  4713. if (!new_entry)
  4714. goto err_dbg;
  4715. strncpy(new_entry->dbf_name, name, DBF_NAME_LEN);
  4716. new_entry->dbf_info = card->debug;
  4717. mutex_lock(&qeth_dbf_list_mutex);
  4718. list_add(&new_entry->dbf_list, &qeth_dbf_list);
  4719. mutex_unlock(&qeth_dbf_list_mutex);
  4720. return 0;
  4721. err_dbg:
  4722. debug_unregister(card->debug);
  4723. err:
  4724. return -ENOMEM;
  4725. }
  4726. static void qeth_clear_dbf_list(void)
  4727. {
  4728. struct qeth_dbf_entry *entry, *tmp;
  4729. mutex_lock(&qeth_dbf_list_mutex);
  4730. list_for_each_entry_safe(entry, tmp, &qeth_dbf_list, dbf_list) {
  4731. list_del(&entry->dbf_list);
  4732. debug_unregister(entry->dbf_info);
  4733. kfree(entry);
  4734. }
  4735. mutex_unlock(&qeth_dbf_list_mutex);
  4736. }
  4737. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  4738. {
  4739. struct qeth_card *card;
  4740. struct device *dev;
  4741. int rc;
  4742. unsigned long flags;
  4743. char dbf_name[DBF_NAME_LEN];
  4744. QETH_DBF_TEXT(SETUP, 2, "probedev");
  4745. dev = &gdev->dev;
  4746. if (!get_device(dev))
  4747. return -ENODEV;
  4748. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  4749. card = qeth_alloc_card();
  4750. if (!card) {
  4751. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  4752. rc = -ENOMEM;
  4753. goto err_dev;
  4754. }
  4755. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  4756. dev_name(&gdev->dev));
  4757. card->debug = qeth_get_dbf_entry(dbf_name);
  4758. if (!card->debug) {
  4759. rc = qeth_add_dbf_entry(card, dbf_name);
  4760. if (rc)
  4761. goto err_card;
  4762. }
  4763. card->read.ccwdev = gdev->cdev[0];
  4764. card->write.ccwdev = gdev->cdev[1];
  4765. card->data.ccwdev = gdev->cdev[2];
  4766. dev_set_drvdata(&gdev->dev, card);
  4767. card->gdev = gdev;
  4768. gdev->cdev[0]->handler = qeth_irq;
  4769. gdev->cdev[1]->handler = qeth_irq;
  4770. gdev->cdev[2]->handler = qeth_irq;
  4771. rc = qeth_determine_card_type(card);
  4772. if (rc) {
  4773. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4774. goto err_card;
  4775. }
  4776. rc = qeth_setup_card(card);
  4777. if (rc) {
  4778. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  4779. goto err_card;
  4780. }
  4781. if (card->info.type == QETH_CARD_TYPE_OSN)
  4782. gdev->dev.type = &qeth_osn_devtype;
  4783. else
  4784. gdev->dev.type = &qeth_generic_devtype;
  4785. switch (card->info.type) {
  4786. case QETH_CARD_TYPE_OSN:
  4787. case QETH_CARD_TYPE_OSM:
  4788. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  4789. if (rc)
  4790. goto err_card;
  4791. rc = card->discipline->setup(card->gdev);
  4792. if (rc)
  4793. goto err_disc;
  4794. case QETH_CARD_TYPE_OSD:
  4795. case QETH_CARD_TYPE_OSX:
  4796. default:
  4797. break;
  4798. }
  4799. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4800. list_add_tail(&card->list, &qeth_core_card_list.list);
  4801. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4802. qeth_determine_capabilities(card);
  4803. return 0;
  4804. err_disc:
  4805. qeth_core_free_discipline(card);
  4806. err_card:
  4807. qeth_core_free_card(card);
  4808. err_dev:
  4809. put_device(dev);
  4810. return rc;
  4811. }
  4812. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  4813. {
  4814. unsigned long flags;
  4815. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4816. QETH_DBF_TEXT(SETUP, 2, "removedv");
  4817. if (card->discipline) {
  4818. card->discipline->remove(gdev);
  4819. qeth_core_free_discipline(card);
  4820. }
  4821. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4822. list_del(&card->list);
  4823. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4824. qeth_core_free_card(card);
  4825. dev_set_drvdata(&gdev->dev, NULL);
  4826. put_device(&gdev->dev);
  4827. return;
  4828. }
  4829. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  4830. {
  4831. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4832. int rc = 0;
  4833. int def_discipline;
  4834. if (!card->discipline) {
  4835. if (card->info.type == QETH_CARD_TYPE_IQD)
  4836. def_discipline = QETH_DISCIPLINE_LAYER3;
  4837. else
  4838. def_discipline = QETH_DISCIPLINE_LAYER2;
  4839. rc = qeth_core_load_discipline(card, def_discipline);
  4840. if (rc)
  4841. goto err;
  4842. rc = card->discipline->setup(card->gdev);
  4843. if (rc)
  4844. goto err;
  4845. }
  4846. rc = card->discipline->set_online(gdev);
  4847. err:
  4848. return rc;
  4849. }
  4850. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  4851. {
  4852. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4853. return card->discipline->set_offline(gdev);
  4854. }
  4855. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  4856. {
  4857. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4858. if (card->discipline && card->discipline->shutdown)
  4859. card->discipline->shutdown(gdev);
  4860. }
  4861. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  4862. {
  4863. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4864. if (card->discipline && card->discipline->prepare)
  4865. return card->discipline->prepare(gdev);
  4866. return 0;
  4867. }
  4868. static void qeth_core_complete(struct ccwgroup_device *gdev)
  4869. {
  4870. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4871. if (card->discipline && card->discipline->complete)
  4872. card->discipline->complete(gdev);
  4873. }
  4874. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  4875. {
  4876. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4877. if (card->discipline && card->discipline->freeze)
  4878. return card->discipline->freeze(gdev);
  4879. return 0;
  4880. }
  4881. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  4882. {
  4883. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4884. if (card->discipline && card->discipline->thaw)
  4885. return card->discipline->thaw(gdev);
  4886. return 0;
  4887. }
  4888. static int qeth_core_restore(struct ccwgroup_device *gdev)
  4889. {
  4890. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4891. if (card->discipline && card->discipline->restore)
  4892. return card->discipline->restore(gdev);
  4893. return 0;
  4894. }
  4895. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4896. .driver = {
  4897. .owner = THIS_MODULE,
  4898. .name = "qeth",
  4899. },
  4900. .setup = qeth_core_probe_device,
  4901. .remove = qeth_core_remove_device,
  4902. .set_online = qeth_core_set_online,
  4903. .set_offline = qeth_core_set_offline,
  4904. .shutdown = qeth_core_shutdown,
  4905. .prepare = qeth_core_prepare,
  4906. .complete = qeth_core_complete,
  4907. .freeze = qeth_core_freeze,
  4908. .thaw = qeth_core_thaw,
  4909. .restore = qeth_core_restore,
  4910. };
  4911. static ssize_t qeth_core_driver_group_store(struct device_driver *ddrv,
  4912. const char *buf, size_t count)
  4913. {
  4914. int err;
  4915. err = ccwgroup_create_dev(qeth_core_root_dev,
  4916. &qeth_core_ccwgroup_driver, 3, buf);
  4917. return err ? err : count;
  4918. }
  4919. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4920. static struct attribute *qeth_drv_attrs[] = {
  4921. &driver_attr_group.attr,
  4922. NULL,
  4923. };
  4924. static struct attribute_group qeth_drv_attr_group = {
  4925. .attrs = qeth_drv_attrs,
  4926. };
  4927. static const struct attribute_group *qeth_drv_attr_groups[] = {
  4928. &qeth_drv_attr_group,
  4929. NULL,
  4930. };
  4931. static struct {
  4932. const char str[ETH_GSTRING_LEN];
  4933. } qeth_ethtool_stats_keys[] = {
  4934. /* 0 */{"rx skbs"},
  4935. {"rx buffers"},
  4936. {"tx skbs"},
  4937. {"tx buffers"},
  4938. {"tx skbs no packing"},
  4939. {"tx buffers no packing"},
  4940. {"tx skbs packing"},
  4941. {"tx buffers packing"},
  4942. {"tx sg skbs"},
  4943. {"tx sg frags"},
  4944. /* 10 */{"rx sg skbs"},
  4945. {"rx sg frags"},
  4946. {"rx sg page allocs"},
  4947. {"tx large kbytes"},
  4948. {"tx large count"},
  4949. {"tx pk state ch n->p"},
  4950. {"tx pk state ch p->n"},
  4951. {"tx pk watermark low"},
  4952. {"tx pk watermark high"},
  4953. {"queue 0 buffer usage"},
  4954. /* 20 */{"queue 1 buffer usage"},
  4955. {"queue 2 buffer usage"},
  4956. {"queue 3 buffer usage"},
  4957. {"rx poll time"},
  4958. {"rx poll count"},
  4959. {"rx do_QDIO time"},
  4960. {"rx do_QDIO count"},
  4961. {"tx handler time"},
  4962. {"tx handler count"},
  4963. {"tx time"},
  4964. /* 30 */{"tx count"},
  4965. {"tx do_QDIO time"},
  4966. {"tx do_QDIO count"},
  4967. {"tx csum"},
  4968. {"tx lin"},
  4969. {"cq handler count"},
  4970. {"cq handler time"}
  4971. };
  4972. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4973. {
  4974. switch (stringset) {
  4975. case ETH_SS_STATS:
  4976. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4977. default:
  4978. return -EINVAL;
  4979. }
  4980. }
  4981. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4982. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4983. struct ethtool_stats *stats, u64 *data)
  4984. {
  4985. struct qeth_card *card = dev->ml_priv;
  4986. data[0] = card->stats.rx_packets -
  4987. card->perf_stats.initial_rx_packets;
  4988. data[1] = card->perf_stats.bufs_rec;
  4989. data[2] = card->stats.tx_packets -
  4990. card->perf_stats.initial_tx_packets;
  4991. data[3] = card->perf_stats.bufs_sent;
  4992. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4993. - card->perf_stats.skbs_sent_pack;
  4994. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4995. data[6] = card->perf_stats.skbs_sent_pack;
  4996. data[7] = card->perf_stats.bufs_sent_pack;
  4997. data[8] = card->perf_stats.sg_skbs_sent;
  4998. data[9] = card->perf_stats.sg_frags_sent;
  4999. data[10] = card->perf_stats.sg_skbs_rx;
  5000. data[11] = card->perf_stats.sg_frags_rx;
  5001. data[12] = card->perf_stats.sg_alloc_page_rx;
  5002. data[13] = (card->perf_stats.large_send_bytes >> 10);
  5003. data[14] = card->perf_stats.large_send_cnt;
  5004. data[15] = card->perf_stats.sc_dp_p;
  5005. data[16] = card->perf_stats.sc_p_dp;
  5006. data[17] = QETH_LOW_WATERMARK_PACK;
  5007. data[18] = QETH_HIGH_WATERMARK_PACK;
  5008. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  5009. data[20] = (card->qdio.no_out_queues > 1) ?
  5010. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  5011. data[21] = (card->qdio.no_out_queues > 2) ?
  5012. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  5013. data[22] = (card->qdio.no_out_queues > 3) ?
  5014. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  5015. data[23] = card->perf_stats.inbound_time;
  5016. data[24] = card->perf_stats.inbound_cnt;
  5017. data[25] = card->perf_stats.inbound_do_qdio_time;
  5018. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  5019. data[27] = card->perf_stats.outbound_handler_time;
  5020. data[28] = card->perf_stats.outbound_handler_cnt;
  5021. data[29] = card->perf_stats.outbound_time;
  5022. data[30] = card->perf_stats.outbound_cnt;
  5023. data[31] = card->perf_stats.outbound_do_qdio_time;
  5024. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  5025. data[33] = card->perf_stats.tx_csum;
  5026. data[34] = card->perf_stats.tx_lin;
  5027. data[35] = card->perf_stats.cq_cnt;
  5028. data[36] = card->perf_stats.cq_time;
  5029. }
  5030. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  5031. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  5032. {
  5033. switch (stringset) {
  5034. case ETH_SS_STATS:
  5035. memcpy(data, &qeth_ethtool_stats_keys,
  5036. sizeof(qeth_ethtool_stats_keys));
  5037. break;
  5038. default:
  5039. WARN_ON(1);
  5040. break;
  5041. }
  5042. }
  5043. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  5044. void qeth_core_get_drvinfo(struct net_device *dev,
  5045. struct ethtool_drvinfo *info)
  5046. {
  5047. struct qeth_card *card = dev->ml_priv;
  5048. strlcpy(info->driver, card->options.layer2 ? "qeth_l2" : "qeth_l3",
  5049. sizeof(info->driver));
  5050. strlcpy(info->version, "1.0", sizeof(info->version));
  5051. strlcpy(info->fw_version, card->info.mcl_level,
  5052. sizeof(info->fw_version));
  5053. snprintf(info->bus_info, sizeof(info->bus_info), "%s/%s/%s",
  5054. CARD_RDEV_ID(card), CARD_WDEV_ID(card), CARD_DDEV_ID(card));
  5055. }
  5056. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  5057. /* Helper function to fill 'advertizing' and 'supported' which are the same. */
  5058. /* Autoneg and full-duplex are supported and advertized uncondionally. */
  5059. /* Always advertize and support all speeds up to specified, and only one */
  5060. /* specified port type. */
  5061. static void qeth_set_ecmd_adv_sup(struct ethtool_cmd *ecmd,
  5062. int maxspeed, int porttype)
  5063. {
  5064. int port_sup, port_adv, spd_sup, spd_adv;
  5065. switch (porttype) {
  5066. case PORT_TP:
  5067. port_sup = SUPPORTED_TP;
  5068. port_adv = ADVERTISED_TP;
  5069. break;
  5070. case PORT_FIBRE:
  5071. port_sup = SUPPORTED_FIBRE;
  5072. port_adv = ADVERTISED_FIBRE;
  5073. break;
  5074. default:
  5075. port_sup = SUPPORTED_TP;
  5076. port_adv = ADVERTISED_TP;
  5077. WARN_ON_ONCE(1);
  5078. }
  5079. /* "Fallthrough" case'es ordered from high to low result in setting */
  5080. /* flags cumulatively, starting from the specified speed and down to */
  5081. /* the lowest possible. */
  5082. spd_sup = 0;
  5083. spd_adv = 0;
  5084. switch (maxspeed) {
  5085. case SPEED_10000:
  5086. spd_sup |= SUPPORTED_10000baseT_Full;
  5087. spd_adv |= ADVERTISED_10000baseT_Full;
  5088. case SPEED_1000:
  5089. spd_sup |= SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full;
  5090. spd_adv |= ADVERTISED_1000baseT_Half |
  5091. ADVERTISED_1000baseT_Full;
  5092. case SPEED_100:
  5093. spd_sup |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
  5094. spd_adv |= ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
  5095. case SPEED_10:
  5096. spd_sup |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
  5097. spd_adv |= ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
  5098. break;
  5099. default:
  5100. spd_sup = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
  5101. spd_adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
  5102. WARN_ON_ONCE(1);
  5103. }
  5104. ecmd->advertising = ADVERTISED_Autoneg | port_adv | spd_adv;
  5105. ecmd->supported = SUPPORTED_Autoneg | port_sup | spd_sup;
  5106. }
  5107. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  5108. struct ethtool_cmd *ecmd)
  5109. {
  5110. struct qeth_card *card = netdev->ml_priv;
  5111. enum qeth_link_types link_type;
  5112. struct carrier_info carrier_info;
  5113. u32 speed;
  5114. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  5115. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  5116. else
  5117. link_type = card->info.link_type;
  5118. ecmd->transceiver = XCVR_INTERNAL;
  5119. ecmd->duplex = DUPLEX_FULL;
  5120. ecmd->autoneg = AUTONEG_ENABLE;
  5121. switch (link_type) {
  5122. case QETH_LINK_TYPE_FAST_ETH:
  5123. case QETH_LINK_TYPE_LANE_ETH100:
  5124. qeth_set_ecmd_adv_sup(ecmd, SPEED_100, PORT_TP);
  5125. speed = SPEED_100;
  5126. ecmd->port = PORT_TP;
  5127. break;
  5128. case QETH_LINK_TYPE_GBIT_ETH:
  5129. case QETH_LINK_TYPE_LANE_ETH1000:
  5130. qeth_set_ecmd_adv_sup(ecmd, SPEED_1000, PORT_FIBRE);
  5131. speed = SPEED_1000;
  5132. ecmd->port = PORT_FIBRE;
  5133. break;
  5134. case QETH_LINK_TYPE_10GBIT_ETH:
  5135. qeth_set_ecmd_adv_sup(ecmd, SPEED_10000, PORT_FIBRE);
  5136. speed = SPEED_10000;
  5137. ecmd->port = PORT_FIBRE;
  5138. break;
  5139. default:
  5140. qeth_set_ecmd_adv_sup(ecmd, SPEED_10, PORT_TP);
  5141. speed = SPEED_10;
  5142. ecmd->port = PORT_TP;
  5143. }
  5144. ethtool_cmd_speed_set(ecmd, speed);
  5145. /* Check if we can obtain more accurate information. */
  5146. /* If QUERY_CARD_INFO command is not supported or fails, */
  5147. /* just return the heuristics that was filled above. */
  5148. if (qeth_query_card_info(card, &carrier_info) != 0)
  5149. return 0;
  5150. netdev_dbg(netdev,
  5151. "card info: card_type=0x%02x, port_mode=0x%04x, port_speed=0x%08x\n",
  5152. carrier_info.card_type,
  5153. carrier_info.port_mode,
  5154. carrier_info.port_speed);
  5155. /* Update attributes for which we've obtained more authoritative */
  5156. /* information, leave the rest the way they where filled above. */
  5157. switch (carrier_info.card_type) {
  5158. case CARD_INFO_TYPE_1G_COPPER_A:
  5159. case CARD_INFO_TYPE_1G_COPPER_B:
  5160. qeth_set_ecmd_adv_sup(ecmd, SPEED_1000, PORT_TP);
  5161. ecmd->port = PORT_TP;
  5162. break;
  5163. case CARD_INFO_TYPE_1G_FIBRE_A:
  5164. case CARD_INFO_TYPE_1G_FIBRE_B:
  5165. qeth_set_ecmd_adv_sup(ecmd, SPEED_1000, PORT_FIBRE);
  5166. ecmd->port = PORT_FIBRE;
  5167. break;
  5168. case CARD_INFO_TYPE_10G_FIBRE_A:
  5169. case CARD_INFO_TYPE_10G_FIBRE_B:
  5170. qeth_set_ecmd_adv_sup(ecmd, SPEED_10000, PORT_FIBRE);
  5171. ecmd->port = PORT_FIBRE;
  5172. break;
  5173. }
  5174. switch (carrier_info.port_mode) {
  5175. case CARD_INFO_PORTM_FULLDUPLEX:
  5176. ecmd->duplex = DUPLEX_FULL;
  5177. break;
  5178. case CARD_INFO_PORTM_HALFDUPLEX:
  5179. ecmd->duplex = DUPLEX_HALF;
  5180. break;
  5181. }
  5182. switch (carrier_info.port_speed) {
  5183. case CARD_INFO_PORTS_10M:
  5184. speed = SPEED_10;
  5185. break;
  5186. case CARD_INFO_PORTS_100M:
  5187. speed = SPEED_100;
  5188. break;
  5189. case CARD_INFO_PORTS_1G:
  5190. speed = SPEED_1000;
  5191. break;
  5192. case CARD_INFO_PORTS_10G:
  5193. speed = SPEED_10000;
  5194. break;
  5195. }
  5196. ethtool_cmd_speed_set(ecmd, speed);
  5197. return 0;
  5198. }
  5199. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  5200. static int __init qeth_core_init(void)
  5201. {
  5202. int rc;
  5203. pr_info("loading core functions\n");
  5204. INIT_LIST_HEAD(&qeth_core_card_list.list);
  5205. INIT_LIST_HEAD(&qeth_dbf_list);
  5206. rwlock_init(&qeth_core_card_list.rwlock);
  5207. mutex_init(&qeth_mod_mutex);
  5208. qeth_wq = create_singlethread_workqueue("qeth_wq");
  5209. rc = qeth_register_dbf_views();
  5210. if (rc)
  5211. goto out_err;
  5212. qeth_core_root_dev = root_device_register("qeth");
  5213. rc = PTR_ERR_OR_ZERO(qeth_core_root_dev);
  5214. if (rc)
  5215. goto register_err;
  5216. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  5217. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  5218. if (!qeth_core_header_cache) {
  5219. rc = -ENOMEM;
  5220. goto slab_err;
  5221. }
  5222. qeth_qdio_outbuf_cache = kmem_cache_create("qeth_buf",
  5223. sizeof(struct qeth_qdio_out_buffer), 0, 0, NULL);
  5224. if (!qeth_qdio_outbuf_cache) {
  5225. rc = -ENOMEM;
  5226. goto cqslab_err;
  5227. }
  5228. rc = ccw_driver_register(&qeth_ccw_driver);
  5229. if (rc)
  5230. goto ccw_err;
  5231. qeth_core_ccwgroup_driver.driver.groups = qeth_drv_attr_groups;
  5232. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  5233. if (rc)
  5234. goto ccwgroup_err;
  5235. return 0;
  5236. ccwgroup_err:
  5237. ccw_driver_unregister(&qeth_ccw_driver);
  5238. ccw_err:
  5239. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  5240. cqslab_err:
  5241. kmem_cache_destroy(qeth_core_header_cache);
  5242. slab_err:
  5243. root_device_unregister(qeth_core_root_dev);
  5244. register_err:
  5245. qeth_unregister_dbf_views();
  5246. out_err:
  5247. pr_err("Initializing the qeth device driver failed\n");
  5248. return rc;
  5249. }
  5250. static void __exit qeth_core_exit(void)
  5251. {
  5252. qeth_clear_dbf_list();
  5253. destroy_workqueue(qeth_wq);
  5254. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  5255. ccw_driver_unregister(&qeth_ccw_driver);
  5256. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  5257. kmem_cache_destroy(qeth_core_header_cache);
  5258. root_device_unregister(qeth_core_root_dev);
  5259. qeth_unregister_dbf_views();
  5260. pr_info("core functions removed\n");
  5261. }
  5262. module_init(qeth_core_init);
  5263. module_exit(qeth_core_exit);
  5264. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  5265. MODULE_DESCRIPTION("qeth core functions");
  5266. MODULE_LICENSE("GPL");