rtc-ds1307.c 32 KB

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  1. /*
  2. * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
  3. *
  4. * Copyright (C) 2005 James Chapman (ds1337 core)
  5. * Copyright (C) 2006 David Brownell
  6. * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
  7. * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/slab.h>
  16. #include <linux/i2c.h>
  17. #include <linux/string.h>
  18. #include <linux/rtc.h>
  19. #include <linux/bcd.h>
  20. #include <linux/rtc/ds1307.h>
  21. /*
  22. * We can't determine type by probing, but if we expect pre-Linux code
  23. * to have set the chip up as a clock (turning on the oscillator and
  24. * setting the date and time), Linux can ignore the non-clock features.
  25. * That's a natural job for a factory or repair bench.
  26. */
  27. enum ds_type {
  28. ds_1307,
  29. ds_1337,
  30. ds_1338,
  31. ds_1339,
  32. ds_1340,
  33. ds_1388,
  34. ds_3231,
  35. m41t00,
  36. mcp7941x,
  37. rx_8025,
  38. last_ds_type /* always last */
  39. /* rs5c372 too? different address... */
  40. };
  41. /* RTC registers don't differ much, except for the century flag */
  42. #define DS1307_REG_SECS 0x00 /* 00-59 */
  43. # define DS1307_BIT_CH 0x80
  44. # define DS1340_BIT_nEOSC 0x80
  45. # define MCP7941X_BIT_ST 0x80
  46. #define DS1307_REG_MIN 0x01 /* 00-59 */
  47. #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
  48. # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
  49. # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
  50. # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
  51. # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
  52. #define DS1307_REG_WDAY 0x03 /* 01-07 */
  53. # define MCP7941X_BIT_VBATEN 0x08
  54. #define DS1307_REG_MDAY 0x04 /* 01-31 */
  55. #define DS1307_REG_MONTH 0x05 /* 01-12 */
  56. # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
  57. #define DS1307_REG_YEAR 0x06 /* 00-99 */
  58. /*
  59. * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
  60. * start at 7, and they differ a LOT. Only control and status matter for
  61. * basic RTC date and time functionality; be careful using them.
  62. */
  63. #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
  64. # define DS1307_BIT_OUT 0x80
  65. # define DS1338_BIT_OSF 0x20
  66. # define DS1307_BIT_SQWE 0x10
  67. # define DS1307_BIT_RS1 0x02
  68. # define DS1307_BIT_RS0 0x01
  69. #define DS1337_REG_CONTROL 0x0e
  70. # define DS1337_BIT_nEOSC 0x80
  71. # define DS1339_BIT_BBSQI 0x20
  72. # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
  73. # define DS1337_BIT_RS2 0x10
  74. # define DS1337_BIT_RS1 0x08
  75. # define DS1337_BIT_INTCN 0x04
  76. # define DS1337_BIT_A2IE 0x02
  77. # define DS1337_BIT_A1IE 0x01
  78. #define DS1340_REG_CONTROL 0x07
  79. # define DS1340_BIT_OUT 0x80
  80. # define DS1340_BIT_FT 0x40
  81. # define DS1340_BIT_CALIB_SIGN 0x20
  82. # define DS1340_M_CALIBRATION 0x1f
  83. #define DS1340_REG_FLAG 0x09
  84. # define DS1340_BIT_OSF 0x80
  85. #define DS1337_REG_STATUS 0x0f
  86. # define DS1337_BIT_OSF 0x80
  87. # define DS1337_BIT_A2I 0x02
  88. # define DS1337_BIT_A1I 0x01
  89. #define DS1339_REG_ALARM1_SECS 0x07
  90. #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
  91. #define RX8025_REG_CTRL1 0x0e
  92. # define RX8025_BIT_2412 0x20
  93. #define RX8025_REG_CTRL2 0x0f
  94. # define RX8025_BIT_PON 0x10
  95. # define RX8025_BIT_VDET 0x40
  96. # define RX8025_BIT_XST 0x20
  97. struct ds1307 {
  98. u8 offset; /* register's offset */
  99. u8 regs[11];
  100. u16 nvram_offset;
  101. struct bin_attribute *nvram;
  102. enum ds_type type;
  103. unsigned long flags;
  104. #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
  105. #define HAS_ALARM 1 /* bit 1 == irq claimed */
  106. struct i2c_client *client;
  107. struct rtc_device *rtc;
  108. struct work_struct work;
  109. s32 (*read_block_data)(const struct i2c_client *client, u8 command,
  110. u8 length, u8 *values);
  111. s32 (*write_block_data)(const struct i2c_client *client, u8 command,
  112. u8 length, const u8 *values);
  113. };
  114. struct chip_desc {
  115. unsigned alarm:1;
  116. u16 nvram_offset;
  117. u16 nvram_size;
  118. u16 trickle_charger_reg;
  119. };
  120. static const struct chip_desc chips[last_ds_type] = {
  121. [ds_1307] = {
  122. .nvram_offset = 8,
  123. .nvram_size = 56,
  124. },
  125. [ds_1337] = {
  126. .alarm = 1,
  127. },
  128. [ds_1338] = {
  129. .nvram_offset = 8,
  130. .nvram_size = 56,
  131. },
  132. [ds_1339] = {
  133. .alarm = 1,
  134. .trickle_charger_reg = 0x10,
  135. },
  136. [ds_1340] = {
  137. .trickle_charger_reg = 0x08,
  138. },
  139. [ds_1388] = {
  140. .trickle_charger_reg = 0x0a,
  141. },
  142. [ds_3231] = {
  143. .alarm = 1,
  144. },
  145. [mcp7941x] = {
  146. .alarm = 1,
  147. /* this is battery backed SRAM */
  148. .nvram_offset = 0x20,
  149. .nvram_size = 0x40,
  150. },
  151. };
  152. static const struct i2c_device_id ds1307_id[] = {
  153. { "ds1307", ds_1307 },
  154. { "ds1337", ds_1337 },
  155. { "ds1338", ds_1338 },
  156. { "ds1339", ds_1339 },
  157. { "ds1388", ds_1388 },
  158. { "ds1340", ds_1340 },
  159. { "ds3231", ds_3231 },
  160. { "m41t00", m41t00 },
  161. { "mcp7941x", mcp7941x },
  162. { "pt7c4338", ds_1307 },
  163. { "rx8025", rx_8025 },
  164. { }
  165. };
  166. MODULE_DEVICE_TABLE(i2c, ds1307_id);
  167. /*----------------------------------------------------------------------*/
  168. #define BLOCK_DATA_MAX_TRIES 10
  169. static s32 ds1307_read_block_data_once(const struct i2c_client *client,
  170. u8 command, u8 length, u8 *values)
  171. {
  172. s32 i, data;
  173. for (i = 0; i < length; i++) {
  174. data = i2c_smbus_read_byte_data(client, command + i);
  175. if (data < 0)
  176. return data;
  177. values[i] = data;
  178. }
  179. return i;
  180. }
  181. static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
  182. u8 length, u8 *values)
  183. {
  184. u8 oldvalues[255];
  185. s32 ret;
  186. int tries = 0;
  187. dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
  188. ret = ds1307_read_block_data_once(client, command, length, values);
  189. if (ret < 0)
  190. return ret;
  191. do {
  192. if (++tries > BLOCK_DATA_MAX_TRIES) {
  193. dev_err(&client->dev,
  194. "ds1307_read_block_data failed\n");
  195. return -EIO;
  196. }
  197. memcpy(oldvalues, values, length);
  198. ret = ds1307_read_block_data_once(client, command, length,
  199. values);
  200. if (ret < 0)
  201. return ret;
  202. } while (memcmp(oldvalues, values, length));
  203. return length;
  204. }
  205. static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
  206. u8 length, const u8 *values)
  207. {
  208. u8 currvalues[255];
  209. int tries = 0;
  210. dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
  211. do {
  212. s32 i, ret;
  213. if (++tries > BLOCK_DATA_MAX_TRIES) {
  214. dev_err(&client->dev,
  215. "ds1307_write_block_data failed\n");
  216. return -EIO;
  217. }
  218. for (i = 0; i < length; i++) {
  219. ret = i2c_smbus_write_byte_data(client, command + i,
  220. values[i]);
  221. if (ret < 0)
  222. return ret;
  223. }
  224. ret = ds1307_read_block_data_once(client, command, length,
  225. currvalues);
  226. if (ret < 0)
  227. return ret;
  228. } while (memcmp(currvalues, values, length));
  229. return length;
  230. }
  231. /*----------------------------------------------------------------------*/
  232. /* These RTC devices are not designed to be connected to a SMbus adapter.
  233. SMbus limits block operations length to 32 bytes, whereas it's not
  234. limited on I2C buses. As a result, accesses may exceed 32 bytes;
  235. in that case, split them into smaller blocks */
  236. static s32 ds1307_native_smbus_write_block_data(const struct i2c_client *client,
  237. u8 command, u8 length, const u8 *values)
  238. {
  239. u8 suboffset = 0;
  240. if (length <= I2C_SMBUS_BLOCK_MAX)
  241. return i2c_smbus_write_i2c_block_data(client,
  242. command, length, values);
  243. while (suboffset < length) {
  244. s32 retval = i2c_smbus_write_i2c_block_data(client,
  245. command + suboffset,
  246. min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
  247. values + suboffset);
  248. if (retval < 0)
  249. return retval;
  250. suboffset += I2C_SMBUS_BLOCK_MAX;
  251. }
  252. return length;
  253. }
  254. static s32 ds1307_native_smbus_read_block_data(const struct i2c_client *client,
  255. u8 command, u8 length, u8 *values)
  256. {
  257. u8 suboffset = 0;
  258. if (length <= I2C_SMBUS_BLOCK_MAX)
  259. return i2c_smbus_read_i2c_block_data(client,
  260. command, length, values);
  261. while (suboffset < length) {
  262. s32 retval = i2c_smbus_read_i2c_block_data(client,
  263. command + suboffset,
  264. min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
  265. values + suboffset);
  266. if (retval < 0)
  267. return retval;
  268. suboffset += I2C_SMBUS_BLOCK_MAX;
  269. }
  270. return length;
  271. }
  272. /*----------------------------------------------------------------------*/
  273. /*
  274. * The IRQ logic includes a "real" handler running in IRQ context just
  275. * long enough to schedule this workqueue entry. We need a task context
  276. * to talk to the RTC, since I2C I/O calls require that; and disable the
  277. * IRQ until we clear its status on the chip, so that this handler can
  278. * work with any type of triggering (not just falling edge).
  279. *
  280. * The ds1337 and ds1339 both have two alarms, but we only use the first
  281. * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
  282. * signal; ds1339 chips have only one alarm signal.
  283. */
  284. static void ds1307_work(struct work_struct *work)
  285. {
  286. struct ds1307 *ds1307;
  287. struct i2c_client *client;
  288. struct mutex *lock;
  289. int stat, control;
  290. ds1307 = container_of(work, struct ds1307, work);
  291. client = ds1307->client;
  292. lock = &ds1307->rtc->ops_lock;
  293. mutex_lock(lock);
  294. stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
  295. if (stat < 0)
  296. goto out;
  297. if (stat & DS1337_BIT_A1I) {
  298. stat &= ~DS1337_BIT_A1I;
  299. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
  300. control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  301. if (control < 0)
  302. goto out;
  303. control &= ~DS1337_BIT_A1IE;
  304. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
  305. rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
  306. }
  307. out:
  308. if (test_bit(HAS_ALARM, &ds1307->flags))
  309. enable_irq(client->irq);
  310. mutex_unlock(lock);
  311. }
  312. static irqreturn_t ds1307_irq(int irq, void *dev_id)
  313. {
  314. struct i2c_client *client = dev_id;
  315. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  316. disable_irq_nosync(irq);
  317. schedule_work(&ds1307->work);
  318. return IRQ_HANDLED;
  319. }
  320. /*----------------------------------------------------------------------*/
  321. static int ds1307_get_time(struct device *dev, struct rtc_time *t)
  322. {
  323. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  324. int tmp;
  325. /* read the RTC date and time registers all at once */
  326. tmp = ds1307->read_block_data(ds1307->client,
  327. ds1307->offset, 7, ds1307->regs);
  328. if (tmp != 7) {
  329. dev_err(dev, "%s error %d\n", "read", tmp);
  330. return -EIO;
  331. }
  332. dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
  333. t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
  334. t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
  335. tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
  336. t->tm_hour = bcd2bin(tmp);
  337. t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
  338. t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
  339. tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
  340. t->tm_mon = bcd2bin(tmp) - 1;
  341. /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
  342. t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
  343. dev_dbg(dev, "%s secs=%d, mins=%d, "
  344. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  345. "read", t->tm_sec, t->tm_min,
  346. t->tm_hour, t->tm_mday,
  347. t->tm_mon, t->tm_year, t->tm_wday);
  348. /* initial clock setting can be undefined */
  349. return rtc_valid_tm(t);
  350. }
  351. static int ds1307_set_time(struct device *dev, struct rtc_time *t)
  352. {
  353. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  354. int result;
  355. int tmp;
  356. u8 *buf = ds1307->regs;
  357. dev_dbg(dev, "%s secs=%d, mins=%d, "
  358. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  359. "write", t->tm_sec, t->tm_min,
  360. t->tm_hour, t->tm_mday,
  361. t->tm_mon, t->tm_year, t->tm_wday);
  362. buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
  363. buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
  364. buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
  365. buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
  366. buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
  367. buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
  368. /* assume 20YY not 19YY */
  369. tmp = t->tm_year - 100;
  370. buf[DS1307_REG_YEAR] = bin2bcd(tmp);
  371. switch (ds1307->type) {
  372. case ds_1337:
  373. case ds_1339:
  374. case ds_3231:
  375. buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
  376. break;
  377. case ds_1340:
  378. buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
  379. | DS1340_BIT_CENTURY;
  380. break;
  381. case mcp7941x:
  382. /*
  383. * these bits were cleared when preparing the date/time
  384. * values and need to be set again before writing the
  385. * buffer out to the device.
  386. */
  387. buf[DS1307_REG_SECS] |= MCP7941X_BIT_ST;
  388. buf[DS1307_REG_WDAY] |= MCP7941X_BIT_VBATEN;
  389. break;
  390. default:
  391. break;
  392. }
  393. dev_dbg(dev, "%s: %7ph\n", "write", buf);
  394. result = ds1307->write_block_data(ds1307->client,
  395. ds1307->offset, 7, buf);
  396. if (result < 0) {
  397. dev_err(dev, "%s error %d\n", "write", result);
  398. return result;
  399. }
  400. return 0;
  401. }
  402. static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
  403. {
  404. struct i2c_client *client = to_i2c_client(dev);
  405. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  406. int ret;
  407. if (!test_bit(HAS_ALARM, &ds1307->flags))
  408. return -EINVAL;
  409. /* read all ALARM1, ALARM2, and status registers at once */
  410. ret = ds1307->read_block_data(client,
  411. DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
  412. if (ret != 9) {
  413. dev_err(dev, "%s error %d\n", "alarm read", ret);
  414. return -EIO;
  415. }
  416. dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
  417. "alarm read",
  418. ds1307->regs[0], ds1307->regs[1],
  419. ds1307->regs[2], ds1307->regs[3],
  420. ds1307->regs[4], ds1307->regs[5],
  421. ds1307->regs[6], ds1307->regs[7],
  422. ds1307->regs[8]);
  423. /*
  424. * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
  425. * and that all four fields are checked matches
  426. */
  427. t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
  428. t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
  429. t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
  430. t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
  431. t->time.tm_mon = -1;
  432. t->time.tm_year = -1;
  433. t->time.tm_wday = -1;
  434. t->time.tm_yday = -1;
  435. t->time.tm_isdst = -1;
  436. /* ... and status */
  437. t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
  438. t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
  439. dev_dbg(dev, "%s secs=%d, mins=%d, "
  440. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  441. "alarm read", t->time.tm_sec, t->time.tm_min,
  442. t->time.tm_hour, t->time.tm_mday,
  443. t->enabled, t->pending);
  444. return 0;
  445. }
  446. static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
  447. {
  448. struct i2c_client *client = to_i2c_client(dev);
  449. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  450. unsigned char *buf = ds1307->regs;
  451. u8 control, status;
  452. int ret;
  453. if (!test_bit(HAS_ALARM, &ds1307->flags))
  454. return -EINVAL;
  455. dev_dbg(dev, "%s secs=%d, mins=%d, "
  456. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  457. "alarm set", t->time.tm_sec, t->time.tm_min,
  458. t->time.tm_hour, t->time.tm_mday,
  459. t->enabled, t->pending);
  460. /* read current status of both alarms and the chip */
  461. ret = ds1307->read_block_data(client,
  462. DS1339_REG_ALARM1_SECS, 9, buf);
  463. if (ret != 9) {
  464. dev_err(dev, "%s error %d\n", "alarm write", ret);
  465. return -EIO;
  466. }
  467. control = ds1307->regs[7];
  468. status = ds1307->regs[8];
  469. dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
  470. "alarm set (old status)",
  471. ds1307->regs[0], ds1307->regs[1],
  472. ds1307->regs[2], ds1307->regs[3],
  473. ds1307->regs[4], ds1307->regs[5],
  474. ds1307->regs[6], control, status);
  475. /* set ALARM1, using 24 hour and day-of-month modes */
  476. buf[0] = bin2bcd(t->time.tm_sec);
  477. buf[1] = bin2bcd(t->time.tm_min);
  478. buf[2] = bin2bcd(t->time.tm_hour);
  479. buf[3] = bin2bcd(t->time.tm_mday);
  480. /* set ALARM2 to non-garbage */
  481. buf[4] = 0;
  482. buf[5] = 0;
  483. buf[6] = 0;
  484. /* optionally enable ALARM1 */
  485. buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
  486. if (t->enabled) {
  487. dev_dbg(dev, "alarm IRQ armed\n");
  488. buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
  489. }
  490. buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
  491. ret = ds1307->write_block_data(client,
  492. DS1339_REG_ALARM1_SECS, 9, buf);
  493. if (ret < 0) {
  494. dev_err(dev, "can't set alarm time\n");
  495. return ret;
  496. }
  497. return 0;
  498. }
  499. static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
  500. {
  501. struct i2c_client *client = to_i2c_client(dev);
  502. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  503. int ret;
  504. if (!test_bit(HAS_ALARM, &ds1307->flags))
  505. return -ENOTTY;
  506. ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  507. if (ret < 0)
  508. return ret;
  509. if (enabled)
  510. ret |= DS1337_BIT_A1IE;
  511. else
  512. ret &= ~DS1337_BIT_A1IE;
  513. ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
  514. if (ret < 0)
  515. return ret;
  516. return 0;
  517. }
  518. static const struct rtc_class_ops ds13xx_rtc_ops = {
  519. .read_time = ds1307_get_time,
  520. .set_time = ds1307_set_time,
  521. .read_alarm = ds1337_read_alarm,
  522. .set_alarm = ds1337_set_alarm,
  523. .alarm_irq_enable = ds1307_alarm_irq_enable,
  524. };
  525. /*----------------------------------------------------------------------*/
  526. /*
  527. * Alarm support for mcp7941x devices.
  528. */
  529. #define MCP7941X_REG_CONTROL 0x07
  530. # define MCP7941X_BIT_ALM0_EN 0x10
  531. # define MCP7941X_BIT_ALM1_EN 0x20
  532. #define MCP7941X_REG_ALARM0_BASE 0x0a
  533. #define MCP7941X_REG_ALARM0_CTRL 0x0d
  534. #define MCP7941X_REG_ALARM1_BASE 0x11
  535. #define MCP7941X_REG_ALARM1_CTRL 0x14
  536. # define MCP7941X_BIT_ALMX_IF (1 << 3)
  537. # define MCP7941X_BIT_ALMX_C0 (1 << 4)
  538. # define MCP7941X_BIT_ALMX_C1 (1 << 5)
  539. # define MCP7941X_BIT_ALMX_C2 (1 << 6)
  540. # define MCP7941X_BIT_ALMX_POL (1 << 7)
  541. # define MCP7941X_MSK_ALMX_MATCH (MCP7941X_BIT_ALMX_C0 | \
  542. MCP7941X_BIT_ALMX_C1 | \
  543. MCP7941X_BIT_ALMX_C2)
  544. static void mcp7941x_work(struct work_struct *work)
  545. {
  546. struct ds1307 *ds1307 = container_of(work, struct ds1307, work);
  547. struct i2c_client *client = ds1307->client;
  548. int reg, ret;
  549. mutex_lock(&ds1307->rtc->ops_lock);
  550. /* Check and clear alarm 0 interrupt flag. */
  551. reg = i2c_smbus_read_byte_data(client, MCP7941X_REG_ALARM0_CTRL);
  552. if (reg < 0)
  553. goto out;
  554. if (!(reg & MCP7941X_BIT_ALMX_IF))
  555. goto out;
  556. reg &= ~MCP7941X_BIT_ALMX_IF;
  557. ret = i2c_smbus_write_byte_data(client, MCP7941X_REG_ALARM0_CTRL, reg);
  558. if (ret < 0)
  559. goto out;
  560. /* Disable alarm 0. */
  561. reg = i2c_smbus_read_byte_data(client, MCP7941X_REG_CONTROL);
  562. if (reg < 0)
  563. goto out;
  564. reg &= ~MCP7941X_BIT_ALM0_EN;
  565. ret = i2c_smbus_write_byte_data(client, MCP7941X_REG_CONTROL, reg);
  566. if (ret < 0)
  567. goto out;
  568. rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
  569. out:
  570. if (test_bit(HAS_ALARM, &ds1307->flags))
  571. enable_irq(client->irq);
  572. mutex_unlock(&ds1307->rtc->ops_lock);
  573. }
  574. static int mcp7941x_read_alarm(struct device *dev, struct rtc_wkalrm *t)
  575. {
  576. struct i2c_client *client = to_i2c_client(dev);
  577. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  578. u8 *regs = ds1307->regs;
  579. int ret;
  580. if (!test_bit(HAS_ALARM, &ds1307->flags))
  581. return -EINVAL;
  582. /* Read control and alarm 0 registers. */
  583. ret = ds1307->read_block_data(client, MCP7941X_REG_CONTROL, 10, regs);
  584. if (ret < 0)
  585. return ret;
  586. t->enabled = !!(regs[0] & MCP7941X_BIT_ALM0_EN);
  587. /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
  588. t->time.tm_sec = bcd2bin(ds1307->regs[3] & 0x7f);
  589. t->time.tm_min = bcd2bin(ds1307->regs[4] & 0x7f);
  590. t->time.tm_hour = bcd2bin(ds1307->regs[5] & 0x3f);
  591. t->time.tm_wday = bcd2bin(ds1307->regs[6] & 0x7) - 1;
  592. t->time.tm_mday = bcd2bin(ds1307->regs[7] & 0x3f);
  593. t->time.tm_mon = bcd2bin(ds1307->regs[8] & 0x1f) - 1;
  594. t->time.tm_year = -1;
  595. t->time.tm_yday = -1;
  596. t->time.tm_isdst = -1;
  597. dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
  598. "enabled=%d polarity=%d irq=%d match=%d\n", __func__,
  599. t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
  600. t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
  601. !!(ds1307->regs[6] & MCP7941X_BIT_ALMX_POL),
  602. !!(ds1307->regs[6] & MCP7941X_BIT_ALMX_IF),
  603. (ds1307->regs[6] & MCP7941X_MSK_ALMX_MATCH) >> 4);
  604. return 0;
  605. }
  606. static int mcp7941x_set_alarm(struct device *dev, struct rtc_wkalrm *t)
  607. {
  608. struct i2c_client *client = to_i2c_client(dev);
  609. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  610. unsigned char *regs = ds1307->regs;
  611. int ret;
  612. if (!test_bit(HAS_ALARM, &ds1307->flags))
  613. return -EINVAL;
  614. dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
  615. "enabled=%d pending=%d\n", __func__,
  616. t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
  617. t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
  618. t->enabled, t->pending);
  619. /* Read control and alarm 0 registers. */
  620. ret = ds1307->read_block_data(client, MCP7941X_REG_CONTROL, 10, regs);
  621. if (ret < 0)
  622. return ret;
  623. /* Set alarm 0, using 24-hour and day-of-month modes. */
  624. regs[3] = bin2bcd(t->time.tm_sec);
  625. regs[4] = bin2bcd(t->time.tm_min);
  626. regs[5] = bin2bcd(t->time.tm_hour);
  627. regs[6] = bin2bcd(t->time.tm_wday) + 1;
  628. regs[7] = bin2bcd(t->time.tm_mday);
  629. regs[8] = bin2bcd(t->time.tm_mon) + 1;
  630. /* Clear the alarm 0 interrupt flag. */
  631. regs[6] &= ~MCP7941X_BIT_ALMX_IF;
  632. /* Set alarm match: second, minute, hour, day, date, month. */
  633. regs[6] |= MCP7941X_MSK_ALMX_MATCH;
  634. if (t->enabled)
  635. regs[0] |= MCP7941X_BIT_ALM0_EN;
  636. else
  637. regs[0] &= ~MCP7941X_BIT_ALM0_EN;
  638. ret = ds1307->write_block_data(client, MCP7941X_REG_CONTROL, 10, regs);
  639. if (ret < 0)
  640. return ret;
  641. return 0;
  642. }
  643. static int mcp7941x_alarm_irq_enable(struct device *dev, unsigned int enabled)
  644. {
  645. struct i2c_client *client = to_i2c_client(dev);
  646. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  647. int reg;
  648. if (!test_bit(HAS_ALARM, &ds1307->flags))
  649. return -EINVAL;
  650. reg = i2c_smbus_read_byte_data(client, MCP7941X_REG_CONTROL);
  651. if (reg < 0)
  652. return reg;
  653. if (enabled)
  654. reg |= MCP7941X_BIT_ALM0_EN;
  655. else
  656. reg &= ~MCP7941X_BIT_ALM0_EN;
  657. return i2c_smbus_write_byte_data(client, MCP7941X_REG_CONTROL, reg);
  658. }
  659. static const struct rtc_class_ops mcp7941x_rtc_ops = {
  660. .read_time = ds1307_get_time,
  661. .set_time = ds1307_set_time,
  662. .read_alarm = mcp7941x_read_alarm,
  663. .set_alarm = mcp7941x_set_alarm,
  664. .alarm_irq_enable = mcp7941x_alarm_irq_enable,
  665. };
  666. /*----------------------------------------------------------------------*/
  667. static ssize_t
  668. ds1307_nvram_read(struct file *filp, struct kobject *kobj,
  669. struct bin_attribute *attr,
  670. char *buf, loff_t off, size_t count)
  671. {
  672. struct i2c_client *client;
  673. struct ds1307 *ds1307;
  674. int result;
  675. client = kobj_to_i2c_client(kobj);
  676. ds1307 = i2c_get_clientdata(client);
  677. if (unlikely(off >= ds1307->nvram->size))
  678. return 0;
  679. if ((off + count) > ds1307->nvram->size)
  680. count = ds1307->nvram->size - off;
  681. if (unlikely(!count))
  682. return count;
  683. result = ds1307->read_block_data(client, ds1307->nvram_offset + off,
  684. count, buf);
  685. if (result < 0)
  686. dev_err(&client->dev, "%s error %d\n", "nvram read", result);
  687. return result;
  688. }
  689. static ssize_t
  690. ds1307_nvram_write(struct file *filp, struct kobject *kobj,
  691. struct bin_attribute *attr,
  692. char *buf, loff_t off, size_t count)
  693. {
  694. struct i2c_client *client;
  695. struct ds1307 *ds1307;
  696. int result;
  697. client = kobj_to_i2c_client(kobj);
  698. ds1307 = i2c_get_clientdata(client);
  699. if (unlikely(off >= ds1307->nvram->size))
  700. return -EFBIG;
  701. if ((off + count) > ds1307->nvram->size)
  702. count = ds1307->nvram->size - off;
  703. if (unlikely(!count))
  704. return count;
  705. result = ds1307->write_block_data(client, ds1307->nvram_offset + off,
  706. count, buf);
  707. if (result < 0) {
  708. dev_err(&client->dev, "%s error %d\n", "nvram write", result);
  709. return result;
  710. }
  711. return count;
  712. }
  713. /*----------------------------------------------------------------------*/
  714. static int ds1307_probe(struct i2c_client *client,
  715. const struct i2c_device_id *id)
  716. {
  717. struct ds1307 *ds1307;
  718. int err = -ENODEV;
  719. int tmp;
  720. const struct chip_desc *chip = &chips[id->driver_data];
  721. struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
  722. bool want_irq = false;
  723. unsigned char *buf;
  724. struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
  725. static const int bbsqi_bitpos[] = {
  726. [ds_1337] = 0,
  727. [ds_1339] = DS1339_BIT_BBSQI,
  728. [ds_3231] = DS3231_BIT_BBSQW,
  729. };
  730. const struct rtc_class_ops *rtc_ops = &ds13xx_rtc_ops;
  731. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
  732. && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
  733. return -EIO;
  734. ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
  735. if (!ds1307)
  736. return -ENOMEM;
  737. i2c_set_clientdata(client, ds1307);
  738. ds1307->client = client;
  739. ds1307->type = id->driver_data;
  740. if (pdata && pdata->trickle_charger_setup && chip->trickle_charger_reg)
  741. i2c_smbus_write_byte_data(client, chip->trickle_charger_reg,
  742. DS13XX_TRICKLE_CHARGER_MAGIC | pdata->trickle_charger_setup);
  743. buf = ds1307->regs;
  744. if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
  745. ds1307->read_block_data = ds1307_native_smbus_read_block_data;
  746. ds1307->write_block_data = ds1307_native_smbus_write_block_data;
  747. } else {
  748. ds1307->read_block_data = ds1307_read_block_data;
  749. ds1307->write_block_data = ds1307_write_block_data;
  750. }
  751. switch (ds1307->type) {
  752. case ds_1337:
  753. case ds_1339:
  754. case ds_3231:
  755. /* get registers that the "rtc" read below won't read... */
  756. tmp = ds1307->read_block_data(ds1307->client,
  757. DS1337_REG_CONTROL, 2, buf);
  758. if (tmp != 2) {
  759. dev_dbg(&client->dev, "read error %d\n", tmp);
  760. err = -EIO;
  761. goto exit;
  762. }
  763. /* oscillator off? turn it on, so clock can tick. */
  764. if (ds1307->regs[0] & DS1337_BIT_nEOSC)
  765. ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
  766. /*
  767. * Using IRQ? Disable the square wave and both alarms.
  768. * For some variants, be sure alarms can trigger when we're
  769. * running on Vbackup (BBSQI/BBSQW)
  770. */
  771. if (ds1307->client->irq > 0 && chip->alarm) {
  772. INIT_WORK(&ds1307->work, ds1307_work);
  773. ds1307->regs[0] |= DS1337_BIT_INTCN
  774. | bbsqi_bitpos[ds1307->type];
  775. ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
  776. want_irq = true;
  777. }
  778. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
  779. ds1307->regs[0]);
  780. /* oscillator fault? clear flag, and warn */
  781. if (ds1307->regs[1] & DS1337_BIT_OSF) {
  782. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
  783. ds1307->regs[1] & ~DS1337_BIT_OSF);
  784. dev_warn(&client->dev, "SET TIME!\n");
  785. }
  786. break;
  787. case rx_8025:
  788. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  789. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  790. if (tmp != 2) {
  791. dev_dbg(&client->dev, "read error %d\n", tmp);
  792. err = -EIO;
  793. goto exit;
  794. }
  795. /* oscillator off? turn it on, so clock can tick. */
  796. if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
  797. ds1307->regs[1] |= RX8025_BIT_XST;
  798. i2c_smbus_write_byte_data(client,
  799. RX8025_REG_CTRL2 << 4 | 0x08,
  800. ds1307->regs[1]);
  801. dev_warn(&client->dev,
  802. "oscillator stop detected - SET TIME!\n");
  803. }
  804. if (ds1307->regs[1] & RX8025_BIT_PON) {
  805. ds1307->regs[1] &= ~RX8025_BIT_PON;
  806. i2c_smbus_write_byte_data(client,
  807. RX8025_REG_CTRL2 << 4 | 0x08,
  808. ds1307->regs[1]);
  809. dev_warn(&client->dev, "power-on detected\n");
  810. }
  811. if (ds1307->regs[1] & RX8025_BIT_VDET) {
  812. ds1307->regs[1] &= ~RX8025_BIT_VDET;
  813. i2c_smbus_write_byte_data(client,
  814. RX8025_REG_CTRL2 << 4 | 0x08,
  815. ds1307->regs[1]);
  816. dev_warn(&client->dev, "voltage drop detected\n");
  817. }
  818. /* make sure we are running in 24hour mode */
  819. if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
  820. u8 hour;
  821. /* switch to 24 hour mode */
  822. i2c_smbus_write_byte_data(client,
  823. RX8025_REG_CTRL1 << 4 | 0x08,
  824. ds1307->regs[0] |
  825. RX8025_BIT_2412);
  826. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  827. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  828. if (tmp != 2) {
  829. dev_dbg(&client->dev, "read error %d\n", tmp);
  830. err = -EIO;
  831. goto exit;
  832. }
  833. /* correct hour */
  834. hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
  835. if (hour == 12)
  836. hour = 0;
  837. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  838. hour += 12;
  839. i2c_smbus_write_byte_data(client,
  840. DS1307_REG_HOUR << 4 | 0x08,
  841. hour);
  842. }
  843. break;
  844. case ds_1388:
  845. ds1307->offset = 1; /* Seconds starts at 1 */
  846. break;
  847. case mcp7941x:
  848. rtc_ops = &mcp7941x_rtc_ops;
  849. if (ds1307->client->irq > 0 && chip->alarm) {
  850. INIT_WORK(&ds1307->work, mcp7941x_work);
  851. want_irq = true;
  852. }
  853. break;
  854. default:
  855. break;
  856. }
  857. read_rtc:
  858. /* read RTC registers */
  859. tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
  860. if (tmp != 8) {
  861. dev_dbg(&client->dev, "read error %d\n", tmp);
  862. err = -EIO;
  863. goto exit;
  864. }
  865. /*
  866. * minimal sanity checking; some chips (like DS1340) don't
  867. * specify the extra bits as must-be-zero, but there are
  868. * still a few values that are clearly out-of-range.
  869. */
  870. tmp = ds1307->regs[DS1307_REG_SECS];
  871. switch (ds1307->type) {
  872. case ds_1307:
  873. case m41t00:
  874. /* clock halted? turn it on, so clock can tick. */
  875. if (tmp & DS1307_BIT_CH) {
  876. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  877. dev_warn(&client->dev, "SET TIME!\n");
  878. goto read_rtc;
  879. }
  880. break;
  881. case ds_1338:
  882. /* clock halted? turn it on, so clock can tick. */
  883. if (tmp & DS1307_BIT_CH)
  884. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  885. /* oscillator fault? clear flag, and warn */
  886. if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
  887. i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
  888. ds1307->regs[DS1307_REG_CONTROL]
  889. & ~DS1338_BIT_OSF);
  890. dev_warn(&client->dev, "SET TIME!\n");
  891. goto read_rtc;
  892. }
  893. break;
  894. case ds_1340:
  895. /* clock halted? turn it on, so clock can tick. */
  896. if (tmp & DS1340_BIT_nEOSC)
  897. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  898. tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
  899. if (tmp < 0) {
  900. dev_dbg(&client->dev, "read error %d\n", tmp);
  901. err = -EIO;
  902. goto exit;
  903. }
  904. /* oscillator fault? clear flag, and warn */
  905. if (tmp & DS1340_BIT_OSF) {
  906. i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
  907. dev_warn(&client->dev, "SET TIME!\n");
  908. }
  909. break;
  910. case mcp7941x:
  911. /* make sure that the backup battery is enabled */
  912. if (!(ds1307->regs[DS1307_REG_WDAY] & MCP7941X_BIT_VBATEN)) {
  913. i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
  914. ds1307->regs[DS1307_REG_WDAY]
  915. | MCP7941X_BIT_VBATEN);
  916. }
  917. /* clock halted? turn it on, so clock can tick. */
  918. if (!(tmp & MCP7941X_BIT_ST)) {
  919. i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
  920. MCP7941X_BIT_ST);
  921. dev_warn(&client->dev, "SET TIME!\n");
  922. goto read_rtc;
  923. }
  924. break;
  925. default:
  926. break;
  927. }
  928. tmp = ds1307->regs[DS1307_REG_HOUR];
  929. switch (ds1307->type) {
  930. case ds_1340:
  931. case m41t00:
  932. /*
  933. * NOTE: ignores century bits; fix before deploying
  934. * systems that will run through year 2100.
  935. */
  936. break;
  937. case rx_8025:
  938. break;
  939. default:
  940. if (!(tmp & DS1307_BIT_12HR))
  941. break;
  942. /*
  943. * Be sure we're in 24 hour mode. Multi-master systems
  944. * take note...
  945. */
  946. tmp = bcd2bin(tmp & 0x1f);
  947. if (tmp == 12)
  948. tmp = 0;
  949. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  950. tmp += 12;
  951. i2c_smbus_write_byte_data(client,
  952. ds1307->offset + DS1307_REG_HOUR,
  953. bin2bcd(tmp));
  954. }
  955. device_set_wakeup_capable(&client->dev, want_irq);
  956. ds1307->rtc = devm_rtc_device_register(&client->dev, client->name,
  957. rtc_ops, THIS_MODULE);
  958. if (IS_ERR(ds1307->rtc)) {
  959. return PTR_ERR(ds1307->rtc);
  960. }
  961. if (want_irq) {
  962. err = request_irq(client->irq, ds1307_irq, IRQF_SHARED,
  963. ds1307->rtc->name, client);
  964. if (err) {
  965. client->irq = 0;
  966. dev_err(&client->dev, "unable to request IRQ!\n");
  967. } else {
  968. set_bit(HAS_ALARM, &ds1307->flags);
  969. dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
  970. }
  971. }
  972. if (chip->nvram_size) {
  973. ds1307->nvram = devm_kzalloc(&client->dev,
  974. sizeof(struct bin_attribute),
  975. GFP_KERNEL);
  976. if (!ds1307->nvram) {
  977. dev_err(&client->dev, "cannot allocate memory for nvram sysfs\n");
  978. } else {
  979. ds1307->nvram->attr.name = "nvram";
  980. ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
  981. sysfs_bin_attr_init(ds1307->nvram);
  982. ds1307->nvram->read = ds1307_nvram_read;
  983. ds1307->nvram->write = ds1307_nvram_write;
  984. ds1307->nvram->size = chip->nvram_size;
  985. ds1307->nvram_offset = chip->nvram_offset;
  986. err = sysfs_create_bin_file(&client->dev.kobj,
  987. ds1307->nvram);
  988. if (err) {
  989. dev_err(&client->dev,
  990. "unable to create sysfs file: %s\n",
  991. ds1307->nvram->attr.name);
  992. } else {
  993. set_bit(HAS_NVRAM, &ds1307->flags);
  994. dev_info(&client->dev, "%zu bytes nvram\n",
  995. ds1307->nvram->size);
  996. }
  997. }
  998. }
  999. return 0;
  1000. exit:
  1001. return err;
  1002. }
  1003. static int ds1307_remove(struct i2c_client *client)
  1004. {
  1005. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  1006. if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
  1007. free_irq(client->irq, client);
  1008. cancel_work_sync(&ds1307->work);
  1009. }
  1010. if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
  1011. sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram);
  1012. return 0;
  1013. }
  1014. static struct i2c_driver ds1307_driver = {
  1015. .driver = {
  1016. .name = "rtc-ds1307",
  1017. .owner = THIS_MODULE,
  1018. },
  1019. .probe = ds1307_probe,
  1020. .remove = ds1307_remove,
  1021. .id_table = ds1307_id,
  1022. };
  1023. module_i2c_driver(ds1307_driver);
  1024. MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
  1025. MODULE_LICENSE("GPL");