phy-sun4i-usb.c 8.3 KB

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  1. /*
  2. * Allwinner sun4i USB phy driver
  3. *
  4. * Copyright (C) 2014 Hans de Goede <hdegoede@redhat.com>
  5. *
  6. * Based on code from
  7. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  8. *
  9. * Modelled after: Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
  10. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  11. * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #include <linux/clk.h>
  24. #include <linux/io.h>
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/mutex.h>
  28. #include <linux/of.h>
  29. #include <linux/of_address.h>
  30. #include <linux/phy/phy.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/regulator/consumer.h>
  33. #include <linux/reset.h>
  34. #define REG_ISCR 0x00
  35. #define REG_PHYCTL 0x04
  36. #define REG_PHYBIST 0x08
  37. #define REG_PHYTUNE 0x0c
  38. #define PHYCTL_DATA BIT(7)
  39. #define SUNXI_AHB_ICHR8_EN BIT(10)
  40. #define SUNXI_AHB_INCR4_BURST_EN BIT(9)
  41. #define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
  42. #define SUNXI_ULPI_BYPASS_EN BIT(0)
  43. /* Common Control Bits for Both PHYs */
  44. #define PHY_PLL_BW 0x03
  45. #define PHY_RES45_CAL_EN 0x0c
  46. /* Private Control Bits for Each PHY */
  47. #define PHY_TX_AMPLITUDE_TUNE 0x20
  48. #define PHY_TX_SLEWRATE_TUNE 0x22
  49. #define PHY_VBUSVALID_TH_SEL 0x25
  50. #define PHY_PULLUP_RES_SEL 0x27
  51. #define PHY_OTG_FUNC_EN 0x28
  52. #define PHY_VBUS_DET_EN 0x29
  53. #define PHY_DISCON_TH_SEL 0x2a
  54. #define MAX_PHYS 3
  55. struct sun4i_usb_phy_data {
  56. void __iomem *base;
  57. struct mutex mutex;
  58. int num_phys;
  59. u32 disc_thresh;
  60. struct sun4i_usb_phy {
  61. struct phy *phy;
  62. void __iomem *pmu;
  63. struct regulator *vbus;
  64. struct reset_control *reset;
  65. struct clk *clk;
  66. int index;
  67. } phys[MAX_PHYS];
  68. };
  69. #define to_sun4i_usb_phy_data(phy) \
  70. container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
  71. static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
  72. int len)
  73. {
  74. struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
  75. u32 temp, usbc_bit = BIT(phy->index * 2);
  76. int i;
  77. mutex_lock(&phy_data->mutex);
  78. for (i = 0; i < len; i++) {
  79. temp = readl(phy_data->base + REG_PHYCTL);
  80. /* clear the address portion */
  81. temp &= ~(0xff << 8);
  82. /* set the address */
  83. temp |= ((addr + i) << 8);
  84. writel(temp, phy_data->base + REG_PHYCTL);
  85. /* set the data bit and clear usbc bit*/
  86. temp = readb(phy_data->base + REG_PHYCTL);
  87. if (data & 0x1)
  88. temp |= PHYCTL_DATA;
  89. else
  90. temp &= ~PHYCTL_DATA;
  91. temp &= ~usbc_bit;
  92. writeb(temp, phy_data->base + REG_PHYCTL);
  93. /* pulse usbc_bit */
  94. temp = readb(phy_data->base + REG_PHYCTL);
  95. temp |= usbc_bit;
  96. writeb(temp, phy_data->base + REG_PHYCTL);
  97. temp = readb(phy_data->base + REG_PHYCTL);
  98. temp &= ~usbc_bit;
  99. writeb(temp, phy_data->base + REG_PHYCTL);
  100. data >>= 1;
  101. }
  102. mutex_unlock(&phy_data->mutex);
  103. }
  104. static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
  105. {
  106. u32 bits, reg_value;
  107. if (!phy->pmu)
  108. return;
  109. bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
  110. SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
  111. reg_value = readl(phy->pmu);
  112. if (enable)
  113. reg_value |= bits;
  114. else
  115. reg_value &= ~bits;
  116. writel(reg_value, phy->pmu);
  117. }
  118. static int sun4i_usb_phy_init(struct phy *_phy)
  119. {
  120. struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
  121. struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
  122. int ret;
  123. ret = clk_prepare_enable(phy->clk);
  124. if (ret)
  125. return ret;
  126. ret = reset_control_deassert(phy->reset);
  127. if (ret) {
  128. clk_disable_unprepare(phy->clk);
  129. return ret;
  130. }
  131. /* Adjust PHY's magnitude and rate */
  132. sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
  133. /* Disconnect threshold adjustment */
  134. sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2);
  135. sun4i_usb_phy_passby(phy, 1);
  136. return 0;
  137. }
  138. static int sun4i_usb_phy_exit(struct phy *_phy)
  139. {
  140. struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
  141. sun4i_usb_phy_passby(phy, 0);
  142. reset_control_assert(phy->reset);
  143. clk_disable_unprepare(phy->clk);
  144. return 0;
  145. }
  146. static int sun4i_usb_phy_power_on(struct phy *_phy)
  147. {
  148. struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
  149. int ret = 0;
  150. if (phy->vbus)
  151. ret = regulator_enable(phy->vbus);
  152. return ret;
  153. }
  154. static int sun4i_usb_phy_power_off(struct phy *_phy)
  155. {
  156. struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
  157. if (phy->vbus)
  158. regulator_disable(phy->vbus);
  159. return 0;
  160. }
  161. static struct phy_ops sun4i_usb_phy_ops = {
  162. .init = sun4i_usb_phy_init,
  163. .exit = sun4i_usb_phy_exit,
  164. .power_on = sun4i_usb_phy_power_on,
  165. .power_off = sun4i_usb_phy_power_off,
  166. .owner = THIS_MODULE,
  167. };
  168. static struct phy *sun4i_usb_phy_xlate(struct device *dev,
  169. struct of_phandle_args *args)
  170. {
  171. struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
  172. if (WARN_ON(args->args[0] == 0 || args->args[0] >= data->num_phys))
  173. return ERR_PTR(-ENODEV);
  174. return data->phys[args->args[0]].phy;
  175. }
  176. static int sun4i_usb_phy_probe(struct platform_device *pdev)
  177. {
  178. struct sun4i_usb_phy_data *data;
  179. struct device *dev = &pdev->dev;
  180. struct device_node *np = dev->of_node;
  181. struct phy_provider *phy_provider;
  182. bool dedicated_clocks;
  183. struct resource *res;
  184. int i;
  185. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  186. if (!data)
  187. return -ENOMEM;
  188. mutex_init(&data->mutex);
  189. if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-phy"))
  190. data->num_phys = 2;
  191. else
  192. data->num_phys = 3;
  193. if (of_device_is_compatible(np, "allwinner,sun4i-a10-usb-phy"))
  194. data->disc_thresh = 3;
  195. else
  196. data->disc_thresh = 2;
  197. if (of_device_is_compatible(np, "allwinner,sun6i-a31-usb-phy"))
  198. dedicated_clocks = true;
  199. else
  200. dedicated_clocks = false;
  201. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
  202. data->base = devm_ioremap_resource(dev, res);
  203. if (IS_ERR(data->base))
  204. return PTR_ERR(data->base);
  205. /* Skip 0, 0 is the phy for otg which is not yet supported. */
  206. for (i = 1; i < data->num_phys; i++) {
  207. struct sun4i_usb_phy *phy = data->phys + i;
  208. char name[16];
  209. snprintf(name, sizeof(name), "usb%d_vbus", i);
  210. phy->vbus = devm_regulator_get_optional(dev, name);
  211. if (IS_ERR(phy->vbus)) {
  212. if (PTR_ERR(phy->vbus) == -EPROBE_DEFER)
  213. return -EPROBE_DEFER;
  214. phy->vbus = NULL;
  215. }
  216. if (dedicated_clocks)
  217. snprintf(name, sizeof(name), "usb%d_phy", i);
  218. else
  219. strlcpy(name, "usb_phy", sizeof(name));
  220. phy->clk = devm_clk_get(dev, name);
  221. if (IS_ERR(phy->clk)) {
  222. dev_err(dev, "failed to get clock %s\n", name);
  223. return PTR_ERR(phy->clk);
  224. }
  225. snprintf(name, sizeof(name), "usb%d_reset", i);
  226. phy->reset = devm_reset_control_get(dev, name);
  227. if (IS_ERR(phy->reset)) {
  228. dev_err(dev, "failed to get reset %s\n", name);
  229. return PTR_ERR(phy->reset);
  230. }
  231. if (i) { /* No pmu for usbc0 */
  232. snprintf(name, sizeof(name), "pmu%d", i);
  233. res = platform_get_resource_byname(pdev,
  234. IORESOURCE_MEM, name);
  235. phy->pmu = devm_ioremap_resource(dev, res);
  236. if (IS_ERR(phy->pmu))
  237. return PTR_ERR(phy->pmu);
  238. }
  239. phy->phy = devm_phy_create(dev, &sun4i_usb_phy_ops, NULL);
  240. if (IS_ERR(phy->phy)) {
  241. dev_err(dev, "failed to create PHY %d\n", i);
  242. return PTR_ERR(phy->phy);
  243. }
  244. phy->index = i;
  245. phy_set_drvdata(phy->phy, &data->phys[i]);
  246. }
  247. dev_set_drvdata(dev, data);
  248. phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate);
  249. if (IS_ERR(phy_provider))
  250. return PTR_ERR(phy_provider);
  251. return 0;
  252. }
  253. static const struct of_device_id sun4i_usb_phy_of_match[] = {
  254. { .compatible = "allwinner,sun4i-a10-usb-phy" },
  255. { .compatible = "allwinner,sun5i-a13-usb-phy" },
  256. { .compatible = "allwinner,sun6i-a31-usb-phy" },
  257. { .compatible = "allwinner,sun7i-a20-usb-phy" },
  258. { },
  259. };
  260. MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
  261. static struct platform_driver sun4i_usb_phy_driver = {
  262. .probe = sun4i_usb_phy_probe,
  263. .driver = {
  264. .of_match_table = sun4i_usb_phy_of_match,
  265. .name = "sun4i-usb-phy",
  266. .owner = THIS_MODULE,
  267. }
  268. };
  269. module_platform_driver(sun4i_usb_phy_driver);
  270. MODULE_DESCRIPTION("Allwinner sun4i USB phy driver");
  271. MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
  272. MODULE_LICENSE("GPL v2");