phy-mvebu-sata.c 3.4 KB

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  1. /*
  2. * phy-mvebu-sata.c: SATA Phy driver for the Marvell mvebu SoCs.
  3. *
  4. * Copyright (C) 2013 Andrew Lunn <andrew@lunn.ch>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/clk.h>
  14. #include <linux/phy/phy.h>
  15. #include <linux/io.h>
  16. #include <linux/platform_device.h>
  17. struct priv {
  18. struct clk *clk;
  19. void __iomem *base;
  20. };
  21. #define SATA_PHY_MODE_2 0x0330
  22. #define MODE_2_FORCE_PU_TX BIT(0)
  23. #define MODE_2_FORCE_PU_RX BIT(1)
  24. #define MODE_2_PU_PLL BIT(2)
  25. #define MODE_2_PU_IVREF BIT(3)
  26. #define SATA_IF_CTRL 0x0050
  27. #define CTRL_PHY_SHUTDOWN BIT(9)
  28. static int phy_mvebu_sata_power_on(struct phy *phy)
  29. {
  30. struct priv *priv = phy_get_drvdata(phy);
  31. u32 reg;
  32. clk_prepare_enable(priv->clk);
  33. /* Enable PLL and IVREF */
  34. reg = readl(priv->base + SATA_PHY_MODE_2);
  35. reg |= (MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
  36. MODE_2_PU_PLL | MODE_2_PU_IVREF);
  37. writel(reg , priv->base + SATA_PHY_MODE_2);
  38. /* Enable PHY */
  39. reg = readl(priv->base + SATA_IF_CTRL);
  40. reg &= ~CTRL_PHY_SHUTDOWN;
  41. writel(reg, priv->base + SATA_IF_CTRL);
  42. clk_disable_unprepare(priv->clk);
  43. return 0;
  44. }
  45. static int phy_mvebu_sata_power_off(struct phy *phy)
  46. {
  47. struct priv *priv = phy_get_drvdata(phy);
  48. u32 reg;
  49. clk_prepare_enable(priv->clk);
  50. /* Disable PLL and IVREF */
  51. reg = readl(priv->base + SATA_PHY_MODE_2);
  52. reg &= ~(MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
  53. MODE_2_PU_PLL | MODE_2_PU_IVREF);
  54. writel(reg, priv->base + SATA_PHY_MODE_2);
  55. /* Disable PHY */
  56. reg = readl(priv->base + SATA_IF_CTRL);
  57. reg |= CTRL_PHY_SHUTDOWN;
  58. writel(reg, priv->base + SATA_IF_CTRL);
  59. clk_disable_unprepare(priv->clk);
  60. return 0;
  61. }
  62. static struct phy_ops phy_mvebu_sata_ops = {
  63. .power_on = phy_mvebu_sata_power_on,
  64. .power_off = phy_mvebu_sata_power_off,
  65. .owner = THIS_MODULE,
  66. };
  67. static int phy_mvebu_sata_probe(struct platform_device *pdev)
  68. {
  69. struct phy_provider *phy_provider;
  70. struct resource *res;
  71. struct priv *priv;
  72. struct phy *phy;
  73. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  74. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  75. priv->base = devm_ioremap_resource(&pdev->dev, res);
  76. if (IS_ERR(priv->base))
  77. return PTR_ERR(priv->base);
  78. priv->clk = devm_clk_get(&pdev->dev, "sata");
  79. if (IS_ERR(priv->clk))
  80. return PTR_ERR(priv->clk);
  81. phy = devm_phy_create(&pdev->dev, &phy_mvebu_sata_ops, NULL);
  82. if (IS_ERR(phy))
  83. return PTR_ERR(phy);
  84. phy_set_drvdata(phy, priv);
  85. phy_provider = devm_of_phy_provider_register(&pdev->dev,
  86. of_phy_simple_xlate);
  87. if (IS_ERR(phy_provider))
  88. return PTR_ERR(phy_provider);
  89. /* The boot loader may of left it on. Turn it off. */
  90. phy_mvebu_sata_power_off(phy);
  91. return 0;
  92. }
  93. static const struct of_device_id phy_mvebu_sata_of_match[] = {
  94. { .compatible = "marvell,mvebu-sata-phy" },
  95. { },
  96. };
  97. MODULE_DEVICE_TABLE(of, phy_mvebu_sata_of_match);
  98. static struct platform_driver phy_mvebu_sata_driver = {
  99. .probe = phy_mvebu_sata_probe,
  100. .driver = {
  101. .name = "phy-mvebu-sata",
  102. .owner = THIS_MODULE,
  103. .of_match_table = phy_mvebu_sata_of_match,
  104. }
  105. };
  106. module_platform_driver(phy_mvebu_sata_driver);
  107. MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
  108. MODULE_DESCRIPTION("Marvell MVEBU SATA PHY driver");
  109. MODULE_LICENSE("GPL v2");