fw.c 19 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2014 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. #include "../wifi.h"
  26. #include "../pci.h"
  27. #include "../base.h"
  28. #include "reg.h"
  29. #include "def.h"
  30. #include "fw.h"
  31. #include "../rtl8723com/fw_common.h"
  32. static bool _rtl8723be_check_fw_read_last_h2c(struct ieee80211_hw *hw,
  33. u8 boxnum)
  34. {
  35. struct rtl_priv *rtlpriv = rtl_priv(hw);
  36. u8 val_hmetfr;
  37. bool result = false;
  38. val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
  39. if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
  40. result = true;
  41. return result;
  42. }
  43. static void _rtl8723be_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
  44. u32 cmd_len, u8 *p_cmdbuffer)
  45. {
  46. struct rtl_priv *rtlpriv = rtl_priv(hw);
  47. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  48. u8 boxnum;
  49. u16 box_reg = 0, box_extreg = 0;
  50. u8 u1b_tmp;
  51. bool isfw_read = false;
  52. u8 buf_index = 0;
  53. bool bwrite_sucess = false;
  54. u8 wait_h2c_limit = 100;
  55. u8 wait_writeh2c_limit = 100;
  56. u8 boxcontent[4], boxextcontent[4];
  57. u32 h2c_waitcounter = 0;
  58. unsigned long flag;
  59. u8 idx;
  60. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n");
  61. while (true) {
  62. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  63. if (rtlhal->h2c_setinprogress) {
  64. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  65. "H2C set in progress! Wait to set.."
  66. "element_id(%d).\n", element_id);
  67. while (rtlhal->h2c_setinprogress) {
  68. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
  69. flag);
  70. h2c_waitcounter++;
  71. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  72. "Wait 100 us (%d times)...\n",
  73. h2c_waitcounter);
  74. udelay(100);
  75. if (h2c_waitcounter > 1000)
  76. return;
  77. spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
  78. flag);
  79. }
  80. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  81. } else {
  82. rtlhal->h2c_setinprogress = true;
  83. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  84. break;
  85. }
  86. }
  87. while (!bwrite_sucess) {
  88. wait_writeh2c_limit--;
  89. if (wait_writeh2c_limit == 0) {
  90. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  91. "Write H2C fail because no trigger "
  92. "for FW INT!\n");
  93. break;
  94. }
  95. boxnum = rtlhal->last_hmeboxnum;
  96. switch (boxnum) {
  97. case 0:
  98. box_reg = REG_HMEBOX_0;
  99. box_extreg = REG_HMEBOX_EXT_0;
  100. break;
  101. case 1:
  102. box_reg = REG_HMEBOX_1;
  103. box_extreg = REG_HMEBOX_EXT_1;
  104. break;
  105. case 2:
  106. box_reg = REG_HMEBOX_2;
  107. box_extreg = REG_HMEBOX_EXT_2;
  108. break;
  109. case 3:
  110. box_reg = REG_HMEBOX_3;
  111. box_extreg = REG_HMEBOX_EXT_3;
  112. break;
  113. default:
  114. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  115. "switch case not processed\n");
  116. break;
  117. }
  118. isfw_read = _rtl8723be_check_fw_read_last_h2c(hw, boxnum);
  119. while (!isfw_read) {
  120. wait_h2c_limit--;
  121. if (wait_h2c_limit == 0) {
  122. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  123. "Wating too long for FW read "
  124. "clear HMEBox(%d)!\n", boxnum);
  125. break;
  126. }
  127. udelay(10);
  128. isfw_read = _rtl8723be_check_fw_read_last_h2c(hw,
  129. boxnum);
  130. u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
  131. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  132. "Wating for FW read clear HMEBox(%d)!!! 0x130 = %2x\n",
  133. boxnum, u1b_tmp);
  134. }
  135. if (!isfw_read) {
  136. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  137. "Write H2C register BOX[%d] fail!!!!! "
  138. "Fw do not read.\n", boxnum);
  139. break;
  140. }
  141. memset(boxcontent, 0, sizeof(boxcontent));
  142. memset(boxextcontent, 0, sizeof(boxextcontent));
  143. boxcontent[0] = element_id;
  144. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  145. "Write element_id box_reg(%4x) = %2x\n",
  146. box_reg, element_id);
  147. switch (cmd_len) {
  148. case 1:
  149. case 2:
  150. case 3:
  151. /*boxcontent[0] &= ~(BIT(7));*/
  152. memcpy((u8 *)(boxcontent) + 1,
  153. p_cmdbuffer + buf_index, cmd_len);
  154. for (idx = 0; idx < 4; idx++) {
  155. rtl_write_byte(rtlpriv, box_reg + idx,
  156. boxcontent[idx]);
  157. }
  158. break;
  159. case 4:
  160. case 5:
  161. case 6:
  162. case 7:
  163. /*boxcontent[0] |= (BIT(7));*/
  164. memcpy((u8 *)(boxextcontent),
  165. p_cmdbuffer + buf_index+3, cmd_len-3);
  166. memcpy((u8 *)(boxcontent) + 1,
  167. p_cmdbuffer + buf_index, 3);
  168. for (idx = 0; idx < 4; idx++) {
  169. rtl_write_byte(rtlpriv, box_extreg + idx,
  170. boxextcontent[idx]);
  171. }
  172. for (idx = 0; idx < 4; idx++) {
  173. rtl_write_byte(rtlpriv, box_reg + idx,
  174. boxcontent[idx]);
  175. }
  176. break;
  177. default:
  178. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  179. "switch case not process\n");
  180. break;
  181. }
  182. bwrite_sucess = true;
  183. rtlhal->last_hmeboxnum = boxnum + 1;
  184. if (rtlhal->last_hmeboxnum == 4)
  185. rtlhal->last_hmeboxnum = 0;
  186. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  187. "pHalData->last_hmeboxnum = %d\n",
  188. rtlhal->last_hmeboxnum);
  189. }
  190. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  191. rtlhal->h2c_setinprogress = false;
  192. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  193. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
  194. }
  195. void rtl8723be_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
  196. u32 cmd_len, u8 *p_cmdbuffer)
  197. {
  198. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  199. u32 tmp_cmdbuf[2];
  200. if (!rtlhal->fw_ready) {
  201. RT_ASSERT(false,
  202. "return H2C cmd because of Fw download fail!!!\n");
  203. return;
  204. }
  205. memset(tmp_cmdbuf, 0, 8);
  206. memcpy(tmp_cmdbuf, p_cmdbuffer, cmd_len);
  207. _rtl8723be_fill_h2c_command(hw, element_id, cmd_len,
  208. (u8 *)&tmp_cmdbuf);
  209. return;
  210. }
  211. void rtl8723be_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
  212. {
  213. struct rtl_priv *rtlpriv = rtl_priv(hw);
  214. u8 u1_h2c_set_pwrmode[H2C_8723BE_PWEMODE_LENGTH] = { 0 };
  215. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  216. u8 rlbm, power_state = 0;
  217. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
  218. SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
  219. rlbm = 0;/*YJ, temp, 120316. FW now not support RLBM = 2.*/
  220. SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, rlbm);
  221. SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
  222. (rtlpriv->mac80211.p2p) ?
  223. ppsc->smart_ps : 1);
  224. SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode,
  225. ppsc->reg_max_lps_awakeintvl);
  226. SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
  227. if (mode == FW_PS_ACTIVE_MODE)
  228. power_state |= FW_PWR_STATE_ACTIVE;
  229. else
  230. power_state |= FW_PWR_STATE_RF_OFF;
  231. SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1_h2c_set_pwrmode, power_state);
  232. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  233. "rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode\n",
  234. u1_h2c_set_pwrmode, H2C_8723BE_PWEMODE_LENGTH);
  235. rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_SETPWRMODE,
  236. H2C_8723BE_PWEMODE_LENGTH,
  237. u1_h2c_set_pwrmode);
  238. }
  239. static bool _rtl8723be_cmd_send_packet(struct ieee80211_hw *hw,
  240. struct sk_buff *skb)
  241. {
  242. struct rtl_priv *rtlpriv = rtl_priv(hw);
  243. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  244. struct rtl8192_tx_ring *ring;
  245. struct rtl_tx_desc *pdesc;
  246. struct sk_buff *pskb = NULL;
  247. u8 own;
  248. unsigned long flags;
  249. ring = &rtlpci->tx_ring[BEACON_QUEUE];
  250. pskb = __skb_dequeue(&ring->queue);
  251. if (pskb)
  252. kfree_skb(pskb);
  253. spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  254. pdesc = &ring->desc[0];
  255. own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc, true, HW_DESC_OWN);
  256. rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb);
  257. __skb_queue_tail(&ring->queue, skb);
  258. spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  259. rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
  260. return true;
  261. }
  262. #define BEACON_PG 0 /* ->1 */
  263. #define PSPOLL_PG 2
  264. #define NULL_PG 3
  265. #define PROBERSP_PG 4 /* ->5 */
  266. #define TOTAL_RESERVED_PKT_LEN 768
  267. static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
  268. /* page 0 beacon */
  269. 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
  270. 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
  271. 0xEC, 0x1A, 0x59, 0x0B, 0xAD, 0xD4, 0x20, 0x00,
  272. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  273. 0x64, 0x00, 0x10, 0x04, 0x00, 0x05, 0x54, 0x65,
  274. 0x73, 0x74, 0x32, 0x01, 0x08, 0x82, 0x84, 0x0B,
  275. 0x16, 0x24, 0x30, 0x48, 0x6C, 0x03, 0x01, 0x06,
  276. 0x06, 0x02, 0x00, 0x00, 0x2A, 0x01, 0x02, 0x32,
  277. 0x04, 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C,
  278. 0x09, 0x03, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
  279. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  280. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  281. 0x00, 0x3D, 0x00, 0xDD, 0x07, 0x00, 0xE0, 0x4C,
  282. 0x02, 0x02, 0x00, 0x00, 0xDD, 0x18, 0x00, 0x50,
  283. 0xF2, 0x01, 0x01, 0x00, 0x00, 0x50, 0xF2, 0x04,
  284. 0x01, 0x00, 0x00, 0x50, 0xF2, 0x04, 0x01, 0x00,
  285. /* page 1 beacon */
  286. 0x00, 0x50, 0xF2, 0x02, 0x00, 0x00, 0x00, 0x00,
  287. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  288. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  289. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  290. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  291. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  292. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  293. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  294. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  295. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  296. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  297. 0x10, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
  298. 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00,
  299. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  300. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  301. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  302. /* page 2 ps-poll */
  303. 0xA4, 0x10, 0x01, 0xC0, 0xEC, 0x1A, 0x59, 0x0B,
  304. 0xAD, 0xD4, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
  305. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  306. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  307. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  308. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  309. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  310. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  311. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  312. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  313. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  314. 0x18, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
  315. 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
  316. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  317. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  318. 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  319. /* page 3 null */
  320. 0x48, 0x01, 0x00, 0x00, 0xEC, 0x1A, 0x59, 0x0B,
  321. 0xAD, 0xD4, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
  322. 0xEC, 0x1A, 0x59, 0x0B, 0xAD, 0xD4, 0x00, 0x00,
  323. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  324. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  325. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  326. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  327. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  328. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  329. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  330. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  331. 0x72, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
  332. 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
  333. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  334. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  335. 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  336. /* page 4 probe_resp */
  337. 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  338. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  339. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  340. 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
  341. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  342. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  343. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  344. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  345. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  346. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  347. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  348. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  349. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  350. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  351. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  352. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  353. /* page 5 probe_resp */
  354. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  355. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  356. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  357. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  358. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  359. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  360. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  361. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  362. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  363. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  364. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  365. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  366. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  367. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  368. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  369. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  370. };
  371. void rtl8723be_set_fw_rsvdpagepkt(struct ieee80211_hw *hw,
  372. bool dl_finished)
  373. {
  374. struct rtl_priv *rtlpriv = rtl_priv(hw);
  375. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  376. struct sk_buff *skb = NULL;
  377. u32 totalpacketlen;
  378. bool rtstatus;
  379. u8 u1rsvdpageloc[5] = { 0 };
  380. bool dlok = false;
  381. u8 *beacon;
  382. u8 *p_pspoll;
  383. u8 *nullfunc;
  384. u8 *p_probersp;
  385. /*---------------------------------------------------------
  386. * (1) beacon
  387. *---------------------------------------------------------
  388. */
  389. beacon = &reserved_page_packet[BEACON_PG * 128];
  390. SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
  391. SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
  392. /*-------------------------------------------------------
  393. * (2) ps-poll
  394. *-------------------------------------------------------
  395. */
  396. p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
  397. SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
  398. SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
  399. SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
  400. SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1rsvdpageloc, PSPOLL_PG);
  401. /*--------------------------------------------------------
  402. * (3) null data
  403. *--------------------------------------------------------
  404. */
  405. nullfunc = &reserved_page_packet[NULL_PG * 128];
  406. SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
  407. SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
  408. SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
  409. SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1rsvdpageloc, NULL_PG);
  410. /*---------------------------------------------------------
  411. * (4) probe response
  412. *---------------------------------------------------------
  413. */
  414. p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
  415. SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
  416. SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
  417. SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
  418. SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1rsvdpageloc, PROBERSP_PG);
  419. totalpacketlen = TOTAL_RESERVED_PKT_LEN;
  420. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
  421. "rtl8723be_set_fw_rsvdpagepkt(): "
  422. "HW_VAR_SET_TX_CMD: ALL\n",
  423. &reserved_page_packet[0], totalpacketlen);
  424. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  425. "rtl8723be_set_fw_rsvdpagepkt(): "
  426. "HW_VAR_SET_TX_CMD: ALL\n", u1rsvdpageloc, 3);
  427. skb = dev_alloc_skb(totalpacketlen);
  428. memcpy((u8 *)skb_put(skb, totalpacketlen),
  429. &reserved_page_packet, totalpacketlen);
  430. rtstatus = _rtl8723be_cmd_send_packet(hw, skb);
  431. if (rtstatus)
  432. dlok = true;
  433. if (dlok) {
  434. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  435. "Set RSVD page location to Fw.\n");
  436. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG, "H2C_RSVDPAGE:\n",
  437. u1rsvdpageloc, 3);
  438. rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_RSVDPAGE,
  439. sizeof(u1rsvdpageloc), u1rsvdpageloc);
  440. } else {
  441. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  442. "Set RSVD page location to Fw FAIL!!!!!!.\n");
  443. }
  444. }
  445. /*Should check FW support p2p or not.*/
  446. static void rtl8723be_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw,
  447. u8 ctwindow)
  448. {
  449. u8 u1_ctwindow_period[1] = {ctwindow};
  450. rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_P2P_PS_CTW_CMD, 1,
  451. u1_ctwindow_period);
  452. }
  453. void rtl8723be_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw,
  454. u8 p2p_ps_state)
  455. {
  456. struct rtl_priv *rtlpriv = rtl_priv(hw);
  457. struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
  458. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  459. struct rtl_p2p_ps_info *p2pinfo = &(rtlps->p2p_ps_info);
  460. struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
  461. u8 i;
  462. u16 ctwindow;
  463. u32 start_time, tsf_low;
  464. switch (p2p_ps_state) {
  465. case P2P_PS_DISABLE:
  466. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
  467. memset(p2p_ps_offload, 0, sizeof(struct p2p_ps_offload_t));
  468. break;
  469. case P2P_PS_ENABLE:
  470. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
  471. /* update CTWindow value. */
  472. if (p2pinfo->ctwindow > 0) {
  473. p2p_ps_offload->ctwindow_en = 1;
  474. ctwindow = p2pinfo->ctwindow;
  475. rtl8723be_set_p2p_ctw_period_cmd(hw, ctwindow);
  476. }
  477. /* hw only support 2 set of NoA */
  478. for (i = 0; i < p2pinfo->noa_num; i++) {
  479. /* To control the register setting
  480. * for which NOA
  481. */
  482. rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
  483. if (i == 0)
  484. p2p_ps_offload->noa0_en = 1;
  485. else
  486. p2p_ps_offload->noa1_en = 1;
  487. /* config P2P NoA Descriptor Register */
  488. rtl_write_dword(rtlpriv, 0x5E0,
  489. p2pinfo->noa_duration[i]);
  490. rtl_write_dword(rtlpriv, 0x5E4,
  491. p2pinfo->noa_interval[i]);
  492. /*Get Current TSF value */
  493. tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
  494. start_time = p2pinfo->noa_start_time[i];
  495. if (p2pinfo->noa_count_type[i] != 1) {
  496. while (start_time <= (tsf_low + (50 * 1024))) {
  497. start_time += p2pinfo->noa_interval[i];
  498. if (p2pinfo->noa_count_type[i] != 255)
  499. p2pinfo->noa_count_type[i]--;
  500. }
  501. }
  502. rtl_write_dword(rtlpriv, 0x5E8, start_time);
  503. rtl_write_dword(rtlpriv, 0x5EC,
  504. p2pinfo->noa_count_type[i]);
  505. }
  506. if ((p2pinfo->opp_ps == 1) ||
  507. (p2pinfo->noa_num > 0)) {
  508. /* rst p2p circuit */
  509. rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
  510. p2p_ps_offload->offload_en = 1;
  511. if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
  512. p2p_ps_offload->role = 1;
  513. p2p_ps_offload->allstasleep = 0;
  514. } else {
  515. p2p_ps_offload->role = 0;
  516. }
  517. p2p_ps_offload->discovery = 0;
  518. }
  519. break;
  520. case P2P_PS_SCAN:
  521. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN\n");
  522. p2p_ps_offload->discovery = 1;
  523. break;
  524. case P2P_PS_SCAN_DONE:
  525. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN_DONE\n");
  526. p2p_ps_offload->discovery = 0;
  527. p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
  528. break;
  529. default:
  530. break;
  531. }
  532. rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_P2P_PS_OFFLOAD, 1,
  533. (u8 *)p2p_ps_offload);
  534. }
  535. void rtl8723be_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
  536. {
  537. u8 u1_joinbssrpt_parm[1] = { 0 };
  538. SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
  539. rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_JOINBSSRPT, 1,
  540. u1_joinbssrpt_parm);
  541. }
  542. void rtl8723be_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw,
  543. u8 ap_offload_enable)
  544. {
  545. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  546. u8 u1_apoffload_parm[H2C_8723BE_AP_OFFLOAD_LENGTH] = { 0 };
  547. SET_H2CCMD_AP_OFFLOAD_ON(u1_apoffload_parm, ap_offload_enable);
  548. SET_H2CCMD_AP_OFFLOAD_HIDDEN(u1_apoffload_parm, mac->hiddenssid);
  549. SET_H2CCMD_AP_OFFLOAD_DENYANY(u1_apoffload_parm, 0);
  550. rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_AP_OFFLOAD,
  551. H2C_8723BE_AP_OFFLOAD_LENGTH, u1_apoffload_parm);
  552. }