fw.c 19 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. ****************************************************************************
  29. */
  30. #include "../wifi.h"
  31. #include "../pci.h"
  32. #include "../base.h"
  33. #include "reg.h"
  34. #include "def.h"
  35. #include "fw.h"
  36. #include "../rtl8723com/fw_common.h"
  37. static bool rtl8723ae_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
  38. {
  39. struct rtl_priv *rtlpriv = rtl_priv(hw);
  40. u8 val_hmetfr, val_mcutst_1;
  41. bool result = false;
  42. val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
  43. val_mcutst_1 = rtl_read_byte(rtlpriv, (REG_MCUTST_1 + boxnum));
  44. if (((val_hmetfr >> boxnum) & BIT(0)) == 0 && val_mcutst_1 == 0)
  45. result = true;
  46. return result;
  47. }
  48. static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
  49. u8 element_id, u32 cmd_len,
  50. u8 *p_cmdbuffer)
  51. {
  52. struct rtl_priv *rtlpriv = rtl_priv(hw);
  53. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  54. u8 boxnum;
  55. u16 box_reg = 0, box_extreg = 0;
  56. u8 u1tmp;
  57. bool isfw_rd = false;
  58. bool bwrite_success = false;
  59. u8 wait_h2c_limmit = 100;
  60. u8 wait_writeh2c_limmit = 100;
  61. u8 boxcontent[4], boxextcontent[2];
  62. u32 h2c_waitcounter = 0;
  63. unsigned long flag;
  64. u8 idx;
  65. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n");
  66. while (true) {
  67. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  68. if (rtlhal->h2c_setinprogress) {
  69. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  70. "H2C set in progress! Wait to set..element_id(%d).\n",
  71. element_id);
  72. while (rtlhal->h2c_setinprogress) {
  73. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
  74. flag);
  75. h2c_waitcounter++;
  76. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  77. "Wait 100 us (%d times)...\n",
  78. h2c_waitcounter);
  79. udelay(100);
  80. if (h2c_waitcounter > 1000)
  81. return;
  82. spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
  83. flag);
  84. }
  85. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  86. } else {
  87. rtlhal->h2c_setinprogress = true;
  88. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  89. break;
  90. }
  91. }
  92. while (!bwrite_success) {
  93. wait_writeh2c_limmit--;
  94. if (wait_writeh2c_limmit == 0) {
  95. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  96. "Write H2C fail because no trigger "
  97. "for FW INT!\n");
  98. break;
  99. }
  100. boxnum = rtlhal->last_hmeboxnum;
  101. switch (boxnum) {
  102. case 0:
  103. box_reg = REG_HMEBOX_0;
  104. box_extreg = REG_HMEBOX_EXT_0;
  105. break;
  106. case 1:
  107. box_reg = REG_HMEBOX_1;
  108. box_extreg = REG_HMEBOX_EXT_1;
  109. break;
  110. case 2:
  111. box_reg = REG_HMEBOX_2;
  112. box_extreg = REG_HMEBOX_EXT_2;
  113. break;
  114. case 3:
  115. box_reg = REG_HMEBOX_3;
  116. box_extreg = REG_HMEBOX_EXT_3;
  117. break;
  118. default:
  119. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  120. "switch case not processed\n");
  121. break;
  122. }
  123. isfw_rd = rtl8723ae_check_fw_read_last_h2c(hw, boxnum);
  124. while (!isfw_rd) {
  125. wait_h2c_limmit--;
  126. if (wait_h2c_limmit == 0) {
  127. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  128. "Waiting too long for FW read clear HMEBox(%d)!\n",
  129. boxnum);
  130. break;
  131. }
  132. udelay(10);
  133. isfw_rd = rtl8723ae_check_fw_read_last_h2c(hw, boxnum);
  134. u1tmp = rtl_read_byte(rtlpriv, 0x1BF);
  135. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  136. "Waiting for FW read clear HMEBox(%d)!!! "
  137. "0x1BF = %2x\n", boxnum, u1tmp);
  138. }
  139. if (!isfw_rd) {
  140. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  141. "Write H2C register BOX[%d] fail!!!!! "
  142. "Fw do not read.\n", boxnum);
  143. break;
  144. }
  145. memset(boxcontent, 0, sizeof(boxcontent));
  146. memset(boxextcontent, 0, sizeof(boxextcontent));
  147. boxcontent[0] = element_id;
  148. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  149. "Write element_id box_reg(%4x) = %2x\n",
  150. box_reg, element_id);
  151. switch (cmd_len) {
  152. case 1:
  153. boxcontent[0] &= ~(BIT(7));
  154. memcpy((u8 *) (boxcontent) + 1,
  155. p_cmdbuffer, 1);
  156. for (idx = 0; idx < 4; idx++) {
  157. rtl_write_byte(rtlpriv, box_reg + idx,
  158. boxcontent[idx]);
  159. }
  160. break;
  161. case 2:
  162. boxcontent[0] &= ~(BIT(7));
  163. memcpy((u8 *) (boxcontent) + 1,
  164. p_cmdbuffer, 2);
  165. for (idx = 0; idx < 4; idx++) {
  166. rtl_write_byte(rtlpriv, box_reg + idx,
  167. boxcontent[idx]);
  168. }
  169. break;
  170. case 3:
  171. boxcontent[0] &= ~(BIT(7));
  172. memcpy((u8 *) (boxcontent) + 1,
  173. p_cmdbuffer, 3);
  174. for (idx = 0; idx < 4; idx++) {
  175. rtl_write_byte(rtlpriv, box_reg + idx,
  176. boxcontent[idx]);
  177. }
  178. break;
  179. case 4:
  180. boxcontent[0] |= (BIT(7));
  181. memcpy((u8 *) (boxextcontent),
  182. p_cmdbuffer, 2);
  183. memcpy((u8 *) (boxcontent) + 1,
  184. p_cmdbuffer + 2, 2);
  185. for (idx = 0; idx < 2; idx++) {
  186. rtl_write_byte(rtlpriv, box_extreg + idx,
  187. boxextcontent[idx]);
  188. }
  189. for (idx = 0; idx < 4; idx++) {
  190. rtl_write_byte(rtlpriv, box_reg + idx,
  191. boxcontent[idx]);
  192. }
  193. break;
  194. case 5:
  195. boxcontent[0] |= (BIT(7));
  196. memcpy((u8 *) (boxextcontent),
  197. p_cmdbuffer, 2);
  198. memcpy((u8 *) (boxcontent) + 1,
  199. p_cmdbuffer + 2, 3);
  200. for (idx = 0; idx < 2; idx++) {
  201. rtl_write_byte(rtlpriv, box_extreg + idx,
  202. boxextcontent[idx]);
  203. }
  204. for (idx = 0; idx < 4; idx++) {
  205. rtl_write_byte(rtlpriv, box_reg + idx,
  206. boxcontent[idx]);
  207. }
  208. break;
  209. default:
  210. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  211. "switch case not process\n");
  212. break;
  213. }
  214. bwrite_success = true;
  215. rtlhal->last_hmeboxnum = boxnum + 1;
  216. if (rtlhal->last_hmeboxnum == 4)
  217. rtlhal->last_hmeboxnum = 0;
  218. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  219. "pHalData->last_hmeboxnum = %d\n",
  220. rtlhal->last_hmeboxnum);
  221. }
  222. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  223. rtlhal->h2c_setinprogress = false;
  224. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  225. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
  226. }
  227. void rtl8723ae_fill_h2c_cmd(struct ieee80211_hw *hw,
  228. u8 element_id, u32 cmd_len, u8 *p_cmdbuffer)
  229. {
  230. struct rtl_priv *rtlpriv = rtl_priv(hw);
  231. struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
  232. if (rtlhal->fw_ready == false) {
  233. RT_ASSERT(false,
  234. "return H2C cmd because of Fw download fail!!!\n");
  235. return;
  236. }
  237. _rtl8723ae_fill_h2c_command(hw, element_id, cmd_len, p_cmdbuffer);
  238. return;
  239. }
  240. static bool _rtl8723ae_cmd_send_packet(struct ieee80211_hw *hw,
  241. struct sk_buff *skb)
  242. {
  243. struct rtl_priv *rtlpriv = rtl_priv(hw);
  244. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  245. struct rtl8192_tx_ring *ring;
  246. struct rtl_tx_desc *pdesc;
  247. unsigned long flags;
  248. struct sk_buff *pskb = NULL;
  249. ring = &rtlpci->tx_ring[BEACON_QUEUE];
  250. pskb = __skb_dequeue(&ring->queue);
  251. if (pskb)
  252. kfree_skb(pskb);
  253. spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  254. pdesc = &ring->desc[0];
  255. rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
  256. __skb_queue_tail(&ring->queue, skb);
  257. spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  258. rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
  259. return true;
  260. }
  261. static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
  262. /* page 0 beacon */
  263. 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
  264. 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  265. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x50, 0x08,
  266. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  267. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  268. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  269. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  270. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  271. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  272. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  273. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  274. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  275. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  276. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  277. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  278. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  279. /* page 1 beacon */
  280. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  281. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  282. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  283. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  284. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  285. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  286. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  287. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  288. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  289. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  290. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  291. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  292. 0x10, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x10, 0x00,
  293. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  294. 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  295. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  296. /* page 2 ps-poll */
  297. 0xA4, 0x10, 0x01, 0xC0, 0x00, 0x40, 0x10, 0x10,
  298. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  299. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  300. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  301. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  302. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  303. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  304. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  305. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  306. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  307. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  308. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  309. 0x18, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  310. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  311. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  312. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  313. /* page 3 null */
  314. 0x48, 0x01, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  315. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  316. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  317. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  318. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  319. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  320. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  321. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  322. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  323. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  324. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  325. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  326. 0x72, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  327. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  328. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  329. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  330. /* page 4 probe_resp */
  331. 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  332. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  333. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  334. 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
  335. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  336. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  337. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  338. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  339. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  340. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  341. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  342. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  343. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  344. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  345. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  346. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  347. /* page 5 probe_resp */
  348. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  349. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  350. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  351. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  352. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  353. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  354. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  355. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  356. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  357. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  358. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  359. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  360. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  361. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  362. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  363. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  364. };
  365. void rtl8723ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished)
  366. {
  367. struct rtl_priv *rtlpriv = rtl_priv(hw);
  368. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  369. struct sk_buff *skb = NULL;
  370. u32 totalpacketlen;
  371. bool rtstatus;
  372. u8 u1RsvdPageLoc[3] = { 0 };
  373. bool dlok = false;
  374. u8 *beacon;
  375. u8 *p_pspoll;
  376. u8 *nullfunc;
  377. u8 *p_probersp;
  378. /*---------------------------------------------------------
  379. (1) beacon
  380. ---------------------------------------------------------
  381. */
  382. beacon = &reserved_page_packet[BEACON_PG * 128];
  383. SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
  384. SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
  385. /*-------------------------------------------------------
  386. (2) ps-poll
  387. --------------------------------------------------------
  388. */
  389. p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
  390. SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
  391. SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
  392. SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
  393. SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
  394. /*--------------------------------------------------------
  395. (3) null data
  396. ---------------------------------------------------------i
  397. */
  398. nullfunc = &reserved_page_packet[NULL_PG * 128];
  399. SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
  400. SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
  401. SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
  402. SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
  403. /*---------------------------------------------------------
  404. (4) probe response
  405. ----------------------------------------------------------
  406. */
  407. p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
  408. SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
  409. SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
  410. SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
  411. SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG);
  412. totalpacketlen = TOTAL_RESERVED_PKT_LEN;
  413. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
  414. "rtl8723ae_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  415. &reserved_page_packet[0], totalpacketlen);
  416. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  417. "rtl8723ae_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  418. u1RsvdPageLoc, 3);
  419. skb = dev_alloc_skb(totalpacketlen);
  420. memcpy((u8 *) skb_put(skb, totalpacketlen),
  421. &reserved_page_packet, totalpacketlen);
  422. rtstatus = _rtl8723ae_cmd_send_packet(hw, skb);
  423. if (rtstatus)
  424. dlok = true;
  425. if (dlok) {
  426. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  427. "Set RSVD page location to Fw.\n");
  428. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  429. "H2C_RSVDPAGE:\n",
  430. u1RsvdPageLoc, 3);
  431. rtl8723ae_fill_h2c_cmd(hw, H2C_RSVDPAGE,
  432. sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
  433. } else
  434. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  435. "Set RSVD page location to Fw FAIL!!!!!!.\n");
  436. }
  437. void rtl8723ae_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
  438. {
  439. u8 u1_joinbssrpt_parm[1] = { 0 };
  440. SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
  441. rtl8723ae_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm);
  442. }
  443. static void rtl8723e_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw,
  444. u8 ctwindow)
  445. {
  446. u8 u1_ctwindow_period[1] = {ctwindow};
  447. rtl8723ae_fill_h2c_cmd(hw, H2C_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
  448. }
  449. void rtl8723ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
  450. {
  451. struct rtl_priv *rtlpriv = rtl_priv(hw);
  452. struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
  453. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  454. struct rtl_p2p_ps_info *p2pinfo = &(rtlps->p2p_ps_info);
  455. struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
  456. u8 i;
  457. u16 ctwindow;
  458. u32 start_time, tsf_low;
  459. switch (p2p_ps_state) {
  460. case P2P_PS_DISABLE:
  461. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
  462. memset(p2p_ps_offload, 0, sizeof(struct p2p_ps_offload_t));
  463. break;
  464. case P2P_PS_ENABLE:
  465. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
  466. /* update CTWindow value. */
  467. if (p2pinfo->ctwindow > 0) {
  468. p2p_ps_offload->ctwindow_en = 1;
  469. ctwindow = p2pinfo->ctwindow;
  470. rtl8723e_set_p2p_ctw_period_cmd(hw, ctwindow);
  471. }
  472. /* hw only support 2 set of NoA */
  473. for (i = 0; i < p2pinfo->noa_num; i++) {
  474. /* To control the register setting for which NOA*/
  475. rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
  476. if (i == 0)
  477. p2p_ps_offload->noa0_en = 1;
  478. else
  479. p2p_ps_offload->noa1_en = 1;
  480. /* config P2P NoA Descriptor Register */
  481. rtl_write_dword(rtlpriv, 0x5E0,
  482. p2pinfo->noa_duration[i]);
  483. rtl_write_dword(rtlpriv, 0x5E4,
  484. p2pinfo->noa_interval[i]);
  485. /*Get Current TSF value */
  486. tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
  487. start_time = p2pinfo->noa_start_time[i];
  488. if (p2pinfo->noa_count_type[i] != 1) {
  489. while (start_time <= (tsf_low+(50*1024))) {
  490. start_time += p2pinfo->noa_interval[i];
  491. if (p2pinfo->noa_count_type[i] != 255)
  492. p2pinfo->noa_count_type[i]--;
  493. }
  494. }
  495. rtl_write_dword(rtlpriv, 0x5E8, start_time);
  496. rtl_write_dword(rtlpriv, 0x5EC,
  497. p2pinfo->noa_count_type[i]);
  498. }
  499. if ((p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0)) {
  500. /* rst p2p circuit */
  501. rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
  502. p2p_ps_offload->offload_en = 1;
  503. if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
  504. p2p_ps_offload->role = 1;
  505. p2p_ps_offload->allstasleep = 0;
  506. } else {
  507. p2p_ps_offload->role = 0;
  508. }
  509. p2p_ps_offload->discovery = 0;
  510. }
  511. break;
  512. case P2P_PS_SCAN:
  513. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN\n");
  514. p2p_ps_offload->discovery = 1;
  515. break;
  516. case P2P_PS_SCAN_DONE:
  517. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN_DONE\n");
  518. p2p_ps_offload->discovery = 0;
  519. p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
  520. break;
  521. default:
  522. break;
  523. }
  524. rtl8723ae_fill_h2c_cmd(hw, H2C_P2P_PS_OFFLOAD, 1, (u8 *)p2p_ps_offload);
  525. }
  526. void rtl8723ae_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
  527. {
  528. struct rtl_priv *rtlpriv = rtl_priv(hw);
  529. u8 u1_h2c_set_pwrmode[3] = { 0 };
  530. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  531. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
  532. SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, mode);
  533. SET_H2CCMD_PWRMODE_PARM_SMART_PS_23A(u1_h2c_set_pwrmode,
  534. (rtlpriv->mac80211.p2p) ?
  535. ppsc->smart_ps : 1);
  536. SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1_h2c_set_pwrmode,
  537. ppsc->reg_max_lps_awakeintvl);
  538. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  539. "rtl8723ae_set_fw_rsvdpagepkt(): u1_h2c_set_pwrmode\n",
  540. u1_h2c_set_pwrmode, 3);
  541. rtl8723ae_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode);
  542. }