init.c 45 KB

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  1. /*
  2. * Copyright (c) 2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18. #include <linux/moduleparam.h>
  19. #include <linux/errno.h>
  20. #include <linux/export.h>
  21. #include <linux/of.h>
  22. #include <linux/mmc/sdio_func.h>
  23. #include <linux/vmalloc.h>
  24. #include "core.h"
  25. #include "cfg80211.h"
  26. #include "target.h"
  27. #include "debug.h"
  28. #include "hif-ops.h"
  29. #include "htc-ops.h"
  30. static const struct ath6kl_hw hw_list[] = {
  31. {
  32. .id = AR6003_HW_2_0_VERSION,
  33. .name = "ar6003 hw 2.0",
  34. .dataset_patch_addr = 0x57e884,
  35. .app_load_addr = 0x543180,
  36. .board_ext_data_addr = 0x57e500,
  37. .reserved_ram_size = 6912,
  38. .refclk_hz = 26000000,
  39. .uarttx_pin = 8,
  40. .flags = ATH6KL_HW_SDIO_CRC_ERROR_WAR,
  41. /* hw2.0 needs override address hardcoded */
  42. .app_start_override_addr = 0x944C00,
  43. .fw = {
  44. .dir = AR6003_HW_2_0_FW_DIR,
  45. .otp = AR6003_HW_2_0_OTP_FILE,
  46. .fw = AR6003_HW_2_0_FIRMWARE_FILE,
  47. .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE,
  48. .patch = AR6003_HW_2_0_PATCH_FILE,
  49. },
  50. .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE,
  51. .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE,
  52. },
  53. {
  54. .id = AR6003_HW_2_1_1_VERSION,
  55. .name = "ar6003 hw 2.1.1",
  56. .dataset_patch_addr = 0x57ff74,
  57. .app_load_addr = 0x1234,
  58. .board_ext_data_addr = 0x542330,
  59. .reserved_ram_size = 512,
  60. .refclk_hz = 26000000,
  61. .uarttx_pin = 8,
  62. .testscript_addr = 0x57ef74,
  63. .flags = ATH6KL_HW_SDIO_CRC_ERROR_WAR,
  64. .fw = {
  65. .dir = AR6003_HW_2_1_1_FW_DIR,
  66. .otp = AR6003_HW_2_1_1_OTP_FILE,
  67. .fw = AR6003_HW_2_1_1_FIRMWARE_FILE,
  68. .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE,
  69. .patch = AR6003_HW_2_1_1_PATCH_FILE,
  70. .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE,
  71. .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE,
  72. },
  73. .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE,
  74. .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE,
  75. },
  76. {
  77. .id = AR6004_HW_1_0_VERSION,
  78. .name = "ar6004 hw 1.0",
  79. .dataset_patch_addr = 0x57e884,
  80. .app_load_addr = 0x1234,
  81. .board_ext_data_addr = 0x437000,
  82. .reserved_ram_size = 19456,
  83. .board_addr = 0x433900,
  84. .refclk_hz = 26000000,
  85. .uarttx_pin = 11,
  86. .flags = ATH6KL_HW_64BIT_RATES |
  87. ATH6KL_HW_AP_INACTIVITY_MINS,
  88. .fw = {
  89. .dir = AR6004_HW_1_0_FW_DIR,
  90. .fw = AR6004_HW_1_0_FIRMWARE_FILE,
  91. },
  92. .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE,
  93. .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE,
  94. },
  95. {
  96. .id = AR6004_HW_1_1_VERSION,
  97. .name = "ar6004 hw 1.1",
  98. .dataset_patch_addr = 0x57e884,
  99. .app_load_addr = 0x1234,
  100. .board_ext_data_addr = 0x437000,
  101. .reserved_ram_size = 11264,
  102. .board_addr = 0x43d400,
  103. .refclk_hz = 40000000,
  104. .uarttx_pin = 11,
  105. .flags = ATH6KL_HW_64BIT_RATES |
  106. ATH6KL_HW_AP_INACTIVITY_MINS,
  107. .fw = {
  108. .dir = AR6004_HW_1_1_FW_DIR,
  109. .fw = AR6004_HW_1_1_FIRMWARE_FILE,
  110. },
  111. .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE,
  112. .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE,
  113. },
  114. {
  115. .id = AR6004_HW_1_2_VERSION,
  116. .name = "ar6004 hw 1.2",
  117. .dataset_patch_addr = 0x436ecc,
  118. .app_load_addr = 0x1234,
  119. .board_ext_data_addr = 0x437000,
  120. .reserved_ram_size = 9216,
  121. .board_addr = 0x435c00,
  122. .refclk_hz = 40000000,
  123. .uarttx_pin = 11,
  124. .flags = ATH6KL_HW_64BIT_RATES |
  125. ATH6KL_HW_AP_INACTIVITY_MINS,
  126. .fw = {
  127. .dir = AR6004_HW_1_2_FW_DIR,
  128. .fw = AR6004_HW_1_2_FIRMWARE_FILE,
  129. },
  130. .fw_board = AR6004_HW_1_2_BOARD_DATA_FILE,
  131. .fw_default_board = AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE,
  132. },
  133. {
  134. .id = AR6004_HW_1_3_VERSION,
  135. .name = "ar6004 hw 1.3",
  136. .dataset_patch_addr = 0x437860,
  137. .app_load_addr = 0x1234,
  138. .board_ext_data_addr = 0x437000,
  139. .reserved_ram_size = 7168,
  140. .board_addr = 0x436400,
  141. .refclk_hz = 40000000,
  142. .uarttx_pin = 11,
  143. .flags = ATH6KL_HW_64BIT_RATES |
  144. ATH6KL_HW_AP_INACTIVITY_MINS |
  145. ATH6KL_HW_MAP_LP_ENDPOINT,
  146. .fw = {
  147. .dir = AR6004_HW_1_3_FW_DIR,
  148. .fw = AR6004_HW_1_3_FIRMWARE_FILE,
  149. },
  150. .fw_board = AR6004_HW_1_3_BOARD_DATA_FILE,
  151. .fw_default_board = AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE,
  152. },
  153. };
  154. /*
  155. * Include definitions here that can be used to tune the WLAN module
  156. * behavior. Different customers can tune the behavior as per their needs,
  157. * here.
  158. */
  159. /*
  160. * This configuration item enable/disable keepalive support.
  161. * Keepalive support: In the absence of any data traffic to AP, null
  162. * frames will be sent to the AP at periodic interval, to keep the association
  163. * active. This configuration item defines the periodic interval.
  164. * Use value of zero to disable keepalive support
  165. * Default: 60 seconds
  166. */
  167. #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60
  168. /*
  169. * This configuration item sets the value of disconnect timeout
  170. * Firmware delays sending the disconnec event to the host for this
  171. * timeout after is gets disconnected from the current AP.
  172. * If the firmware successly roams within the disconnect timeout
  173. * it sends a new connect event
  174. */
  175. #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10
  176. #define ATH6KL_DATA_OFFSET 64
  177. struct sk_buff *ath6kl_buf_alloc(int size)
  178. {
  179. struct sk_buff *skb;
  180. u16 reserved;
  181. /* Add chacheline space at front and back of buffer */
  182. reserved = roundup((2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET +
  183. sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES, 4);
  184. skb = dev_alloc_skb(size + reserved);
  185. if (skb)
  186. skb_reserve(skb, reserved - L1_CACHE_BYTES);
  187. return skb;
  188. }
  189. void ath6kl_init_profile_info(struct ath6kl_vif *vif)
  190. {
  191. vif->ssid_len = 0;
  192. memset(vif->ssid, 0, sizeof(vif->ssid));
  193. vif->dot11_auth_mode = OPEN_AUTH;
  194. vif->auth_mode = NONE_AUTH;
  195. vif->prwise_crypto = NONE_CRYPT;
  196. vif->prwise_crypto_len = 0;
  197. vif->grp_crypto = NONE_CRYPT;
  198. vif->grp_crypto_len = 0;
  199. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  200. memset(vif->req_bssid, 0, sizeof(vif->req_bssid));
  201. memset(vif->bssid, 0, sizeof(vif->bssid));
  202. vif->bss_ch = 0;
  203. }
  204. static int ath6kl_set_host_app_area(struct ath6kl *ar)
  205. {
  206. u32 address, data;
  207. struct host_app_area host_app_area;
  208. /* Fetch the address of the host_app_area_s
  209. * instance in the host interest area */
  210. address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest));
  211. address = TARG_VTOP(ar->target_type, address);
  212. if (ath6kl_diag_read32(ar, address, &data))
  213. return -EIO;
  214. address = TARG_VTOP(ar->target_type, data);
  215. host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION);
  216. if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area,
  217. sizeof(struct host_app_area)))
  218. return -EIO;
  219. return 0;
  220. }
  221. static inline void set_ac2_ep_map(struct ath6kl *ar,
  222. u8 ac,
  223. enum htc_endpoint_id ep)
  224. {
  225. ar->ac2ep_map[ac] = ep;
  226. ar->ep2ac_map[ep] = ac;
  227. }
  228. /* connect to a service */
  229. static int ath6kl_connectservice(struct ath6kl *ar,
  230. struct htc_service_connect_req *con_req,
  231. char *desc)
  232. {
  233. int status;
  234. struct htc_service_connect_resp response;
  235. memset(&response, 0, sizeof(response));
  236. status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response);
  237. if (status) {
  238. ath6kl_err("failed to connect to %s service status:%d\n",
  239. desc, status);
  240. return status;
  241. }
  242. switch (con_req->svc_id) {
  243. case WMI_CONTROL_SVC:
  244. if (test_bit(WMI_ENABLED, &ar->flag))
  245. ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint);
  246. ar->ctrl_ep = response.endpoint;
  247. break;
  248. case WMI_DATA_BE_SVC:
  249. set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint);
  250. break;
  251. case WMI_DATA_BK_SVC:
  252. set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint);
  253. break;
  254. case WMI_DATA_VI_SVC:
  255. set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint);
  256. break;
  257. case WMI_DATA_VO_SVC:
  258. set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint);
  259. break;
  260. default:
  261. ath6kl_err("service id is not mapped %d\n", con_req->svc_id);
  262. return -EINVAL;
  263. }
  264. return 0;
  265. }
  266. static int ath6kl_init_service_ep(struct ath6kl *ar)
  267. {
  268. struct htc_service_connect_req connect;
  269. memset(&connect, 0, sizeof(connect));
  270. /* these fields are the same for all service endpoints */
  271. connect.ep_cb.tx_comp_multi = ath6kl_tx_complete;
  272. connect.ep_cb.rx = ath6kl_rx;
  273. connect.ep_cb.rx_refill = ath6kl_rx_refill;
  274. connect.ep_cb.tx_full = ath6kl_tx_queue_full;
  275. /*
  276. * Set the max queue depth so that our ath6kl_tx_queue_full handler
  277. * gets called.
  278. */
  279. connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
  280. connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4;
  281. if (!connect.ep_cb.rx_refill_thresh)
  282. connect.ep_cb.rx_refill_thresh++;
  283. /* connect to control service */
  284. connect.svc_id = WMI_CONTROL_SVC;
  285. if (ath6kl_connectservice(ar, &connect, "WMI CONTROL"))
  286. return -EIO;
  287. connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN;
  288. /*
  289. * Limit the HTC message size on the send path, although e can
  290. * receive A-MSDU frames of 4K, we will only send ethernet-sized
  291. * (802.3) frames on the send path.
  292. */
  293. connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH;
  294. /*
  295. * To reduce the amount of committed memory for larger A_MSDU
  296. * frames, use the recv-alloc threshold mechanism for larger
  297. * packets.
  298. */
  299. connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE;
  300. connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf;
  301. /*
  302. * For the remaining data services set the connection flag to
  303. * reduce dribbling, if configured to do so.
  304. */
  305. connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB;
  306. connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK;
  307. connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF;
  308. connect.svc_id = WMI_DATA_BE_SVC;
  309. if (ath6kl_connectservice(ar, &connect, "WMI DATA BE"))
  310. return -EIO;
  311. /* connect to back-ground map this to WMI LOW_PRI */
  312. connect.svc_id = WMI_DATA_BK_SVC;
  313. if (ath6kl_connectservice(ar, &connect, "WMI DATA BK"))
  314. return -EIO;
  315. /* connect to Video service, map this to HI PRI */
  316. connect.svc_id = WMI_DATA_VI_SVC;
  317. if (ath6kl_connectservice(ar, &connect, "WMI DATA VI"))
  318. return -EIO;
  319. /*
  320. * Connect to VO service, this is currently not mapped to a WMI
  321. * priority stream due to historical reasons. WMI originally
  322. * defined 3 priorities over 3 mailboxes We can change this when
  323. * WMI is reworked so that priorities are not dependent on
  324. * mailboxes.
  325. */
  326. connect.svc_id = WMI_DATA_VO_SVC;
  327. if (ath6kl_connectservice(ar, &connect, "WMI DATA VO"))
  328. return -EIO;
  329. return 0;
  330. }
  331. void ath6kl_init_control_info(struct ath6kl_vif *vif)
  332. {
  333. ath6kl_init_profile_info(vif);
  334. vif->def_txkey_index = 0;
  335. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  336. vif->ch_hint = 0;
  337. }
  338. /*
  339. * Set HTC/Mbox operational parameters, this can only be called when the
  340. * target is in the BMI phase.
  341. */
  342. static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
  343. u8 htc_ctrl_buf)
  344. {
  345. int status;
  346. u32 blk_size;
  347. blk_size = ar->mbox_info.block_size;
  348. if (htc_ctrl_buf)
  349. blk_size |= ((u32)htc_ctrl_buf) << 16;
  350. /* set the host interest area for the block size */
  351. status = ath6kl_bmi_write_hi32(ar, hi_mbox_io_block_sz, blk_size);
  352. if (status) {
  353. ath6kl_err("bmi_write_memory for IO block size failed\n");
  354. goto out;
  355. }
  356. ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n",
  357. blk_size,
  358. ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz)));
  359. if (mbox_isr_yield_val) {
  360. /* set the host interest area for the mbox ISR yield limit */
  361. status = ath6kl_bmi_write_hi32(ar, hi_mbox_isr_yield_limit,
  362. mbox_isr_yield_val);
  363. if (status) {
  364. ath6kl_err("bmi_write_memory for yield limit failed\n");
  365. goto out;
  366. }
  367. }
  368. out:
  369. return status;
  370. }
  371. static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
  372. {
  373. int ret;
  374. /*
  375. * Configure the device for rx dot11 header rules. "0,0" are the
  376. * default values. Required if checksum offload is needed. Set
  377. * RxMetaVersion to 2.
  378. */
  379. ret = ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx,
  380. ar->rx_meta_ver, 0, 0);
  381. if (ret) {
  382. ath6kl_err("unable to set the rx frame format: %d\n", ret);
  383. return ret;
  384. }
  385. if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) {
  386. ret = ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1,
  387. IGNORE_PS_FAIL_DURING_SCAN);
  388. if (ret) {
  389. ath6kl_err("unable to set power save fail event policy: %d\n",
  390. ret);
  391. return ret;
  392. }
  393. }
  394. if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) {
  395. ret = ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0,
  396. WMI_FOLLOW_BARKER_IN_ERP);
  397. if (ret) {
  398. ath6kl_err("unable to set barker preamble policy: %d\n",
  399. ret);
  400. return ret;
  401. }
  402. }
  403. ret = ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx,
  404. WLAN_CONFIG_KEEP_ALIVE_INTERVAL);
  405. if (ret) {
  406. ath6kl_err("unable to set keep alive interval: %d\n", ret);
  407. return ret;
  408. }
  409. ret = ath6kl_wmi_disctimeout_cmd(ar->wmi, idx,
  410. WLAN_CONFIG_DISCONNECT_TIMEOUT);
  411. if (ret) {
  412. ath6kl_err("unable to set disconnect timeout: %d\n", ret);
  413. return ret;
  414. }
  415. if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) {
  416. ret = ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED);
  417. if (ret) {
  418. ath6kl_err("unable to set txop bursting: %d\n", ret);
  419. return ret;
  420. }
  421. }
  422. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  423. ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx,
  424. P2P_FLAG_CAPABILITIES_REQ |
  425. P2P_FLAG_MACADDR_REQ |
  426. P2P_FLAG_HMODEL_REQ);
  427. if (ret) {
  428. ath6kl_dbg(ATH6KL_DBG_TRC,
  429. "failed to request P2P capabilities (%d) - assuming P2P not supported\n",
  430. ret);
  431. ar->p2p = false;
  432. }
  433. }
  434. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  435. /* Enable Probe Request reporting for P2P */
  436. ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true);
  437. if (ret) {
  438. ath6kl_dbg(ATH6KL_DBG_TRC,
  439. "failed to enable Probe Request reporting (%d)\n",
  440. ret);
  441. }
  442. }
  443. return ret;
  444. }
  445. int ath6kl_configure_target(struct ath6kl *ar)
  446. {
  447. u32 param, ram_reserved_size;
  448. u8 fw_iftype, fw_mode = 0, fw_submode = 0;
  449. int i, status;
  450. param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG);
  451. if (ath6kl_bmi_write_hi32(ar, hi_serial_enable, param)) {
  452. ath6kl_err("bmi_write_memory for uart debug failed\n");
  453. return -EIO;
  454. }
  455. /*
  456. * Note: Even though the firmware interface type is
  457. * chosen as BSS_STA for all three interfaces, can
  458. * be configured to IBSS/AP as long as the fw submode
  459. * remains normal mode (0 - AP, STA and IBSS). But
  460. * due to an target assert in firmware only one interface is
  461. * configured for now.
  462. */
  463. fw_iftype = HI_OPTION_FW_MODE_BSS_STA;
  464. for (i = 0; i < ar->vif_max; i++)
  465. fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS);
  466. /*
  467. * Submodes when fw does not support dynamic interface
  468. * switching:
  469. * vif[0] - AP/STA/IBSS
  470. * vif[1] - "P2P dev"/"P2P GO"/"P2P Client"
  471. * vif[2] - "P2P dev"/"P2P GO"/"P2P Client"
  472. * Otherwise, All the interface are initialized to p2p dev.
  473. */
  474. if (test_bit(ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
  475. ar->fw_capabilities)) {
  476. for (i = 0; i < ar->vif_max; i++)
  477. fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
  478. (i * HI_OPTION_FW_SUBMODE_BITS);
  479. } else {
  480. for (i = 0; i < ar->max_norm_iface; i++)
  481. fw_submode |= HI_OPTION_FW_SUBMODE_NONE <<
  482. (i * HI_OPTION_FW_SUBMODE_BITS);
  483. for (i = ar->max_norm_iface; i < ar->vif_max; i++)
  484. fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
  485. (i * HI_OPTION_FW_SUBMODE_BITS);
  486. if (ar->p2p && ar->vif_max == 1)
  487. fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV;
  488. }
  489. if (ath6kl_bmi_write_hi32(ar, hi_app_host_interest,
  490. HTC_PROTOCOL_VERSION) != 0) {
  491. ath6kl_err("bmi_write_memory for htc version failed\n");
  492. return -EIO;
  493. }
  494. /* set the firmware mode to STA/IBSS/AP */
  495. param = 0;
  496. if (ath6kl_bmi_read_hi32(ar, hi_option_flag, &param) != 0) {
  497. ath6kl_err("bmi_read_memory for setting fwmode failed\n");
  498. return -EIO;
  499. }
  500. param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT);
  501. param |= fw_mode << HI_OPTION_FW_MODE_SHIFT;
  502. param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT;
  503. param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  504. param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  505. if (ath6kl_bmi_write_hi32(ar, hi_option_flag, param) != 0) {
  506. ath6kl_err("bmi_write_memory for setting fwmode failed\n");
  507. return -EIO;
  508. }
  509. ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n");
  510. /*
  511. * Hardcode the address use for the extended board data
  512. * Ideally this should be pre-allocate by the OS at boot time
  513. * But since it is a new feature and board data is loaded
  514. * at init time, we have to workaround this from host.
  515. * It is difficult to patch the firmware boot code,
  516. * but possible in theory.
  517. */
  518. if (ar->target_type == TARGET_TYPE_AR6003) {
  519. param = ar->hw.board_ext_data_addr;
  520. ram_reserved_size = ar->hw.reserved_ram_size;
  521. if (ath6kl_bmi_write_hi32(ar, hi_board_ext_data, param) != 0) {
  522. ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n");
  523. return -EIO;
  524. }
  525. if (ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz,
  526. ram_reserved_size) != 0) {
  527. ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n");
  528. return -EIO;
  529. }
  530. }
  531. /* set the block size for the target */
  532. if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0))
  533. /* use default number of control buffers */
  534. return -EIO;
  535. /* Configure GPIO AR600x UART */
  536. status = ath6kl_bmi_write_hi32(ar, hi_dbg_uart_txpin,
  537. ar->hw.uarttx_pin);
  538. if (status)
  539. return status;
  540. /* Configure target refclk_hz */
  541. status = ath6kl_bmi_write_hi32(ar, hi_refclk_hz, ar->hw.refclk_hz);
  542. if (status)
  543. return status;
  544. return 0;
  545. }
  546. /* firmware upload */
  547. static int ath6kl_get_fw(struct ath6kl *ar, const char *filename,
  548. u8 **fw, size_t *fw_len)
  549. {
  550. const struct firmware *fw_entry;
  551. int ret;
  552. ret = request_firmware(&fw_entry, filename, ar->dev);
  553. if (ret)
  554. return ret;
  555. *fw_len = fw_entry->size;
  556. *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
  557. if (*fw == NULL)
  558. ret = -ENOMEM;
  559. release_firmware(fw_entry);
  560. return ret;
  561. }
  562. #ifdef CONFIG_OF
  563. /*
  564. * Check the device tree for a board-id and use it to construct
  565. * the pathname to the firmware file. Used (for now) to find a
  566. * fallback to the "bdata.bin" file--typically a symlink to the
  567. * appropriate board-specific file.
  568. */
  569. static bool check_device_tree(struct ath6kl *ar)
  570. {
  571. static const char *board_id_prop = "atheros,board-id";
  572. struct device_node *node;
  573. char board_filename[64];
  574. const char *board_id;
  575. int ret;
  576. for_each_compatible_node(node, NULL, "atheros,ath6kl") {
  577. board_id = of_get_property(node, board_id_prop, NULL);
  578. if (board_id == NULL) {
  579. ath6kl_warn("No \"%s\" property on %s node.\n",
  580. board_id_prop, node->name);
  581. continue;
  582. }
  583. snprintf(board_filename, sizeof(board_filename),
  584. "%s/bdata.%s.bin", ar->hw.fw.dir, board_id);
  585. ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board,
  586. &ar->fw_board_len);
  587. if (ret) {
  588. ath6kl_err("Failed to get DT board file %s: %d\n",
  589. board_filename, ret);
  590. continue;
  591. }
  592. return true;
  593. }
  594. return false;
  595. }
  596. #else
  597. static bool check_device_tree(struct ath6kl *ar)
  598. {
  599. return false;
  600. }
  601. #endif /* CONFIG_OF */
  602. static int ath6kl_fetch_board_file(struct ath6kl *ar)
  603. {
  604. const char *filename;
  605. int ret;
  606. if (ar->fw_board != NULL)
  607. return 0;
  608. if (WARN_ON(ar->hw.fw_board == NULL))
  609. return -EINVAL;
  610. filename = ar->hw.fw_board;
  611. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  612. &ar->fw_board_len);
  613. if (ret == 0) {
  614. /* managed to get proper board file */
  615. return 0;
  616. }
  617. if (check_device_tree(ar)) {
  618. /* got board file from device tree */
  619. return 0;
  620. }
  621. /* there was no proper board file, try to use default instead */
  622. ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n",
  623. filename, ret);
  624. filename = ar->hw.fw_default_board;
  625. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  626. &ar->fw_board_len);
  627. if (ret) {
  628. ath6kl_err("Failed to get default board file %s: %d\n",
  629. filename, ret);
  630. return ret;
  631. }
  632. ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n");
  633. ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n");
  634. return 0;
  635. }
  636. static int ath6kl_fetch_otp_file(struct ath6kl *ar)
  637. {
  638. char filename[100];
  639. int ret;
  640. if (ar->fw_otp != NULL)
  641. return 0;
  642. if (ar->hw.fw.otp == NULL) {
  643. ath6kl_dbg(ATH6KL_DBG_BOOT,
  644. "no OTP file configured for this hw\n");
  645. return 0;
  646. }
  647. snprintf(filename, sizeof(filename), "%s/%s",
  648. ar->hw.fw.dir, ar->hw.fw.otp);
  649. ret = ath6kl_get_fw(ar, filename, &ar->fw_otp,
  650. &ar->fw_otp_len);
  651. if (ret) {
  652. ath6kl_err("Failed to get OTP file %s: %d\n",
  653. filename, ret);
  654. return ret;
  655. }
  656. return 0;
  657. }
  658. static int ath6kl_fetch_testmode_file(struct ath6kl *ar)
  659. {
  660. char filename[100];
  661. int ret;
  662. if (ar->testmode == 0)
  663. return 0;
  664. ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode);
  665. if (ar->testmode == 2) {
  666. if (ar->hw.fw.utf == NULL) {
  667. ath6kl_warn("testmode 2 not supported\n");
  668. return -EOPNOTSUPP;
  669. }
  670. snprintf(filename, sizeof(filename), "%s/%s",
  671. ar->hw.fw.dir, ar->hw.fw.utf);
  672. } else {
  673. if (ar->hw.fw.tcmd == NULL) {
  674. ath6kl_warn("testmode 1 not supported\n");
  675. return -EOPNOTSUPP;
  676. }
  677. snprintf(filename, sizeof(filename), "%s/%s",
  678. ar->hw.fw.dir, ar->hw.fw.tcmd);
  679. }
  680. set_bit(TESTMODE, &ar->flag);
  681. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  682. if (ret) {
  683. ath6kl_err("Failed to get testmode %d firmware file %s: %d\n",
  684. ar->testmode, filename, ret);
  685. return ret;
  686. }
  687. return 0;
  688. }
  689. static int ath6kl_fetch_fw_file(struct ath6kl *ar)
  690. {
  691. char filename[100];
  692. int ret;
  693. if (ar->fw != NULL)
  694. return 0;
  695. /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */
  696. if (WARN_ON(ar->hw.fw.fw == NULL))
  697. return -EINVAL;
  698. snprintf(filename, sizeof(filename), "%s/%s",
  699. ar->hw.fw.dir, ar->hw.fw.fw);
  700. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  701. if (ret) {
  702. ath6kl_err("Failed to get firmware file %s: %d\n",
  703. filename, ret);
  704. return ret;
  705. }
  706. return 0;
  707. }
  708. static int ath6kl_fetch_patch_file(struct ath6kl *ar)
  709. {
  710. char filename[100];
  711. int ret;
  712. if (ar->fw_patch != NULL)
  713. return 0;
  714. if (ar->hw.fw.patch == NULL)
  715. return 0;
  716. snprintf(filename, sizeof(filename), "%s/%s",
  717. ar->hw.fw.dir, ar->hw.fw.patch);
  718. ret = ath6kl_get_fw(ar, filename, &ar->fw_patch,
  719. &ar->fw_patch_len);
  720. if (ret) {
  721. ath6kl_err("Failed to get patch file %s: %d\n",
  722. filename, ret);
  723. return ret;
  724. }
  725. return 0;
  726. }
  727. static int ath6kl_fetch_testscript_file(struct ath6kl *ar)
  728. {
  729. char filename[100];
  730. int ret;
  731. if (ar->testmode != 2)
  732. return 0;
  733. if (ar->fw_testscript != NULL)
  734. return 0;
  735. if (ar->hw.fw.testscript == NULL)
  736. return 0;
  737. snprintf(filename, sizeof(filename), "%s/%s",
  738. ar->hw.fw.dir, ar->hw.fw.testscript);
  739. ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript,
  740. &ar->fw_testscript_len);
  741. if (ret) {
  742. ath6kl_err("Failed to get testscript file %s: %d\n",
  743. filename, ret);
  744. return ret;
  745. }
  746. return 0;
  747. }
  748. static int ath6kl_fetch_fw_api1(struct ath6kl *ar)
  749. {
  750. int ret;
  751. ret = ath6kl_fetch_otp_file(ar);
  752. if (ret)
  753. return ret;
  754. ret = ath6kl_fetch_fw_file(ar);
  755. if (ret)
  756. return ret;
  757. ret = ath6kl_fetch_patch_file(ar);
  758. if (ret)
  759. return ret;
  760. ret = ath6kl_fetch_testscript_file(ar);
  761. if (ret)
  762. return ret;
  763. return 0;
  764. }
  765. static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
  766. {
  767. size_t magic_len, len, ie_len;
  768. const struct firmware *fw;
  769. struct ath6kl_fw_ie *hdr;
  770. char filename[100];
  771. const u8 *data;
  772. int ret, ie_id, i, index, bit;
  773. __le32 *val;
  774. snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name);
  775. ret = request_firmware(&fw, filename, ar->dev);
  776. if (ret)
  777. return ret;
  778. data = fw->data;
  779. len = fw->size;
  780. /* magic also includes the null byte, check that as well */
  781. magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1;
  782. if (len < magic_len) {
  783. ret = -EINVAL;
  784. goto out;
  785. }
  786. if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) {
  787. ret = -EINVAL;
  788. goto out;
  789. }
  790. len -= magic_len;
  791. data += magic_len;
  792. /* loop elements */
  793. while (len > sizeof(struct ath6kl_fw_ie)) {
  794. /* hdr is unaligned! */
  795. hdr = (struct ath6kl_fw_ie *) data;
  796. ie_id = le32_to_cpup(&hdr->id);
  797. ie_len = le32_to_cpup(&hdr->len);
  798. len -= sizeof(*hdr);
  799. data += sizeof(*hdr);
  800. if (len < ie_len) {
  801. ret = -EINVAL;
  802. goto out;
  803. }
  804. switch (ie_id) {
  805. case ATH6KL_FW_IE_FW_VERSION:
  806. strlcpy(ar->wiphy->fw_version, data,
  807. sizeof(ar->wiphy->fw_version));
  808. ath6kl_dbg(ATH6KL_DBG_BOOT,
  809. "found fw version %s\n",
  810. ar->wiphy->fw_version);
  811. break;
  812. case ATH6KL_FW_IE_OTP_IMAGE:
  813. ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n",
  814. ie_len);
  815. ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL);
  816. if (ar->fw_otp == NULL) {
  817. ret = -ENOMEM;
  818. goto out;
  819. }
  820. ar->fw_otp_len = ie_len;
  821. break;
  822. case ATH6KL_FW_IE_FW_IMAGE:
  823. ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n",
  824. ie_len);
  825. /* in testmode we already might have a fw file */
  826. if (ar->fw != NULL)
  827. break;
  828. ar->fw = vmalloc(ie_len);
  829. if (ar->fw == NULL) {
  830. ret = -ENOMEM;
  831. goto out;
  832. }
  833. memcpy(ar->fw, data, ie_len);
  834. ar->fw_len = ie_len;
  835. break;
  836. case ATH6KL_FW_IE_PATCH_IMAGE:
  837. ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n",
  838. ie_len);
  839. ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL);
  840. if (ar->fw_patch == NULL) {
  841. ret = -ENOMEM;
  842. goto out;
  843. }
  844. ar->fw_patch_len = ie_len;
  845. break;
  846. case ATH6KL_FW_IE_RESERVED_RAM_SIZE:
  847. val = (__le32 *) data;
  848. ar->hw.reserved_ram_size = le32_to_cpup(val);
  849. ath6kl_dbg(ATH6KL_DBG_BOOT,
  850. "found reserved ram size ie 0x%d\n",
  851. ar->hw.reserved_ram_size);
  852. break;
  853. case ATH6KL_FW_IE_CAPABILITIES:
  854. ath6kl_dbg(ATH6KL_DBG_BOOT,
  855. "found firmware capabilities ie (%zd B)\n",
  856. ie_len);
  857. for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) {
  858. index = i / 8;
  859. bit = i % 8;
  860. if (index == ie_len)
  861. break;
  862. if (data[index] & (1 << bit))
  863. __set_bit(i, ar->fw_capabilities);
  864. }
  865. ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "",
  866. ar->fw_capabilities,
  867. sizeof(ar->fw_capabilities));
  868. break;
  869. case ATH6KL_FW_IE_PATCH_ADDR:
  870. if (ie_len != sizeof(*val))
  871. break;
  872. val = (__le32 *) data;
  873. ar->hw.dataset_patch_addr = le32_to_cpup(val);
  874. ath6kl_dbg(ATH6KL_DBG_BOOT,
  875. "found patch address ie 0x%x\n",
  876. ar->hw.dataset_patch_addr);
  877. break;
  878. case ATH6KL_FW_IE_BOARD_ADDR:
  879. if (ie_len != sizeof(*val))
  880. break;
  881. val = (__le32 *) data;
  882. ar->hw.board_addr = le32_to_cpup(val);
  883. ath6kl_dbg(ATH6KL_DBG_BOOT,
  884. "found board address ie 0x%x\n",
  885. ar->hw.board_addr);
  886. break;
  887. case ATH6KL_FW_IE_VIF_MAX:
  888. if (ie_len != sizeof(*val))
  889. break;
  890. val = (__le32 *) data;
  891. ar->vif_max = min_t(unsigned int, le32_to_cpup(val),
  892. ATH6KL_VIF_MAX);
  893. if (ar->vif_max > 1 && !ar->p2p)
  894. ar->max_norm_iface = 2;
  895. ath6kl_dbg(ATH6KL_DBG_BOOT,
  896. "found vif max ie %d\n", ar->vif_max);
  897. break;
  898. default:
  899. ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n",
  900. le32_to_cpup(&hdr->id));
  901. break;
  902. }
  903. len -= ie_len;
  904. data += ie_len;
  905. };
  906. ret = 0;
  907. out:
  908. release_firmware(fw);
  909. return ret;
  910. }
  911. int ath6kl_init_fetch_firmwares(struct ath6kl *ar)
  912. {
  913. int ret;
  914. ret = ath6kl_fetch_board_file(ar);
  915. if (ret)
  916. return ret;
  917. ret = ath6kl_fetch_testmode_file(ar);
  918. if (ret)
  919. return ret;
  920. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API4_FILE);
  921. if (ret == 0) {
  922. ar->fw_api = 4;
  923. goto out;
  924. }
  925. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE);
  926. if (ret == 0) {
  927. ar->fw_api = 3;
  928. goto out;
  929. }
  930. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE);
  931. if (ret == 0) {
  932. ar->fw_api = 2;
  933. goto out;
  934. }
  935. ret = ath6kl_fetch_fw_api1(ar);
  936. if (ret)
  937. return ret;
  938. ar->fw_api = 1;
  939. out:
  940. ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  941. return 0;
  942. }
  943. static int ath6kl_upload_board_file(struct ath6kl *ar)
  944. {
  945. u32 board_address, board_ext_address, param;
  946. u32 board_data_size, board_ext_data_size;
  947. int ret;
  948. if (WARN_ON(ar->fw_board == NULL))
  949. return -ENOENT;
  950. /*
  951. * Determine where in Target RAM to write Board Data.
  952. * For AR6004, host determine Target RAM address for
  953. * writing board data.
  954. */
  955. if (ar->hw.board_addr != 0) {
  956. board_address = ar->hw.board_addr;
  957. ath6kl_bmi_write_hi32(ar, hi_board_data,
  958. board_address);
  959. } else {
  960. ath6kl_bmi_read_hi32(ar, hi_board_data, &board_address);
  961. }
  962. /* determine where in target ram to write extended board data */
  963. ath6kl_bmi_read_hi32(ar, hi_board_ext_data, &board_ext_address);
  964. if (ar->target_type == TARGET_TYPE_AR6003 &&
  965. board_ext_address == 0) {
  966. ath6kl_err("Failed to get board file target address.\n");
  967. return -EINVAL;
  968. }
  969. switch (ar->target_type) {
  970. case TARGET_TYPE_AR6003:
  971. board_data_size = AR6003_BOARD_DATA_SZ;
  972. board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ;
  973. if (ar->fw_board_len > (board_data_size + board_ext_data_size))
  974. board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ_V2;
  975. break;
  976. case TARGET_TYPE_AR6004:
  977. board_data_size = AR6004_BOARD_DATA_SZ;
  978. board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ;
  979. break;
  980. default:
  981. WARN_ON(1);
  982. return -EINVAL;
  983. break;
  984. }
  985. if (board_ext_address &&
  986. ar->fw_board_len == (board_data_size + board_ext_data_size)) {
  987. /* write extended board data */
  988. ath6kl_dbg(ATH6KL_DBG_BOOT,
  989. "writing extended board data to 0x%x (%d B)\n",
  990. board_ext_address, board_ext_data_size);
  991. ret = ath6kl_bmi_write(ar, board_ext_address,
  992. ar->fw_board + board_data_size,
  993. board_ext_data_size);
  994. if (ret) {
  995. ath6kl_err("Failed to write extended board data: %d\n",
  996. ret);
  997. return ret;
  998. }
  999. /* record that extended board data is initialized */
  1000. param = (board_ext_data_size << 16) | 1;
  1001. ath6kl_bmi_write_hi32(ar, hi_board_ext_data_config, param);
  1002. }
  1003. if (ar->fw_board_len < board_data_size) {
  1004. ath6kl_err("Too small board file: %zu\n", ar->fw_board_len);
  1005. ret = -EINVAL;
  1006. return ret;
  1007. }
  1008. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n",
  1009. board_address, board_data_size);
  1010. ret = ath6kl_bmi_write(ar, board_address, ar->fw_board,
  1011. board_data_size);
  1012. if (ret) {
  1013. ath6kl_err("Board file bmi write failed: %d\n", ret);
  1014. return ret;
  1015. }
  1016. /* record the fact that Board Data IS initialized */
  1017. ath6kl_bmi_write_hi32(ar, hi_board_data_initialized, 1);
  1018. return ret;
  1019. }
  1020. static int ath6kl_upload_otp(struct ath6kl *ar)
  1021. {
  1022. u32 address, param;
  1023. bool from_hw = false;
  1024. int ret;
  1025. if (ar->fw_otp == NULL)
  1026. return 0;
  1027. address = ar->hw.app_load_addr;
  1028. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address,
  1029. ar->fw_otp_len);
  1030. ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp,
  1031. ar->fw_otp_len);
  1032. if (ret) {
  1033. ath6kl_err("Failed to upload OTP file: %d\n", ret);
  1034. return ret;
  1035. }
  1036. /* read firmware start address */
  1037. ret = ath6kl_bmi_read_hi32(ar, hi_app_start, &address);
  1038. if (ret) {
  1039. ath6kl_err("Failed to read hi_app_start: %d\n", ret);
  1040. return ret;
  1041. }
  1042. if (ar->hw.app_start_override_addr == 0) {
  1043. ar->hw.app_start_override_addr = address;
  1044. from_hw = true;
  1045. }
  1046. ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n",
  1047. from_hw ? " (from hw)" : "",
  1048. ar->hw.app_start_override_addr);
  1049. /* execute the OTP code */
  1050. ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n",
  1051. ar->hw.app_start_override_addr);
  1052. param = 0;
  1053. ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, &param);
  1054. return ret;
  1055. }
  1056. static int ath6kl_upload_firmware(struct ath6kl *ar)
  1057. {
  1058. u32 address;
  1059. int ret;
  1060. if (WARN_ON(ar->fw == NULL))
  1061. return 0;
  1062. address = ar->hw.app_load_addr;
  1063. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n",
  1064. address, ar->fw_len);
  1065. ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len);
  1066. if (ret) {
  1067. ath6kl_err("Failed to write firmware: %d\n", ret);
  1068. return ret;
  1069. }
  1070. /*
  1071. * Set starting address for firmware
  1072. * Don't need to setup app_start override addr on AR6004
  1073. */
  1074. if (ar->target_type != TARGET_TYPE_AR6004) {
  1075. address = ar->hw.app_start_override_addr;
  1076. ath6kl_bmi_set_app_start(ar, address);
  1077. }
  1078. return ret;
  1079. }
  1080. static int ath6kl_upload_patch(struct ath6kl *ar)
  1081. {
  1082. u32 address;
  1083. int ret;
  1084. if (ar->fw_patch == NULL)
  1085. return 0;
  1086. address = ar->hw.dataset_patch_addr;
  1087. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n",
  1088. address, ar->fw_patch_len);
  1089. ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len);
  1090. if (ret) {
  1091. ath6kl_err("Failed to write patch file: %d\n", ret);
  1092. return ret;
  1093. }
  1094. ath6kl_bmi_write_hi32(ar, hi_dset_list_head, address);
  1095. return 0;
  1096. }
  1097. static int ath6kl_upload_testscript(struct ath6kl *ar)
  1098. {
  1099. u32 address;
  1100. int ret;
  1101. if (ar->testmode != 2)
  1102. return 0;
  1103. if (ar->fw_testscript == NULL)
  1104. return 0;
  1105. address = ar->hw.testscript_addr;
  1106. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n",
  1107. address, ar->fw_testscript_len);
  1108. ret = ath6kl_bmi_write(ar, address, ar->fw_testscript,
  1109. ar->fw_testscript_len);
  1110. if (ret) {
  1111. ath6kl_err("Failed to write testscript file: %d\n", ret);
  1112. return ret;
  1113. }
  1114. ath6kl_bmi_write_hi32(ar, hi_ota_testscript, address);
  1115. ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 4096);
  1116. ath6kl_bmi_write_hi32(ar, hi_test_apps_related, 1);
  1117. return 0;
  1118. }
  1119. static int ath6kl_init_upload(struct ath6kl *ar)
  1120. {
  1121. u32 param, options, sleep, address;
  1122. int status = 0;
  1123. if (ar->target_type != TARGET_TYPE_AR6003 &&
  1124. ar->target_type != TARGET_TYPE_AR6004)
  1125. return -EINVAL;
  1126. /* temporarily disable system sleep */
  1127. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1128. status = ath6kl_bmi_reg_read(ar, address, &param);
  1129. if (status)
  1130. return status;
  1131. options = param;
  1132. param |= ATH6KL_OPTION_SLEEP_DISABLE;
  1133. status = ath6kl_bmi_reg_write(ar, address, param);
  1134. if (status)
  1135. return status;
  1136. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1137. status = ath6kl_bmi_reg_read(ar, address, &param);
  1138. if (status)
  1139. return status;
  1140. sleep = param;
  1141. param |= SM(SYSTEM_SLEEP_DISABLE, 1);
  1142. status = ath6kl_bmi_reg_write(ar, address, param);
  1143. if (status)
  1144. return status;
  1145. ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n",
  1146. options, sleep);
  1147. /* program analog PLL register */
  1148. /* no need to control 40/44MHz clock on AR6004 */
  1149. if (ar->target_type != TARGET_TYPE_AR6004) {
  1150. status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER,
  1151. 0xF9104001);
  1152. if (status)
  1153. return status;
  1154. /* Run at 80/88MHz by default */
  1155. param = SM(CPU_CLOCK_STANDARD, 1);
  1156. address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
  1157. status = ath6kl_bmi_reg_write(ar, address, param);
  1158. if (status)
  1159. return status;
  1160. }
  1161. param = 0;
  1162. address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
  1163. param = SM(LPO_CAL_ENABLE, 1);
  1164. status = ath6kl_bmi_reg_write(ar, address, param);
  1165. if (status)
  1166. return status;
  1167. /* WAR to avoid SDIO CRC err */
  1168. if (ar->hw.flags & ATH6KL_HW_SDIO_CRC_ERROR_WAR) {
  1169. ath6kl_err("temporary war to avoid sdio crc error\n");
  1170. param = 0x28;
  1171. address = GPIO_BASE_ADDRESS + GPIO_PIN9_ADDRESS;
  1172. status = ath6kl_bmi_reg_write(ar, address, param);
  1173. if (status)
  1174. return status;
  1175. param = 0x20;
  1176. address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
  1177. status = ath6kl_bmi_reg_write(ar, address, param);
  1178. if (status)
  1179. return status;
  1180. address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
  1181. status = ath6kl_bmi_reg_write(ar, address, param);
  1182. if (status)
  1183. return status;
  1184. address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
  1185. status = ath6kl_bmi_reg_write(ar, address, param);
  1186. if (status)
  1187. return status;
  1188. address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
  1189. status = ath6kl_bmi_reg_write(ar, address, param);
  1190. if (status)
  1191. return status;
  1192. }
  1193. /* write EEPROM data to Target RAM */
  1194. status = ath6kl_upload_board_file(ar);
  1195. if (status)
  1196. return status;
  1197. /* transfer One time Programmable data */
  1198. status = ath6kl_upload_otp(ar);
  1199. if (status)
  1200. return status;
  1201. /* Download Target firmware */
  1202. status = ath6kl_upload_firmware(ar);
  1203. if (status)
  1204. return status;
  1205. status = ath6kl_upload_patch(ar);
  1206. if (status)
  1207. return status;
  1208. /* Download the test script */
  1209. status = ath6kl_upload_testscript(ar);
  1210. if (status)
  1211. return status;
  1212. /* Restore system sleep */
  1213. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1214. status = ath6kl_bmi_reg_write(ar, address, sleep);
  1215. if (status)
  1216. return status;
  1217. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1218. param = options | 0x20;
  1219. status = ath6kl_bmi_reg_write(ar, address, param);
  1220. if (status)
  1221. return status;
  1222. return status;
  1223. }
  1224. int ath6kl_init_hw_params(struct ath6kl *ar)
  1225. {
  1226. const struct ath6kl_hw *uninitialized_var(hw);
  1227. int i;
  1228. for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
  1229. hw = &hw_list[i];
  1230. if (hw->id == ar->version.target_ver)
  1231. break;
  1232. }
  1233. if (i == ARRAY_SIZE(hw_list)) {
  1234. ath6kl_err("Unsupported hardware version: 0x%x\n",
  1235. ar->version.target_ver);
  1236. return -EINVAL;
  1237. }
  1238. ar->hw = *hw;
  1239. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1240. "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n",
  1241. ar->version.target_ver, ar->target_type,
  1242. ar->hw.dataset_patch_addr, ar->hw.app_load_addr);
  1243. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1244. "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x",
  1245. ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr,
  1246. ar->hw.reserved_ram_size);
  1247. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1248. "refclk_hz %d uarttx_pin %d",
  1249. ar->hw.refclk_hz, ar->hw.uarttx_pin);
  1250. return 0;
  1251. }
  1252. static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type)
  1253. {
  1254. switch (type) {
  1255. case ATH6KL_HIF_TYPE_SDIO:
  1256. return "sdio";
  1257. case ATH6KL_HIF_TYPE_USB:
  1258. return "usb";
  1259. }
  1260. return NULL;
  1261. }
  1262. static const struct fw_capa_str_map {
  1263. int id;
  1264. const char *name;
  1265. } fw_capa_map[] = {
  1266. { ATH6KL_FW_CAPABILITY_HOST_P2P, "host-p2p" },
  1267. { ATH6KL_FW_CAPABILITY_SCHED_SCAN, "sched-scan" },
  1268. { ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX, "sta-p2pdev-duplex" },
  1269. { ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT, "inactivity-timeout" },
  1270. { ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE, "rsn-cap-override" },
  1271. { ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER, "wow-mc-filter" },
  1272. { ATH6KL_FW_CAPABILITY_BMISS_ENHANCE, "bmiss-enhance" },
  1273. { ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST, "sscan-match-list" },
  1274. { ATH6KL_FW_CAPABILITY_RSSI_SCAN_THOLD, "rssi-scan-thold" },
  1275. { ATH6KL_FW_CAPABILITY_CUSTOM_MAC_ADDR, "custom-mac-addr" },
  1276. { ATH6KL_FW_CAPABILITY_TX_ERR_NOTIFY, "tx-err-notify" },
  1277. { ATH6KL_FW_CAPABILITY_REGDOMAIN, "regdomain" },
  1278. { ATH6KL_FW_CAPABILITY_SCHED_SCAN_V2, "sched-scan-v2" },
  1279. { ATH6KL_FW_CAPABILITY_HEART_BEAT_POLL, "hb-poll" },
  1280. };
  1281. static const char *ath6kl_init_get_fw_capa_name(unsigned int id)
  1282. {
  1283. int i;
  1284. for (i = 0; i < ARRAY_SIZE(fw_capa_map); i++) {
  1285. if (fw_capa_map[i].id == id)
  1286. return fw_capa_map[i].name;
  1287. }
  1288. return "<unknown>";
  1289. }
  1290. static void ath6kl_init_get_fwcaps(struct ath6kl *ar, char *buf, size_t buf_len)
  1291. {
  1292. u8 *data = (u8 *) ar->fw_capabilities;
  1293. size_t trunc_len, len = 0;
  1294. int i, index, bit;
  1295. char *trunc = "...";
  1296. for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) {
  1297. index = i / 8;
  1298. bit = i % 8;
  1299. if (index >= sizeof(ar->fw_capabilities) * 4)
  1300. break;
  1301. if (buf_len - len < 4) {
  1302. ath6kl_warn("firmware capability buffer too small!\n");
  1303. /* add "..." to the end of string */
  1304. trunc_len = strlen(trunc) + 1;
  1305. strncpy(buf + buf_len - trunc_len, trunc, trunc_len);
  1306. return;
  1307. }
  1308. if (data[index] & (1 << bit)) {
  1309. len += scnprintf(buf + len, buf_len - len, "%s,",
  1310. ath6kl_init_get_fw_capa_name(i));
  1311. }
  1312. }
  1313. /* overwrite the last comma */
  1314. if (len > 0)
  1315. len--;
  1316. buf[len] = '\0';
  1317. }
  1318. static int ath6kl_init_hw_reset(struct ath6kl *ar)
  1319. {
  1320. ath6kl_dbg(ATH6KL_DBG_BOOT, "cold resetting the device");
  1321. return ath6kl_diag_write32(ar, RESET_CONTROL_ADDRESS,
  1322. cpu_to_le32(RESET_CONTROL_COLD_RST));
  1323. }
  1324. static int __ath6kl_init_hw_start(struct ath6kl *ar)
  1325. {
  1326. long timeleft;
  1327. int ret, i;
  1328. char buf[200];
  1329. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n");
  1330. ret = ath6kl_hif_power_on(ar);
  1331. if (ret)
  1332. return ret;
  1333. ret = ath6kl_configure_target(ar);
  1334. if (ret)
  1335. goto err_power_off;
  1336. ret = ath6kl_init_upload(ar);
  1337. if (ret)
  1338. goto err_power_off;
  1339. /* Do we need to finish the BMI phase */
  1340. ret = ath6kl_bmi_done(ar);
  1341. if (ret)
  1342. goto err_power_off;
  1343. /*
  1344. * The reason we have to wait for the target here is that the
  1345. * driver layer has to init BMI in order to set the host block
  1346. * size.
  1347. */
  1348. ret = ath6kl_htc_wait_target(ar->htc_target);
  1349. if (ret == -ETIMEDOUT) {
  1350. /*
  1351. * Most likely USB target is in odd state after reboot and
  1352. * needs a reset. A cold reset makes the whole device
  1353. * disappear from USB bus and initialisation starts from
  1354. * beginning.
  1355. */
  1356. ath6kl_warn("htc wait target timed out, resetting device\n");
  1357. ath6kl_init_hw_reset(ar);
  1358. goto err_power_off;
  1359. } else if (ret) {
  1360. ath6kl_err("htc wait target failed: %d\n", ret);
  1361. goto err_power_off;
  1362. }
  1363. ret = ath6kl_init_service_ep(ar);
  1364. if (ret) {
  1365. ath6kl_err("Endpoint service initilisation failed: %d\n", ret);
  1366. goto err_cleanup_scatter;
  1367. }
  1368. /* setup credit distribution */
  1369. ath6kl_htc_credit_setup(ar->htc_target, &ar->credit_state_info);
  1370. /* start HTC */
  1371. ret = ath6kl_htc_start(ar->htc_target);
  1372. if (ret) {
  1373. /* FIXME: call this */
  1374. ath6kl_cookie_cleanup(ar);
  1375. goto err_cleanup_scatter;
  1376. }
  1377. /* Wait for Wmi event to be ready */
  1378. timeleft = wait_event_interruptible_timeout(ar->event_wq,
  1379. test_bit(WMI_READY,
  1380. &ar->flag),
  1381. WMI_TIMEOUT);
  1382. if (timeleft <= 0) {
  1383. clear_bit(WMI_READY, &ar->flag);
  1384. ath6kl_err("wmi is not ready or wait was interrupted: %ld\n",
  1385. timeleft);
  1386. ret = -EIO;
  1387. goto err_htc_stop;
  1388. }
  1389. ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n");
  1390. if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) {
  1391. ath6kl_info("%s %s fw %s api %d%s\n",
  1392. ar->hw.name,
  1393. ath6kl_init_get_hif_name(ar->hif_type),
  1394. ar->wiphy->fw_version,
  1395. ar->fw_api,
  1396. test_bit(TESTMODE, &ar->flag) ? " testmode" : "");
  1397. ath6kl_init_get_fwcaps(ar, buf, sizeof(buf));
  1398. ath6kl_info("firmware supports: %s\n", buf);
  1399. }
  1400. if (ar->version.abi_ver != ATH6KL_ABI_VERSION) {
  1401. ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n",
  1402. ATH6KL_ABI_VERSION, ar->version.abi_ver);
  1403. ret = -EIO;
  1404. goto err_htc_stop;
  1405. }
  1406. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__);
  1407. /* communicate the wmi protocol verision to the target */
  1408. /* FIXME: return error */
  1409. if ((ath6kl_set_host_app_area(ar)) != 0)
  1410. ath6kl_err("unable to set the host app area\n");
  1411. for (i = 0; i < ar->vif_max; i++) {
  1412. ret = ath6kl_target_config_wlan_params(ar, i);
  1413. if (ret)
  1414. goto err_htc_stop;
  1415. }
  1416. return 0;
  1417. err_htc_stop:
  1418. ath6kl_htc_stop(ar->htc_target);
  1419. err_cleanup_scatter:
  1420. ath6kl_hif_cleanup_scatter(ar);
  1421. err_power_off:
  1422. ath6kl_hif_power_off(ar);
  1423. return ret;
  1424. }
  1425. int ath6kl_init_hw_start(struct ath6kl *ar)
  1426. {
  1427. int err;
  1428. err = __ath6kl_init_hw_start(ar);
  1429. if (err)
  1430. return err;
  1431. ar->state = ATH6KL_STATE_ON;
  1432. return 0;
  1433. }
  1434. static int __ath6kl_init_hw_stop(struct ath6kl *ar)
  1435. {
  1436. int ret;
  1437. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n");
  1438. ath6kl_htc_stop(ar->htc_target);
  1439. ath6kl_hif_stop(ar);
  1440. ath6kl_bmi_reset(ar);
  1441. ret = ath6kl_hif_power_off(ar);
  1442. if (ret)
  1443. ath6kl_warn("failed to power off hif: %d\n", ret);
  1444. return 0;
  1445. }
  1446. int ath6kl_init_hw_stop(struct ath6kl *ar)
  1447. {
  1448. int err;
  1449. err = __ath6kl_init_hw_stop(ar);
  1450. if (err)
  1451. return err;
  1452. ar->state = ATH6KL_STATE_OFF;
  1453. return 0;
  1454. }
  1455. void ath6kl_init_hw_restart(struct ath6kl *ar)
  1456. {
  1457. clear_bit(WMI_READY, &ar->flag);
  1458. ath6kl_cfg80211_stop_all(ar);
  1459. if (__ath6kl_init_hw_stop(ar)) {
  1460. ath6kl_dbg(ATH6KL_DBG_RECOVERY, "Failed to stop during fw error recovery\n");
  1461. return;
  1462. }
  1463. if (__ath6kl_init_hw_start(ar)) {
  1464. ath6kl_dbg(ATH6KL_DBG_RECOVERY, "Failed to restart during fw error recovery\n");
  1465. return;
  1466. }
  1467. }
  1468. void ath6kl_stop_txrx(struct ath6kl *ar)
  1469. {
  1470. struct ath6kl_vif *vif, *tmp_vif;
  1471. int i;
  1472. set_bit(DESTROY_IN_PROGRESS, &ar->flag);
  1473. if (down_interruptible(&ar->sem)) {
  1474. ath6kl_err("down_interruptible failed\n");
  1475. return;
  1476. }
  1477. for (i = 0; i < AP_MAX_NUM_STA; i++)
  1478. aggr_reset_state(ar->sta_list[i].aggr_conn);
  1479. spin_lock_bh(&ar->list_lock);
  1480. list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) {
  1481. list_del(&vif->list);
  1482. spin_unlock_bh(&ar->list_lock);
  1483. ath6kl_cfg80211_vif_stop(vif, test_bit(WMI_READY, &ar->flag));
  1484. rtnl_lock();
  1485. ath6kl_cfg80211_vif_cleanup(vif);
  1486. rtnl_unlock();
  1487. spin_lock_bh(&ar->list_lock);
  1488. }
  1489. spin_unlock_bh(&ar->list_lock);
  1490. clear_bit(WMI_READY, &ar->flag);
  1491. if (ar->fw_recovery.enable)
  1492. del_timer_sync(&ar->fw_recovery.hb_timer);
  1493. /*
  1494. * After wmi_shudown all WMI events will be dropped. We
  1495. * need to cleanup the buffers allocated in AP mode and
  1496. * give disconnect notification to stack, which usually
  1497. * happens in the disconnect_event. Simulate the disconnect
  1498. * event by calling the function directly. Sometimes
  1499. * disconnect_event will be received when the debug logs
  1500. * are collected.
  1501. */
  1502. ath6kl_wmi_shutdown(ar->wmi);
  1503. clear_bit(WMI_ENABLED, &ar->flag);
  1504. if (ar->htc_target) {
  1505. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__);
  1506. ath6kl_htc_stop(ar->htc_target);
  1507. }
  1508. /*
  1509. * Try to reset the device if we can. The driver may have been
  1510. * configure NOT to reset the target during a debug session.
  1511. */
  1512. ath6kl_init_hw_reset(ar);
  1513. up(&ar->sem);
  1514. }
  1515. EXPORT_SYMBOL(ath6kl_stop_txrx);