smsc95xx.c 50 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2008 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. *****************************************************************************/
  19. #include <linux/module.h>
  20. #include <linux/kmod.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/etherdevice.h>
  23. #include <linux/ethtool.h>
  24. #include <linux/mii.h>
  25. #include <linux/usb.h>
  26. #include <linux/bitrev.h>
  27. #include <linux/crc16.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include <linux/slab.h>
  31. #include "smsc95xx.h"
  32. #define SMSC_CHIPNAME "smsc95xx"
  33. #define SMSC_DRIVER_VERSION "1.0.4"
  34. #define HS_USB_PKT_SIZE (512)
  35. #define FS_USB_PKT_SIZE (64)
  36. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  37. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  38. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  39. #define MAX_SINGLE_PACKET_SIZE (2048)
  40. #define LAN95XX_EEPROM_MAGIC (0x9500)
  41. #define EEPROM_MAC_OFFSET (0x01)
  42. #define DEFAULT_TX_CSUM_ENABLE (true)
  43. #define DEFAULT_RX_CSUM_ENABLE (true)
  44. #define SMSC95XX_INTERNAL_PHY_ID (1)
  45. #define SMSC95XX_TX_OVERHEAD (8)
  46. #define SMSC95XX_TX_OVERHEAD_CSUM (12)
  47. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  48. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  49. #define FEATURE_8_WAKEUP_FILTERS (0x01)
  50. #define FEATURE_PHY_NLP_CROSSOVER (0x02)
  51. #define FEATURE_REMOTE_WAKEUP (0x04)
  52. #define SUSPEND_SUSPEND0 (0x01)
  53. #define SUSPEND_SUSPEND1 (0x02)
  54. #define SUSPEND_SUSPEND2 (0x04)
  55. #define SUSPEND_SUSPEND3 (0x08)
  56. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  57. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  58. struct smsc95xx_priv {
  59. u32 mac_cr;
  60. u32 hash_hi;
  61. u32 hash_lo;
  62. u32 wolopts;
  63. spinlock_t mac_cr_lock;
  64. u8 features;
  65. u8 suspend_flags;
  66. };
  67. static bool turbo_mode = true;
  68. module_param(turbo_mode, bool, 0644);
  69. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  70. static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
  71. u32 *data, int in_pm)
  72. {
  73. u32 buf;
  74. int ret;
  75. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  76. BUG_ON(!dev);
  77. if (!in_pm)
  78. fn = usbnet_read_cmd;
  79. else
  80. fn = usbnet_read_cmd_nopm;
  81. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  82. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  83. 0, index, &buf, 4);
  84. if (unlikely(ret < 0))
  85. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  86. index, ret);
  87. le32_to_cpus(&buf);
  88. *data = buf;
  89. return ret;
  90. }
  91. static int __must_check __smsc95xx_write_reg(struct usbnet *dev, u32 index,
  92. u32 data, int in_pm)
  93. {
  94. u32 buf;
  95. int ret;
  96. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  97. BUG_ON(!dev);
  98. if (!in_pm)
  99. fn = usbnet_write_cmd;
  100. else
  101. fn = usbnet_write_cmd_nopm;
  102. buf = data;
  103. cpu_to_le32s(&buf);
  104. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  105. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  106. 0, index, &buf, 4);
  107. if (unlikely(ret < 0))
  108. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  109. index, ret);
  110. return ret;
  111. }
  112. static int __must_check smsc95xx_read_reg_nopm(struct usbnet *dev, u32 index,
  113. u32 *data)
  114. {
  115. return __smsc95xx_read_reg(dev, index, data, 1);
  116. }
  117. static int __must_check smsc95xx_write_reg_nopm(struct usbnet *dev, u32 index,
  118. u32 data)
  119. {
  120. return __smsc95xx_write_reg(dev, index, data, 1);
  121. }
  122. static int __must_check smsc95xx_read_reg(struct usbnet *dev, u32 index,
  123. u32 *data)
  124. {
  125. return __smsc95xx_read_reg(dev, index, data, 0);
  126. }
  127. static int __must_check smsc95xx_write_reg(struct usbnet *dev, u32 index,
  128. u32 data)
  129. {
  130. return __smsc95xx_write_reg(dev, index, data, 0);
  131. }
  132. /* Loop until the read is completed with timeout
  133. * called with phy_mutex held */
  134. static int __must_check __smsc95xx_phy_wait_not_busy(struct usbnet *dev,
  135. int in_pm)
  136. {
  137. unsigned long start_time = jiffies;
  138. u32 val;
  139. int ret;
  140. do {
  141. ret = __smsc95xx_read_reg(dev, MII_ADDR, &val, in_pm);
  142. if (ret < 0) {
  143. netdev_warn(dev->net, "Error reading MII_ACCESS\n");
  144. return ret;
  145. }
  146. if (!(val & MII_BUSY_))
  147. return 0;
  148. } while (!time_after(jiffies, start_time + HZ));
  149. return -EIO;
  150. }
  151. static int __smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  152. int in_pm)
  153. {
  154. struct usbnet *dev = netdev_priv(netdev);
  155. u32 val, addr;
  156. int ret;
  157. mutex_lock(&dev->phy_mutex);
  158. /* confirm MII not busy */
  159. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  160. if (ret < 0) {
  161. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_read\n");
  162. goto done;
  163. }
  164. /* set the address, index & direction (read from PHY) */
  165. phy_id &= dev->mii.phy_id_mask;
  166. idx &= dev->mii.reg_num_mask;
  167. addr = (phy_id << 11) | (idx << 6) | MII_READ_ | MII_BUSY_;
  168. ret = __smsc95xx_write_reg(dev, MII_ADDR, addr, in_pm);
  169. if (ret < 0) {
  170. netdev_warn(dev->net, "Error writing MII_ADDR\n");
  171. goto done;
  172. }
  173. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  174. if (ret < 0) {
  175. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  176. goto done;
  177. }
  178. ret = __smsc95xx_read_reg(dev, MII_DATA, &val, in_pm);
  179. if (ret < 0) {
  180. netdev_warn(dev->net, "Error reading MII_DATA\n");
  181. goto done;
  182. }
  183. ret = (u16)(val & 0xFFFF);
  184. done:
  185. mutex_unlock(&dev->phy_mutex);
  186. return ret;
  187. }
  188. static void __smsc95xx_mdio_write(struct net_device *netdev, int phy_id,
  189. int idx, int regval, int in_pm)
  190. {
  191. struct usbnet *dev = netdev_priv(netdev);
  192. u32 val, addr;
  193. int ret;
  194. mutex_lock(&dev->phy_mutex);
  195. /* confirm MII not busy */
  196. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  197. if (ret < 0) {
  198. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_write\n");
  199. goto done;
  200. }
  201. val = regval;
  202. ret = __smsc95xx_write_reg(dev, MII_DATA, val, in_pm);
  203. if (ret < 0) {
  204. netdev_warn(dev->net, "Error writing MII_DATA\n");
  205. goto done;
  206. }
  207. /* set the address, index & direction (write to PHY) */
  208. phy_id &= dev->mii.phy_id_mask;
  209. idx &= dev->mii.reg_num_mask;
  210. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_ | MII_BUSY_;
  211. ret = __smsc95xx_write_reg(dev, MII_ADDR, addr, in_pm);
  212. if (ret < 0) {
  213. netdev_warn(dev->net, "Error writing MII_ADDR\n");
  214. goto done;
  215. }
  216. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  217. if (ret < 0) {
  218. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  219. goto done;
  220. }
  221. done:
  222. mutex_unlock(&dev->phy_mutex);
  223. }
  224. static int smsc95xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  225. int idx)
  226. {
  227. return __smsc95xx_mdio_read(netdev, phy_id, idx, 1);
  228. }
  229. static void smsc95xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  230. int idx, int regval)
  231. {
  232. __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 1);
  233. }
  234. static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  235. {
  236. return __smsc95xx_mdio_read(netdev, phy_id, idx, 0);
  237. }
  238. static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  239. int regval)
  240. {
  241. __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 0);
  242. }
  243. static int __must_check smsc95xx_wait_eeprom(struct usbnet *dev)
  244. {
  245. unsigned long start_time = jiffies;
  246. u32 val;
  247. int ret;
  248. do {
  249. ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
  250. if (ret < 0) {
  251. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  252. return ret;
  253. }
  254. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  255. break;
  256. udelay(40);
  257. } while (!time_after(jiffies, start_time + HZ));
  258. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  259. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  260. return -EIO;
  261. }
  262. return 0;
  263. }
  264. static int __must_check smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
  265. {
  266. unsigned long start_time = jiffies;
  267. u32 val;
  268. int ret;
  269. do {
  270. ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
  271. if (ret < 0) {
  272. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  273. return ret;
  274. }
  275. if (!(val & E2P_CMD_BUSY_))
  276. return 0;
  277. udelay(40);
  278. } while (!time_after(jiffies, start_time + HZ));
  279. netdev_warn(dev->net, "EEPROM is busy\n");
  280. return -EIO;
  281. }
  282. static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  283. u8 *data)
  284. {
  285. u32 val;
  286. int i, ret;
  287. BUG_ON(!dev);
  288. BUG_ON(!data);
  289. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  290. if (ret)
  291. return ret;
  292. for (i = 0; i < length; i++) {
  293. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  294. ret = smsc95xx_write_reg(dev, E2P_CMD, val);
  295. if (ret < 0) {
  296. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  297. return ret;
  298. }
  299. ret = smsc95xx_wait_eeprom(dev);
  300. if (ret < 0)
  301. return ret;
  302. ret = smsc95xx_read_reg(dev, E2P_DATA, &val);
  303. if (ret < 0) {
  304. netdev_warn(dev->net, "Error reading E2P_DATA\n");
  305. return ret;
  306. }
  307. data[i] = val & 0xFF;
  308. offset++;
  309. }
  310. return 0;
  311. }
  312. static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  313. u8 *data)
  314. {
  315. u32 val;
  316. int i, ret;
  317. BUG_ON(!dev);
  318. BUG_ON(!data);
  319. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  320. if (ret)
  321. return ret;
  322. /* Issue write/erase enable command */
  323. val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
  324. ret = smsc95xx_write_reg(dev, E2P_CMD, val);
  325. if (ret < 0) {
  326. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  327. return ret;
  328. }
  329. ret = smsc95xx_wait_eeprom(dev);
  330. if (ret < 0)
  331. return ret;
  332. for (i = 0; i < length; i++) {
  333. /* Fill data register */
  334. val = data[i];
  335. ret = smsc95xx_write_reg(dev, E2P_DATA, val);
  336. if (ret < 0) {
  337. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  338. return ret;
  339. }
  340. /* Send "write" command */
  341. val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
  342. ret = smsc95xx_write_reg(dev, E2P_CMD, val);
  343. if (ret < 0) {
  344. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  345. return ret;
  346. }
  347. ret = smsc95xx_wait_eeprom(dev);
  348. if (ret < 0)
  349. return ret;
  350. offset++;
  351. }
  352. return 0;
  353. }
  354. static int __must_check smsc95xx_write_reg_async(struct usbnet *dev, u16 index,
  355. u32 data)
  356. {
  357. const u16 size = 4;
  358. u32 buf;
  359. int ret;
  360. buf = data;
  361. cpu_to_le32s(&buf);
  362. ret = usbnet_write_cmd_async(dev, USB_VENDOR_REQUEST_WRITE_REGISTER,
  363. USB_DIR_OUT | USB_TYPE_VENDOR |
  364. USB_RECIP_DEVICE,
  365. 0, index, &buf, size);
  366. if (ret < 0)
  367. netdev_warn(dev->net, "Error write async cmd, sts=%d\n",
  368. ret);
  369. return ret;
  370. }
  371. /* returns hash bit number for given MAC address
  372. * example:
  373. * 01 00 5E 00 00 01 -> returns bit number 31 */
  374. static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
  375. {
  376. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  377. }
  378. static void smsc95xx_set_multicast(struct net_device *netdev)
  379. {
  380. struct usbnet *dev = netdev_priv(netdev);
  381. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  382. unsigned long flags;
  383. int ret;
  384. pdata->hash_hi = 0;
  385. pdata->hash_lo = 0;
  386. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  387. if (dev->net->flags & IFF_PROMISC) {
  388. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  389. pdata->mac_cr |= MAC_CR_PRMS_;
  390. pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  391. } else if (dev->net->flags & IFF_ALLMULTI) {
  392. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  393. pdata->mac_cr |= MAC_CR_MCPAS_;
  394. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  395. } else if (!netdev_mc_empty(dev->net)) {
  396. struct netdev_hw_addr *ha;
  397. pdata->mac_cr |= MAC_CR_HPFILT_;
  398. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  399. netdev_for_each_mc_addr(ha, netdev) {
  400. u32 bitnum = smsc95xx_hash(ha->addr);
  401. u32 mask = 0x01 << (bitnum & 0x1F);
  402. if (bitnum & 0x20)
  403. pdata->hash_hi |= mask;
  404. else
  405. pdata->hash_lo |= mask;
  406. }
  407. netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n",
  408. pdata->hash_hi, pdata->hash_lo);
  409. } else {
  410. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  411. pdata->mac_cr &=
  412. ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  413. }
  414. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  415. /* Initiate async writes, as we can't wait for completion here */
  416. ret = smsc95xx_write_reg_async(dev, HASHH, pdata->hash_hi);
  417. if (ret < 0)
  418. netdev_warn(dev->net, "failed to initiate async write to HASHH\n");
  419. ret = smsc95xx_write_reg_async(dev, HASHL, pdata->hash_lo);
  420. if (ret < 0)
  421. netdev_warn(dev->net, "failed to initiate async write to HASHL\n");
  422. ret = smsc95xx_write_reg_async(dev, MAC_CR, pdata->mac_cr);
  423. if (ret < 0)
  424. netdev_warn(dev->net, "failed to initiate async write to MAC_CR\n");
  425. }
  426. static int smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
  427. u16 lcladv, u16 rmtadv)
  428. {
  429. u32 flow, afc_cfg = 0;
  430. int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
  431. if (ret < 0)
  432. return ret;
  433. if (duplex == DUPLEX_FULL) {
  434. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  435. if (cap & FLOW_CTRL_RX)
  436. flow = 0xFFFF0002;
  437. else
  438. flow = 0;
  439. if (cap & FLOW_CTRL_TX)
  440. afc_cfg |= 0xF;
  441. else
  442. afc_cfg &= ~0xF;
  443. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  444. cap & FLOW_CTRL_RX ? "enabled" : "disabled",
  445. cap & FLOW_CTRL_TX ? "enabled" : "disabled");
  446. } else {
  447. netif_dbg(dev, link, dev->net, "half duplex\n");
  448. flow = 0;
  449. afc_cfg |= 0xF;
  450. }
  451. ret = smsc95xx_write_reg(dev, FLOW, flow);
  452. if (ret < 0)
  453. return ret;
  454. return smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
  455. }
  456. static int smsc95xx_link_reset(struct usbnet *dev)
  457. {
  458. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  459. struct mii_if_info *mii = &dev->mii;
  460. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  461. unsigned long flags;
  462. u16 lcladv, rmtadv;
  463. int ret;
  464. /* clear interrupt status */
  465. ret = smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
  466. if (ret < 0)
  467. return ret;
  468. ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
  469. if (ret < 0)
  470. return ret;
  471. mii_check_media(mii, 1, 1);
  472. mii_ethtool_gset(&dev->mii, &ecmd);
  473. lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  474. rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  475. netif_dbg(dev, link, dev->net,
  476. "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  477. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  478. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  479. if (ecmd.duplex != DUPLEX_FULL) {
  480. pdata->mac_cr &= ~MAC_CR_FDPX_;
  481. pdata->mac_cr |= MAC_CR_RCVOWN_;
  482. } else {
  483. pdata->mac_cr &= ~MAC_CR_RCVOWN_;
  484. pdata->mac_cr |= MAC_CR_FDPX_;
  485. }
  486. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  487. ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  488. if (ret < 0)
  489. return ret;
  490. ret = smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  491. if (ret < 0)
  492. netdev_warn(dev->net, "Error updating PHY flow control\n");
  493. return ret;
  494. }
  495. static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
  496. {
  497. u32 intdata;
  498. if (urb->actual_length != 4) {
  499. netdev_warn(dev->net, "unexpected urb length %d\n",
  500. urb->actual_length);
  501. return;
  502. }
  503. memcpy(&intdata, urb->transfer_buffer, 4);
  504. le32_to_cpus(&intdata);
  505. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  506. if (intdata & INT_ENP_PHY_INT_)
  507. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  508. else
  509. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  510. intdata);
  511. }
  512. /* Enable or disable Tx & Rx checksum offload engines */
  513. static int smsc95xx_set_features(struct net_device *netdev,
  514. netdev_features_t features)
  515. {
  516. struct usbnet *dev = netdev_priv(netdev);
  517. u32 read_buf;
  518. int ret;
  519. ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
  520. if (ret < 0)
  521. return ret;
  522. if (features & NETIF_F_HW_CSUM)
  523. read_buf |= Tx_COE_EN_;
  524. else
  525. read_buf &= ~Tx_COE_EN_;
  526. if (features & NETIF_F_RXCSUM)
  527. read_buf |= Rx_COE_EN_;
  528. else
  529. read_buf &= ~Rx_COE_EN_;
  530. ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
  531. if (ret < 0)
  532. return ret;
  533. netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf);
  534. return 0;
  535. }
  536. static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
  537. {
  538. return MAX_EEPROM_SIZE;
  539. }
  540. static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
  541. struct ethtool_eeprom *ee, u8 *data)
  542. {
  543. struct usbnet *dev = netdev_priv(netdev);
  544. ee->magic = LAN95XX_EEPROM_MAGIC;
  545. return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
  546. }
  547. static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
  548. struct ethtool_eeprom *ee, u8 *data)
  549. {
  550. struct usbnet *dev = netdev_priv(netdev);
  551. if (ee->magic != LAN95XX_EEPROM_MAGIC) {
  552. netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n",
  553. ee->magic);
  554. return -EINVAL;
  555. }
  556. return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
  557. }
  558. static int smsc95xx_ethtool_getregslen(struct net_device *netdev)
  559. {
  560. /* all smsc95xx registers */
  561. return COE_CR - ID_REV + sizeof(u32);
  562. }
  563. static void
  564. smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs,
  565. void *buf)
  566. {
  567. struct usbnet *dev = netdev_priv(netdev);
  568. unsigned int i, j;
  569. int retval;
  570. u32 *data = buf;
  571. retval = smsc95xx_read_reg(dev, ID_REV, &regs->version);
  572. if (retval < 0) {
  573. netdev_warn(netdev, "REGS: cannot read ID_REV\n");
  574. return;
  575. }
  576. for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) {
  577. retval = smsc95xx_read_reg(dev, i, &data[j]);
  578. if (retval < 0) {
  579. netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i);
  580. return;
  581. }
  582. }
  583. }
  584. static void smsc95xx_ethtool_get_wol(struct net_device *net,
  585. struct ethtool_wolinfo *wolinfo)
  586. {
  587. struct usbnet *dev = netdev_priv(net);
  588. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  589. wolinfo->supported = SUPPORTED_WAKE;
  590. wolinfo->wolopts = pdata->wolopts;
  591. }
  592. static int smsc95xx_ethtool_set_wol(struct net_device *net,
  593. struct ethtool_wolinfo *wolinfo)
  594. {
  595. struct usbnet *dev = netdev_priv(net);
  596. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  597. int ret;
  598. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  599. ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
  600. if (ret < 0)
  601. netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
  602. return ret;
  603. }
  604. static const struct ethtool_ops smsc95xx_ethtool_ops = {
  605. .get_link = usbnet_get_link,
  606. .nway_reset = usbnet_nway_reset,
  607. .get_drvinfo = usbnet_get_drvinfo,
  608. .get_msglevel = usbnet_get_msglevel,
  609. .set_msglevel = usbnet_set_msglevel,
  610. .get_settings = usbnet_get_settings,
  611. .set_settings = usbnet_set_settings,
  612. .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
  613. .get_eeprom = smsc95xx_ethtool_get_eeprom,
  614. .set_eeprom = smsc95xx_ethtool_set_eeprom,
  615. .get_regs_len = smsc95xx_ethtool_getregslen,
  616. .get_regs = smsc95xx_ethtool_getregs,
  617. .get_wol = smsc95xx_ethtool_get_wol,
  618. .set_wol = smsc95xx_ethtool_set_wol,
  619. };
  620. static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  621. {
  622. struct usbnet *dev = netdev_priv(netdev);
  623. if (!netif_running(netdev))
  624. return -EINVAL;
  625. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  626. }
  627. static void smsc95xx_init_mac_address(struct usbnet *dev)
  628. {
  629. /* try reading mac address from EEPROM */
  630. if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  631. dev->net->dev_addr) == 0) {
  632. if (is_valid_ether_addr(dev->net->dev_addr)) {
  633. /* eeprom values are valid so use them */
  634. netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n");
  635. return;
  636. }
  637. }
  638. /* no eeprom, or eeprom values are invalid. generate random MAC */
  639. eth_hw_addr_random(dev->net);
  640. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  641. }
  642. static int smsc95xx_set_mac_address(struct usbnet *dev)
  643. {
  644. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  645. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  646. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  647. int ret;
  648. ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
  649. if (ret < 0)
  650. return ret;
  651. return smsc95xx_write_reg(dev, ADDRH, addr_hi);
  652. }
  653. /* starts the TX path */
  654. static int smsc95xx_start_tx_path(struct usbnet *dev)
  655. {
  656. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  657. unsigned long flags;
  658. int ret;
  659. /* Enable Tx at MAC */
  660. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  661. pdata->mac_cr |= MAC_CR_TXEN_;
  662. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  663. ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  664. if (ret < 0)
  665. return ret;
  666. /* Enable Tx at SCSRs */
  667. return smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_);
  668. }
  669. /* Starts the Receive path */
  670. static int smsc95xx_start_rx_path(struct usbnet *dev, int in_pm)
  671. {
  672. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  673. unsigned long flags;
  674. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  675. pdata->mac_cr |= MAC_CR_RXEN_;
  676. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  677. return __smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr, in_pm);
  678. }
  679. static int smsc95xx_phy_initialize(struct usbnet *dev)
  680. {
  681. int bmcr, ret, timeout = 0;
  682. /* Initialize MII structure */
  683. dev->mii.dev = dev->net;
  684. dev->mii.mdio_read = smsc95xx_mdio_read;
  685. dev->mii.mdio_write = smsc95xx_mdio_write;
  686. dev->mii.phy_id_mask = 0x1f;
  687. dev->mii.reg_num_mask = 0x1f;
  688. dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
  689. /* reset phy and wait for reset to complete */
  690. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  691. do {
  692. msleep(10);
  693. bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  694. timeout++;
  695. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  696. if (timeout >= 100) {
  697. netdev_warn(dev->net, "timeout on PHY Reset");
  698. return -EIO;
  699. }
  700. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  701. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  702. ADVERTISE_PAUSE_ASYM);
  703. /* read to clear */
  704. ret = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  705. if (ret < 0) {
  706. netdev_warn(dev->net, "Failed to read PHY_INT_SRC during init\n");
  707. return ret;
  708. }
  709. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  710. PHY_INT_MASK_DEFAULT_);
  711. mii_nway_restart(&dev->mii);
  712. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  713. return 0;
  714. }
  715. static int smsc95xx_reset(struct usbnet *dev)
  716. {
  717. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  718. u32 read_buf, write_buf, burst_cap;
  719. int ret = 0, timeout;
  720. netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n");
  721. ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_);
  722. if (ret < 0)
  723. return ret;
  724. timeout = 0;
  725. do {
  726. msleep(10);
  727. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  728. if (ret < 0)
  729. return ret;
  730. timeout++;
  731. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  732. if (timeout >= 100) {
  733. netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
  734. return ret;
  735. }
  736. ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_);
  737. if (ret < 0)
  738. return ret;
  739. timeout = 0;
  740. do {
  741. msleep(10);
  742. ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
  743. if (ret < 0)
  744. return ret;
  745. timeout++;
  746. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  747. if (timeout >= 100) {
  748. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  749. return ret;
  750. }
  751. ret = smsc95xx_set_mac_address(dev);
  752. if (ret < 0)
  753. return ret;
  754. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  755. dev->net->dev_addr);
  756. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  757. if (ret < 0)
  758. return ret;
  759. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  760. read_buf);
  761. read_buf |= HW_CFG_BIR_;
  762. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  763. if (ret < 0)
  764. return ret;
  765. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  766. if (ret < 0)
  767. return ret;
  768. netif_dbg(dev, ifup, dev->net,
  769. "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n",
  770. read_buf);
  771. if (!turbo_mode) {
  772. burst_cap = 0;
  773. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  774. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  775. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  776. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  777. } else {
  778. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  779. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  780. }
  781. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  782. (ulong)dev->rx_urb_size);
  783. ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
  784. if (ret < 0)
  785. return ret;
  786. ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
  787. if (ret < 0)
  788. return ret;
  789. netif_dbg(dev, ifup, dev->net,
  790. "Read Value from BURST_CAP after writing: 0x%08x\n",
  791. read_buf);
  792. ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  793. if (ret < 0)
  794. return ret;
  795. ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
  796. if (ret < 0)
  797. return ret;
  798. netif_dbg(dev, ifup, dev->net,
  799. "Read Value from BULK_IN_DLY after writing: 0x%08x\n",
  800. read_buf);
  801. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  802. if (ret < 0)
  803. return ret;
  804. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG: 0x%08x\n",
  805. read_buf);
  806. if (turbo_mode)
  807. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  808. read_buf &= ~HW_CFG_RXDOFF_;
  809. /* set Rx data offset=2, Make IP header aligns on word boundary. */
  810. read_buf |= NET_IP_ALIGN << 9;
  811. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  812. if (ret < 0)
  813. return ret;
  814. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  815. if (ret < 0)
  816. return ret;
  817. netif_dbg(dev, ifup, dev->net,
  818. "Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
  819. ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
  820. if (ret < 0)
  821. return ret;
  822. ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
  823. if (ret < 0)
  824. return ret;
  825. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf);
  826. /* Configure GPIO pins as LED outputs */
  827. write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
  828. LED_GPIO_CFG_FDX_LED;
  829. ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
  830. if (ret < 0)
  831. return ret;
  832. /* Init Tx */
  833. ret = smsc95xx_write_reg(dev, FLOW, 0);
  834. if (ret < 0)
  835. return ret;
  836. ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT);
  837. if (ret < 0)
  838. return ret;
  839. /* Don't need mac_cr_lock during initialisation */
  840. ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
  841. if (ret < 0)
  842. return ret;
  843. /* Init Rx */
  844. /* Set Vlan */
  845. ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q);
  846. if (ret < 0)
  847. return ret;
  848. /* Enable or disable checksum offload engines */
  849. ret = smsc95xx_set_features(dev->net, dev->net->features);
  850. if (ret < 0) {
  851. netdev_warn(dev->net, "Failed to set checksum offload features\n");
  852. return ret;
  853. }
  854. smsc95xx_set_multicast(dev->net);
  855. ret = smsc95xx_phy_initialize(dev);
  856. if (ret < 0) {
  857. netdev_warn(dev->net, "Failed to init PHY\n");
  858. return ret;
  859. }
  860. ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
  861. if (ret < 0)
  862. return ret;
  863. /* enable PHY interrupts */
  864. read_buf |= INT_EP_CTL_PHY_INT_;
  865. ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
  866. if (ret < 0)
  867. return ret;
  868. ret = smsc95xx_start_tx_path(dev);
  869. if (ret < 0) {
  870. netdev_warn(dev->net, "Failed to start TX path\n");
  871. return ret;
  872. }
  873. ret = smsc95xx_start_rx_path(dev, 0);
  874. if (ret < 0) {
  875. netdev_warn(dev->net, "Failed to start RX path\n");
  876. return ret;
  877. }
  878. netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n");
  879. return 0;
  880. }
  881. static const struct net_device_ops smsc95xx_netdev_ops = {
  882. .ndo_open = usbnet_open,
  883. .ndo_stop = usbnet_stop,
  884. .ndo_start_xmit = usbnet_start_xmit,
  885. .ndo_tx_timeout = usbnet_tx_timeout,
  886. .ndo_change_mtu = usbnet_change_mtu,
  887. .ndo_set_mac_address = eth_mac_addr,
  888. .ndo_validate_addr = eth_validate_addr,
  889. .ndo_do_ioctl = smsc95xx_ioctl,
  890. .ndo_set_rx_mode = smsc95xx_set_multicast,
  891. .ndo_set_features = smsc95xx_set_features,
  892. };
  893. static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
  894. {
  895. struct smsc95xx_priv *pdata = NULL;
  896. u32 val;
  897. int ret;
  898. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  899. ret = usbnet_get_endpoints(dev, intf);
  900. if (ret < 0) {
  901. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  902. return ret;
  903. }
  904. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
  905. GFP_KERNEL);
  906. pdata = (struct smsc95xx_priv *)(dev->data[0]);
  907. if (!pdata)
  908. return -ENOMEM;
  909. spin_lock_init(&pdata->mac_cr_lock);
  910. if (DEFAULT_TX_CSUM_ENABLE)
  911. dev->net->features |= NETIF_F_HW_CSUM;
  912. if (DEFAULT_RX_CSUM_ENABLE)
  913. dev->net->features |= NETIF_F_RXCSUM;
  914. dev->net->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
  915. smsc95xx_init_mac_address(dev);
  916. /* Init all registers */
  917. ret = smsc95xx_reset(dev);
  918. /* detect device revision as different features may be available */
  919. ret = smsc95xx_read_reg(dev, ID_REV, &val);
  920. if (ret < 0)
  921. return ret;
  922. val >>= 16;
  923. if ((val == ID_REV_CHIP_ID_9500A_) || (val == ID_REV_CHIP_ID_9530_) ||
  924. (val == ID_REV_CHIP_ID_89530_) || (val == ID_REV_CHIP_ID_9730_))
  925. pdata->features = (FEATURE_8_WAKEUP_FILTERS |
  926. FEATURE_PHY_NLP_CROSSOVER |
  927. FEATURE_REMOTE_WAKEUP);
  928. else if (val == ID_REV_CHIP_ID_9512_)
  929. pdata->features = FEATURE_8_WAKEUP_FILTERS;
  930. dev->net->netdev_ops = &smsc95xx_netdev_ops;
  931. dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
  932. dev->net->flags |= IFF_MULTICAST;
  933. dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM;
  934. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  935. return 0;
  936. }
  937. static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  938. {
  939. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  940. if (pdata) {
  941. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  942. kfree(pdata);
  943. pdata = NULL;
  944. dev->data[0] = 0;
  945. }
  946. }
  947. static u32 smsc_crc(const u8 *buffer, size_t len, int filter)
  948. {
  949. u32 crc = bitrev16(crc16(0xFFFF, buffer, len));
  950. return crc << ((filter % 2) * 16);
  951. }
  952. static int smsc95xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  953. {
  954. struct mii_if_info *mii = &dev->mii;
  955. int ret;
  956. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  957. /* read to clear */
  958. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  959. if (ret < 0)
  960. return ret;
  961. /* enable interrupt source */
  962. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  963. if (ret < 0)
  964. return ret;
  965. ret |= mask;
  966. smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  967. return 0;
  968. }
  969. static int smsc95xx_link_ok_nopm(struct usbnet *dev)
  970. {
  971. struct mii_if_info *mii = &dev->mii;
  972. int ret;
  973. /* first, a dummy read, needed to latch some MII phys */
  974. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  975. if (ret < 0)
  976. return ret;
  977. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  978. if (ret < 0)
  979. return ret;
  980. return !!(ret & BMSR_LSTATUS);
  981. }
  982. static int smsc95xx_enter_suspend0(struct usbnet *dev)
  983. {
  984. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  985. u32 val;
  986. int ret;
  987. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  988. if (ret < 0)
  989. return ret;
  990. val &= (~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_));
  991. val |= PM_CTL_SUS_MODE_0;
  992. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  993. if (ret < 0)
  994. return ret;
  995. /* clear wol status */
  996. val &= ~PM_CTL_WUPS_;
  997. val |= PM_CTL_WUPS_WOL_;
  998. /* enable energy detection */
  999. if (pdata->wolopts & WAKE_PHY)
  1000. val |= PM_CTL_WUPS_ED_;
  1001. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1002. if (ret < 0)
  1003. return ret;
  1004. /* read back PM_CTRL */
  1005. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1006. if (ret < 0)
  1007. return ret;
  1008. pdata->suspend_flags |= SUSPEND_SUSPEND0;
  1009. return 0;
  1010. }
  1011. static int smsc95xx_enter_suspend1(struct usbnet *dev)
  1012. {
  1013. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1014. struct mii_if_info *mii = &dev->mii;
  1015. u32 val;
  1016. int ret;
  1017. /* reconfigure link pulse detection timing for
  1018. * compatibility with non-standard link partners
  1019. */
  1020. if (pdata->features & FEATURE_PHY_NLP_CROSSOVER)
  1021. smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_EDPD_CONFIG,
  1022. PHY_EDPD_CONFIG_DEFAULT);
  1023. /* enable energy detect power-down mode */
  1024. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_MODE_CTRL_STS);
  1025. if (ret < 0)
  1026. return ret;
  1027. ret |= MODE_CTRL_STS_EDPWRDOWN_;
  1028. smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_MODE_CTRL_STS, ret);
  1029. /* enter SUSPEND1 mode */
  1030. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1031. if (ret < 0)
  1032. return ret;
  1033. val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
  1034. val |= PM_CTL_SUS_MODE_1;
  1035. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1036. if (ret < 0)
  1037. return ret;
  1038. /* clear wol status, enable energy detection */
  1039. val &= ~PM_CTL_WUPS_;
  1040. val |= (PM_CTL_WUPS_ED_ | PM_CTL_ED_EN_);
  1041. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1042. if (ret < 0)
  1043. return ret;
  1044. pdata->suspend_flags |= SUSPEND_SUSPEND1;
  1045. return 0;
  1046. }
  1047. static int smsc95xx_enter_suspend2(struct usbnet *dev)
  1048. {
  1049. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1050. u32 val;
  1051. int ret;
  1052. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1053. if (ret < 0)
  1054. return ret;
  1055. val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
  1056. val |= PM_CTL_SUS_MODE_2;
  1057. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1058. if (ret < 0)
  1059. return ret;
  1060. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1061. return 0;
  1062. }
  1063. static int smsc95xx_enter_suspend3(struct usbnet *dev)
  1064. {
  1065. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1066. u32 val;
  1067. int ret;
  1068. ret = smsc95xx_read_reg_nopm(dev, RX_FIFO_INF, &val);
  1069. if (ret < 0)
  1070. return ret;
  1071. if (val & 0xFFFF) {
  1072. netdev_info(dev->net, "rx fifo not empty in autosuspend\n");
  1073. return -EBUSY;
  1074. }
  1075. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1076. if (ret < 0)
  1077. return ret;
  1078. val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
  1079. val |= PM_CTL_SUS_MODE_3 | PM_CTL_RES_CLR_WKP_STS;
  1080. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1081. if (ret < 0)
  1082. return ret;
  1083. /* clear wol status */
  1084. val &= ~PM_CTL_WUPS_;
  1085. val |= PM_CTL_WUPS_WOL_;
  1086. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1087. if (ret < 0)
  1088. return ret;
  1089. pdata->suspend_flags |= SUSPEND_SUSPEND3;
  1090. return 0;
  1091. }
  1092. static int smsc95xx_autosuspend(struct usbnet *dev, u32 link_up)
  1093. {
  1094. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1095. int ret;
  1096. if (!netif_running(dev->net)) {
  1097. /* interface is ifconfig down so fully power down hw */
  1098. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1099. return smsc95xx_enter_suspend2(dev);
  1100. }
  1101. if (!link_up) {
  1102. /* link is down so enter EDPD mode, but only if device can
  1103. * reliably resume from it. This check should be redundant
  1104. * as current FEATURE_REMOTE_WAKEUP parts also support
  1105. * FEATURE_PHY_NLP_CROSSOVER but it's included for clarity */
  1106. if (!(pdata->features & FEATURE_PHY_NLP_CROSSOVER)) {
  1107. netdev_warn(dev->net, "EDPD not supported\n");
  1108. return -EBUSY;
  1109. }
  1110. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1111. /* enable PHY wakeup events for if cable is attached */
  1112. ret = smsc95xx_enable_phy_wakeup_interrupts(dev,
  1113. PHY_INT_MASK_ANEG_COMP_);
  1114. if (ret < 0) {
  1115. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1116. return ret;
  1117. }
  1118. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1119. return smsc95xx_enter_suspend1(dev);
  1120. }
  1121. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1122. ret = smsc95xx_enable_phy_wakeup_interrupts(dev,
  1123. PHY_INT_MASK_LINK_DOWN_);
  1124. if (ret < 0) {
  1125. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1126. return ret;
  1127. }
  1128. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1129. return smsc95xx_enter_suspend3(dev);
  1130. }
  1131. static int smsc95xx_suspend(struct usb_interface *intf, pm_message_t message)
  1132. {
  1133. struct usbnet *dev = usb_get_intfdata(intf);
  1134. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1135. u32 val, link_up;
  1136. int ret;
  1137. ret = usbnet_suspend(intf, message);
  1138. if (ret < 0) {
  1139. netdev_warn(dev->net, "usbnet_suspend error\n");
  1140. return ret;
  1141. }
  1142. if (pdata->suspend_flags) {
  1143. netdev_warn(dev->net, "error during last resume\n");
  1144. pdata->suspend_flags = 0;
  1145. }
  1146. /* determine if link is up using only _nopm functions */
  1147. link_up = smsc95xx_link_ok_nopm(dev);
  1148. if (message.event == PM_EVENT_AUTO_SUSPEND &&
  1149. (pdata->features & FEATURE_REMOTE_WAKEUP)) {
  1150. ret = smsc95xx_autosuspend(dev, link_up);
  1151. goto done;
  1152. }
  1153. /* if we get this far we're not autosuspending */
  1154. /* if no wol options set, or if link is down and we're not waking on
  1155. * PHY activity, enter lowest power SUSPEND2 mode
  1156. */
  1157. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1158. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1159. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1160. /* disable energy detect (link up) & wake up events */
  1161. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1162. if (ret < 0)
  1163. goto done;
  1164. val &= ~(WUCSR_MPEN_ | WUCSR_WAKE_EN_);
  1165. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1166. if (ret < 0)
  1167. goto done;
  1168. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1169. if (ret < 0)
  1170. goto done;
  1171. val &= ~(PM_CTL_ED_EN_ | PM_CTL_WOL_EN_);
  1172. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1173. if (ret < 0)
  1174. goto done;
  1175. ret = smsc95xx_enter_suspend2(dev);
  1176. goto done;
  1177. }
  1178. if (pdata->wolopts & WAKE_PHY) {
  1179. ret = smsc95xx_enable_phy_wakeup_interrupts(dev,
  1180. (PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_LINK_DOWN_));
  1181. if (ret < 0) {
  1182. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1183. goto done;
  1184. }
  1185. /* if link is down then configure EDPD and enter SUSPEND1,
  1186. * otherwise enter SUSPEND0 below
  1187. */
  1188. if (!link_up) {
  1189. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1190. ret = smsc95xx_enter_suspend1(dev);
  1191. goto done;
  1192. }
  1193. }
  1194. if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) {
  1195. u32 *filter_mask = kzalloc(sizeof(u32) * 32, GFP_KERNEL);
  1196. u32 command[2];
  1197. u32 offset[2];
  1198. u32 crc[4];
  1199. int wuff_filter_count =
  1200. (pdata->features & FEATURE_8_WAKEUP_FILTERS) ?
  1201. LAN9500A_WUFF_NUM : LAN9500_WUFF_NUM;
  1202. int i, filter = 0;
  1203. if (!filter_mask) {
  1204. netdev_warn(dev->net, "Unable to allocate filter_mask\n");
  1205. ret = -ENOMEM;
  1206. goto done;
  1207. }
  1208. memset(command, 0, sizeof(command));
  1209. memset(offset, 0, sizeof(offset));
  1210. memset(crc, 0, sizeof(crc));
  1211. if (pdata->wolopts & WAKE_BCAST) {
  1212. const u8 bcast[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
  1213. netdev_info(dev->net, "enabling broadcast detection\n");
  1214. filter_mask[filter * 4] = 0x003F;
  1215. filter_mask[filter * 4 + 1] = 0x00;
  1216. filter_mask[filter * 4 + 2] = 0x00;
  1217. filter_mask[filter * 4 + 3] = 0x00;
  1218. command[filter/4] |= 0x05UL << ((filter % 4) * 8);
  1219. offset[filter/4] |= 0x00 << ((filter % 4) * 8);
  1220. crc[filter/2] |= smsc_crc(bcast, 6, filter);
  1221. filter++;
  1222. }
  1223. if (pdata->wolopts & WAKE_MCAST) {
  1224. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1225. netdev_info(dev->net, "enabling multicast detection\n");
  1226. filter_mask[filter * 4] = 0x0007;
  1227. filter_mask[filter * 4 + 1] = 0x00;
  1228. filter_mask[filter * 4 + 2] = 0x00;
  1229. filter_mask[filter * 4 + 3] = 0x00;
  1230. command[filter/4] |= 0x09UL << ((filter % 4) * 8);
  1231. offset[filter/4] |= 0x00 << ((filter % 4) * 8);
  1232. crc[filter/2] |= smsc_crc(mcast, 3, filter);
  1233. filter++;
  1234. }
  1235. if (pdata->wolopts & WAKE_ARP) {
  1236. const u8 arp[] = {0x08, 0x06};
  1237. netdev_info(dev->net, "enabling ARP detection\n");
  1238. filter_mask[filter * 4] = 0x0003;
  1239. filter_mask[filter * 4 + 1] = 0x00;
  1240. filter_mask[filter * 4 + 2] = 0x00;
  1241. filter_mask[filter * 4 + 3] = 0x00;
  1242. command[filter/4] |= 0x05UL << ((filter % 4) * 8);
  1243. offset[filter/4] |= 0x0C << ((filter % 4) * 8);
  1244. crc[filter/2] |= smsc_crc(arp, 2, filter);
  1245. filter++;
  1246. }
  1247. if (pdata->wolopts & WAKE_UCAST) {
  1248. netdev_info(dev->net, "enabling unicast detection\n");
  1249. filter_mask[filter * 4] = 0x003F;
  1250. filter_mask[filter * 4 + 1] = 0x00;
  1251. filter_mask[filter * 4 + 2] = 0x00;
  1252. filter_mask[filter * 4 + 3] = 0x00;
  1253. command[filter/4] |= 0x01UL << ((filter % 4) * 8);
  1254. offset[filter/4] |= 0x00 << ((filter % 4) * 8);
  1255. crc[filter/2] |= smsc_crc(dev->net->dev_addr, ETH_ALEN, filter);
  1256. filter++;
  1257. }
  1258. for (i = 0; i < (wuff_filter_count * 4); i++) {
  1259. ret = smsc95xx_write_reg_nopm(dev, WUFF, filter_mask[i]);
  1260. if (ret < 0) {
  1261. kfree(filter_mask);
  1262. goto done;
  1263. }
  1264. }
  1265. kfree(filter_mask);
  1266. for (i = 0; i < (wuff_filter_count / 4); i++) {
  1267. ret = smsc95xx_write_reg_nopm(dev, WUFF, command[i]);
  1268. if (ret < 0)
  1269. goto done;
  1270. }
  1271. for (i = 0; i < (wuff_filter_count / 4); i++) {
  1272. ret = smsc95xx_write_reg_nopm(dev, WUFF, offset[i]);
  1273. if (ret < 0)
  1274. goto done;
  1275. }
  1276. for (i = 0; i < (wuff_filter_count / 2); i++) {
  1277. ret = smsc95xx_write_reg_nopm(dev, WUFF, crc[i]);
  1278. if (ret < 0)
  1279. goto done;
  1280. }
  1281. /* clear any pending pattern match packet status */
  1282. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1283. if (ret < 0)
  1284. goto done;
  1285. val |= WUCSR_WUFR_;
  1286. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1287. if (ret < 0)
  1288. goto done;
  1289. }
  1290. if (pdata->wolopts & WAKE_MAGIC) {
  1291. /* clear any pending magic packet status */
  1292. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1293. if (ret < 0)
  1294. goto done;
  1295. val |= WUCSR_MPR_;
  1296. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1297. if (ret < 0)
  1298. goto done;
  1299. }
  1300. /* enable/disable wakeup sources */
  1301. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1302. if (ret < 0)
  1303. goto done;
  1304. if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) {
  1305. netdev_info(dev->net, "enabling pattern match wakeup\n");
  1306. val |= WUCSR_WAKE_EN_;
  1307. } else {
  1308. netdev_info(dev->net, "disabling pattern match wakeup\n");
  1309. val &= ~WUCSR_WAKE_EN_;
  1310. }
  1311. if (pdata->wolopts & WAKE_MAGIC) {
  1312. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1313. val |= WUCSR_MPEN_;
  1314. } else {
  1315. netdev_info(dev->net, "disabling magic packet wakeup\n");
  1316. val &= ~WUCSR_MPEN_;
  1317. }
  1318. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1319. if (ret < 0)
  1320. goto done;
  1321. /* enable wol wakeup source */
  1322. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1323. if (ret < 0)
  1324. goto done;
  1325. val |= PM_CTL_WOL_EN_;
  1326. /* phy energy detect wakeup source */
  1327. if (pdata->wolopts & WAKE_PHY)
  1328. val |= PM_CTL_ED_EN_;
  1329. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1330. if (ret < 0)
  1331. goto done;
  1332. /* enable receiver to enable frame reception */
  1333. smsc95xx_start_rx_path(dev, 1);
  1334. /* some wol options are enabled, so enter SUSPEND0 */
  1335. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1336. ret = smsc95xx_enter_suspend0(dev);
  1337. done:
  1338. /*
  1339. * TODO: resume() might need to handle the suspend failure
  1340. * in system sleep
  1341. */
  1342. if (ret && PMSG_IS_AUTO(message))
  1343. usbnet_resume(intf);
  1344. return ret;
  1345. }
  1346. static int smsc95xx_resume(struct usb_interface *intf)
  1347. {
  1348. struct usbnet *dev = usb_get_intfdata(intf);
  1349. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1350. u8 suspend_flags = pdata->suspend_flags;
  1351. int ret;
  1352. u32 val;
  1353. BUG_ON(!dev);
  1354. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1355. /* do this first to ensure it's cleared even in error case */
  1356. pdata->suspend_flags = 0;
  1357. if (suspend_flags & SUSPEND_ALLMODES) {
  1358. /* clear wake-up sources */
  1359. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1360. if (ret < 0)
  1361. return ret;
  1362. val &= ~(WUCSR_WAKE_EN_ | WUCSR_MPEN_);
  1363. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1364. if (ret < 0)
  1365. return ret;
  1366. /* clear wake-up status */
  1367. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1368. if (ret < 0)
  1369. return ret;
  1370. val &= ~PM_CTL_WOL_EN_;
  1371. val |= PM_CTL_WUPS_;
  1372. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1373. if (ret < 0)
  1374. return ret;
  1375. }
  1376. ret = usbnet_resume(intf);
  1377. if (ret < 0)
  1378. netdev_warn(dev->net, "usbnet_resume error\n");
  1379. return ret;
  1380. }
  1381. static int smsc95xx_reset_resume(struct usb_interface *intf)
  1382. {
  1383. struct usbnet *dev = usb_get_intfdata(intf);
  1384. int ret;
  1385. ret = smsc95xx_reset(dev);
  1386. if (ret < 0)
  1387. return ret;
  1388. return smsc95xx_resume(intf);
  1389. }
  1390. static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
  1391. {
  1392. skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
  1393. skb->ip_summed = CHECKSUM_COMPLETE;
  1394. skb_trim(skb, skb->len - 2);
  1395. }
  1396. static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1397. {
  1398. /* This check is no longer done by usbnet */
  1399. if (skb->len < dev->net->hard_header_len)
  1400. return 0;
  1401. while (skb->len > 0) {
  1402. u32 header, align_count;
  1403. struct sk_buff *ax_skb;
  1404. unsigned char *packet;
  1405. u16 size;
  1406. memcpy(&header, skb->data, sizeof(header));
  1407. le32_to_cpus(&header);
  1408. skb_pull(skb, 4 + NET_IP_ALIGN);
  1409. packet = skb->data;
  1410. /* get the packet length */
  1411. size = (u16)((header & RX_STS_FL_) >> 16);
  1412. align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
  1413. if (unlikely(header & RX_STS_ES_)) {
  1414. netif_dbg(dev, rx_err, dev->net,
  1415. "Error header=0x%08x\n", header);
  1416. dev->net->stats.rx_errors++;
  1417. dev->net->stats.rx_dropped++;
  1418. if (header & RX_STS_CRC_) {
  1419. dev->net->stats.rx_crc_errors++;
  1420. } else {
  1421. if (header & (RX_STS_TL_ | RX_STS_RF_))
  1422. dev->net->stats.rx_frame_errors++;
  1423. if ((header & RX_STS_LE_) &&
  1424. (!(header & RX_STS_FT_)))
  1425. dev->net->stats.rx_length_errors++;
  1426. }
  1427. } else {
  1428. /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
  1429. if (unlikely(size > (ETH_FRAME_LEN + 12))) {
  1430. netif_dbg(dev, rx_err, dev->net,
  1431. "size err header=0x%08x\n", header);
  1432. return 0;
  1433. }
  1434. /* last frame in this batch */
  1435. if (skb->len == size) {
  1436. if (dev->net->features & NETIF_F_RXCSUM)
  1437. smsc95xx_rx_csum_offload(skb);
  1438. skb_trim(skb, skb->len - 4); /* remove fcs */
  1439. skb->truesize = size + sizeof(struct sk_buff);
  1440. return 1;
  1441. }
  1442. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1443. if (unlikely(!ax_skb)) {
  1444. netdev_warn(dev->net, "Error allocating skb\n");
  1445. return 0;
  1446. }
  1447. ax_skb->len = size;
  1448. ax_skb->data = packet;
  1449. skb_set_tail_pointer(ax_skb, size);
  1450. if (dev->net->features & NETIF_F_RXCSUM)
  1451. smsc95xx_rx_csum_offload(ax_skb);
  1452. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  1453. ax_skb->truesize = size + sizeof(struct sk_buff);
  1454. usbnet_skb_return(dev, ax_skb);
  1455. }
  1456. skb_pull(skb, size);
  1457. /* padding bytes before the next frame starts */
  1458. if (skb->len)
  1459. skb_pull(skb, align_count);
  1460. }
  1461. if (unlikely(skb->len < 0)) {
  1462. netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
  1463. return 0;
  1464. }
  1465. return 1;
  1466. }
  1467. static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
  1468. {
  1469. u16 low_16 = (u16)skb_checksum_start_offset(skb);
  1470. u16 high_16 = low_16 + skb->csum_offset;
  1471. return (high_16 << 16) | low_16;
  1472. }
  1473. static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
  1474. struct sk_buff *skb, gfp_t flags)
  1475. {
  1476. bool csum = skb->ip_summed == CHECKSUM_PARTIAL;
  1477. int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
  1478. u32 tx_cmd_a, tx_cmd_b;
  1479. /* We do not advertise SG, so skbs should be already linearized */
  1480. BUG_ON(skb_shinfo(skb)->nr_frags);
  1481. if (skb_headroom(skb) < overhead) {
  1482. struct sk_buff *skb2 = skb_copy_expand(skb,
  1483. overhead, 0, flags);
  1484. dev_kfree_skb_any(skb);
  1485. skb = skb2;
  1486. if (!skb)
  1487. return NULL;
  1488. }
  1489. if (csum) {
  1490. if (skb->len <= 45) {
  1491. /* workaround - hardware tx checksum does not work
  1492. * properly with extremely small packets */
  1493. long csstart = skb_checksum_start_offset(skb);
  1494. __wsum calc = csum_partial(skb->data + csstart,
  1495. skb->len - csstart, 0);
  1496. *((__sum16 *)(skb->data + csstart
  1497. + skb->csum_offset)) = csum_fold(calc);
  1498. csum = false;
  1499. } else {
  1500. u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
  1501. skb_push(skb, 4);
  1502. cpu_to_le32s(&csum_preamble);
  1503. memcpy(skb->data, &csum_preamble, 4);
  1504. }
  1505. }
  1506. skb_push(skb, 4);
  1507. tx_cmd_b = (u32)(skb->len - 4);
  1508. if (csum)
  1509. tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
  1510. cpu_to_le32s(&tx_cmd_b);
  1511. memcpy(skb->data, &tx_cmd_b, 4);
  1512. skb_push(skb, 4);
  1513. tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
  1514. TX_CMD_A_LAST_SEG_;
  1515. cpu_to_le32s(&tx_cmd_a);
  1516. memcpy(skb->data, &tx_cmd_a, 4);
  1517. return skb;
  1518. }
  1519. static int smsc95xx_manage_power(struct usbnet *dev, int on)
  1520. {
  1521. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1522. dev->intf->needs_remote_wakeup = on;
  1523. if (pdata->features & FEATURE_REMOTE_WAKEUP)
  1524. return 0;
  1525. /* this chip revision isn't capable of remote wakeup */
  1526. netdev_info(dev->net, "hardware isn't capable of remote wakeup\n");
  1527. if (on)
  1528. usb_autopm_get_interface_no_resume(dev->intf);
  1529. else
  1530. usb_autopm_put_interface(dev->intf);
  1531. return 0;
  1532. }
  1533. static const struct driver_info smsc95xx_info = {
  1534. .description = "smsc95xx USB 2.0 Ethernet",
  1535. .bind = smsc95xx_bind,
  1536. .unbind = smsc95xx_unbind,
  1537. .link_reset = smsc95xx_link_reset,
  1538. .reset = smsc95xx_reset,
  1539. .rx_fixup = smsc95xx_rx_fixup,
  1540. .tx_fixup = smsc95xx_tx_fixup,
  1541. .status = smsc95xx_status,
  1542. .manage_power = smsc95xx_manage_power,
  1543. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1544. };
  1545. static const struct usb_device_id products[] = {
  1546. {
  1547. /* SMSC9500 USB Ethernet Device */
  1548. USB_DEVICE(0x0424, 0x9500),
  1549. .driver_info = (unsigned long) &smsc95xx_info,
  1550. },
  1551. {
  1552. /* SMSC9505 USB Ethernet Device */
  1553. USB_DEVICE(0x0424, 0x9505),
  1554. .driver_info = (unsigned long) &smsc95xx_info,
  1555. },
  1556. {
  1557. /* SMSC9500A USB Ethernet Device */
  1558. USB_DEVICE(0x0424, 0x9E00),
  1559. .driver_info = (unsigned long) &smsc95xx_info,
  1560. },
  1561. {
  1562. /* SMSC9505A USB Ethernet Device */
  1563. USB_DEVICE(0x0424, 0x9E01),
  1564. .driver_info = (unsigned long) &smsc95xx_info,
  1565. },
  1566. {
  1567. /* SMSC9512/9514 USB Hub & Ethernet Device */
  1568. USB_DEVICE(0x0424, 0xec00),
  1569. .driver_info = (unsigned long) &smsc95xx_info,
  1570. },
  1571. {
  1572. /* SMSC9500 USB Ethernet Device (SAL10) */
  1573. USB_DEVICE(0x0424, 0x9900),
  1574. .driver_info = (unsigned long) &smsc95xx_info,
  1575. },
  1576. {
  1577. /* SMSC9505 USB Ethernet Device (SAL10) */
  1578. USB_DEVICE(0x0424, 0x9901),
  1579. .driver_info = (unsigned long) &smsc95xx_info,
  1580. },
  1581. {
  1582. /* SMSC9500A USB Ethernet Device (SAL10) */
  1583. USB_DEVICE(0x0424, 0x9902),
  1584. .driver_info = (unsigned long) &smsc95xx_info,
  1585. },
  1586. {
  1587. /* SMSC9505A USB Ethernet Device (SAL10) */
  1588. USB_DEVICE(0x0424, 0x9903),
  1589. .driver_info = (unsigned long) &smsc95xx_info,
  1590. },
  1591. {
  1592. /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */
  1593. USB_DEVICE(0x0424, 0x9904),
  1594. .driver_info = (unsigned long) &smsc95xx_info,
  1595. },
  1596. {
  1597. /* SMSC9500A USB Ethernet Device (HAL) */
  1598. USB_DEVICE(0x0424, 0x9905),
  1599. .driver_info = (unsigned long) &smsc95xx_info,
  1600. },
  1601. {
  1602. /* SMSC9505A USB Ethernet Device (HAL) */
  1603. USB_DEVICE(0x0424, 0x9906),
  1604. .driver_info = (unsigned long) &smsc95xx_info,
  1605. },
  1606. {
  1607. /* SMSC9500 USB Ethernet Device (Alternate ID) */
  1608. USB_DEVICE(0x0424, 0x9907),
  1609. .driver_info = (unsigned long) &smsc95xx_info,
  1610. },
  1611. {
  1612. /* SMSC9500A USB Ethernet Device (Alternate ID) */
  1613. USB_DEVICE(0x0424, 0x9908),
  1614. .driver_info = (unsigned long) &smsc95xx_info,
  1615. },
  1616. {
  1617. /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */
  1618. USB_DEVICE(0x0424, 0x9909),
  1619. .driver_info = (unsigned long) &smsc95xx_info,
  1620. },
  1621. {
  1622. /* SMSC LAN9530 USB Ethernet Device */
  1623. USB_DEVICE(0x0424, 0x9530),
  1624. .driver_info = (unsigned long) &smsc95xx_info,
  1625. },
  1626. {
  1627. /* SMSC LAN9730 USB Ethernet Device */
  1628. USB_DEVICE(0x0424, 0x9730),
  1629. .driver_info = (unsigned long) &smsc95xx_info,
  1630. },
  1631. {
  1632. /* SMSC LAN89530 USB Ethernet Device */
  1633. USB_DEVICE(0x0424, 0x9E08),
  1634. .driver_info = (unsigned long) &smsc95xx_info,
  1635. },
  1636. { }, /* END */
  1637. };
  1638. MODULE_DEVICE_TABLE(usb, products);
  1639. static struct usb_driver smsc95xx_driver = {
  1640. .name = "smsc95xx",
  1641. .id_table = products,
  1642. .probe = usbnet_probe,
  1643. .suspend = smsc95xx_suspend,
  1644. .resume = smsc95xx_resume,
  1645. .reset_resume = smsc95xx_reset_resume,
  1646. .disconnect = usbnet_disconnect,
  1647. .disable_hub_initiated_lpm = 1,
  1648. .supports_autosuspend = 1,
  1649. };
  1650. module_usb_driver(smsc95xx_driver);
  1651. MODULE_AUTHOR("Nancy Lin");
  1652. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1653. MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
  1654. MODULE_LICENSE("GPL");