enic_main.c 61 KB

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  1. /*
  2. * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
  3. * Copyright 2007 Nuova Systems, Inc. All rights reserved.
  4. *
  5. * This program is free software; you may redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; version 2 of the License.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  10. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  11. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  12. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  13. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  14. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  15. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  16. * SOFTWARE.
  17. *
  18. */
  19. #include <linux/module.h>
  20. #include <linux/kernel.h>
  21. #include <linux/string.h>
  22. #include <linux/errno.h>
  23. #include <linux/types.h>
  24. #include <linux/init.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/workqueue.h>
  27. #include <linux/pci.h>
  28. #include <linux/netdevice.h>
  29. #include <linux/etherdevice.h>
  30. #include <linux/if.h>
  31. #include <linux/if_ether.h>
  32. #include <linux/if_vlan.h>
  33. #include <linux/in.h>
  34. #include <linux/ip.h>
  35. #include <linux/ipv6.h>
  36. #include <linux/tcp.h>
  37. #include <linux/rtnetlink.h>
  38. #include <linux/prefetch.h>
  39. #include <net/ip6_checksum.h>
  40. #include <linux/ktime.h>
  41. #include "cq_enet_desc.h"
  42. #include "vnic_dev.h"
  43. #include "vnic_intr.h"
  44. #include "vnic_stats.h"
  45. #include "vnic_vic.h"
  46. #include "enic_res.h"
  47. #include "enic.h"
  48. #include "enic_dev.h"
  49. #include "enic_pp.h"
  50. #define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ)
  51. #define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS)
  52. #define MAX_TSO (1 << 16)
  53. #define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1)
  54. #define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
  55. #define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */
  56. #define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */
  57. /* Supported devices */
  58. static DEFINE_PCI_DEVICE_TABLE(enic_id_table) = {
  59. { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) },
  60. { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) },
  61. { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) },
  62. { 0, } /* end of table */
  63. };
  64. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  65. MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>");
  66. MODULE_LICENSE("GPL");
  67. MODULE_VERSION(DRV_VERSION);
  68. MODULE_DEVICE_TABLE(pci, enic_id_table);
  69. #define ENIC_LARGE_PKT_THRESHOLD 1000
  70. #define ENIC_MAX_COALESCE_TIMERS 10
  71. /* Interrupt moderation table, which will be used to decide the
  72. * coalescing timer values
  73. * {rx_rate in Mbps, mapping percentage of the range}
  74. */
  75. struct enic_intr_mod_table mod_table[ENIC_MAX_COALESCE_TIMERS + 1] = {
  76. {4000, 0},
  77. {4400, 10},
  78. {5060, 20},
  79. {5230, 30},
  80. {5540, 40},
  81. {5820, 50},
  82. {6120, 60},
  83. {6435, 70},
  84. {6745, 80},
  85. {7000, 90},
  86. {0xFFFFFFFF, 100}
  87. };
  88. /* This table helps the driver to pick different ranges for rx coalescing
  89. * timer depending on the link speed.
  90. */
  91. struct enic_intr_mod_range mod_range[ENIC_MAX_LINK_SPEEDS] = {
  92. {0, 0}, /* 0 - 4 Gbps */
  93. {0, 3}, /* 4 - 10 Gbps */
  94. {3, 6}, /* 10 - 40 Gbps */
  95. };
  96. int enic_is_dynamic(struct enic *enic)
  97. {
  98. return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN;
  99. }
  100. int enic_sriov_enabled(struct enic *enic)
  101. {
  102. return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0;
  103. }
  104. static int enic_is_sriov_vf(struct enic *enic)
  105. {
  106. return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF;
  107. }
  108. int enic_is_valid_vf(struct enic *enic, int vf)
  109. {
  110. #ifdef CONFIG_PCI_IOV
  111. return vf >= 0 && vf < enic->num_vfs;
  112. #else
  113. return 0;
  114. #endif
  115. }
  116. static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf)
  117. {
  118. struct enic *enic = vnic_dev_priv(wq->vdev);
  119. if (buf->sop)
  120. pci_unmap_single(enic->pdev, buf->dma_addr,
  121. buf->len, PCI_DMA_TODEVICE);
  122. else
  123. pci_unmap_page(enic->pdev, buf->dma_addr,
  124. buf->len, PCI_DMA_TODEVICE);
  125. if (buf->os_buf)
  126. dev_kfree_skb_any(buf->os_buf);
  127. }
  128. static void enic_wq_free_buf(struct vnic_wq *wq,
  129. struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque)
  130. {
  131. enic_free_wq_buf(wq, buf);
  132. }
  133. static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
  134. u8 type, u16 q_number, u16 completed_index, void *opaque)
  135. {
  136. struct enic *enic = vnic_dev_priv(vdev);
  137. spin_lock(&enic->wq_lock[q_number]);
  138. vnic_wq_service(&enic->wq[q_number], cq_desc,
  139. completed_index, enic_wq_free_buf,
  140. opaque);
  141. if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) &&
  142. vnic_wq_desc_avail(&enic->wq[q_number]) >=
  143. (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS))
  144. netif_wake_subqueue(enic->netdev, q_number);
  145. spin_unlock(&enic->wq_lock[q_number]);
  146. return 0;
  147. }
  148. static void enic_log_q_error(struct enic *enic)
  149. {
  150. unsigned int i;
  151. u32 error_status;
  152. for (i = 0; i < enic->wq_count; i++) {
  153. error_status = vnic_wq_error_status(&enic->wq[i]);
  154. if (error_status)
  155. netdev_err(enic->netdev, "WQ[%d] error_status %d\n",
  156. i, error_status);
  157. }
  158. for (i = 0; i < enic->rq_count; i++) {
  159. error_status = vnic_rq_error_status(&enic->rq[i]);
  160. if (error_status)
  161. netdev_err(enic->netdev, "RQ[%d] error_status %d\n",
  162. i, error_status);
  163. }
  164. }
  165. static void enic_msglvl_check(struct enic *enic)
  166. {
  167. u32 msg_enable = vnic_dev_msg_lvl(enic->vdev);
  168. if (msg_enable != enic->msg_enable) {
  169. netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n",
  170. enic->msg_enable, msg_enable);
  171. enic->msg_enable = msg_enable;
  172. }
  173. }
  174. static void enic_mtu_check(struct enic *enic)
  175. {
  176. u32 mtu = vnic_dev_mtu(enic->vdev);
  177. struct net_device *netdev = enic->netdev;
  178. if (mtu && mtu != enic->port_mtu) {
  179. enic->port_mtu = mtu;
  180. if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
  181. mtu = max_t(int, ENIC_MIN_MTU,
  182. min_t(int, ENIC_MAX_MTU, mtu));
  183. if (mtu != netdev->mtu)
  184. schedule_work(&enic->change_mtu_work);
  185. } else {
  186. if (mtu < netdev->mtu)
  187. netdev_warn(netdev,
  188. "interface MTU (%d) set higher "
  189. "than switch port MTU (%d)\n",
  190. netdev->mtu, mtu);
  191. }
  192. }
  193. }
  194. static void enic_link_check(struct enic *enic)
  195. {
  196. int link_status = vnic_dev_link_status(enic->vdev);
  197. int carrier_ok = netif_carrier_ok(enic->netdev);
  198. if (link_status && !carrier_ok) {
  199. netdev_info(enic->netdev, "Link UP\n");
  200. netif_carrier_on(enic->netdev);
  201. } else if (!link_status && carrier_ok) {
  202. netdev_info(enic->netdev, "Link DOWN\n");
  203. netif_carrier_off(enic->netdev);
  204. }
  205. }
  206. static void enic_notify_check(struct enic *enic)
  207. {
  208. enic_msglvl_check(enic);
  209. enic_mtu_check(enic);
  210. enic_link_check(enic);
  211. }
  212. #define ENIC_TEST_INTR(pba, i) (pba & (1 << i))
  213. static irqreturn_t enic_isr_legacy(int irq, void *data)
  214. {
  215. struct net_device *netdev = data;
  216. struct enic *enic = netdev_priv(netdev);
  217. unsigned int io_intr = enic_legacy_io_intr();
  218. unsigned int err_intr = enic_legacy_err_intr();
  219. unsigned int notify_intr = enic_legacy_notify_intr();
  220. u32 pba;
  221. vnic_intr_mask(&enic->intr[io_intr]);
  222. pba = vnic_intr_legacy_pba(enic->legacy_pba);
  223. if (!pba) {
  224. vnic_intr_unmask(&enic->intr[io_intr]);
  225. return IRQ_NONE; /* not our interrupt */
  226. }
  227. if (ENIC_TEST_INTR(pba, notify_intr)) {
  228. vnic_intr_return_all_credits(&enic->intr[notify_intr]);
  229. enic_notify_check(enic);
  230. }
  231. if (ENIC_TEST_INTR(pba, err_intr)) {
  232. vnic_intr_return_all_credits(&enic->intr[err_intr]);
  233. enic_log_q_error(enic);
  234. /* schedule recovery from WQ/RQ error */
  235. schedule_work(&enic->reset);
  236. return IRQ_HANDLED;
  237. }
  238. if (ENIC_TEST_INTR(pba, io_intr)) {
  239. if (napi_schedule_prep(&enic->napi[0]))
  240. __napi_schedule(&enic->napi[0]);
  241. } else {
  242. vnic_intr_unmask(&enic->intr[io_intr]);
  243. }
  244. return IRQ_HANDLED;
  245. }
  246. static irqreturn_t enic_isr_msi(int irq, void *data)
  247. {
  248. struct enic *enic = data;
  249. /* With MSI, there is no sharing of interrupts, so this is
  250. * our interrupt and there is no need to ack it. The device
  251. * is not providing per-vector masking, so the OS will not
  252. * write to PCI config space to mask/unmask the interrupt.
  253. * We're using mask_on_assertion for MSI, so the device
  254. * automatically masks the interrupt when the interrupt is
  255. * generated. Later, when exiting polling, the interrupt
  256. * will be unmasked (see enic_poll).
  257. *
  258. * Also, the device uses the same PCIe Traffic Class (TC)
  259. * for Memory Write data and MSI, so there are no ordering
  260. * issues; the MSI will always arrive at the Root Complex
  261. * _after_ corresponding Memory Writes (i.e. descriptor
  262. * writes).
  263. */
  264. napi_schedule(&enic->napi[0]);
  265. return IRQ_HANDLED;
  266. }
  267. static irqreturn_t enic_isr_msix_rq(int irq, void *data)
  268. {
  269. struct napi_struct *napi = data;
  270. /* schedule NAPI polling for RQ cleanup */
  271. napi_schedule(napi);
  272. return IRQ_HANDLED;
  273. }
  274. static irqreturn_t enic_isr_msix_wq(int irq, void *data)
  275. {
  276. struct enic *enic = data;
  277. unsigned int cq;
  278. unsigned int intr;
  279. unsigned int wq_work_to_do = -1; /* no limit */
  280. unsigned int wq_work_done;
  281. unsigned int wq_irq;
  282. wq_irq = (u32)irq - enic->msix_entry[enic_msix_wq_intr(enic, 0)].vector;
  283. cq = enic_cq_wq(enic, wq_irq);
  284. intr = enic_msix_wq_intr(enic, wq_irq);
  285. wq_work_done = vnic_cq_service(&enic->cq[cq],
  286. wq_work_to_do, enic_wq_service, NULL);
  287. vnic_intr_return_credits(&enic->intr[intr],
  288. wq_work_done,
  289. 1 /* unmask intr */,
  290. 1 /* reset intr timer */);
  291. return IRQ_HANDLED;
  292. }
  293. static irqreturn_t enic_isr_msix_err(int irq, void *data)
  294. {
  295. struct enic *enic = data;
  296. unsigned int intr = enic_msix_err_intr(enic);
  297. vnic_intr_return_all_credits(&enic->intr[intr]);
  298. enic_log_q_error(enic);
  299. /* schedule recovery from WQ/RQ error */
  300. schedule_work(&enic->reset);
  301. return IRQ_HANDLED;
  302. }
  303. static irqreturn_t enic_isr_msix_notify(int irq, void *data)
  304. {
  305. struct enic *enic = data;
  306. unsigned int intr = enic_msix_notify_intr(enic);
  307. vnic_intr_return_all_credits(&enic->intr[intr]);
  308. enic_notify_check(enic);
  309. return IRQ_HANDLED;
  310. }
  311. static inline void enic_queue_wq_skb_cont(struct enic *enic,
  312. struct vnic_wq *wq, struct sk_buff *skb,
  313. unsigned int len_left, int loopback)
  314. {
  315. const skb_frag_t *frag;
  316. /* Queue additional data fragments */
  317. for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
  318. len_left -= skb_frag_size(frag);
  319. enic_queue_wq_desc_cont(wq, skb,
  320. skb_frag_dma_map(&enic->pdev->dev,
  321. frag, 0, skb_frag_size(frag),
  322. DMA_TO_DEVICE),
  323. skb_frag_size(frag),
  324. (len_left == 0), /* EOP? */
  325. loopback);
  326. }
  327. }
  328. static inline void enic_queue_wq_skb_vlan(struct enic *enic,
  329. struct vnic_wq *wq, struct sk_buff *skb,
  330. int vlan_tag_insert, unsigned int vlan_tag, int loopback)
  331. {
  332. unsigned int head_len = skb_headlen(skb);
  333. unsigned int len_left = skb->len - head_len;
  334. int eop = (len_left == 0);
  335. /* Queue the main skb fragment. The fragments are no larger
  336. * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
  337. * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
  338. * per fragment is queued.
  339. */
  340. enic_queue_wq_desc(wq, skb,
  341. pci_map_single(enic->pdev, skb->data,
  342. head_len, PCI_DMA_TODEVICE),
  343. head_len,
  344. vlan_tag_insert, vlan_tag,
  345. eop, loopback);
  346. if (!eop)
  347. enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
  348. }
  349. static inline void enic_queue_wq_skb_csum_l4(struct enic *enic,
  350. struct vnic_wq *wq, struct sk_buff *skb,
  351. int vlan_tag_insert, unsigned int vlan_tag, int loopback)
  352. {
  353. unsigned int head_len = skb_headlen(skb);
  354. unsigned int len_left = skb->len - head_len;
  355. unsigned int hdr_len = skb_checksum_start_offset(skb);
  356. unsigned int csum_offset = hdr_len + skb->csum_offset;
  357. int eop = (len_left == 0);
  358. /* Queue the main skb fragment. The fragments are no larger
  359. * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
  360. * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
  361. * per fragment is queued.
  362. */
  363. enic_queue_wq_desc_csum_l4(wq, skb,
  364. pci_map_single(enic->pdev, skb->data,
  365. head_len, PCI_DMA_TODEVICE),
  366. head_len,
  367. csum_offset,
  368. hdr_len,
  369. vlan_tag_insert, vlan_tag,
  370. eop, loopback);
  371. if (!eop)
  372. enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
  373. }
  374. static inline void enic_queue_wq_skb_tso(struct enic *enic,
  375. struct vnic_wq *wq, struct sk_buff *skb, unsigned int mss,
  376. int vlan_tag_insert, unsigned int vlan_tag, int loopback)
  377. {
  378. unsigned int frag_len_left = skb_headlen(skb);
  379. unsigned int len_left = skb->len - frag_len_left;
  380. unsigned int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  381. int eop = (len_left == 0);
  382. unsigned int len;
  383. dma_addr_t dma_addr;
  384. unsigned int offset = 0;
  385. skb_frag_t *frag;
  386. /* Preload TCP csum field with IP pseudo hdr calculated
  387. * with IP length set to zero. HW will later add in length
  388. * to each TCP segment resulting from the TSO.
  389. */
  390. if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
  391. ip_hdr(skb)->check = 0;
  392. tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
  393. ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
  394. } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
  395. tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
  396. &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
  397. }
  398. /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
  399. * for the main skb fragment
  400. */
  401. while (frag_len_left) {
  402. len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN);
  403. dma_addr = pci_map_single(enic->pdev, skb->data + offset,
  404. len, PCI_DMA_TODEVICE);
  405. enic_queue_wq_desc_tso(wq, skb,
  406. dma_addr,
  407. len,
  408. mss, hdr_len,
  409. vlan_tag_insert, vlan_tag,
  410. eop && (len == frag_len_left), loopback);
  411. frag_len_left -= len;
  412. offset += len;
  413. }
  414. if (eop)
  415. return;
  416. /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
  417. * for additional data fragments
  418. */
  419. for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
  420. len_left -= skb_frag_size(frag);
  421. frag_len_left = skb_frag_size(frag);
  422. offset = 0;
  423. while (frag_len_left) {
  424. len = min(frag_len_left,
  425. (unsigned int)WQ_ENET_MAX_DESC_LEN);
  426. dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag,
  427. offset, len,
  428. DMA_TO_DEVICE);
  429. enic_queue_wq_desc_cont(wq, skb,
  430. dma_addr,
  431. len,
  432. (len_left == 0) &&
  433. (len == frag_len_left), /* EOP? */
  434. loopback);
  435. frag_len_left -= len;
  436. offset += len;
  437. }
  438. }
  439. }
  440. static inline void enic_queue_wq_skb(struct enic *enic,
  441. struct vnic_wq *wq, struct sk_buff *skb)
  442. {
  443. unsigned int mss = skb_shinfo(skb)->gso_size;
  444. unsigned int vlan_tag = 0;
  445. int vlan_tag_insert = 0;
  446. int loopback = 0;
  447. if (vlan_tx_tag_present(skb)) {
  448. /* VLAN tag from trunking driver */
  449. vlan_tag_insert = 1;
  450. vlan_tag = vlan_tx_tag_get(skb);
  451. } else if (enic->loop_enable) {
  452. vlan_tag = enic->loop_tag;
  453. loopback = 1;
  454. }
  455. if (mss)
  456. enic_queue_wq_skb_tso(enic, wq, skb, mss,
  457. vlan_tag_insert, vlan_tag, loopback);
  458. else if (skb->ip_summed == CHECKSUM_PARTIAL)
  459. enic_queue_wq_skb_csum_l4(enic, wq, skb,
  460. vlan_tag_insert, vlan_tag, loopback);
  461. else
  462. enic_queue_wq_skb_vlan(enic, wq, skb,
  463. vlan_tag_insert, vlan_tag, loopback);
  464. }
  465. /* netif_tx_lock held, process context with BHs disabled, or BH */
  466. static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb,
  467. struct net_device *netdev)
  468. {
  469. struct enic *enic = netdev_priv(netdev);
  470. struct vnic_wq *wq;
  471. unsigned long flags;
  472. unsigned int txq_map;
  473. if (skb->len <= 0) {
  474. dev_kfree_skb_any(skb);
  475. return NETDEV_TX_OK;
  476. }
  477. txq_map = skb_get_queue_mapping(skb) % enic->wq_count;
  478. wq = &enic->wq[txq_map];
  479. /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs,
  480. * which is very likely. In the off chance it's going to take
  481. * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb.
  482. */
  483. if (skb_shinfo(skb)->gso_size == 0 &&
  484. skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC &&
  485. skb_linearize(skb)) {
  486. dev_kfree_skb_any(skb);
  487. return NETDEV_TX_OK;
  488. }
  489. spin_lock_irqsave(&enic->wq_lock[txq_map], flags);
  490. if (vnic_wq_desc_avail(wq) <
  491. skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) {
  492. netif_tx_stop_queue(netdev_get_tx_queue(netdev, txq_map));
  493. /* This is a hard error, log it */
  494. netdev_err(netdev, "BUG! Tx ring full when queue awake!\n");
  495. spin_unlock_irqrestore(&enic->wq_lock[txq_map], flags);
  496. return NETDEV_TX_BUSY;
  497. }
  498. enic_queue_wq_skb(enic, wq, skb);
  499. if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)
  500. netif_tx_stop_queue(netdev_get_tx_queue(netdev, txq_map));
  501. spin_unlock_irqrestore(&enic->wq_lock[txq_map], flags);
  502. return NETDEV_TX_OK;
  503. }
  504. /* dev_base_lock rwlock held, nominally process context */
  505. static struct rtnl_link_stats64 *enic_get_stats(struct net_device *netdev,
  506. struct rtnl_link_stats64 *net_stats)
  507. {
  508. struct enic *enic = netdev_priv(netdev);
  509. struct vnic_stats *stats;
  510. enic_dev_stats_dump(enic, &stats);
  511. net_stats->tx_packets = stats->tx.tx_frames_ok;
  512. net_stats->tx_bytes = stats->tx.tx_bytes_ok;
  513. net_stats->tx_errors = stats->tx.tx_errors;
  514. net_stats->tx_dropped = stats->tx.tx_drops;
  515. net_stats->rx_packets = stats->rx.rx_frames_ok;
  516. net_stats->rx_bytes = stats->rx.rx_bytes_ok;
  517. net_stats->rx_errors = stats->rx.rx_errors;
  518. net_stats->multicast = stats->rx.rx_multicast_frames_ok;
  519. net_stats->rx_over_errors = enic->rq_truncated_pkts;
  520. net_stats->rx_crc_errors = enic->rq_bad_fcs;
  521. net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop;
  522. return net_stats;
  523. }
  524. static int enic_mc_sync(struct net_device *netdev, const u8 *mc_addr)
  525. {
  526. struct enic *enic = netdev_priv(netdev);
  527. if (enic->mc_count == ENIC_MULTICAST_PERFECT_FILTERS) {
  528. unsigned int mc_count = netdev_mc_count(netdev);
  529. netdev_warn(netdev, "Registering only %d out of %d multicast addresses\n",
  530. ENIC_MULTICAST_PERFECT_FILTERS, mc_count);
  531. return -ENOSPC;
  532. }
  533. enic_dev_add_addr(enic, mc_addr);
  534. enic->mc_count++;
  535. return 0;
  536. }
  537. static int enic_mc_unsync(struct net_device *netdev, const u8 *mc_addr)
  538. {
  539. struct enic *enic = netdev_priv(netdev);
  540. enic_dev_del_addr(enic, mc_addr);
  541. enic->mc_count--;
  542. return 0;
  543. }
  544. static int enic_uc_sync(struct net_device *netdev, const u8 *uc_addr)
  545. {
  546. struct enic *enic = netdev_priv(netdev);
  547. if (enic->uc_count == ENIC_UNICAST_PERFECT_FILTERS) {
  548. unsigned int uc_count = netdev_uc_count(netdev);
  549. netdev_warn(netdev, "Registering only %d out of %d unicast addresses\n",
  550. ENIC_UNICAST_PERFECT_FILTERS, uc_count);
  551. return -ENOSPC;
  552. }
  553. enic_dev_add_addr(enic, uc_addr);
  554. enic->uc_count++;
  555. return 0;
  556. }
  557. static int enic_uc_unsync(struct net_device *netdev, const u8 *uc_addr)
  558. {
  559. struct enic *enic = netdev_priv(netdev);
  560. enic_dev_del_addr(enic, uc_addr);
  561. enic->uc_count--;
  562. return 0;
  563. }
  564. void enic_reset_addr_lists(struct enic *enic)
  565. {
  566. struct net_device *netdev = enic->netdev;
  567. __dev_uc_unsync(netdev, NULL);
  568. __dev_mc_unsync(netdev, NULL);
  569. enic->mc_count = 0;
  570. enic->uc_count = 0;
  571. enic->flags = 0;
  572. }
  573. static int enic_set_mac_addr(struct net_device *netdev, char *addr)
  574. {
  575. struct enic *enic = netdev_priv(netdev);
  576. if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
  577. if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr))
  578. return -EADDRNOTAVAIL;
  579. } else {
  580. if (!is_valid_ether_addr(addr))
  581. return -EADDRNOTAVAIL;
  582. }
  583. memcpy(netdev->dev_addr, addr, netdev->addr_len);
  584. return 0;
  585. }
  586. static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p)
  587. {
  588. struct enic *enic = netdev_priv(netdev);
  589. struct sockaddr *saddr = p;
  590. char *addr = saddr->sa_data;
  591. int err;
  592. if (netif_running(enic->netdev)) {
  593. err = enic_dev_del_station_addr(enic);
  594. if (err)
  595. return err;
  596. }
  597. err = enic_set_mac_addr(netdev, addr);
  598. if (err)
  599. return err;
  600. if (netif_running(enic->netdev)) {
  601. err = enic_dev_add_station_addr(enic);
  602. if (err)
  603. return err;
  604. }
  605. return err;
  606. }
  607. static int enic_set_mac_address(struct net_device *netdev, void *p)
  608. {
  609. struct sockaddr *saddr = p;
  610. char *addr = saddr->sa_data;
  611. struct enic *enic = netdev_priv(netdev);
  612. int err;
  613. err = enic_dev_del_station_addr(enic);
  614. if (err)
  615. return err;
  616. err = enic_set_mac_addr(netdev, addr);
  617. if (err)
  618. return err;
  619. return enic_dev_add_station_addr(enic);
  620. }
  621. /* netif_tx_lock held, BHs disabled */
  622. static void enic_set_rx_mode(struct net_device *netdev)
  623. {
  624. struct enic *enic = netdev_priv(netdev);
  625. int directed = 1;
  626. int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0;
  627. int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0;
  628. int promisc = (netdev->flags & IFF_PROMISC) ||
  629. netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS;
  630. int allmulti = (netdev->flags & IFF_ALLMULTI) ||
  631. netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS;
  632. unsigned int flags = netdev->flags |
  633. (allmulti ? IFF_ALLMULTI : 0) |
  634. (promisc ? IFF_PROMISC : 0);
  635. if (enic->flags != flags) {
  636. enic->flags = flags;
  637. enic_dev_packet_filter(enic, directed,
  638. multicast, broadcast, promisc, allmulti);
  639. }
  640. if (!promisc) {
  641. __dev_uc_sync(netdev, enic_uc_sync, enic_uc_unsync);
  642. if (!allmulti)
  643. __dev_mc_sync(netdev, enic_mc_sync, enic_mc_unsync);
  644. }
  645. }
  646. /* netif_tx_lock held, BHs disabled */
  647. static void enic_tx_timeout(struct net_device *netdev)
  648. {
  649. struct enic *enic = netdev_priv(netdev);
  650. schedule_work(&enic->reset);
  651. }
  652. static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
  653. {
  654. struct enic *enic = netdev_priv(netdev);
  655. struct enic_port_profile *pp;
  656. int err;
  657. ENIC_PP_BY_INDEX(enic, vf, pp, &err);
  658. if (err)
  659. return err;
  660. if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) {
  661. if (vf == PORT_SELF_VF) {
  662. memcpy(pp->vf_mac, mac, ETH_ALEN);
  663. return 0;
  664. } else {
  665. /*
  666. * For sriov vf's set the mac in hw
  667. */
  668. ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
  669. vnic_dev_set_mac_addr, mac);
  670. return enic_dev_status_to_errno(err);
  671. }
  672. } else
  673. return -EINVAL;
  674. }
  675. static int enic_set_vf_port(struct net_device *netdev, int vf,
  676. struct nlattr *port[])
  677. {
  678. struct enic *enic = netdev_priv(netdev);
  679. struct enic_port_profile prev_pp;
  680. struct enic_port_profile *pp;
  681. int err = 0, restore_pp = 1;
  682. ENIC_PP_BY_INDEX(enic, vf, pp, &err);
  683. if (err)
  684. return err;
  685. if (!port[IFLA_PORT_REQUEST])
  686. return -EOPNOTSUPP;
  687. memcpy(&prev_pp, pp, sizeof(*enic->pp));
  688. memset(pp, 0, sizeof(*enic->pp));
  689. pp->set |= ENIC_SET_REQUEST;
  690. pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]);
  691. if (port[IFLA_PORT_PROFILE]) {
  692. pp->set |= ENIC_SET_NAME;
  693. memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]),
  694. PORT_PROFILE_MAX);
  695. }
  696. if (port[IFLA_PORT_INSTANCE_UUID]) {
  697. pp->set |= ENIC_SET_INSTANCE;
  698. memcpy(pp->instance_uuid,
  699. nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX);
  700. }
  701. if (port[IFLA_PORT_HOST_UUID]) {
  702. pp->set |= ENIC_SET_HOST;
  703. memcpy(pp->host_uuid,
  704. nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX);
  705. }
  706. if (vf == PORT_SELF_VF) {
  707. /* Special case handling: mac came from IFLA_VF_MAC */
  708. if (!is_zero_ether_addr(prev_pp.vf_mac))
  709. memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN);
  710. if (is_zero_ether_addr(netdev->dev_addr))
  711. eth_hw_addr_random(netdev);
  712. } else {
  713. /* SR-IOV VF: get mac from adapter */
  714. ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
  715. vnic_dev_get_mac_addr, pp->mac_addr);
  716. if (err) {
  717. netdev_err(netdev, "Error getting mac for vf %d\n", vf);
  718. memcpy(pp, &prev_pp, sizeof(*pp));
  719. return enic_dev_status_to_errno(err);
  720. }
  721. }
  722. err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp);
  723. if (err) {
  724. if (restore_pp) {
  725. /* Things are still the way they were: Implicit
  726. * DISASSOCIATE failed
  727. */
  728. memcpy(pp, &prev_pp, sizeof(*pp));
  729. } else {
  730. memset(pp, 0, sizeof(*pp));
  731. if (vf == PORT_SELF_VF)
  732. memset(netdev->dev_addr, 0, ETH_ALEN);
  733. }
  734. } else {
  735. /* Set flag to indicate that the port assoc/disassoc
  736. * request has been sent out to fw
  737. */
  738. pp->set |= ENIC_PORT_REQUEST_APPLIED;
  739. /* If DISASSOCIATE, clean up all assigned/saved macaddresses */
  740. if (pp->request == PORT_REQUEST_DISASSOCIATE) {
  741. memset(pp->mac_addr, 0, ETH_ALEN);
  742. if (vf == PORT_SELF_VF)
  743. memset(netdev->dev_addr, 0, ETH_ALEN);
  744. }
  745. }
  746. if (vf == PORT_SELF_VF)
  747. memset(pp->vf_mac, 0, ETH_ALEN);
  748. return err;
  749. }
  750. static int enic_get_vf_port(struct net_device *netdev, int vf,
  751. struct sk_buff *skb)
  752. {
  753. struct enic *enic = netdev_priv(netdev);
  754. u16 response = PORT_PROFILE_RESPONSE_SUCCESS;
  755. struct enic_port_profile *pp;
  756. int err;
  757. ENIC_PP_BY_INDEX(enic, vf, pp, &err);
  758. if (err)
  759. return err;
  760. if (!(pp->set & ENIC_PORT_REQUEST_APPLIED))
  761. return -ENODATA;
  762. err = enic_process_get_pp_request(enic, vf, pp->request, &response);
  763. if (err)
  764. return err;
  765. if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) ||
  766. nla_put_u16(skb, IFLA_PORT_RESPONSE, response) ||
  767. ((pp->set & ENIC_SET_NAME) &&
  768. nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) ||
  769. ((pp->set & ENIC_SET_INSTANCE) &&
  770. nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX,
  771. pp->instance_uuid)) ||
  772. ((pp->set & ENIC_SET_HOST) &&
  773. nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid)))
  774. goto nla_put_failure;
  775. return 0;
  776. nla_put_failure:
  777. return -EMSGSIZE;
  778. }
  779. static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf)
  780. {
  781. struct enic *enic = vnic_dev_priv(rq->vdev);
  782. if (!buf->os_buf)
  783. return;
  784. pci_unmap_single(enic->pdev, buf->dma_addr,
  785. buf->len, PCI_DMA_FROMDEVICE);
  786. dev_kfree_skb_any(buf->os_buf);
  787. }
  788. static int enic_rq_alloc_buf(struct vnic_rq *rq)
  789. {
  790. struct enic *enic = vnic_dev_priv(rq->vdev);
  791. struct net_device *netdev = enic->netdev;
  792. struct sk_buff *skb;
  793. unsigned int len = netdev->mtu + VLAN_ETH_HLEN;
  794. unsigned int os_buf_index = 0;
  795. dma_addr_t dma_addr;
  796. skb = netdev_alloc_skb_ip_align(netdev, len);
  797. if (!skb)
  798. return -ENOMEM;
  799. dma_addr = pci_map_single(enic->pdev, skb->data,
  800. len, PCI_DMA_FROMDEVICE);
  801. enic_queue_rq_desc(rq, skb, os_buf_index,
  802. dma_addr, len);
  803. return 0;
  804. }
  805. static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size,
  806. u32 pkt_len)
  807. {
  808. if (ENIC_LARGE_PKT_THRESHOLD <= pkt_len)
  809. pkt_size->large_pkt_bytes_cnt += pkt_len;
  810. else
  811. pkt_size->small_pkt_bytes_cnt += pkt_len;
  812. }
  813. static void enic_rq_indicate_buf(struct vnic_rq *rq,
  814. struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
  815. int skipped, void *opaque)
  816. {
  817. struct enic *enic = vnic_dev_priv(rq->vdev);
  818. struct net_device *netdev = enic->netdev;
  819. struct sk_buff *skb;
  820. struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
  821. u8 type, color, eop, sop, ingress_port, vlan_stripped;
  822. u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof;
  823. u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok;
  824. u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc;
  825. u8 packet_error;
  826. u16 q_number, completed_index, bytes_written, vlan_tci, checksum;
  827. u32 rss_hash;
  828. if (skipped)
  829. return;
  830. skb = buf->os_buf;
  831. prefetch(skb->data - NET_IP_ALIGN);
  832. pci_unmap_single(enic->pdev, buf->dma_addr,
  833. buf->len, PCI_DMA_FROMDEVICE);
  834. cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc,
  835. &type, &color, &q_number, &completed_index,
  836. &ingress_port, &fcoe, &eop, &sop, &rss_type,
  837. &csum_not_calc, &rss_hash, &bytes_written,
  838. &packet_error, &vlan_stripped, &vlan_tci, &checksum,
  839. &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error,
  840. &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp,
  841. &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment,
  842. &fcs_ok);
  843. if (packet_error) {
  844. if (!fcs_ok) {
  845. if (bytes_written > 0)
  846. enic->rq_bad_fcs++;
  847. else if (bytes_written == 0)
  848. enic->rq_truncated_pkts++;
  849. }
  850. dev_kfree_skb_any(skb);
  851. return;
  852. }
  853. if (eop && bytes_written > 0) {
  854. /* Good receive
  855. */
  856. skb_put(skb, bytes_written);
  857. skb->protocol = eth_type_trans(skb, netdev);
  858. skb_record_rx_queue(skb, q_number);
  859. if (netdev->features & NETIF_F_RXHASH) {
  860. skb_set_hash(skb, rss_hash,
  861. (rss_type &
  862. (NIC_CFG_RSS_HASH_TYPE_TCP_IPV6_EX |
  863. NIC_CFG_RSS_HASH_TYPE_TCP_IPV6 |
  864. NIC_CFG_RSS_HASH_TYPE_TCP_IPV4)) ?
  865. PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
  866. }
  867. if ((netdev->features & NETIF_F_RXCSUM) && !csum_not_calc) {
  868. skb->csum = htons(checksum);
  869. skb->ip_summed = CHECKSUM_COMPLETE;
  870. }
  871. if (vlan_stripped)
  872. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
  873. if (netdev->features & NETIF_F_GRO)
  874. napi_gro_receive(&enic->napi[q_number], skb);
  875. else
  876. netif_receive_skb(skb);
  877. if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
  878. enic_intr_update_pkt_size(&cq->pkt_size_counter,
  879. bytes_written);
  880. } else {
  881. /* Buffer overflow
  882. */
  883. dev_kfree_skb_any(skb);
  884. }
  885. }
  886. static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
  887. u8 type, u16 q_number, u16 completed_index, void *opaque)
  888. {
  889. struct enic *enic = vnic_dev_priv(vdev);
  890. vnic_rq_service(&enic->rq[q_number], cq_desc,
  891. completed_index, VNIC_RQ_RETURN_DESC,
  892. enic_rq_indicate_buf, opaque);
  893. return 0;
  894. }
  895. static int enic_poll(struct napi_struct *napi, int budget)
  896. {
  897. struct net_device *netdev = napi->dev;
  898. struct enic *enic = netdev_priv(netdev);
  899. unsigned int cq_rq = enic_cq_rq(enic, 0);
  900. unsigned int cq_wq = enic_cq_wq(enic, 0);
  901. unsigned int intr = enic_legacy_io_intr();
  902. unsigned int rq_work_to_do = budget;
  903. unsigned int wq_work_to_do = -1; /* no limit */
  904. unsigned int work_done, rq_work_done = 0, wq_work_done;
  905. int err;
  906. /* Service RQ (first) and WQ
  907. */
  908. if (budget > 0)
  909. rq_work_done = vnic_cq_service(&enic->cq[cq_rq],
  910. rq_work_to_do, enic_rq_service, NULL);
  911. wq_work_done = vnic_cq_service(&enic->cq[cq_wq],
  912. wq_work_to_do, enic_wq_service, NULL);
  913. /* Accumulate intr event credits for this polling
  914. * cycle. An intr event is the completion of a
  915. * a WQ or RQ packet.
  916. */
  917. work_done = rq_work_done + wq_work_done;
  918. if (work_done > 0)
  919. vnic_intr_return_credits(&enic->intr[intr],
  920. work_done,
  921. 0 /* don't unmask intr */,
  922. 0 /* don't reset intr timer */);
  923. err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
  924. /* Buffer allocation failed. Stay in polling
  925. * mode so we can try to fill the ring again.
  926. */
  927. if (err)
  928. rq_work_done = rq_work_to_do;
  929. if (rq_work_done < rq_work_to_do) {
  930. /* Some work done, but not enough to stay in polling,
  931. * exit polling
  932. */
  933. napi_complete(napi);
  934. vnic_intr_unmask(&enic->intr[intr]);
  935. }
  936. return rq_work_done;
  937. }
  938. static void enic_set_int_moderation(struct enic *enic, struct vnic_rq *rq)
  939. {
  940. unsigned int intr = enic_msix_rq_intr(enic, rq->index);
  941. struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
  942. u32 timer = cq->tobe_rx_coal_timeval;
  943. if (cq->tobe_rx_coal_timeval != cq->cur_rx_coal_timeval) {
  944. vnic_intr_coalescing_timer_set(&enic->intr[intr], timer);
  945. cq->cur_rx_coal_timeval = cq->tobe_rx_coal_timeval;
  946. }
  947. }
  948. static void enic_calc_int_moderation(struct enic *enic, struct vnic_rq *rq)
  949. {
  950. struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
  951. struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
  952. struct vnic_rx_bytes_counter *pkt_size_counter = &cq->pkt_size_counter;
  953. int index;
  954. u32 timer;
  955. u32 range_start;
  956. u32 traffic;
  957. u64 delta;
  958. ktime_t now = ktime_get();
  959. delta = ktime_us_delta(now, cq->prev_ts);
  960. if (delta < ENIC_AIC_TS_BREAK)
  961. return;
  962. cq->prev_ts = now;
  963. traffic = pkt_size_counter->large_pkt_bytes_cnt +
  964. pkt_size_counter->small_pkt_bytes_cnt;
  965. /* The table takes Mbps
  966. * traffic *= 8 => bits
  967. * traffic *= (10^6 / delta) => bps
  968. * traffic /= 10^6 => Mbps
  969. *
  970. * Combining, traffic *= (8 / delta)
  971. */
  972. traffic <<= 3;
  973. traffic = delta > UINT_MAX ? 0 : traffic / (u32)delta;
  974. for (index = 0; index < ENIC_MAX_COALESCE_TIMERS; index++)
  975. if (traffic < mod_table[index].rx_rate)
  976. break;
  977. range_start = (pkt_size_counter->small_pkt_bytes_cnt >
  978. pkt_size_counter->large_pkt_bytes_cnt << 1) ?
  979. rx_coal->small_pkt_range_start :
  980. rx_coal->large_pkt_range_start;
  981. timer = range_start + ((rx_coal->range_end - range_start) *
  982. mod_table[index].range_percent / 100);
  983. /* Damping */
  984. cq->tobe_rx_coal_timeval = (timer + cq->tobe_rx_coal_timeval) >> 1;
  985. pkt_size_counter->large_pkt_bytes_cnt = 0;
  986. pkt_size_counter->small_pkt_bytes_cnt = 0;
  987. }
  988. static int enic_poll_msix(struct napi_struct *napi, int budget)
  989. {
  990. struct net_device *netdev = napi->dev;
  991. struct enic *enic = netdev_priv(netdev);
  992. unsigned int rq = (napi - &enic->napi[0]);
  993. unsigned int cq = enic_cq_rq(enic, rq);
  994. unsigned int intr = enic_msix_rq_intr(enic, rq);
  995. unsigned int work_to_do = budget;
  996. unsigned int work_done = 0;
  997. int err;
  998. /* Service RQ
  999. */
  1000. if (budget > 0)
  1001. work_done = vnic_cq_service(&enic->cq[cq],
  1002. work_to_do, enic_rq_service, NULL);
  1003. /* Return intr event credits for this polling
  1004. * cycle. An intr event is the completion of a
  1005. * RQ packet.
  1006. */
  1007. if (work_done > 0)
  1008. vnic_intr_return_credits(&enic->intr[intr],
  1009. work_done,
  1010. 0 /* don't unmask intr */,
  1011. 0 /* don't reset intr timer */);
  1012. err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
  1013. /* Buffer allocation failed. Stay in polling mode
  1014. * so we can try to fill the ring again.
  1015. */
  1016. if (err)
  1017. work_done = work_to_do;
  1018. if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
  1019. /* Call the function which refreshes
  1020. * the intr coalescing timer value based on
  1021. * the traffic. This is supported only in
  1022. * the case of MSI-x mode
  1023. */
  1024. enic_calc_int_moderation(enic, &enic->rq[rq]);
  1025. if (work_done < work_to_do) {
  1026. /* Some work done, but not enough to stay in polling,
  1027. * exit polling
  1028. */
  1029. napi_complete(napi);
  1030. if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
  1031. enic_set_int_moderation(enic, &enic->rq[rq]);
  1032. vnic_intr_unmask(&enic->intr[intr]);
  1033. }
  1034. return work_done;
  1035. }
  1036. static void enic_notify_timer(unsigned long data)
  1037. {
  1038. struct enic *enic = (struct enic *)data;
  1039. enic_notify_check(enic);
  1040. mod_timer(&enic->notify_timer,
  1041. round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD));
  1042. }
  1043. static void enic_free_intr(struct enic *enic)
  1044. {
  1045. struct net_device *netdev = enic->netdev;
  1046. unsigned int i;
  1047. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1048. case VNIC_DEV_INTR_MODE_INTX:
  1049. free_irq(enic->pdev->irq, netdev);
  1050. break;
  1051. case VNIC_DEV_INTR_MODE_MSI:
  1052. free_irq(enic->pdev->irq, enic);
  1053. break;
  1054. case VNIC_DEV_INTR_MODE_MSIX:
  1055. for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
  1056. if (enic->msix[i].requested)
  1057. free_irq(enic->msix_entry[i].vector,
  1058. enic->msix[i].devid);
  1059. break;
  1060. default:
  1061. break;
  1062. }
  1063. }
  1064. static int enic_request_intr(struct enic *enic)
  1065. {
  1066. struct net_device *netdev = enic->netdev;
  1067. unsigned int i, intr;
  1068. int err = 0;
  1069. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1070. case VNIC_DEV_INTR_MODE_INTX:
  1071. err = request_irq(enic->pdev->irq, enic_isr_legacy,
  1072. IRQF_SHARED, netdev->name, netdev);
  1073. break;
  1074. case VNIC_DEV_INTR_MODE_MSI:
  1075. err = request_irq(enic->pdev->irq, enic_isr_msi,
  1076. 0, netdev->name, enic);
  1077. break;
  1078. case VNIC_DEV_INTR_MODE_MSIX:
  1079. for (i = 0; i < enic->rq_count; i++) {
  1080. intr = enic_msix_rq_intr(enic, i);
  1081. snprintf(enic->msix[intr].devname,
  1082. sizeof(enic->msix[intr].devname),
  1083. "%.11s-rx-%d", netdev->name, i);
  1084. enic->msix[intr].isr = enic_isr_msix_rq;
  1085. enic->msix[intr].devid = &enic->napi[i];
  1086. }
  1087. for (i = 0; i < enic->wq_count; i++) {
  1088. intr = enic_msix_wq_intr(enic, i);
  1089. snprintf(enic->msix[intr].devname,
  1090. sizeof(enic->msix[intr].devname),
  1091. "%.11s-tx-%d", netdev->name, i);
  1092. enic->msix[intr].isr = enic_isr_msix_wq;
  1093. enic->msix[intr].devid = enic;
  1094. }
  1095. intr = enic_msix_err_intr(enic);
  1096. snprintf(enic->msix[intr].devname,
  1097. sizeof(enic->msix[intr].devname),
  1098. "%.11s-err", netdev->name);
  1099. enic->msix[intr].isr = enic_isr_msix_err;
  1100. enic->msix[intr].devid = enic;
  1101. intr = enic_msix_notify_intr(enic);
  1102. snprintf(enic->msix[intr].devname,
  1103. sizeof(enic->msix[intr].devname),
  1104. "%.11s-notify", netdev->name);
  1105. enic->msix[intr].isr = enic_isr_msix_notify;
  1106. enic->msix[intr].devid = enic;
  1107. for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
  1108. enic->msix[i].requested = 0;
  1109. for (i = 0; i < enic->intr_count; i++) {
  1110. err = request_irq(enic->msix_entry[i].vector,
  1111. enic->msix[i].isr, 0,
  1112. enic->msix[i].devname,
  1113. enic->msix[i].devid);
  1114. if (err) {
  1115. enic_free_intr(enic);
  1116. break;
  1117. }
  1118. enic->msix[i].requested = 1;
  1119. }
  1120. break;
  1121. default:
  1122. break;
  1123. }
  1124. return err;
  1125. }
  1126. static void enic_synchronize_irqs(struct enic *enic)
  1127. {
  1128. unsigned int i;
  1129. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1130. case VNIC_DEV_INTR_MODE_INTX:
  1131. case VNIC_DEV_INTR_MODE_MSI:
  1132. synchronize_irq(enic->pdev->irq);
  1133. break;
  1134. case VNIC_DEV_INTR_MODE_MSIX:
  1135. for (i = 0; i < enic->intr_count; i++)
  1136. synchronize_irq(enic->msix_entry[i].vector);
  1137. break;
  1138. default:
  1139. break;
  1140. }
  1141. }
  1142. static void enic_set_rx_coal_setting(struct enic *enic)
  1143. {
  1144. unsigned int speed;
  1145. int index = -1;
  1146. struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
  1147. /* If intr mode is not MSIX, do not do adaptive coalescing */
  1148. if (VNIC_DEV_INTR_MODE_MSIX != vnic_dev_get_intr_mode(enic->vdev)) {
  1149. netdev_info(enic->netdev, "INTR mode is not MSIX, Not initializing adaptive coalescing");
  1150. return;
  1151. }
  1152. /* 1. Read the link speed from fw
  1153. * 2. Pick the default range for the speed
  1154. * 3. Update it in enic->rx_coalesce_setting
  1155. */
  1156. speed = vnic_dev_port_speed(enic->vdev);
  1157. if (ENIC_LINK_SPEED_10G < speed)
  1158. index = ENIC_LINK_40G_INDEX;
  1159. else if (ENIC_LINK_SPEED_4G < speed)
  1160. index = ENIC_LINK_10G_INDEX;
  1161. else
  1162. index = ENIC_LINK_4G_INDEX;
  1163. rx_coal->small_pkt_range_start = mod_range[index].small_pkt_range_start;
  1164. rx_coal->large_pkt_range_start = mod_range[index].large_pkt_range_start;
  1165. rx_coal->range_end = ENIC_RX_COALESCE_RANGE_END;
  1166. /* Start with the value provided by UCSM */
  1167. for (index = 0; index < enic->rq_count; index++)
  1168. enic->cq[index].cur_rx_coal_timeval =
  1169. enic->config.intr_timer_usec;
  1170. rx_coal->use_adaptive_rx_coalesce = 1;
  1171. }
  1172. static int enic_dev_notify_set(struct enic *enic)
  1173. {
  1174. int err;
  1175. spin_lock(&enic->devcmd_lock);
  1176. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1177. case VNIC_DEV_INTR_MODE_INTX:
  1178. err = vnic_dev_notify_set(enic->vdev,
  1179. enic_legacy_notify_intr());
  1180. break;
  1181. case VNIC_DEV_INTR_MODE_MSIX:
  1182. err = vnic_dev_notify_set(enic->vdev,
  1183. enic_msix_notify_intr(enic));
  1184. break;
  1185. default:
  1186. err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */);
  1187. break;
  1188. }
  1189. spin_unlock(&enic->devcmd_lock);
  1190. return err;
  1191. }
  1192. static void enic_notify_timer_start(struct enic *enic)
  1193. {
  1194. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1195. case VNIC_DEV_INTR_MODE_MSI:
  1196. mod_timer(&enic->notify_timer, jiffies);
  1197. break;
  1198. default:
  1199. /* Using intr for notification for INTx/MSI-X */
  1200. break;
  1201. }
  1202. }
  1203. /* rtnl lock is held, process context */
  1204. static int enic_open(struct net_device *netdev)
  1205. {
  1206. struct enic *enic = netdev_priv(netdev);
  1207. unsigned int i;
  1208. int err;
  1209. err = enic_request_intr(enic);
  1210. if (err) {
  1211. netdev_err(netdev, "Unable to request irq.\n");
  1212. return err;
  1213. }
  1214. err = enic_dev_notify_set(enic);
  1215. if (err) {
  1216. netdev_err(netdev,
  1217. "Failed to alloc notify buffer, aborting.\n");
  1218. goto err_out_free_intr;
  1219. }
  1220. for (i = 0; i < enic->rq_count; i++) {
  1221. vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf);
  1222. /* Need at least one buffer on ring to get going */
  1223. if (vnic_rq_desc_used(&enic->rq[i]) == 0) {
  1224. netdev_err(netdev, "Unable to alloc receive buffers\n");
  1225. err = -ENOMEM;
  1226. goto err_out_notify_unset;
  1227. }
  1228. }
  1229. for (i = 0; i < enic->wq_count; i++)
  1230. vnic_wq_enable(&enic->wq[i]);
  1231. for (i = 0; i < enic->rq_count; i++)
  1232. vnic_rq_enable(&enic->rq[i]);
  1233. if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
  1234. enic_dev_add_station_addr(enic);
  1235. enic_set_rx_mode(netdev);
  1236. netif_tx_wake_all_queues(netdev);
  1237. for (i = 0; i < enic->rq_count; i++)
  1238. napi_enable(&enic->napi[i]);
  1239. enic_dev_enable(enic);
  1240. for (i = 0; i < enic->intr_count; i++)
  1241. vnic_intr_unmask(&enic->intr[i]);
  1242. enic_notify_timer_start(enic);
  1243. return 0;
  1244. err_out_notify_unset:
  1245. enic_dev_notify_unset(enic);
  1246. err_out_free_intr:
  1247. enic_free_intr(enic);
  1248. return err;
  1249. }
  1250. /* rtnl lock is held, process context */
  1251. static int enic_stop(struct net_device *netdev)
  1252. {
  1253. struct enic *enic = netdev_priv(netdev);
  1254. unsigned int i;
  1255. int err;
  1256. for (i = 0; i < enic->intr_count; i++) {
  1257. vnic_intr_mask(&enic->intr[i]);
  1258. (void)vnic_intr_masked(&enic->intr[i]); /* flush write */
  1259. }
  1260. enic_synchronize_irqs(enic);
  1261. del_timer_sync(&enic->notify_timer);
  1262. enic_dev_disable(enic);
  1263. for (i = 0; i < enic->rq_count; i++)
  1264. napi_disable(&enic->napi[i]);
  1265. netif_carrier_off(netdev);
  1266. netif_tx_disable(netdev);
  1267. if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
  1268. enic_dev_del_station_addr(enic);
  1269. for (i = 0; i < enic->wq_count; i++) {
  1270. err = vnic_wq_disable(&enic->wq[i]);
  1271. if (err)
  1272. return err;
  1273. }
  1274. for (i = 0; i < enic->rq_count; i++) {
  1275. err = vnic_rq_disable(&enic->rq[i]);
  1276. if (err)
  1277. return err;
  1278. }
  1279. enic_dev_notify_unset(enic);
  1280. enic_free_intr(enic);
  1281. for (i = 0; i < enic->wq_count; i++)
  1282. vnic_wq_clean(&enic->wq[i], enic_free_wq_buf);
  1283. for (i = 0; i < enic->rq_count; i++)
  1284. vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
  1285. for (i = 0; i < enic->cq_count; i++)
  1286. vnic_cq_clean(&enic->cq[i]);
  1287. for (i = 0; i < enic->intr_count; i++)
  1288. vnic_intr_clean(&enic->intr[i]);
  1289. return 0;
  1290. }
  1291. static int enic_change_mtu(struct net_device *netdev, int new_mtu)
  1292. {
  1293. struct enic *enic = netdev_priv(netdev);
  1294. int running = netif_running(netdev);
  1295. if (new_mtu < ENIC_MIN_MTU || new_mtu > ENIC_MAX_MTU)
  1296. return -EINVAL;
  1297. if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
  1298. return -EOPNOTSUPP;
  1299. if (running)
  1300. enic_stop(netdev);
  1301. netdev->mtu = new_mtu;
  1302. if (netdev->mtu > enic->port_mtu)
  1303. netdev_warn(netdev,
  1304. "interface MTU (%d) set higher than port MTU (%d)\n",
  1305. netdev->mtu, enic->port_mtu);
  1306. if (running)
  1307. enic_open(netdev);
  1308. return 0;
  1309. }
  1310. static void enic_change_mtu_work(struct work_struct *work)
  1311. {
  1312. struct enic *enic = container_of(work, struct enic, change_mtu_work);
  1313. struct net_device *netdev = enic->netdev;
  1314. int new_mtu = vnic_dev_mtu(enic->vdev);
  1315. int err;
  1316. unsigned int i;
  1317. new_mtu = max_t(int, ENIC_MIN_MTU, min_t(int, ENIC_MAX_MTU, new_mtu));
  1318. rtnl_lock();
  1319. /* Stop RQ */
  1320. del_timer_sync(&enic->notify_timer);
  1321. for (i = 0; i < enic->rq_count; i++)
  1322. napi_disable(&enic->napi[i]);
  1323. vnic_intr_mask(&enic->intr[0]);
  1324. enic_synchronize_irqs(enic);
  1325. err = vnic_rq_disable(&enic->rq[0]);
  1326. if (err) {
  1327. rtnl_unlock();
  1328. netdev_err(netdev, "Unable to disable RQ.\n");
  1329. return;
  1330. }
  1331. vnic_rq_clean(&enic->rq[0], enic_free_rq_buf);
  1332. vnic_cq_clean(&enic->cq[0]);
  1333. vnic_intr_clean(&enic->intr[0]);
  1334. /* Fill RQ with new_mtu-sized buffers */
  1335. netdev->mtu = new_mtu;
  1336. vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
  1337. /* Need at least one buffer on ring to get going */
  1338. if (vnic_rq_desc_used(&enic->rq[0]) == 0) {
  1339. rtnl_unlock();
  1340. netdev_err(netdev, "Unable to alloc receive buffers.\n");
  1341. return;
  1342. }
  1343. /* Start RQ */
  1344. vnic_rq_enable(&enic->rq[0]);
  1345. napi_enable(&enic->napi[0]);
  1346. vnic_intr_unmask(&enic->intr[0]);
  1347. enic_notify_timer_start(enic);
  1348. rtnl_unlock();
  1349. netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu);
  1350. }
  1351. #ifdef CONFIG_NET_POLL_CONTROLLER
  1352. static void enic_poll_controller(struct net_device *netdev)
  1353. {
  1354. struct enic *enic = netdev_priv(netdev);
  1355. struct vnic_dev *vdev = enic->vdev;
  1356. unsigned int i, intr;
  1357. switch (vnic_dev_get_intr_mode(vdev)) {
  1358. case VNIC_DEV_INTR_MODE_MSIX:
  1359. for (i = 0; i < enic->rq_count; i++) {
  1360. intr = enic_msix_rq_intr(enic, i);
  1361. enic_isr_msix_rq(enic->msix_entry[intr].vector,
  1362. &enic->napi[i]);
  1363. }
  1364. for (i = 0; i < enic->wq_count; i++) {
  1365. intr = enic_msix_wq_intr(enic, i);
  1366. enic_isr_msix_wq(enic->msix_entry[intr].vector, enic);
  1367. }
  1368. break;
  1369. case VNIC_DEV_INTR_MODE_MSI:
  1370. enic_isr_msi(enic->pdev->irq, enic);
  1371. break;
  1372. case VNIC_DEV_INTR_MODE_INTX:
  1373. enic_isr_legacy(enic->pdev->irq, netdev);
  1374. break;
  1375. default:
  1376. break;
  1377. }
  1378. }
  1379. #endif
  1380. static int enic_dev_wait(struct vnic_dev *vdev,
  1381. int (*start)(struct vnic_dev *, int),
  1382. int (*finished)(struct vnic_dev *, int *),
  1383. int arg)
  1384. {
  1385. unsigned long time;
  1386. int done;
  1387. int err;
  1388. BUG_ON(in_interrupt());
  1389. err = start(vdev, arg);
  1390. if (err)
  1391. return err;
  1392. /* Wait for func to complete...2 seconds max
  1393. */
  1394. time = jiffies + (HZ * 2);
  1395. do {
  1396. err = finished(vdev, &done);
  1397. if (err)
  1398. return err;
  1399. if (done)
  1400. return 0;
  1401. schedule_timeout_uninterruptible(HZ / 10);
  1402. } while (time_after(time, jiffies));
  1403. return -ETIMEDOUT;
  1404. }
  1405. static int enic_dev_open(struct enic *enic)
  1406. {
  1407. int err;
  1408. err = enic_dev_wait(enic->vdev, vnic_dev_open,
  1409. vnic_dev_open_done, 0);
  1410. if (err)
  1411. dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n",
  1412. err);
  1413. return err;
  1414. }
  1415. static int enic_dev_hang_reset(struct enic *enic)
  1416. {
  1417. int err;
  1418. err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset,
  1419. vnic_dev_hang_reset_done, 0);
  1420. if (err)
  1421. netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n",
  1422. err);
  1423. return err;
  1424. }
  1425. static int enic_set_rsskey(struct enic *enic)
  1426. {
  1427. dma_addr_t rss_key_buf_pa;
  1428. union vnic_rss_key *rss_key_buf_va = NULL;
  1429. union vnic_rss_key rss_key = {
  1430. .key[0].b = {85, 67, 83, 97, 119, 101, 115, 111, 109, 101},
  1431. .key[1].b = {80, 65, 76, 79, 117, 110, 105, 113, 117, 101},
  1432. .key[2].b = {76, 73, 78, 85, 88, 114, 111, 99, 107, 115},
  1433. .key[3].b = {69, 78, 73, 67, 105, 115, 99, 111, 111, 108},
  1434. };
  1435. int err;
  1436. rss_key_buf_va = pci_alloc_consistent(enic->pdev,
  1437. sizeof(union vnic_rss_key), &rss_key_buf_pa);
  1438. if (!rss_key_buf_va)
  1439. return -ENOMEM;
  1440. memcpy(rss_key_buf_va, &rss_key, sizeof(union vnic_rss_key));
  1441. spin_lock(&enic->devcmd_lock);
  1442. err = enic_set_rss_key(enic,
  1443. rss_key_buf_pa,
  1444. sizeof(union vnic_rss_key));
  1445. spin_unlock(&enic->devcmd_lock);
  1446. pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key),
  1447. rss_key_buf_va, rss_key_buf_pa);
  1448. return err;
  1449. }
  1450. static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits)
  1451. {
  1452. dma_addr_t rss_cpu_buf_pa;
  1453. union vnic_rss_cpu *rss_cpu_buf_va = NULL;
  1454. unsigned int i;
  1455. int err;
  1456. rss_cpu_buf_va = pci_alloc_consistent(enic->pdev,
  1457. sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa);
  1458. if (!rss_cpu_buf_va)
  1459. return -ENOMEM;
  1460. for (i = 0; i < (1 << rss_hash_bits); i++)
  1461. (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count;
  1462. spin_lock(&enic->devcmd_lock);
  1463. err = enic_set_rss_cpu(enic,
  1464. rss_cpu_buf_pa,
  1465. sizeof(union vnic_rss_cpu));
  1466. spin_unlock(&enic->devcmd_lock);
  1467. pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu),
  1468. rss_cpu_buf_va, rss_cpu_buf_pa);
  1469. return err;
  1470. }
  1471. static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu,
  1472. u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable)
  1473. {
  1474. const u8 tso_ipid_split_en = 0;
  1475. const u8 ig_vlan_strip_en = 1;
  1476. int err;
  1477. /* Enable VLAN tag stripping.
  1478. */
  1479. spin_lock(&enic->devcmd_lock);
  1480. err = enic_set_nic_cfg(enic,
  1481. rss_default_cpu, rss_hash_type,
  1482. rss_hash_bits, rss_base_cpu,
  1483. rss_enable, tso_ipid_split_en,
  1484. ig_vlan_strip_en);
  1485. spin_unlock(&enic->devcmd_lock);
  1486. return err;
  1487. }
  1488. static int enic_set_rss_nic_cfg(struct enic *enic)
  1489. {
  1490. struct device *dev = enic_get_dev(enic);
  1491. const u8 rss_default_cpu = 0;
  1492. const u8 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 |
  1493. NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 |
  1494. NIC_CFG_RSS_HASH_TYPE_IPV6 |
  1495. NIC_CFG_RSS_HASH_TYPE_TCP_IPV6;
  1496. const u8 rss_hash_bits = 7;
  1497. const u8 rss_base_cpu = 0;
  1498. u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1);
  1499. if (rss_enable) {
  1500. if (!enic_set_rsskey(enic)) {
  1501. if (enic_set_rsscpu(enic, rss_hash_bits)) {
  1502. rss_enable = 0;
  1503. dev_warn(dev, "RSS disabled, "
  1504. "Failed to set RSS cpu indirection table.");
  1505. }
  1506. } else {
  1507. rss_enable = 0;
  1508. dev_warn(dev, "RSS disabled, Failed to set RSS key.\n");
  1509. }
  1510. }
  1511. return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type,
  1512. rss_hash_bits, rss_base_cpu, rss_enable);
  1513. }
  1514. static void enic_reset(struct work_struct *work)
  1515. {
  1516. struct enic *enic = container_of(work, struct enic, reset);
  1517. if (!netif_running(enic->netdev))
  1518. return;
  1519. rtnl_lock();
  1520. spin_lock(&enic->enic_api_lock);
  1521. enic_dev_hang_notify(enic);
  1522. enic_stop(enic->netdev);
  1523. enic_dev_hang_reset(enic);
  1524. enic_reset_addr_lists(enic);
  1525. enic_init_vnic_resources(enic);
  1526. enic_set_rss_nic_cfg(enic);
  1527. enic_dev_set_ig_vlan_rewrite_mode(enic);
  1528. enic_open(enic->netdev);
  1529. spin_unlock(&enic->enic_api_lock);
  1530. call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
  1531. rtnl_unlock();
  1532. }
  1533. static int enic_set_intr_mode(struct enic *enic)
  1534. {
  1535. unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX);
  1536. unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX);
  1537. unsigned int i;
  1538. /* Set interrupt mode (INTx, MSI, MSI-X) depending
  1539. * on system capabilities.
  1540. *
  1541. * Try MSI-X first
  1542. *
  1543. * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs
  1544. * (the second to last INTR is used for WQ/RQ errors)
  1545. * (the last INTR is used for notifications)
  1546. */
  1547. BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2);
  1548. for (i = 0; i < n + m + 2; i++)
  1549. enic->msix_entry[i].entry = i;
  1550. /* Use multiple RQs if RSS is enabled
  1551. */
  1552. if (ENIC_SETTING(enic, RSS) &&
  1553. enic->config.intr_mode < 1 &&
  1554. enic->rq_count >= n &&
  1555. enic->wq_count >= m &&
  1556. enic->cq_count >= n + m &&
  1557. enic->intr_count >= n + m + 2) {
  1558. if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
  1559. n + m + 2, n + m + 2) > 0) {
  1560. enic->rq_count = n;
  1561. enic->wq_count = m;
  1562. enic->cq_count = n + m;
  1563. enic->intr_count = n + m + 2;
  1564. vnic_dev_set_intr_mode(enic->vdev,
  1565. VNIC_DEV_INTR_MODE_MSIX);
  1566. return 0;
  1567. }
  1568. }
  1569. if (enic->config.intr_mode < 1 &&
  1570. enic->rq_count >= 1 &&
  1571. enic->wq_count >= m &&
  1572. enic->cq_count >= 1 + m &&
  1573. enic->intr_count >= 1 + m + 2) {
  1574. if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
  1575. 1 + m + 2, 1 + m + 2) > 0) {
  1576. enic->rq_count = 1;
  1577. enic->wq_count = m;
  1578. enic->cq_count = 1 + m;
  1579. enic->intr_count = 1 + m + 2;
  1580. vnic_dev_set_intr_mode(enic->vdev,
  1581. VNIC_DEV_INTR_MODE_MSIX);
  1582. return 0;
  1583. }
  1584. }
  1585. /* Next try MSI
  1586. *
  1587. * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR
  1588. */
  1589. if (enic->config.intr_mode < 2 &&
  1590. enic->rq_count >= 1 &&
  1591. enic->wq_count >= 1 &&
  1592. enic->cq_count >= 2 &&
  1593. enic->intr_count >= 1 &&
  1594. !pci_enable_msi(enic->pdev)) {
  1595. enic->rq_count = 1;
  1596. enic->wq_count = 1;
  1597. enic->cq_count = 2;
  1598. enic->intr_count = 1;
  1599. vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI);
  1600. return 0;
  1601. }
  1602. /* Next try INTx
  1603. *
  1604. * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs
  1605. * (the first INTR is used for WQ/RQ)
  1606. * (the second INTR is used for WQ/RQ errors)
  1607. * (the last INTR is used for notifications)
  1608. */
  1609. if (enic->config.intr_mode < 3 &&
  1610. enic->rq_count >= 1 &&
  1611. enic->wq_count >= 1 &&
  1612. enic->cq_count >= 2 &&
  1613. enic->intr_count >= 3) {
  1614. enic->rq_count = 1;
  1615. enic->wq_count = 1;
  1616. enic->cq_count = 2;
  1617. enic->intr_count = 3;
  1618. vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX);
  1619. return 0;
  1620. }
  1621. vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
  1622. return -EINVAL;
  1623. }
  1624. static void enic_clear_intr_mode(struct enic *enic)
  1625. {
  1626. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1627. case VNIC_DEV_INTR_MODE_MSIX:
  1628. pci_disable_msix(enic->pdev);
  1629. break;
  1630. case VNIC_DEV_INTR_MODE_MSI:
  1631. pci_disable_msi(enic->pdev);
  1632. break;
  1633. default:
  1634. break;
  1635. }
  1636. vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
  1637. }
  1638. static const struct net_device_ops enic_netdev_dynamic_ops = {
  1639. .ndo_open = enic_open,
  1640. .ndo_stop = enic_stop,
  1641. .ndo_start_xmit = enic_hard_start_xmit,
  1642. .ndo_get_stats64 = enic_get_stats,
  1643. .ndo_validate_addr = eth_validate_addr,
  1644. .ndo_set_rx_mode = enic_set_rx_mode,
  1645. .ndo_set_mac_address = enic_set_mac_address_dynamic,
  1646. .ndo_change_mtu = enic_change_mtu,
  1647. .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
  1648. .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
  1649. .ndo_tx_timeout = enic_tx_timeout,
  1650. .ndo_set_vf_port = enic_set_vf_port,
  1651. .ndo_get_vf_port = enic_get_vf_port,
  1652. .ndo_set_vf_mac = enic_set_vf_mac,
  1653. #ifdef CONFIG_NET_POLL_CONTROLLER
  1654. .ndo_poll_controller = enic_poll_controller,
  1655. #endif
  1656. };
  1657. static const struct net_device_ops enic_netdev_ops = {
  1658. .ndo_open = enic_open,
  1659. .ndo_stop = enic_stop,
  1660. .ndo_start_xmit = enic_hard_start_xmit,
  1661. .ndo_get_stats64 = enic_get_stats,
  1662. .ndo_validate_addr = eth_validate_addr,
  1663. .ndo_set_mac_address = enic_set_mac_address,
  1664. .ndo_set_rx_mode = enic_set_rx_mode,
  1665. .ndo_change_mtu = enic_change_mtu,
  1666. .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
  1667. .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
  1668. .ndo_tx_timeout = enic_tx_timeout,
  1669. .ndo_set_vf_port = enic_set_vf_port,
  1670. .ndo_get_vf_port = enic_get_vf_port,
  1671. .ndo_set_vf_mac = enic_set_vf_mac,
  1672. #ifdef CONFIG_NET_POLL_CONTROLLER
  1673. .ndo_poll_controller = enic_poll_controller,
  1674. #endif
  1675. };
  1676. static void enic_dev_deinit(struct enic *enic)
  1677. {
  1678. unsigned int i;
  1679. for (i = 0; i < enic->rq_count; i++)
  1680. netif_napi_del(&enic->napi[i]);
  1681. enic_free_vnic_resources(enic);
  1682. enic_clear_intr_mode(enic);
  1683. }
  1684. static int enic_dev_init(struct enic *enic)
  1685. {
  1686. struct device *dev = enic_get_dev(enic);
  1687. struct net_device *netdev = enic->netdev;
  1688. unsigned int i;
  1689. int err;
  1690. /* Get interrupt coalesce timer info */
  1691. err = enic_dev_intr_coal_timer_info(enic);
  1692. if (err) {
  1693. dev_warn(dev, "Using default conversion factor for "
  1694. "interrupt coalesce timer\n");
  1695. vnic_dev_intr_coal_timer_info_default(enic->vdev);
  1696. }
  1697. /* Get vNIC configuration
  1698. */
  1699. err = enic_get_vnic_config(enic);
  1700. if (err) {
  1701. dev_err(dev, "Get vNIC configuration failed, aborting\n");
  1702. return err;
  1703. }
  1704. /* Get available resource counts
  1705. */
  1706. enic_get_res_counts(enic);
  1707. /* Set interrupt mode based on resource counts and system
  1708. * capabilities
  1709. */
  1710. err = enic_set_intr_mode(enic);
  1711. if (err) {
  1712. dev_err(dev, "Failed to set intr mode based on resource "
  1713. "counts and system capabilities, aborting\n");
  1714. return err;
  1715. }
  1716. /* Allocate and configure vNIC resources
  1717. */
  1718. err = enic_alloc_vnic_resources(enic);
  1719. if (err) {
  1720. dev_err(dev, "Failed to alloc vNIC resources, aborting\n");
  1721. goto err_out_free_vnic_resources;
  1722. }
  1723. enic_init_vnic_resources(enic);
  1724. err = enic_set_rss_nic_cfg(enic);
  1725. if (err) {
  1726. dev_err(dev, "Failed to config nic, aborting\n");
  1727. goto err_out_free_vnic_resources;
  1728. }
  1729. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1730. default:
  1731. netif_napi_add(netdev, &enic->napi[0], enic_poll, 64);
  1732. break;
  1733. case VNIC_DEV_INTR_MODE_MSIX:
  1734. for (i = 0; i < enic->rq_count; i++)
  1735. netif_napi_add(netdev, &enic->napi[i],
  1736. enic_poll_msix, 64);
  1737. break;
  1738. }
  1739. return 0;
  1740. err_out_free_vnic_resources:
  1741. enic_clear_intr_mode(enic);
  1742. enic_free_vnic_resources(enic);
  1743. return err;
  1744. }
  1745. static void enic_iounmap(struct enic *enic)
  1746. {
  1747. unsigned int i;
  1748. for (i = 0; i < ARRAY_SIZE(enic->bar); i++)
  1749. if (enic->bar[i].vaddr)
  1750. iounmap(enic->bar[i].vaddr);
  1751. }
  1752. static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1753. {
  1754. struct device *dev = &pdev->dev;
  1755. struct net_device *netdev;
  1756. struct enic *enic;
  1757. int using_dac = 0;
  1758. unsigned int i;
  1759. int err;
  1760. #ifdef CONFIG_PCI_IOV
  1761. int pos = 0;
  1762. #endif
  1763. int num_pps = 1;
  1764. /* Allocate net device structure and initialize. Private
  1765. * instance data is initialized to zero.
  1766. */
  1767. netdev = alloc_etherdev_mqs(sizeof(struct enic),
  1768. ENIC_RQ_MAX, ENIC_WQ_MAX);
  1769. if (!netdev)
  1770. return -ENOMEM;
  1771. pci_set_drvdata(pdev, netdev);
  1772. SET_NETDEV_DEV(netdev, &pdev->dev);
  1773. enic = netdev_priv(netdev);
  1774. enic->netdev = netdev;
  1775. enic->pdev = pdev;
  1776. /* Setup PCI resources
  1777. */
  1778. err = pci_enable_device_mem(pdev);
  1779. if (err) {
  1780. dev_err(dev, "Cannot enable PCI device, aborting\n");
  1781. goto err_out_free_netdev;
  1782. }
  1783. err = pci_request_regions(pdev, DRV_NAME);
  1784. if (err) {
  1785. dev_err(dev, "Cannot request PCI regions, aborting\n");
  1786. goto err_out_disable_device;
  1787. }
  1788. pci_set_master(pdev);
  1789. /* Query PCI controller on system for DMA addressing
  1790. * limitation for the device. Try 64-bit first, and
  1791. * fail to 32-bit.
  1792. */
  1793. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  1794. if (err) {
  1795. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  1796. if (err) {
  1797. dev_err(dev, "No usable DMA configuration, aborting\n");
  1798. goto err_out_release_regions;
  1799. }
  1800. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  1801. if (err) {
  1802. dev_err(dev, "Unable to obtain %u-bit DMA "
  1803. "for consistent allocations, aborting\n", 32);
  1804. goto err_out_release_regions;
  1805. }
  1806. } else {
  1807. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  1808. if (err) {
  1809. dev_err(dev, "Unable to obtain %u-bit DMA "
  1810. "for consistent allocations, aborting\n", 64);
  1811. goto err_out_release_regions;
  1812. }
  1813. using_dac = 1;
  1814. }
  1815. /* Map vNIC resources from BAR0-5
  1816. */
  1817. for (i = 0; i < ARRAY_SIZE(enic->bar); i++) {
  1818. if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
  1819. continue;
  1820. enic->bar[i].len = pci_resource_len(pdev, i);
  1821. enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len);
  1822. if (!enic->bar[i].vaddr) {
  1823. dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i);
  1824. err = -ENODEV;
  1825. goto err_out_iounmap;
  1826. }
  1827. enic->bar[i].bus_addr = pci_resource_start(pdev, i);
  1828. }
  1829. /* Register vNIC device
  1830. */
  1831. enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar,
  1832. ARRAY_SIZE(enic->bar));
  1833. if (!enic->vdev) {
  1834. dev_err(dev, "vNIC registration failed, aborting\n");
  1835. err = -ENODEV;
  1836. goto err_out_iounmap;
  1837. }
  1838. #ifdef CONFIG_PCI_IOV
  1839. /* Get number of subvnics */
  1840. pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
  1841. if (pos) {
  1842. pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF,
  1843. &enic->num_vfs);
  1844. if (enic->num_vfs) {
  1845. err = pci_enable_sriov(pdev, enic->num_vfs);
  1846. if (err) {
  1847. dev_err(dev, "SRIOV enable failed, aborting."
  1848. " pci_enable_sriov() returned %d\n",
  1849. err);
  1850. goto err_out_vnic_unregister;
  1851. }
  1852. enic->priv_flags |= ENIC_SRIOV_ENABLED;
  1853. num_pps = enic->num_vfs;
  1854. }
  1855. }
  1856. #endif
  1857. /* Allocate structure for port profiles */
  1858. enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL);
  1859. if (!enic->pp) {
  1860. err = -ENOMEM;
  1861. goto err_out_disable_sriov_pp;
  1862. }
  1863. /* Issue device open to get device in known state
  1864. */
  1865. err = enic_dev_open(enic);
  1866. if (err) {
  1867. dev_err(dev, "vNIC dev open failed, aborting\n");
  1868. goto err_out_disable_sriov;
  1869. }
  1870. /* Setup devcmd lock
  1871. */
  1872. spin_lock_init(&enic->devcmd_lock);
  1873. spin_lock_init(&enic->enic_api_lock);
  1874. /*
  1875. * Set ingress vlan rewrite mode before vnic initialization
  1876. */
  1877. err = enic_dev_set_ig_vlan_rewrite_mode(enic);
  1878. if (err) {
  1879. dev_err(dev,
  1880. "Failed to set ingress vlan rewrite mode, aborting.\n");
  1881. goto err_out_dev_close;
  1882. }
  1883. /* Issue device init to initialize the vnic-to-switch link.
  1884. * We'll start with carrier off and wait for link UP
  1885. * notification later to turn on carrier. We don't need
  1886. * to wait here for the vnic-to-switch link initialization
  1887. * to complete; link UP notification is the indication that
  1888. * the process is complete.
  1889. */
  1890. netif_carrier_off(netdev);
  1891. /* Do not call dev_init for a dynamic vnic.
  1892. * For a dynamic vnic, init_prov_info will be
  1893. * called later by an upper layer.
  1894. */
  1895. if (!enic_is_dynamic(enic)) {
  1896. err = vnic_dev_init(enic->vdev, 0);
  1897. if (err) {
  1898. dev_err(dev, "vNIC dev init failed, aborting\n");
  1899. goto err_out_dev_close;
  1900. }
  1901. }
  1902. err = enic_dev_init(enic);
  1903. if (err) {
  1904. dev_err(dev, "Device initialization failed, aborting\n");
  1905. goto err_out_dev_close;
  1906. }
  1907. netif_set_real_num_tx_queues(netdev, enic->wq_count);
  1908. netif_set_real_num_rx_queues(netdev, enic->rq_count);
  1909. /* Setup notification timer, HW reset task, and wq locks
  1910. */
  1911. init_timer(&enic->notify_timer);
  1912. enic->notify_timer.function = enic_notify_timer;
  1913. enic->notify_timer.data = (unsigned long)enic;
  1914. enic_set_rx_coal_setting(enic);
  1915. INIT_WORK(&enic->reset, enic_reset);
  1916. INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work);
  1917. for (i = 0; i < enic->wq_count; i++)
  1918. spin_lock_init(&enic->wq_lock[i]);
  1919. /* Register net device
  1920. */
  1921. enic->port_mtu = enic->config.mtu;
  1922. (void)enic_change_mtu(netdev, enic->port_mtu);
  1923. err = enic_set_mac_addr(netdev, enic->mac_addr);
  1924. if (err) {
  1925. dev_err(dev, "Invalid MAC address, aborting\n");
  1926. goto err_out_dev_deinit;
  1927. }
  1928. enic->tx_coalesce_usecs = enic->config.intr_timer_usec;
  1929. /* rx coalesce time already got initialized. This gets used
  1930. * if adaptive coal is turned off
  1931. */
  1932. enic->rx_coalesce_usecs = enic->tx_coalesce_usecs;
  1933. if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
  1934. netdev->netdev_ops = &enic_netdev_dynamic_ops;
  1935. else
  1936. netdev->netdev_ops = &enic_netdev_ops;
  1937. netdev->watchdog_timeo = 2 * HZ;
  1938. enic_set_ethtool_ops(netdev);
  1939. netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
  1940. if (ENIC_SETTING(enic, LOOP)) {
  1941. netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX;
  1942. enic->loop_enable = 1;
  1943. enic->loop_tag = enic->config.loop_tag;
  1944. dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag);
  1945. }
  1946. if (ENIC_SETTING(enic, TXCSUM))
  1947. netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM;
  1948. if (ENIC_SETTING(enic, TSO))
  1949. netdev->hw_features |= NETIF_F_TSO |
  1950. NETIF_F_TSO6 | NETIF_F_TSO_ECN;
  1951. if (ENIC_SETTING(enic, RSS))
  1952. netdev->hw_features |= NETIF_F_RXHASH;
  1953. if (ENIC_SETTING(enic, RXCSUM))
  1954. netdev->hw_features |= NETIF_F_RXCSUM;
  1955. netdev->features |= netdev->hw_features;
  1956. if (using_dac)
  1957. netdev->features |= NETIF_F_HIGHDMA;
  1958. netdev->priv_flags |= IFF_UNICAST_FLT;
  1959. err = register_netdev(netdev);
  1960. if (err) {
  1961. dev_err(dev, "Cannot register net device, aborting\n");
  1962. goto err_out_dev_deinit;
  1963. }
  1964. return 0;
  1965. err_out_dev_deinit:
  1966. enic_dev_deinit(enic);
  1967. err_out_dev_close:
  1968. vnic_dev_close(enic->vdev);
  1969. err_out_disable_sriov:
  1970. kfree(enic->pp);
  1971. err_out_disable_sriov_pp:
  1972. #ifdef CONFIG_PCI_IOV
  1973. if (enic_sriov_enabled(enic)) {
  1974. pci_disable_sriov(pdev);
  1975. enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
  1976. }
  1977. err_out_vnic_unregister:
  1978. #endif
  1979. vnic_dev_unregister(enic->vdev);
  1980. err_out_iounmap:
  1981. enic_iounmap(enic);
  1982. err_out_release_regions:
  1983. pci_release_regions(pdev);
  1984. err_out_disable_device:
  1985. pci_disable_device(pdev);
  1986. err_out_free_netdev:
  1987. free_netdev(netdev);
  1988. return err;
  1989. }
  1990. static void enic_remove(struct pci_dev *pdev)
  1991. {
  1992. struct net_device *netdev = pci_get_drvdata(pdev);
  1993. if (netdev) {
  1994. struct enic *enic = netdev_priv(netdev);
  1995. cancel_work_sync(&enic->reset);
  1996. cancel_work_sync(&enic->change_mtu_work);
  1997. unregister_netdev(netdev);
  1998. enic_dev_deinit(enic);
  1999. vnic_dev_close(enic->vdev);
  2000. #ifdef CONFIG_PCI_IOV
  2001. if (enic_sriov_enabled(enic)) {
  2002. pci_disable_sriov(pdev);
  2003. enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
  2004. }
  2005. #endif
  2006. kfree(enic->pp);
  2007. vnic_dev_unregister(enic->vdev);
  2008. enic_iounmap(enic);
  2009. pci_release_regions(pdev);
  2010. pci_disable_device(pdev);
  2011. free_netdev(netdev);
  2012. }
  2013. }
  2014. static struct pci_driver enic_driver = {
  2015. .name = DRV_NAME,
  2016. .id_table = enic_id_table,
  2017. .probe = enic_probe,
  2018. .remove = enic_remove,
  2019. };
  2020. static int __init enic_init_module(void)
  2021. {
  2022. pr_info("%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION);
  2023. return pci_register_driver(&enic_driver);
  2024. }
  2025. static void __exit enic_cleanup_module(void)
  2026. {
  2027. pci_unregister_driver(&enic_driver);
  2028. }
  2029. module_init(enic_init_module);
  2030. module_exit(enic_cleanup_module);