xgbe-main.c 16 KB

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  1. /*
  2. * AMD 10Gb Ethernet driver
  3. *
  4. * This file is available to you under your choice of the following two
  5. * licenses:
  6. *
  7. * License 1: GPLv2
  8. *
  9. * Copyright (c) 2014 Advanced Micro Devices, Inc.
  10. *
  11. * This file is free software; you may copy, redistribute and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation, either version 2 of the License, or (at
  14. * your option) any later version.
  15. *
  16. * This file is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  23. *
  24. * This file incorporates work covered by the following copyright and
  25. * permission notice:
  26. * The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27. * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28. * Inc. unless otherwise expressly agreed to in writing between Synopsys
  29. * and you.
  30. *
  31. * The Software IS NOT an item of Licensed Software or Licensed Product
  32. * under any End User Software License Agreement or Agreement for Licensed
  33. * Product with Synopsys or any supplement thereto. Permission is hereby
  34. * granted, free of charge, to any person obtaining a copy of this software
  35. * annotated with this license and the Software, to deal in the Software
  36. * without restriction, including without limitation the rights to use,
  37. * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38. * of the Software, and to permit persons to whom the Software is furnished
  39. * to do so, subject to the following conditions:
  40. *
  41. * The above copyright notice and this permission notice shall be included
  42. * in all copies or substantial portions of the Software.
  43. *
  44. * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45. * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46. * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47. * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54. * THE POSSIBILITY OF SUCH DAMAGE.
  55. *
  56. *
  57. * License 2: Modified BSD
  58. *
  59. * Copyright (c) 2014 Advanced Micro Devices, Inc.
  60. * All rights reserved.
  61. *
  62. * Redistribution and use in source and binary forms, with or without
  63. * modification, are permitted provided that the following conditions are met:
  64. * * Redistributions of source code must retain the above copyright
  65. * notice, this list of conditions and the following disclaimer.
  66. * * Redistributions in binary form must reproduce the above copyright
  67. * notice, this list of conditions and the following disclaimer in the
  68. * documentation and/or other materials provided with the distribution.
  69. * * Neither the name of Advanced Micro Devices, Inc. nor the
  70. * names of its contributors may be used to endorse or promote products
  71. * derived from this software without specific prior written permission.
  72. *
  73. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76. * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83. *
  84. * This file incorporates work covered by the following copyright and
  85. * permission notice:
  86. * The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87. * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88. * Inc. unless otherwise expressly agreed to in writing between Synopsys
  89. * and you.
  90. *
  91. * The Software IS NOT an item of Licensed Software or Licensed Product
  92. * under any End User Software License Agreement or Agreement for Licensed
  93. * Product with Synopsys or any supplement thereto. Permission is hereby
  94. * granted, free of charge, to any person obtaining a copy of this software
  95. * annotated with this license and the Software, to deal in the Software
  96. * without restriction, including without limitation the rights to use,
  97. * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98. * of the Software, and to permit persons to whom the Software is furnished
  99. * to do so, subject to the following conditions:
  100. *
  101. * The above copyright notice and this permission notice shall be included
  102. * in all copies or substantial portions of the Software.
  103. *
  104. * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  105. * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  106. * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  107. * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  108. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  109. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  110. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  111. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  112. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  113. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  114. * THE POSSIBILITY OF SUCH DAMAGE.
  115. */
  116. #include <linux/module.h>
  117. #include <linux/device.h>
  118. #include <linux/platform_device.h>
  119. #include <linux/spinlock.h>
  120. #include <linux/netdevice.h>
  121. #include <linux/etherdevice.h>
  122. #include <linux/io.h>
  123. #include <linux/of.h>
  124. #include <linux/of_net.h>
  125. #include <linux/clk.h>
  126. #include "xgbe.h"
  127. #include "xgbe-common.h"
  128. MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
  129. MODULE_LICENSE("Dual BSD/GPL");
  130. MODULE_VERSION(XGBE_DRV_VERSION);
  131. MODULE_DESCRIPTION(XGBE_DRV_DESC);
  132. static struct xgbe_channel *xgbe_alloc_rings(struct xgbe_prv_data *pdata)
  133. {
  134. struct xgbe_channel *channel_mem, *channel;
  135. struct xgbe_ring *tx_ring, *rx_ring;
  136. unsigned int count, i;
  137. DBGPR("-->xgbe_alloc_rings\n");
  138. count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
  139. channel_mem = devm_kcalloc(pdata->dev, count,
  140. sizeof(struct xgbe_channel), GFP_KERNEL);
  141. if (!channel_mem)
  142. return NULL;
  143. tx_ring = devm_kcalloc(pdata->dev, pdata->tx_ring_count,
  144. sizeof(struct xgbe_ring), GFP_KERNEL);
  145. if (!tx_ring)
  146. return NULL;
  147. rx_ring = devm_kcalloc(pdata->dev, pdata->rx_ring_count,
  148. sizeof(struct xgbe_ring), GFP_KERNEL);
  149. if (!rx_ring)
  150. return NULL;
  151. for (i = 0, channel = channel_mem; i < count; i++, channel++) {
  152. snprintf(channel->name, sizeof(channel->name), "channel-%d", i);
  153. channel->pdata = pdata;
  154. channel->queue_index = i;
  155. channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
  156. (DMA_CH_INC * i);
  157. if (i < pdata->tx_ring_count) {
  158. spin_lock_init(&tx_ring->lock);
  159. channel->tx_ring = tx_ring++;
  160. }
  161. if (i < pdata->rx_ring_count) {
  162. spin_lock_init(&tx_ring->lock);
  163. channel->rx_ring = rx_ring++;
  164. }
  165. DBGPR(" %s - queue_index=%u, dma_regs=%p, tx=%p, rx=%p\n",
  166. channel->name, channel->queue_index, channel->dma_regs,
  167. channel->tx_ring, channel->rx_ring);
  168. }
  169. pdata->channel_count = count;
  170. DBGPR("<--xgbe_alloc_rings\n");
  171. return channel_mem;
  172. }
  173. static void xgbe_default_config(struct xgbe_prv_data *pdata)
  174. {
  175. DBGPR("-->xgbe_default_config\n");
  176. pdata->pblx8 = DMA_PBL_X8_ENABLE;
  177. pdata->tx_sf_mode = MTL_TSF_ENABLE;
  178. pdata->tx_threshold = MTL_TX_THRESHOLD_64;
  179. pdata->tx_pbl = DMA_PBL_16;
  180. pdata->tx_osp_mode = DMA_OSP_ENABLE;
  181. pdata->rx_sf_mode = MTL_RSF_DISABLE;
  182. pdata->rx_threshold = MTL_RX_THRESHOLD_64;
  183. pdata->rx_pbl = DMA_PBL_16;
  184. pdata->pause_autoneg = 1;
  185. pdata->tx_pause = 1;
  186. pdata->rx_pause = 1;
  187. pdata->power_down = 0;
  188. pdata->default_autoneg = AUTONEG_ENABLE;
  189. pdata->default_speed = SPEED_10000;
  190. DBGPR("<--xgbe_default_config\n");
  191. }
  192. static void xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
  193. {
  194. xgbe_init_function_ptrs_dev(&pdata->hw_if);
  195. xgbe_init_function_ptrs_desc(&pdata->desc_if);
  196. }
  197. static int xgbe_probe(struct platform_device *pdev)
  198. {
  199. struct xgbe_prv_data *pdata;
  200. struct xgbe_hw_if *hw_if;
  201. struct xgbe_desc_if *desc_if;
  202. struct net_device *netdev;
  203. struct device *dev = &pdev->dev;
  204. struct resource *res;
  205. const u8 *mac_addr;
  206. int ret;
  207. DBGPR("--> xgbe_probe\n");
  208. netdev = alloc_etherdev_mq(sizeof(struct xgbe_prv_data),
  209. XGBE_MAX_DMA_CHANNELS);
  210. if (!netdev) {
  211. dev_err(dev, "alloc_etherdev failed\n");
  212. ret = -ENOMEM;
  213. goto err_alloc;
  214. }
  215. SET_NETDEV_DEV(netdev, dev);
  216. pdata = netdev_priv(netdev);
  217. pdata->netdev = netdev;
  218. pdata->pdev = pdev;
  219. pdata->dev = dev;
  220. platform_set_drvdata(pdev, netdev);
  221. spin_lock_init(&pdata->lock);
  222. mutex_init(&pdata->xpcs_mutex);
  223. /* Set and validate the number of descriptors for a ring */
  224. BUILD_BUG_ON_NOT_POWER_OF_2(TX_DESC_CNT);
  225. pdata->tx_desc_count = TX_DESC_CNT;
  226. if (pdata->tx_desc_count & (pdata->tx_desc_count - 1)) {
  227. dev_err(dev, "tx descriptor count (%d) is not valid\n",
  228. pdata->tx_desc_count);
  229. ret = -EINVAL;
  230. goto err_io;
  231. }
  232. BUILD_BUG_ON_NOT_POWER_OF_2(RX_DESC_CNT);
  233. pdata->rx_desc_count = RX_DESC_CNT;
  234. if (pdata->rx_desc_count & (pdata->rx_desc_count - 1)) {
  235. dev_err(dev, "rx descriptor count (%d) is not valid\n",
  236. pdata->rx_desc_count);
  237. ret = -EINVAL;
  238. goto err_io;
  239. }
  240. /* Obtain the system clock setting */
  241. pdata->sysclock = devm_clk_get(dev, NULL);
  242. if (IS_ERR(pdata->sysclock)) {
  243. dev_err(dev, "devm_clk_get failed\n");
  244. ret = PTR_ERR(pdata->sysclock);
  245. goto err_io;
  246. }
  247. /* Obtain the mmio areas for the device */
  248. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  249. pdata->xgmac_regs = devm_ioremap_resource(dev, res);
  250. if (IS_ERR(pdata->xgmac_regs)) {
  251. dev_err(dev, "xgmac ioremap failed\n");
  252. ret = PTR_ERR(pdata->xgmac_regs);
  253. goto err_io;
  254. }
  255. DBGPR(" xgmac_regs = %p\n", pdata->xgmac_regs);
  256. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  257. pdata->xpcs_regs = devm_ioremap_resource(dev, res);
  258. if (IS_ERR(pdata->xpcs_regs)) {
  259. dev_err(dev, "xpcs ioremap failed\n");
  260. ret = PTR_ERR(pdata->xpcs_regs);
  261. goto err_io;
  262. }
  263. DBGPR(" xpcs_regs = %p\n", pdata->xpcs_regs);
  264. /* Set the DMA mask */
  265. if (!dev->dma_mask)
  266. dev->dma_mask = &dev->coherent_dma_mask;
  267. *(dev->dma_mask) = DMA_BIT_MASK(40);
  268. dev->coherent_dma_mask = DMA_BIT_MASK(40);
  269. ret = platform_get_irq(pdev, 0);
  270. if (ret < 0) {
  271. dev_err(dev, "platform_get_irq failed\n");
  272. goto err_io;
  273. }
  274. netdev->irq = ret;
  275. netdev->base_addr = (unsigned long)pdata->xgmac_regs;
  276. /* Set all the function pointers */
  277. xgbe_init_all_fptrs(pdata);
  278. hw_if = &pdata->hw_if;
  279. desc_if = &pdata->desc_if;
  280. /* Issue software reset to device */
  281. hw_if->exit(pdata);
  282. /* Populate the hardware features */
  283. xgbe_get_all_hw_features(pdata);
  284. /* Retrieve the MAC address */
  285. mac_addr = of_get_mac_address(dev->of_node);
  286. if (!mac_addr) {
  287. dev_err(dev, "invalid mac address for this device\n");
  288. ret = -EINVAL;
  289. goto err_io;
  290. }
  291. memcpy(netdev->dev_addr, mac_addr, netdev->addr_len);
  292. /* Retrieve the PHY mode - it must be "xgmii" */
  293. pdata->phy_mode = of_get_phy_mode(dev->of_node);
  294. if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
  295. dev_err(dev, "invalid phy-mode specified for this device\n");
  296. ret = -EINVAL;
  297. goto err_io;
  298. }
  299. /* Set default configuration data */
  300. xgbe_default_config(pdata);
  301. /* Calculate the number of Tx and Rx rings to be created */
  302. pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(),
  303. pdata->hw_feat.tx_ch_cnt);
  304. ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
  305. if (ret) {
  306. dev_err(dev, "error setting real tx queue count\n");
  307. goto err_io;
  308. }
  309. pdata->rx_ring_count = min_t(unsigned int,
  310. netif_get_num_default_rss_queues(),
  311. pdata->hw_feat.rx_ch_cnt);
  312. ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count);
  313. if (ret) {
  314. dev_err(dev, "error setting real rx queue count\n");
  315. goto err_io;
  316. }
  317. /* Allocate the rings for the DMA channels */
  318. pdata->channel = xgbe_alloc_rings(pdata);
  319. if (!pdata->channel) {
  320. dev_err(dev, "ring allocation failed\n");
  321. ret = -ENOMEM;
  322. goto err_io;
  323. }
  324. /* Prepare to regsiter with MDIO */
  325. pdata->mii_bus_id = kasprintf(GFP_KERNEL, "%s", pdev->name);
  326. if (!pdata->mii_bus_id) {
  327. dev_err(dev, "failed to allocate mii bus id\n");
  328. ret = -ENOMEM;
  329. goto err_io;
  330. }
  331. ret = xgbe_mdio_register(pdata);
  332. if (ret)
  333. goto err_bus_id;
  334. /* Set network and ethtool operations */
  335. netdev->netdev_ops = xgbe_get_netdev_ops();
  336. netdev->ethtool_ops = xgbe_get_ethtool_ops();
  337. /* Set device features */
  338. netdev->hw_features = NETIF_F_SG |
  339. NETIF_F_IP_CSUM |
  340. NETIF_F_IPV6_CSUM |
  341. NETIF_F_RXCSUM |
  342. NETIF_F_TSO |
  343. NETIF_F_TSO6 |
  344. NETIF_F_GRO |
  345. NETIF_F_HW_VLAN_CTAG_RX |
  346. NETIF_F_HW_VLAN_CTAG_TX;
  347. netdev->vlan_features |= NETIF_F_SG |
  348. NETIF_F_IP_CSUM |
  349. NETIF_F_IPV6_CSUM |
  350. NETIF_F_TSO |
  351. NETIF_F_TSO6;
  352. netdev->features |= netdev->hw_features;
  353. pdata->netdev_features = netdev->features;
  354. xgbe_init_rx_coalesce(pdata);
  355. xgbe_init_tx_coalesce(pdata);
  356. netif_carrier_off(netdev);
  357. ret = register_netdev(netdev);
  358. if (ret) {
  359. dev_err(dev, "net device registration failed\n");
  360. goto err_reg_netdev;
  361. }
  362. xgbe_debugfs_init(pdata);
  363. netdev_notice(netdev, "net device enabled\n");
  364. DBGPR("<-- xgbe_probe\n");
  365. return 0;
  366. err_reg_netdev:
  367. xgbe_mdio_unregister(pdata);
  368. err_bus_id:
  369. kfree(pdata->mii_bus_id);
  370. err_io:
  371. free_netdev(netdev);
  372. err_alloc:
  373. dev_notice(dev, "net device not enabled\n");
  374. return ret;
  375. }
  376. static int xgbe_remove(struct platform_device *pdev)
  377. {
  378. struct net_device *netdev = platform_get_drvdata(pdev);
  379. struct xgbe_prv_data *pdata = netdev_priv(netdev);
  380. DBGPR("-->xgbe_remove\n");
  381. xgbe_debugfs_exit(pdata);
  382. unregister_netdev(netdev);
  383. xgbe_mdio_unregister(pdata);
  384. kfree(pdata->mii_bus_id);
  385. free_netdev(netdev);
  386. DBGPR("<--xgbe_remove\n");
  387. return 0;
  388. }
  389. #ifdef CONFIG_PM
  390. static int xgbe_suspend(struct device *dev)
  391. {
  392. struct net_device *netdev = dev_get_drvdata(dev);
  393. int ret;
  394. DBGPR("-->xgbe_suspend\n");
  395. if (!netif_running(netdev)) {
  396. DBGPR("<--xgbe_dev_suspend\n");
  397. return -EINVAL;
  398. }
  399. ret = xgbe_powerdown(netdev, XGMAC_DRIVER_CONTEXT);
  400. DBGPR("<--xgbe_suspend\n");
  401. return ret;
  402. }
  403. static int xgbe_resume(struct device *dev)
  404. {
  405. struct net_device *netdev = dev_get_drvdata(dev);
  406. int ret;
  407. DBGPR("-->xgbe_resume\n");
  408. if (!netif_running(netdev)) {
  409. DBGPR("<--xgbe_dev_resume\n");
  410. return -EINVAL;
  411. }
  412. ret = xgbe_powerup(netdev, XGMAC_DRIVER_CONTEXT);
  413. DBGPR("<--xgbe_resume\n");
  414. return ret;
  415. }
  416. #endif /* CONFIG_PM */
  417. static const struct of_device_id xgbe_of_match[] = {
  418. { .compatible = "amd,xgbe-seattle-v1a", },
  419. {},
  420. };
  421. MODULE_DEVICE_TABLE(of, xgbe_of_match);
  422. static SIMPLE_DEV_PM_OPS(xgbe_pm_ops, xgbe_suspend, xgbe_resume);
  423. static struct platform_driver xgbe_driver = {
  424. .driver = {
  425. .name = "amd-xgbe",
  426. .of_match_table = xgbe_of_match,
  427. .pm = &xgbe_pm_ops,
  428. },
  429. .probe = xgbe_probe,
  430. .remove = xgbe_remove,
  431. };
  432. module_platform_driver(xgbe_driver);