au1000_eth.c 33 KB

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  1. /*
  2. *
  3. * Alchemy Au1x00 ethernet driver
  4. *
  5. * Copyright 2001-2003, 2006 MontaVista Software Inc.
  6. * Copyright 2002 TimeSys Corp.
  7. * Added ethtool/mii-tool support,
  8. * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
  9. * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
  10. * or riemer@riemer-nt.de: fixed the link beat detection with
  11. * ioctls (SIOCGMIIPHY)
  12. * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
  13. * converted to use linux-2.6.x's PHY framework
  14. *
  15. * Author: MontaVista Software, Inc.
  16. * ppopov@mvista.com or source@mvista.com
  17. *
  18. * ########################################################################
  19. *
  20. * This program is free software; you can distribute it and/or modify it
  21. * under the terms of the GNU General Public License (Version 2) as
  22. * published by the Free Software Foundation.
  23. *
  24. * This program is distributed in the hope it will be useful, but WITHOUT
  25. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  26. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  27. * for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License along
  30. * with this program; if not, see <http://www.gnu.org/licenses/>.
  31. *
  32. * ########################################################################
  33. *
  34. *
  35. */
  36. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  37. #include <linux/capability.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/module.h>
  40. #include <linux/kernel.h>
  41. #include <linux/string.h>
  42. #include <linux/timer.h>
  43. #include <linux/errno.h>
  44. #include <linux/in.h>
  45. #include <linux/ioport.h>
  46. #include <linux/bitops.h>
  47. #include <linux/slab.h>
  48. #include <linux/interrupt.h>
  49. #include <linux/netdevice.h>
  50. #include <linux/etherdevice.h>
  51. #include <linux/ethtool.h>
  52. #include <linux/mii.h>
  53. #include <linux/skbuff.h>
  54. #include <linux/delay.h>
  55. #include <linux/crc32.h>
  56. #include <linux/phy.h>
  57. #include <linux/platform_device.h>
  58. #include <linux/cpu.h>
  59. #include <linux/io.h>
  60. #include <asm/mipsregs.h>
  61. #include <asm/irq.h>
  62. #include <asm/processor.h>
  63. #include <au1000.h>
  64. #include <au1xxx_eth.h>
  65. #include <prom.h>
  66. #include "au1000_eth.h"
  67. #ifdef AU1000_ETH_DEBUG
  68. static int au1000_debug = 5;
  69. #else
  70. static int au1000_debug = 3;
  71. #endif
  72. #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
  73. NETIF_MSG_PROBE | \
  74. NETIF_MSG_LINK)
  75. #define DRV_NAME "au1000_eth"
  76. #define DRV_VERSION "1.7"
  77. #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
  78. #define DRV_DESC "Au1xxx on-chip Ethernet driver"
  79. MODULE_AUTHOR(DRV_AUTHOR);
  80. MODULE_DESCRIPTION(DRV_DESC);
  81. MODULE_LICENSE("GPL");
  82. MODULE_VERSION(DRV_VERSION);
  83. /*
  84. * Theory of operation
  85. *
  86. * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
  87. * There are four receive and four transmit descriptors. These
  88. * descriptors are not in memory; rather, they are just a set of
  89. * hardware registers.
  90. *
  91. * Since the Au1000 has a coherent data cache, the receive and
  92. * transmit buffers are allocated from the KSEG0 segment. The
  93. * hardware registers, however, are still mapped at KSEG1 to
  94. * make sure there's no out-of-order writes, and that all writes
  95. * complete immediately.
  96. */
  97. /*
  98. * board-specific configurations
  99. *
  100. * PHY detection algorithm
  101. *
  102. * If phy_static_config is undefined, the PHY setup is
  103. * autodetected:
  104. *
  105. * mii_probe() first searches the current MAC's MII bus for a PHY,
  106. * selecting the first (or last, if phy_search_highest_addr is
  107. * defined) PHY address not already claimed by another netdev.
  108. *
  109. * If nothing was found that way when searching for the 2nd ethernet
  110. * controller's PHY and phy1_search_mac0 is defined, then
  111. * the first MII bus is searched as well for an unclaimed PHY; this is
  112. * needed in case of a dual-PHY accessible only through the MAC0's MII
  113. * bus.
  114. *
  115. * Finally, if no PHY is found, then the corresponding ethernet
  116. * controller is not registered to the network subsystem.
  117. */
  118. /* autodetection defaults: phy1_search_mac0 */
  119. /* static PHY setup
  120. *
  121. * most boards PHY setup should be detectable properly with the
  122. * autodetection algorithm in mii_probe(), but in some cases (e.g. if
  123. * you have a switch attached, or want to use the PHY's interrupt
  124. * notification capabilities) you can provide a static PHY
  125. * configuration here
  126. *
  127. * IRQs may only be set, if a PHY address was configured
  128. * If a PHY address is given, also a bus id is required to be set
  129. *
  130. * ps: make sure the used irqs are configured properly in the board
  131. * specific irq-map
  132. */
  133. static void au1000_enable_mac(struct net_device *dev, int force_reset)
  134. {
  135. unsigned long flags;
  136. struct au1000_private *aup = netdev_priv(dev);
  137. spin_lock_irqsave(&aup->lock, flags);
  138. if (force_reset || (!aup->mac_enabled)) {
  139. writel(MAC_EN_CLOCK_ENABLE, aup->enable);
  140. au_sync_delay(2);
  141. writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
  142. | MAC_EN_CLOCK_ENABLE), aup->enable);
  143. au_sync_delay(2);
  144. aup->mac_enabled = 1;
  145. }
  146. spin_unlock_irqrestore(&aup->lock, flags);
  147. }
  148. /*
  149. * MII operations
  150. */
  151. static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
  152. {
  153. struct au1000_private *aup = netdev_priv(dev);
  154. u32 *const mii_control_reg = &aup->mac->mii_control;
  155. u32 *const mii_data_reg = &aup->mac->mii_data;
  156. u32 timedout = 20;
  157. u32 mii_control;
  158. while (readl(mii_control_reg) & MAC_MII_BUSY) {
  159. mdelay(1);
  160. if (--timedout == 0) {
  161. netdev_err(dev, "read_MII busy timeout!!\n");
  162. return -1;
  163. }
  164. }
  165. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  166. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
  167. writel(mii_control, mii_control_reg);
  168. timedout = 20;
  169. while (readl(mii_control_reg) & MAC_MII_BUSY) {
  170. mdelay(1);
  171. if (--timedout == 0) {
  172. netdev_err(dev, "mdio_read busy timeout!!\n");
  173. return -1;
  174. }
  175. }
  176. return readl(mii_data_reg);
  177. }
  178. static void au1000_mdio_write(struct net_device *dev, int phy_addr,
  179. int reg, u16 value)
  180. {
  181. struct au1000_private *aup = netdev_priv(dev);
  182. u32 *const mii_control_reg = &aup->mac->mii_control;
  183. u32 *const mii_data_reg = &aup->mac->mii_data;
  184. u32 timedout = 20;
  185. u32 mii_control;
  186. while (readl(mii_control_reg) & MAC_MII_BUSY) {
  187. mdelay(1);
  188. if (--timedout == 0) {
  189. netdev_err(dev, "mdio_write busy timeout!!\n");
  190. return;
  191. }
  192. }
  193. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  194. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
  195. writel(value, mii_data_reg);
  196. writel(mii_control, mii_control_reg);
  197. }
  198. static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
  199. {
  200. /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
  201. * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus)
  202. */
  203. struct net_device *const dev = bus->priv;
  204. /* make sure the MAC associated with this
  205. * mii_bus is enabled
  206. */
  207. au1000_enable_mac(dev, 0);
  208. return au1000_mdio_read(dev, phy_addr, regnum);
  209. }
  210. static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
  211. u16 value)
  212. {
  213. struct net_device *const dev = bus->priv;
  214. /* make sure the MAC associated with this
  215. * mii_bus is enabled
  216. */
  217. au1000_enable_mac(dev, 0);
  218. au1000_mdio_write(dev, phy_addr, regnum, value);
  219. return 0;
  220. }
  221. static int au1000_mdiobus_reset(struct mii_bus *bus)
  222. {
  223. struct net_device *const dev = bus->priv;
  224. /* make sure the MAC associated with this
  225. * mii_bus is enabled
  226. */
  227. au1000_enable_mac(dev, 0);
  228. return 0;
  229. }
  230. static void au1000_hard_stop(struct net_device *dev)
  231. {
  232. struct au1000_private *aup = netdev_priv(dev);
  233. u32 reg;
  234. netif_dbg(aup, drv, dev, "hard stop\n");
  235. reg = readl(&aup->mac->control);
  236. reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
  237. writel(reg, &aup->mac->control);
  238. au_sync_delay(10);
  239. }
  240. static void au1000_enable_rx_tx(struct net_device *dev)
  241. {
  242. struct au1000_private *aup = netdev_priv(dev);
  243. u32 reg;
  244. netif_dbg(aup, hw, dev, "enable_rx_tx\n");
  245. reg = readl(&aup->mac->control);
  246. reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
  247. writel(reg, &aup->mac->control);
  248. au_sync_delay(10);
  249. }
  250. static void
  251. au1000_adjust_link(struct net_device *dev)
  252. {
  253. struct au1000_private *aup = netdev_priv(dev);
  254. struct phy_device *phydev = aup->phy_dev;
  255. unsigned long flags;
  256. u32 reg;
  257. int status_change = 0;
  258. BUG_ON(!aup->phy_dev);
  259. spin_lock_irqsave(&aup->lock, flags);
  260. if (phydev->link && (aup->old_speed != phydev->speed)) {
  261. /* speed changed */
  262. switch (phydev->speed) {
  263. case SPEED_10:
  264. case SPEED_100:
  265. break;
  266. default:
  267. netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
  268. phydev->speed);
  269. break;
  270. }
  271. aup->old_speed = phydev->speed;
  272. status_change = 1;
  273. }
  274. if (phydev->link && (aup->old_duplex != phydev->duplex)) {
  275. /* duplex mode changed */
  276. /* switching duplex mode requires to disable rx and tx! */
  277. au1000_hard_stop(dev);
  278. reg = readl(&aup->mac->control);
  279. if (DUPLEX_FULL == phydev->duplex) {
  280. reg |= MAC_FULL_DUPLEX;
  281. reg &= ~MAC_DISABLE_RX_OWN;
  282. } else {
  283. reg &= ~MAC_FULL_DUPLEX;
  284. reg |= MAC_DISABLE_RX_OWN;
  285. }
  286. writel(reg, &aup->mac->control);
  287. au_sync_delay(1);
  288. au1000_enable_rx_tx(dev);
  289. aup->old_duplex = phydev->duplex;
  290. status_change = 1;
  291. }
  292. if (phydev->link != aup->old_link) {
  293. /* link state changed */
  294. if (!phydev->link) {
  295. /* link went down */
  296. aup->old_speed = 0;
  297. aup->old_duplex = -1;
  298. }
  299. aup->old_link = phydev->link;
  300. status_change = 1;
  301. }
  302. spin_unlock_irqrestore(&aup->lock, flags);
  303. if (status_change) {
  304. if (phydev->link)
  305. netdev_info(dev, "link up (%d/%s)\n",
  306. phydev->speed,
  307. DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
  308. else
  309. netdev_info(dev, "link down\n");
  310. }
  311. }
  312. static int au1000_mii_probe(struct net_device *dev)
  313. {
  314. struct au1000_private *const aup = netdev_priv(dev);
  315. struct phy_device *phydev = NULL;
  316. int phy_addr;
  317. if (aup->phy_static_config) {
  318. BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
  319. if (aup->phy_addr)
  320. phydev = aup->mii_bus->phy_map[aup->phy_addr];
  321. else
  322. netdev_info(dev, "using PHY-less setup\n");
  323. return 0;
  324. }
  325. /* find the first (lowest address) PHY
  326. * on the current MAC's MII bus
  327. */
  328. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
  329. if (aup->mii_bus->phy_map[phy_addr]) {
  330. phydev = aup->mii_bus->phy_map[phy_addr];
  331. if (!aup->phy_search_highest_addr)
  332. /* break out with first one found */
  333. break;
  334. }
  335. if (aup->phy1_search_mac0) {
  336. /* try harder to find a PHY */
  337. if (!phydev && (aup->mac_id == 1)) {
  338. /* no PHY found, maybe we have a dual PHY? */
  339. dev_info(&dev->dev, ": no PHY found on MAC1, "
  340. "let's see if it's attached to MAC0...\n");
  341. /* find the first (lowest address) non-attached
  342. * PHY on the MAC0 MII bus
  343. */
  344. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
  345. struct phy_device *const tmp_phydev =
  346. aup->mii_bus->phy_map[phy_addr];
  347. if (aup->mac_id == 1)
  348. break;
  349. /* no PHY here... */
  350. if (!tmp_phydev)
  351. continue;
  352. /* already claimed by MAC0 */
  353. if (tmp_phydev->attached_dev)
  354. continue;
  355. phydev = tmp_phydev;
  356. break; /* found it */
  357. }
  358. }
  359. }
  360. if (!phydev) {
  361. netdev_err(dev, "no PHY found\n");
  362. return -1;
  363. }
  364. /* now we are supposed to have a proper phydev, to attach to... */
  365. BUG_ON(phydev->attached_dev);
  366. phydev = phy_connect(dev, dev_name(&phydev->dev),
  367. &au1000_adjust_link, PHY_INTERFACE_MODE_MII);
  368. if (IS_ERR(phydev)) {
  369. netdev_err(dev, "Could not attach to PHY\n");
  370. return PTR_ERR(phydev);
  371. }
  372. /* mask with MAC supported features */
  373. phydev->supported &= (SUPPORTED_10baseT_Half
  374. | SUPPORTED_10baseT_Full
  375. | SUPPORTED_100baseT_Half
  376. | SUPPORTED_100baseT_Full
  377. | SUPPORTED_Autoneg
  378. /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
  379. | SUPPORTED_MII
  380. | SUPPORTED_TP);
  381. phydev->advertising = phydev->supported;
  382. aup->old_link = 0;
  383. aup->old_speed = 0;
  384. aup->old_duplex = -1;
  385. aup->phy_dev = phydev;
  386. netdev_info(dev, "attached PHY driver [%s] "
  387. "(mii_bus:phy_addr=%s, irq=%d)\n",
  388. phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
  389. return 0;
  390. }
  391. /*
  392. * Buffer allocation/deallocation routines. The buffer descriptor returned
  393. * has the virtual and dma address of a buffer suitable for
  394. * both, receive and transmit operations.
  395. */
  396. static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
  397. {
  398. struct db_dest *pDB;
  399. pDB = aup->pDBfree;
  400. if (pDB)
  401. aup->pDBfree = pDB->pnext;
  402. return pDB;
  403. }
  404. void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
  405. {
  406. struct db_dest *pDBfree = aup->pDBfree;
  407. if (pDBfree)
  408. pDBfree->pnext = pDB;
  409. aup->pDBfree = pDB;
  410. }
  411. static void au1000_reset_mac_unlocked(struct net_device *dev)
  412. {
  413. struct au1000_private *const aup = netdev_priv(dev);
  414. int i;
  415. au1000_hard_stop(dev);
  416. writel(MAC_EN_CLOCK_ENABLE, aup->enable);
  417. au_sync_delay(2);
  418. writel(0, aup->enable);
  419. au_sync_delay(2);
  420. aup->tx_full = 0;
  421. for (i = 0; i < NUM_RX_DMA; i++) {
  422. /* reset control bits */
  423. aup->rx_dma_ring[i]->buff_stat &= ~0xf;
  424. }
  425. for (i = 0; i < NUM_TX_DMA; i++) {
  426. /* reset control bits */
  427. aup->tx_dma_ring[i]->buff_stat &= ~0xf;
  428. }
  429. aup->mac_enabled = 0;
  430. }
  431. static void au1000_reset_mac(struct net_device *dev)
  432. {
  433. struct au1000_private *const aup = netdev_priv(dev);
  434. unsigned long flags;
  435. netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
  436. (unsigned)aup);
  437. spin_lock_irqsave(&aup->lock, flags);
  438. au1000_reset_mac_unlocked(dev);
  439. spin_unlock_irqrestore(&aup->lock, flags);
  440. }
  441. /*
  442. * Setup the receive and transmit "rings". These pointers are the addresses
  443. * of the rx and tx MAC DMA registers so they are fixed by the hardware --
  444. * these are not descriptors sitting in memory.
  445. */
  446. static void
  447. au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base)
  448. {
  449. int i;
  450. for (i = 0; i < NUM_RX_DMA; i++) {
  451. aup->rx_dma_ring[i] = (struct rx_dma *)
  452. (tx_base + 0x100 + sizeof(struct rx_dma) * i);
  453. }
  454. for (i = 0; i < NUM_TX_DMA; i++) {
  455. aup->tx_dma_ring[i] = (struct tx_dma *)
  456. (tx_base + sizeof(struct tx_dma) * i);
  457. }
  458. }
  459. /*
  460. * ethtool operations
  461. */
  462. static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  463. {
  464. struct au1000_private *aup = netdev_priv(dev);
  465. if (aup->phy_dev)
  466. return phy_ethtool_gset(aup->phy_dev, cmd);
  467. return -EINVAL;
  468. }
  469. static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  470. {
  471. struct au1000_private *aup = netdev_priv(dev);
  472. if (!capable(CAP_NET_ADMIN))
  473. return -EPERM;
  474. if (aup->phy_dev)
  475. return phy_ethtool_sset(aup->phy_dev, cmd);
  476. return -EINVAL;
  477. }
  478. static void
  479. au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  480. {
  481. struct au1000_private *aup = netdev_priv(dev);
  482. strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
  483. strlcpy(info->version, DRV_VERSION, sizeof(info->version));
  484. snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME,
  485. aup->mac_id);
  486. info->regdump_len = 0;
  487. }
  488. static void au1000_set_msglevel(struct net_device *dev, u32 value)
  489. {
  490. struct au1000_private *aup = netdev_priv(dev);
  491. aup->msg_enable = value;
  492. }
  493. static u32 au1000_get_msglevel(struct net_device *dev)
  494. {
  495. struct au1000_private *aup = netdev_priv(dev);
  496. return aup->msg_enable;
  497. }
  498. static const struct ethtool_ops au1000_ethtool_ops = {
  499. .get_settings = au1000_get_settings,
  500. .set_settings = au1000_set_settings,
  501. .get_drvinfo = au1000_get_drvinfo,
  502. .get_link = ethtool_op_get_link,
  503. .get_msglevel = au1000_get_msglevel,
  504. .set_msglevel = au1000_set_msglevel,
  505. };
  506. /*
  507. * Initialize the interface.
  508. *
  509. * When the device powers up, the clocks are disabled and the
  510. * mac is in reset state. When the interface is closed, we
  511. * do the same -- reset the device and disable the clocks to
  512. * conserve power. Thus, whenever au1000_init() is called,
  513. * the device should already be in reset state.
  514. */
  515. static int au1000_init(struct net_device *dev)
  516. {
  517. struct au1000_private *aup = netdev_priv(dev);
  518. unsigned long flags;
  519. int i;
  520. u32 control;
  521. netif_dbg(aup, hw, dev, "au1000_init\n");
  522. /* bring the device out of reset */
  523. au1000_enable_mac(dev, 1);
  524. spin_lock_irqsave(&aup->lock, flags);
  525. writel(0, &aup->mac->control);
  526. aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
  527. aup->tx_tail = aup->tx_head;
  528. aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
  529. writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
  530. &aup->mac->mac_addr_high);
  531. writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
  532. dev->dev_addr[1]<<8 | dev->dev_addr[0],
  533. &aup->mac->mac_addr_low);
  534. for (i = 0; i < NUM_RX_DMA; i++)
  535. aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
  536. au_sync();
  537. control = MAC_RX_ENABLE | MAC_TX_ENABLE;
  538. #ifndef CONFIG_CPU_LITTLE_ENDIAN
  539. control |= MAC_BIG_ENDIAN;
  540. #endif
  541. if (aup->phy_dev) {
  542. if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
  543. control |= MAC_FULL_DUPLEX;
  544. else
  545. control |= MAC_DISABLE_RX_OWN;
  546. } else { /* PHY-less op, assume full-duplex */
  547. control |= MAC_FULL_DUPLEX;
  548. }
  549. writel(control, &aup->mac->control);
  550. writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
  551. au_sync();
  552. spin_unlock_irqrestore(&aup->lock, flags);
  553. return 0;
  554. }
  555. static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
  556. {
  557. struct net_device_stats *ps = &dev->stats;
  558. ps->rx_packets++;
  559. if (status & RX_MCAST_FRAME)
  560. ps->multicast++;
  561. if (status & RX_ERROR) {
  562. ps->rx_errors++;
  563. if (status & RX_MISSED_FRAME)
  564. ps->rx_missed_errors++;
  565. if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
  566. ps->rx_length_errors++;
  567. if (status & RX_CRC_ERROR)
  568. ps->rx_crc_errors++;
  569. if (status & RX_COLL)
  570. ps->collisions++;
  571. } else
  572. ps->rx_bytes += status & RX_FRAME_LEN_MASK;
  573. }
  574. /*
  575. * Au1000 receive routine.
  576. */
  577. static int au1000_rx(struct net_device *dev)
  578. {
  579. struct au1000_private *aup = netdev_priv(dev);
  580. struct sk_buff *skb;
  581. struct rx_dma *prxd;
  582. u32 buff_stat, status;
  583. struct db_dest *pDB;
  584. u32 frmlen;
  585. netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
  586. prxd = aup->rx_dma_ring[aup->rx_head];
  587. buff_stat = prxd->buff_stat;
  588. while (buff_stat & RX_T_DONE) {
  589. status = prxd->status;
  590. pDB = aup->rx_db_inuse[aup->rx_head];
  591. au1000_update_rx_stats(dev, status);
  592. if (!(status & RX_ERROR)) {
  593. /* good frame */
  594. frmlen = (status & RX_FRAME_LEN_MASK);
  595. frmlen -= 4; /* Remove FCS */
  596. skb = netdev_alloc_skb(dev, frmlen + 2);
  597. if (skb == NULL) {
  598. dev->stats.rx_dropped++;
  599. continue;
  600. }
  601. skb_reserve(skb, 2); /* 16 byte IP header align */
  602. skb_copy_to_linear_data(skb,
  603. (unsigned char *)pDB->vaddr, frmlen);
  604. skb_put(skb, frmlen);
  605. skb->protocol = eth_type_trans(skb, dev);
  606. netif_rx(skb); /* pass the packet to upper layers */
  607. } else {
  608. if (au1000_debug > 4) {
  609. pr_err("rx_error(s):");
  610. if (status & RX_MISSED_FRAME)
  611. pr_cont(" miss");
  612. if (status & RX_WDOG_TIMER)
  613. pr_cont(" wdog");
  614. if (status & RX_RUNT)
  615. pr_cont(" runt");
  616. if (status & RX_OVERLEN)
  617. pr_cont(" overlen");
  618. if (status & RX_COLL)
  619. pr_cont(" coll");
  620. if (status & RX_MII_ERROR)
  621. pr_cont(" mii error");
  622. if (status & RX_CRC_ERROR)
  623. pr_cont(" crc error");
  624. if (status & RX_LEN_ERROR)
  625. pr_cont(" len error");
  626. if (status & RX_U_CNTRL_FRAME)
  627. pr_cont(" u control frame");
  628. pr_cont("\n");
  629. }
  630. }
  631. prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
  632. aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
  633. au_sync();
  634. /* next descriptor */
  635. prxd = aup->rx_dma_ring[aup->rx_head];
  636. buff_stat = prxd->buff_stat;
  637. }
  638. return 0;
  639. }
  640. static void au1000_update_tx_stats(struct net_device *dev, u32 status)
  641. {
  642. struct au1000_private *aup = netdev_priv(dev);
  643. struct net_device_stats *ps = &dev->stats;
  644. if (status & TX_FRAME_ABORTED) {
  645. if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
  646. if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
  647. /* any other tx errors are only valid
  648. * in half duplex mode
  649. */
  650. ps->tx_errors++;
  651. ps->tx_aborted_errors++;
  652. }
  653. } else {
  654. ps->tx_errors++;
  655. ps->tx_aborted_errors++;
  656. if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
  657. ps->tx_carrier_errors++;
  658. }
  659. }
  660. }
  661. /*
  662. * Called from the interrupt service routine to acknowledge
  663. * the TX DONE bits. This is a must if the irq is setup as
  664. * edge triggered.
  665. */
  666. static void au1000_tx_ack(struct net_device *dev)
  667. {
  668. struct au1000_private *aup = netdev_priv(dev);
  669. struct tx_dma *ptxd;
  670. ptxd = aup->tx_dma_ring[aup->tx_tail];
  671. while (ptxd->buff_stat & TX_T_DONE) {
  672. au1000_update_tx_stats(dev, ptxd->status);
  673. ptxd->buff_stat &= ~TX_T_DONE;
  674. ptxd->len = 0;
  675. au_sync();
  676. aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
  677. ptxd = aup->tx_dma_ring[aup->tx_tail];
  678. if (aup->tx_full) {
  679. aup->tx_full = 0;
  680. netif_wake_queue(dev);
  681. }
  682. }
  683. }
  684. /*
  685. * Au1000 interrupt service routine.
  686. */
  687. static irqreturn_t au1000_interrupt(int irq, void *dev_id)
  688. {
  689. struct net_device *dev = dev_id;
  690. /* Handle RX interrupts first to minimize chance of overrun */
  691. au1000_rx(dev);
  692. au1000_tx_ack(dev);
  693. return IRQ_RETVAL(1);
  694. }
  695. static int au1000_open(struct net_device *dev)
  696. {
  697. int retval;
  698. struct au1000_private *aup = netdev_priv(dev);
  699. netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
  700. retval = request_irq(dev->irq, au1000_interrupt, 0,
  701. dev->name, dev);
  702. if (retval) {
  703. netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
  704. return retval;
  705. }
  706. retval = au1000_init(dev);
  707. if (retval) {
  708. netdev_err(dev, "error in au1000_init\n");
  709. free_irq(dev->irq, dev);
  710. return retval;
  711. }
  712. if (aup->phy_dev) {
  713. /* cause the PHY state machine to schedule a link state check */
  714. aup->phy_dev->state = PHY_CHANGELINK;
  715. phy_start(aup->phy_dev);
  716. }
  717. netif_start_queue(dev);
  718. netif_dbg(aup, drv, dev, "open: Initialization done.\n");
  719. return 0;
  720. }
  721. static int au1000_close(struct net_device *dev)
  722. {
  723. unsigned long flags;
  724. struct au1000_private *const aup = netdev_priv(dev);
  725. netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
  726. if (aup->phy_dev)
  727. phy_stop(aup->phy_dev);
  728. spin_lock_irqsave(&aup->lock, flags);
  729. au1000_reset_mac_unlocked(dev);
  730. /* stop the device */
  731. netif_stop_queue(dev);
  732. /* disable the interrupt */
  733. free_irq(dev->irq, dev);
  734. spin_unlock_irqrestore(&aup->lock, flags);
  735. return 0;
  736. }
  737. /*
  738. * Au1000 transmit routine.
  739. */
  740. static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
  741. {
  742. struct au1000_private *aup = netdev_priv(dev);
  743. struct net_device_stats *ps = &dev->stats;
  744. struct tx_dma *ptxd;
  745. u32 buff_stat;
  746. struct db_dest *pDB;
  747. int i;
  748. netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
  749. (unsigned)aup, skb->len,
  750. skb->data, aup->tx_head);
  751. ptxd = aup->tx_dma_ring[aup->tx_head];
  752. buff_stat = ptxd->buff_stat;
  753. if (buff_stat & TX_DMA_ENABLE) {
  754. /* We've wrapped around and the transmitter is still busy */
  755. netif_stop_queue(dev);
  756. aup->tx_full = 1;
  757. return NETDEV_TX_BUSY;
  758. } else if (buff_stat & TX_T_DONE) {
  759. au1000_update_tx_stats(dev, ptxd->status);
  760. ptxd->len = 0;
  761. }
  762. if (aup->tx_full) {
  763. aup->tx_full = 0;
  764. netif_wake_queue(dev);
  765. }
  766. pDB = aup->tx_db_inuse[aup->tx_head];
  767. skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
  768. if (skb->len < ETH_ZLEN) {
  769. for (i = skb->len; i < ETH_ZLEN; i++)
  770. ((char *)pDB->vaddr)[i] = 0;
  771. ptxd->len = ETH_ZLEN;
  772. } else
  773. ptxd->len = skb->len;
  774. ps->tx_packets++;
  775. ps->tx_bytes += ptxd->len;
  776. ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
  777. au_sync();
  778. dev_kfree_skb(skb);
  779. aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
  780. return NETDEV_TX_OK;
  781. }
  782. /*
  783. * The Tx ring has been full longer than the watchdog timeout
  784. * value. The transmitter must be hung?
  785. */
  786. static void au1000_tx_timeout(struct net_device *dev)
  787. {
  788. netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
  789. au1000_reset_mac(dev);
  790. au1000_init(dev);
  791. dev->trans_start = jiffies; /* prevent tx timeout */
  792. netif_wake_queue(dev);
  793. }
  794. static void au1000_multicast_list(struct net_device *dev)
  795. {
  796. struct au1000_private *aup = netdev_priv(dev);
  797. u32 reg;
  798. netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
  799. reg = readl(&aup->mac->control);
  800. if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
  801. reg |= MAC_PROMISCUOUS;
  802. } else if ((dev->flags & IFF_ALLMULTI) ||
  803. netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
  804. reg |= MAC_PASS_ALL_MULTI;
  805. reg &= ~MAC_PROMISCUOUS;
  806. netdev_info(dev, "Pass all multicast\n");
  807. } else {
  808. struct netdev_hw_addr *ha;
  809. u32 mc_filter[2]; /* Multicast hash filter */
  810. mc_filter[1] = mc_filter[0] = 0;
  811. netdev_for_each_mc_addr(ha, dev)
  812. set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
  813. (long *)mc_filter);
  814. writel(mc_filter[1], &aup->mac->multi_hash_high);
  815. writel(mc_filter[0], &aup->mac->multi_hash_low);
  816. reg &= ~MAC_PROMISCUOUS;
  817. reg |= MAC_HASH_MODE;
  818. }
  819. writel(reg, &aup->mac->control);
  820. }
  821. static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  822. {
  823. struct au1000_private *aup = netdev_priv(dev);
  824. if (!netif_running(dev))
  825. return -EINVAL;
  826. if (!aup->phy_dev)
  827. return -EINVAL; /* PHY not controllable */
  828. return phy_mii_ioctl(aup->phy_dev, rq, cmd);
  829. }
  830. static const struct net_device_ops au1000_netdev_ops = {
  831. .ndo_open = au1000_open,
  832. .ndo_stop = au1000_close,
  833. .ndo_start_xmit = au1000_tx,
  834. .ndo_set_rx_mode = au1000_multicast_list,
  835. .ndo_do_ioctl = au1000_ioctl,
  836. .ndo_tx_timeout = au1000_tx_timeout,
  837. .ndo_set_mac_address = eth_mac_addr,
  838. .ndo_validate_addr = eth_validate_addr,
  839. .ndo_change_mtu = eth_change_mtu,
  840. };
  841. static int au1000_probe(struct platform_device *pdev)
  842. {
  843. static unsigned version_printed;
  844. struct au1000_private *aup = NULL;
  845. struct au1000_eth_platform_data *pd;
  846. struct net_device *dev = NULL;
  847. struct db_dest *pDB, *pDBfree;
  848. int irq, i, err = 0;
  849. struct resource *base, *macen, *macdma;
  850. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  851. if (!base) {
  852. dev_err(&pdev->dev, "failed to retrieve base register\n");
  853. err = -ENODEV;
  854. goto out;
  855. }
  856. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  857. if (!macen) {
  858. dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
  859. err = -ENODEV;
  860. goto out;
  861. }
  862. irq = platform_get_irq(pdev, 0);
  863. if (irq < 0) {
  864. dev_err(&pdev->dev, "failed to retrieve IRQ\n");
  865. err = -ENODEV;
  866. goto out;
  867. }
  868. macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2);
  869. if (!macdma) {
  870. dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n");
  871. err = -ENODEV;
  872. goto out;
  873. }
  874. if (!request_mem_region(base->start, resource_size(base),
  875. pdev->name)) {
  876. dev_err(&pdev->dev, "failed to request memory region for base registers\n");
  877. err = -ENXIO;
  878. goto out;
  879. }
  880. if (!request_mem_region(macen->start, resource_size(macen),
  881. pdev->name)) {
  882. dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
  883. err = -ENXIO;
  884. goto err_request;
  885. }
  886. if (!request_mem_region(macdma->start, resource_size(macdma),
  887. pdev->name)) {
  888. dev_err(&pdev->dev, "failed to request MACDMA memory region\n");
  889. err = -ENXIO;
  890. goto err_macdma;
  891. }
  892. dev = alloc_etherdev(sizeof(struct au1000_private));
  893. if (!dev) {
  894. err = -ENOMEM;
  895. goto err_alloc;
  896. }
  897. SET_NETDEV_DEV(dev, &pdev->dev);
  898. platform_set_drvdata(pdev, dev);
  899. aup = netdev_priv(dev);
  900. spin_lock_init(&aup->lock);
  901. aup->msg_enable = (au1000_debug < 4 ?
  902. AU1000_DEF_MSG_ENABLE : au1000_debug);
  903. /* Allocate the data buffers
  904. * Snooping works fine with eth on all au1xxx
  905. */
  906. aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
  907. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  908. &aup->dma_addr, 0);
  909. if (!aup->vaddr) {
  910. dev_err(&pdev->dev, "failed to allocate data buffers\n");
  911. err = -ENOMEM;
  912. goto err_vaddr;
  913. }
  914. /* aup->mac is the base address of the MAC's registers */
  915. aup->mac = (struct mac_reg *)
  916. ioremap_nocache(base->start, resource_size(base));
  917. if (!aup->mac) {
  918. dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
  919. err = -ENXIO;
  920. goto err_remap1;
  921. }
  922. /* Setup some variables for quick register address access */
  923. aup->enable = (u32 *)ioremap_nocache(macen->start,
  924. resource_size(macen));
  925. if (!aup->enable) {
  926. dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
  927. err = -ENXIO;
  928. goto err_remap2;
  929. }
  930. aup->mac_id = pdev->id;
  931. aup->macdma = ioremap_nocache(macdma->start, resource_size(macdma));
  932. if (!aup->macdma) {
  933. dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n");
  934. err = -ENXIO;
  935. goto err_remap3;
  936. }
  937. au1000_setup_hw_rings(aup, aup->macdma);
  938. writel(0, aup->enable);
  939. aup->mac_enabled = 0;
  940. pd = dev_get_platdata(&pdev->dev);
  941. if (!pd) {
  942. dev_info(&pdev->dev, "no platform_data passed,"
  943. " PHY search on MAC0\n");
  944. aup->phy1_search_mac0 = 1;
  945. } else {
  946. if (is_valid_ether_addr(pd->mac)) {
  947. memcpy(dev->dev_addr, pd->mac, ETH_ALEN);
  948. } else {
  949. /* Set a random MAC since no valid provided by platform_data. */
  950. eth_hw_addr_random(dev);
  951. }
  952. aup->phy_static_config = pd->phy_static_config;
  953. aup->phy_search_highest_addr = pd->phy_search_highest_addr;
  954. aup->phy1_search_mac0 = pd->phy1_search_mac0;
  955. aup->phy_addr = pd->phy_addr;
  956. aup->phy_busid = pd->phy_busid;
  957. aup->phy_irq = pd->phy_irq;
  958. }
  959. if (aup->phy_busid && aup->phy_busid > 0) {
  960. dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
  961. err = -ENODEV;
  962. goto err_mdiobus_alloc;
  963. }
  964. aup->mii_bus = mdiobus_alloc();
  965. if (aup->mii_bus == NULL) {
  966. dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
  967. err = -ENOMEM;
  968. goto err_mdiobus_alloc;
  969. }
  970. aup->mii_bus->priv = dev;
  971. aup->mii_bus->read = au1000_mdiobus_read;
  972. aup->mii_bus->write = au1000_mdiobus_write;
  973. aup->mii_bus->reset = au1000_mdiobus_reset;
  974. aup->mii_bus->name = "au1000_eth_mii";
  975. snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  976. pdev->name, aup->mac_id);
  977. aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
  978. if (aup->mii_bus->irq == NULL) {
  979. err = -ENOMEM;
  980. goto err_out;
  981. }
  982. for (i = 0; i < PHY_MAX_ADDR; ++i)
  983. aup->mii_bus->irq[i] = PHY_POLL;
  984. /* if known, set corresponding PHY IRQs */
  985. if (aup->phy_static_config)
  986. if (aup->phy_irq && aup->phy_busid == aup->mac_id)
  987. aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
  988. err = mdiobus_register(aup->mii_bus);
  989. if (err) {
  990. dev_err(&pdev->dev, "failed to register MDIO bus\n");
  991. goto err_mdiobus_reg;
  992. }
  993. err = au1000_mii_probe(dev);
  994. if (err != 0)
  995. goto err_out;
  996. pDBfree = NULL;
  997. /* setup the data buffer descriptors and attach a buffer to each one */
  998. pDB = aup->db;
  999. for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
  1000. pDB->pnext = pDBfree;
  1001. pDBfree = pDB;
  1002. pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
  1003. pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
  1004. pDB++;
  1005. }
  1006. aup->pDBfree = pDBfree;
  1007. err = -ENODEV;
  1008. for (i = 0; i < NUM_RX_DMA; i++) {
  1009. pDB = au1000_GetFreeDB(aup);
  1010. if (!pDB)
  1011. goto err_out;
  1012. aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  1013. aup->rx_db_inuse[i] = pDB;
  1014. }
  1015. err = -ENODEV;
  1016. for (i = 0; i < NUM_TX_DMA; i++) {
  1017. pDB = au1000_GetFreeDB(aup);
  1018. if (!pDB)
  1019. goto err_out;
  1020. aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  1021. aup->tx_dma_ring[i]->len = 0;
  1022. aup->tx_db_inuse[i] = pDB;
  1023. }
  1024. dev->base_addr = base->start;
  1025. dev->irq = irq;
  1026. dev->netdev_ops = &au1000_netdev_ops;
  1027. dev->ethtool_ops = &au1000_ethtool_ops;
  1028. dev->watchdog_timeo = ETH_TX_TIMEOUT;
  1029. /*
  1030. * The boot code uses the ethernet controller, so reset it to start
  1031. * fresh. au1000_init() expects that the device is in reset state.
  1032. */
  1033. au1000_reset_mac(dev);
  1034. err = register_netdev(dev);
  1035. if (err) {
  1036. netdev_err(dev, "Cannot register net device, aborting.\n");
  1037. goto err_out;
  1038. }
  1039. netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
  1040. (unsigned long)base->start, irq);
  1041. if (version_printed++ == 0)
  1042. pr_info("%s version %s %s\n",
  1043. DRV_NAME, DRV_VERSION, DRV_AUTHOR);
  1044. return 0;
  1045. err_out:
  1046. if (aup->mii_bus != NULL)
  1047. mdiobus_unregister(aup->mii_bus);
  1048. /* here we should have a valid dev plus aup-> register addresses
  1049. * so we can reset the mac properly.
  1050. */
  1051. au1000_reset_mac(dev);
  1052. for (i = 0; i < NUM_RX_DMA; i++) {
  1053. if (aup->rx_db_inuse[i])
  1054. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1055. }
  1056. for (i = 0; i < NUM_TX_DMA; i++) {
  1057. if (aup->tx_db_inuse[i])
  1058. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1059. }
  1060. err_mdiobus_reg:
  1061. mdiobus_free(aup->mii_bus);
  1062. err_mdiobus_alloc:
  1063. iounmap(aup->macdma);
  1064. err_remap3:
  1065. iounmap(aup->enable);
  1066. err_remap2:
  1067. iounmap(aup->mac);
  1068. err_remap1:
  1069. dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1070. (void *)aup->vaddr, aup->dma_addr);
  1071. err_vaddr:
  1072. free_netdev(dev);
  1073. err_alloc:
  1074. release_mem_region(macdma->start, resource_size(macdma));
  1075. err_macdma:
  1076. release_mem_region(macen->start, resource_size(macen));
  1077. err_request:
  1078. release_mem_region(base->start, resource_size(base));
  1079. out:
  1080. return err;
  1081. }
  1082. static int au1000_remove(struct platform_device *pdev)
  1083. {
  1084. struct net_device *dev = platform_get_drvdata(pdev);
  1085. struct au1000_private *aup = netdev_priv(dev);
  1086. int i;
  1087. struct resource *base, *macen;
  1088. unregister_netdev(dev);
  1089. mdiobus_unregister(aup->mii_bus);
  1090. mdiobus_free(aup->mii_bus);
  1091. for (i = 0; i < NUM_RX_DMA; i++)
  1092. if (aup->rx_db_inuse[i])
  1093. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1094. for (i = 0; i < NUM_TX_DMA; i++)
  1095. if (aup->tx_db_inuse[i])
  1096. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1097. dma_free_noncoherent(NULL, MAX_BUF_SIZE *
  1098. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1099. (void *)aup->vaddr, aup->dma_addr);
  1100. iounmap(aup->macdma);
  1101. iounmap(aup->mac);
  1102. iounmap(aup->enable);
  1103. base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
  1104. release_mem_region(base->start, resource_size(base));
  1105. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1106. release_mem_region(base->start, resource_size(base));
  1107. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1108. release_mem_region(macen->start, resource_size(macen));
  1109. free_netdev(dev);
  1110. return 0;
  1111. }
  1112. static struct platform_driver au1000_eth_driver = {
  1113. .probe = au1000_probe,
  1114. .remove = au1000_remove,
  1115. .driver = {
  1116. .name = "au1000-eth",
  1117. .owner = THIS_MODULE,
  1118. },
  1119. };
  1120. module_platform_driver(au1000_eth_driver);
  1121. MODULE_ALIAS("platform:au1000-eth");