mtd_dataflash.c 24 KB

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  1. /*
  2. * Atmel AT45xxx DataFlash MTD driver for lightweight SPI framework
  3. *
  4. * Largely derived from at91_dataflash.c:
  5. * Copyright (C) 2003-2005 SAN People (Pty) Ltd
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/slab.h>
  14. #include <linux/delay.h>
  15. #include <linux/device.h>
  16. #include <linux/mutex.h>
  17. #include <linux/err.h>
  18. #include <linux/math64.h>
  19. #include <linux/of.h>
  20. #include <linux/of_device.h>
  21. #include <linux/spi/spi.h>
  22. #include <linux/spi/flash.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/partitions.h>
  25. /*
  26. * DataFlash is a kind of SPI flash. Most AT45 chips have two buffers in
  27. * each chip, which may be used for double buffered I/O; but this driver
  28. * doesn't (yet) use these for any kind of i/o overlap or prefetching.
  29. *
  30. * Sometimes DataFlash is packaged in MMC-format cards, although the
  31. * MMC stack can't (yet?) distinguish between MMC and DataFlash
  32. * protocols during enumeration.
  33. */
  34. /* reads can bypass the buffers */
  35. #define OP_READ_CONTINUOUS 0xE8
  36. #define OP_READ_PAGE 0xD2
  37. /* group B requests can run even while status reports "busy" */
  38. #define OP_READ_STATUS 0xD7 /* group B */
  39. /* move data between host and buffer */
  40. #define OP_READ_BUFFER1 0xD4 /* group B */
  41. #define OP_READ_BUFFER2 0xD6 /* group B */
  42. #define OP_WRITE_BUFFER1 0x84 /* group B */
  43. #define OP_WRITE_BUFFER2 0x87 /* group B */
  44. /* erasing flash */
  45. #define OP_ERASE_PAGE 0x81
  46. #define OP_ERASE_BLOCK 0x50
  47. /* move data between buffer and flash */
  48. #define OP_TRANSFER_BUF1 0x53
  49. #define OP_TRANSFER_BUF2 0x55
  50. #define OP_MREAD_BUFFER1 0xD4
  51. #define OP_MREAD_BUFFER2 0xD6
  52. #define OP_MWERASE_BUFFER1 0x83
  53. #define OP_MWERASE_BUFFER2 0x86
  54. #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
  55. #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
  56. /* write to buffer, then write-erase to flash */
  57. #define OP_PROGRAM_VIA_BUF1 0x82
  58. #define OP_PROGRAM_VIA_BUF2 0x85
  59. /* compare buffer to flash */
  60. #define OP_COMPARE_BUF1 0x60
  61. #define OP_COMPARE_BUF2 0x61
  62. /* read flash to buffer, then write-erase to flash */
  63. #define OP_REWRITE_VIA_BUF1 0x58
  64. #define OP_REWRITE_VIA_BUF2 0x59
  65. /* newer chips report JEDEC manufacturer and device IDs; chip
  66. * serial number and OTP bits; and per-sector writeprotect.
  67. */
  68. #define OP_READ_ID 0x9F
  69. #define OP_READ_SECURITY 0x77
  70. #define OP_WRITE_SECURITY_REVC 0x9A
  71. #define OP_WRITE_SECURITY 0x9B /* revision D */
  72. struct dataflash {
  73. uint8_t command[4];
  74. char name[24];
  75. unsigned short page_offset; /* offset in flash address */
  76. unsigned int page_size; /* of bytes per page */
  77. struct mutex lock;
  78. struct spi_device *spi;
  79. struct mtd_info mtd;
  80. };
  81. #ifdef CONFIG_OF
  82. static const struct of_device_id dataflash_dt_ids[] = {
  83. { .compatible = "atmel,at45", },
  84. { .compatible = "atmel,dataflash", },
  85. { /* sentinel */ }
  86. };
  87. #endif
  88. /* ......................................................................... */
  89. /*
  90. * Return the status of the DataFlash device.
  91. */
  92. static inline int dataflash_status(struct spi_device *spi)
  93. {
  94. /* NOTE: at45db321c over 25 MHz wants to write
  95. * a dummy byte after the opcode...
  96. */
  97. return spi_w8r8(spi, OP_READ_STATUS);
  98. }
  99. /*
  100. * Poll the DataFlash device until it is READY.
  101. * This usually takes 5-20 msec or so; more for sector erase.
  102. */
  103. static int dataflash_waitready(struct spi_device *spi)
  104. {
  105. int status;
  106. for (;;) {
  107. status = dataflash_status(spi);
  108. if (status < 0) {
  109. pr_debug("%s: status %d?\n",
  110. dev_name(&spi->dev), status);
  111. status = 0;
  112. }
  113. if (status & (1 << 7)) /* RDY/nBSY */
  114. return status;
  115. msleep(3);
  116. }
  117. }
  118. /* ......................................................................... */
  119. /*
  120. * Erase pages of flash.
  121. */
  122. static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
  123. {
  124. struct dataflash *priv = mtd->priv;
  125. struct spi_device *spi = priv->spi;
  126. struct spi_transfer x = { .tx_dma = 0, };
  127. struct spi_message msg;
  128. unsigned blocksize = priv->page_size << 3;
  129. uint8_t *command;
  130. uint32_t rem;
  131. pr_debug("%s: erase addr=0x%llx len 0x%llx\n",
  132. dev_name(&spi->dev), (long long)instr->addr,
  133. (long long)instr->len);
  134. div_u64_rem(instr->len, priv->page_size, &rem);
  135. if (rem)
  136. return -EINVAL;
  137. div_u64_rem(instr->addr, priv->page_size, &rem);
  138. if (rem)
  139. return -EINVAL;
  140. spi_message_init(&msg);
  141. x.tx_buf = command = priv->command;
  142. x.len = 4;
  143. spi_message_add_tail(&x, &msg);
  144. mutex_lock(&priv->lock);
  145. while (instr->len > 0) {
  146. unsigned int pageaddr;
  147. int status;
  148. int do_block;
  149. /* Calculate flash page address; use block erase (for speed) if
  150. * we're at a block boundary and need to erase the whole block.
  151. */
  152. pageaddr = div_u64(instr->addr, priv->page_size);
  153. do_block = (pageaddr & 0x7) == 0 && instr->len >= blocksize;
  154. pageaddr = pageaddr << priv->page_offset;
  155. command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
  156. command[1] = (uint8_t)(pageaddr >> 16);
  157. command[2] = (uint8_t)(pageaddr >> 8);
  158. command[3] = 0;
  159. pr_debug("ERASE %s: (%x) %x %x %x [%i]\n",
  160. do_block ? "block" : "page",
  161. command[0], command[1], command[2], command[3],
  162. pageaddr);
  163. status = spi_sync(spi, &msg);
  164. (void) dataflash_waitready(spi);
  165. if (status < 0) {
  166. printk(KERN_ERR "%s: erase %x, err %d\n",
  167. dev_name(&spi->dev), pageaddr, status);
  168. /* REVISIT: can retry instr->retries times; or
  169. * giveup and instr->fail_addr = instr->addr;
  170. */
  171. continue;
  172. }
  173. if (do_block) {
  174. instr->addr += blocksize;
  175. instr->len -= blocksize;
  176. } else {
  177. instr->addr += priv->page_size;
  178. instr->len -= priv->page_size;
  179. }
  180. }
  181. mutex_unlock(&priv->lock);
  182. /* Inform MTD subsystem that erase is complete */
  183. instr->state = MTD_ERASE_DONE;
  184. mtd_erase_callback(instr);
  185. return 0;
  186. }
  187. /*
  188. * Read from the DataFlash device.
  189. * from : Start offset in flash device
  190. * len : Amount to read
  191. * retlen : About of data actually read
  192. * buf : Buffer containing the data
  193. */
  194. static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len,
  195. size_t *retlen, u_char *buf)
  196. {
  197. struct dataflash *priv = mtd->priv;
  198. struct spi_transfer x[2] = { { .tx_dma = 0, }, };
  199. struct spi_message msg;
  200. unsigned int addr;
  201. uint8_t *command;
  202. int status;
  203. pr_debug("%s: read 0x%x..0x%x\n", dev_name(&priv->spi->dev),
  204. (unsigned)from, (unsigned)(from + len));
  205. /* Calculate flash page/byte address */
  206. addr = (((unsigned)from / priv->page_size) << priv->page_offset)
  207. + ((unsigned)from % priv->page_size);
  208. command = priv->command;
  209. pr_debug("READ: (%x) %x %x %x\n",
  210. command[0], command[1], command[2], command[3]);
  211. spi_message_init(&msg);
  212. x[0].tx_buf = command;
  213. x[0].len = 8;
  214. spi_message_add_tail(&x[0], &msg);
  215. x[1].rx_buf = buf;
  216. x[1].len = len;
  217. spi_message_add_tail(&x[1], &msg);
  218. mutex_lock(&priv->lock);
  219. /* Continuous read, max clock = f(car) which may be less than
  220. * the peak rate available. Some chips support commands with
  221. * fewer "don't care" bytes. Both buffers stay unchanged.
  222. */
  223. command[0] = OP_READ_CONTINUOUS;
  224. command[1] = (uint8_t)(addr >> 16);
  225. command[2] = (uint8_t)(addr >> 8);
  226. command[3] = (uint8_t)(addr >> 0);
  227. /* plus 4 "don't care" bytes */
  228. status = spi_sync(priv->spi, &msg);
  229. mutex_unlock(&priv->lock);
  230. if (status >= 0) {
  231. *retlen = msg.actual_length - 8;
  232. status = 0;
  233. } else
  234. pr_debug("%s: read %x..%x --> %d\n",
  235. dev_name(&priv->spi->dev),
  236. (unsigned)from, (unsigned)(from + len),
  237. status);
  238. return status;
  239. }
  240. /*
  241. * Write to the DataFlash device.
  242. * to : Start offset in flash device
  243. * len : Amount to write
  244. * retlen : Amount of data actually written
  245. * buf : Buffer containing the data
  246. */
  247. static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len,
  248. size_t * retlen, const u_char * buf)
  249. {
  250. struct dataflash *priv = mtd->priv;
  251. struct spi_device *spi = priv->spi;
  252. struct spi_transfer x[2] = { { .tx_dma = 0, }, };
  253. struct spi_message msg;
  254. unsigned int pageaddr, addr, offset, writelen;
  255. size_t remaining = len;
  256. u_char *writebuf = (u_char *) buf;
  257. int status = -EINVAL;
  258. uint8_t *command;
  259. pr_debug("%s: write 0x%x..0x%x\n",
  260. dev_name(&spi->dev), (unsigned)to, (unsigned)(to + len));
  261. spi_message_init(&msg);
  262. x[0].tx_buf = command = priv->command;
  263. x[0].len = 4;
  264. spi_message_add_tail(&x[0], &msg);
  265. pageaddr = ((unsigned)to / priv->page_size);
  266. offset = ((unsigned)to % priv->page_size);
  267. if (offset + len > priv->page_size)
  268. writelen = priv->page_size - offset;
  269. else
  270. writelen = len;
  271. mutex_lock(&priv->lock);
  272. while (remaining > 0) {
  273. pr_debug("write @ %i:%i len=%i\n",
  274. pageaddr, offset, writelen);
  275. /* REVISIT:
  276. * (a) each page in a sector must be rewritten at least
  277. * once every 10K sibling erase/program operations.
  278. * (b) for pages that are already erased, we could
  279. * use WRITE+MWRITE not PROGRAM for ~30% speedup.
  280. * (c) WRITE to buffer could be done while waiting for
  281. * a previous MWRITE/MWERASE to complete ...
  282. * (d) error handling here seems to be mostly missing.
  283. *
  284. * Two persistent bits per page, plus a per-sector counter,
  285. * could support (a) and (b) ... we might consider using
  286. * the second half of sector zero, which is just one block,
  287. * to track that state. (On AT91, that sector should also
  288. * support boot-from-DataFlash.)
  289. */
  290. addr = pageaddr << priv->page_offset;
  291. /* (1) Maybe transfer partial page to Buffer1 */
  292. if (writelen != priv->page_size) {
  293. command[0] = OP_TRANSFER_BUF1;
  294. command[1] = (addr & 0x00FF0000) >> 16;
  295. command[2] = (addr & 0x0000FF00) >> 8;
  296. command[3] = 0;
  297. pr_debug("TRANSFER: (%x) %x %x %x\n",
  298. command[0], command[1], command[2], command[3]);
  299. status = spi_sync(spi, &msg);
  300. if (status < 0)
  301. pr_debug("%s: xfer %u -> %d\n",
  302. dev_name(&spi->dev), addr, status);
  303. (void) dataflash_waitready(priv->spi);
  304. }
  305. /* (2) Program full page via Buffer1 */
  306. addr += offset;
  307. command[0] = OP_PROGRAM_VIA_BUF1;
  308. command[1] = (addr & 0x00FF0000) >> 16;
  309. command[2] = (addr & 0x0000FF00) >> 8;
  310. command[3] = (addr & 0x000000FF);
  311. pr_debug("PROGRAM: (%x) %x %x %x\n",
  312. command[0], command[1], command[2], command[3]);
  313. x[1].tx_buf = writebuf;
  314. x[1].len = writelen;
  315. spi_message_add_tail(x + 1, &msg);
  316. status = spi_sync(spi, &msg);
  317. spi_transfer_del(x + 1);
  318. if (status < 0)
  319. pr_debug("%s: pgm %u/%u -> %d\n",
  320. dev_name(&spi->dev), addr, writelen, status);
  321. (void) dataflash_waitready(priv->spi);
  322. #ifdef CONFIG_MTD_DATAFLASH_WRITE_VERIFY
  323. /* (3) Compare to Buffer1 */
  324. addr = pageaddr << priv->page_offset;
  325. command[0] = OP_COMPARE_BUF1;
  326. command[1] = (addr & 0x00FF0000) >> 16;
  327. command[2] = (addr & 0x0000FF00) >> 8;
  328. command[3] = 0;
  329. pr_debug("COMPARE: (%x) %x %x %x\n",
  330. command[0], command[1], command[2], command[3]);
  331. status = spi_sync(spi, &msg);
  332. if (status < 0)
  333. pr_debug("%s: compare %u -> %d\n",
  334. dev_name(&spi->dev), addr, status);
  335. status = dataflash_waitready(priv->spi);
  336. /* Check result of the compare operation */
  337. if (status & (1 << 6)) {
  338. printk(KERN_ERR "%s: compare page %u, err %d\n",
  339. dev_name(&spi->dev), pageaddr, status);
  340. remaining = 0;
  341. status = -EIO;
  342. break;
  343. } else
  344. status = 0;
  345. #endif /* CONFIG_MTD_DATAFLASH_WRITE_VERIFY */
  346. remaining = remaining - writelen;
  347. pageaddr++;
  348. offset = 0;
  349. writebuf += writelen;
  350. *retlen += writelen;
  351. if (remaining > priv->page_size)
  352. writelen = priv->page_size;
  353. else
  354. writelen = remaining;
  355. }
  356. mutex_unlock(&priv->lock);
  357. return status;
  358. }
  359. /* ......................................................................... */
  360. #ifdef CONFIG_MTD_DATAFLASH_OTP
  361. static int dataflash_get_otp_info(struct mtd_info *mtd, size_t len,
  362. size_t *retlen, struct otp_info *info)
  363. {
  364. /* Report both blocks as identical: bytes 0..64, locked.
  365. * Unless the user block changed from all-ones, we can't
  366. * tell whether it's still writable; so we assume it isn't.
  367. */
  368. info->start = 0;
  369. info->length = 64;
  370. info->locked = 1;
  371. *retlen = sizeof(*info);
  372. return 0;
  373. }
  374. static ssize_t otp_read(struct spi_device *spi, unsigned base,
  375. uint8_t *buf, loff_t off, size_t len)
  376. {
  377. struct spi_message m;
  378. size_t l;
  379. uint8_t *scratch;
  380. struct spi_transfer t;
  381. int status;
  382. if (off > 64)
  383. return -EINVAL;
  384. if ((off + len) > 64)
  385. len = 64 - off;
  386. spi_message_init(&m);
  387. l = 4 + base + off + len;
  388. scratch = kzalloc(l, GFP_KERNEL);
  389. if (!scratch)
  390. return -ENOMEM;
  391. /* OUT: OP_READ_SECURITY, 3 don't-care bytes, zeroes
  392. * IN: ignore 4 bytes, data bytes 0..N (max 127)
  393. */
  394. scratch[0] = OP_READ_SECURITY;
  395. memset(&t, 0, sizeof t);
  396. t.tx_buf = scratch;
  397. t.rx_buf = scratch;
  398. t.len = l;
  399. spi_message_add_tail(&t, &m);
  400. dataflash_waitready(spi);
  401. status = spi_sync(spi, &m);
  402. if (status >= 0) {
  403. memcpy(buf, scratch + 4 + base + off, len);
  404. status = len;
  405. }
  406. kfree(scratch);
  407. return status;
  408. }
  409. static int dataflash_read_fact_otp(struct mtd_info *mtd,
  410. loff_t from, size_t len, size_t *retlen, u_char *buf)
  411. {
  412. struct dataflash *priv = mtd->priv;
  413. int status;
  414. /* 64 bytes, from 0..63 ... start at 64 on-chip */
  415. mutex_lock(&priv->lock);
  416. status = otp_read(priv->spi, 64, buf, from, len);
  417. mutex_unlock(&priv->lock);
  418. if (status < 0)
  419. return status;
  420. *retlen = status;
  421. return 0;
  422. }
  423. static int dataflash_read_user_otp(struct mtd_info *mtd,
  424. loff_t from, size_t len, size_t *retlen, u_char *buf)
  425. {
  426. struct dataflash *priv = mtd->priv;
  427. int status;
  428. /* 64 bytes, from 0..63 ... start at 0 on-chip */
  429. mutex_lock(&priv->lock);
  430. status = otp_read(priv->spi, 0, buf, from, len);
  431. mutex_unlock(&priv->lock);
  432. if (status < 0)
  433. return status;
  434. *retlen = status;
  435. return 0;
  436. }
  437. static int dataflash_write_user_otp(struct mtd_info *mtd,
  438. loff_t from, size_t len, size_t *retlen, u_char *buf)
  439. {
  440. struct spi_message m;
  441. const size_t l = 4 + 64;
  442. uint8_t *scratch;
  443. struct spi_transfer t;
  444. struct dataflash *priv = mtd->priv;
  445. int status;
  446. if (from >= 64) {
  447. /*
  448. * Attempting to write beyond the end of OTP memory,
  449. * no data can be written.
  450. */
  451. *retlen = 0;
  452. return 0;
  453. }
  454. /* Truncate the write to fit into OTP memory. */
  455. if ((from + len) > 64)
  456. len = 64 - from;
  457. /* OUT: OP_WRITE_SECURITY, 3 zeroes, 64 data-or-zero bytes
  458. * IN: ignore all
  459. */
  460. scratch = kzalloc(l, GFP_KERNEL);
  461. if (!scratch)
  462. return -ENOMEM;
  463. scratch[0] = OP_WRITE_SECURITY;
  464. memcpy(scratch + 4 + from, buf, len);
  465. spi_message_init(&m);
  466. memset(&t, 0, sizeof t);
  467. t.tx_buf = scratch;
  468. t.len = l;
  469. spi_message_add_tail(&t, &m);
  470. /* Write the OTP bits, if they've not yet been written.
  471. * This modifies SRAM buffer1.
  472. */
  473. mutex_lock(&priv->lock);
  474. dataflash_waitready(priv->spi);
  475. status = spi_sync(priv->spi, &m);
  476. mutex_unlock(&priv->lock);
  477. kfree(scratch);
  478. if (status >= 0) {
  479. status = 0;
  480. *retlen = len;
  481. }
  482. return status;
  483. }
  484. static char *otp_setup(struct mtd_info *device, char revision)
  485. {
  486. device->_get_fact_prot_info = dataflash_get_otp_info;
  487. device->_read_fact_prot_reg = dataflash_read_fact_otp;
  488. device->_get_user_prot_info = dataflash_get_otp_info;
  489. device->_read_user_prot_reg = dataflash_read_user_otp;
  490. /* rev c parts (at45db321c and at45db1281 only!) use a
  491. * different write procedure; not (yet?) implemented.
  492. */
  493. if (revision > 'c')
  494. device->_write_user_prot_reg = dataflash_write_user_otp;
  495. return ", OTP";
  496. }
  497. #else
  498. static char *otp_setup(struct mtd_info *device, char revision)
  499. {
  500. return " (OTP)";
  501. }
  502. #endif
  503. /* ......................................................................... */
  504. /*
  505. * Register DataFlash device with MTD subsystem.
  506. */
  507. static int add_dataflash_otp(struct spi_device *spi, char *name, int nr_pages,
  508. int pagesize, int pageoffset, char revision)
  509. {
  510. struct dataflash *priv;
  511. struct mtd_info *device;
  512. struct mtd_part_parser_data ppdata;
  513. struct flash_platform_data *pdata = dev_get_platdata(&spi->dev);
  514. char *otp_tag = "";
  515. int err = 0;
  516. priv = kzalloc(sizeof *priv, GFP_KERNEL);
  517. if (!priv)
  518. return -ENOMEM;
  519. mutex_init(&priv->lock);
  520. priv->spi = spi;
  521. priv->page_size = pagesize;
  522. priv->page_offset = pageoffset;
  523. /* name must be usable with cmdlinepart */
  524. sprintf(priv->name, "spi%d.%d-%s",
  525. spi->master->bus_num, spi->chip_select,
  526. name);
  527. device = &priv->mtd;
  528. device->name = (pdata && pdata->name) ? pdata->name : priv->name;
  529. device->size = nr_pages * pagesize;
  530. device->erasesize = pagesize;
  531. device->writesize = pagesize;
  532. device->owner = THIS_MODULE;
  533. device->type = MTD_DATAFLASH;
  534. device->flags = MTD_WRITEABLE;
  535. device->_erase = dataflash_erase;
  536. device->_read = dataflash_read;
  537. device->_write = dataflash_write;
  538. device->priv = priv;
  539. device->dev.parent = &spi->dev;
  540. if (revision >= 'c')
  541. otp_tag = otp_setup(device, revision);
  542. dev_info(&spi->dev, "%s (%lld KBytes) pagesize %d bytes%s\n",
  543. name, (long long)((device->size + 1023) >> 10),
  544. pagesize, otp_tag);
  545. spi_set_drvdata(spi, priv);
  546. ppdata.of_node = spi->dev.of_node;
  547. err = mtd_device_parse_register(device, NULL, &ppdata,
  548. pdata ? pdata->parts : NULL,
  549. pdata ? pdata->nr_parts : 0);
  550. if (!err)
  551. return 0;
  552. kfree(priv);
  553. return err;
  554. }
  555. static inline int add_dataflash(struct spi_device *spi, char *name,
  556. int nr_pages, int pagesize, int pageoffset)
  557. {
  558. return add_dataflash_otp(spi, name, nr_pages, pagesize,
  559. pageoffset, 0);
  560. }
  561. struct flash_info {
  562. char *name;
  563. /* JEDEC id has a high byte of zero plus three data bytes:
  564. * the manufacturer id, then a two byte device id.
  565. */
  566. uint32_t jedec_id;
  567. /* The size listed here is what works with OP_ERASE_PAGE. */
  568. unsigned nr_pages;
  569. uint16_t pagesize;
  570. uint16_t pageoffset;
  571. uint16_t flags;
  572. #define SUP_POW2PS 0x0002 /* supports 2^N byte pages */
  573. #define IS_POW2PS 0x0001 /* uses 2^N byte pages */
  574. };
  575. static struct flash_info dataflash_data[] = {
  576. /*
  577. * NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
  578. * one with IS_POW2PS and the other without. The entry with the
  579. * non-2^N byte page size can't name exact chip revisions without
  580. * losing backwards compatibility for cmdlinepart.
  581. *
  582. * These newer chips also support 128-byte security registers (with
  583. * 64 bytes one-time-programmable) and software write-protection.
  584. */
  585. { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS},
  586. { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS},
  587. { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS},
  588. { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS},
  589. { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS},
  590. { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS},
  591. { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS},
  592. { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS},
  593. { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS},
  594. { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS},
  595. { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */
  596. { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS},
  597. { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS},
  598. { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS},
  599. { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
  600. };
  601. static struct flash_info *jedec_probe(struct spi_device *spi)
  602. {
  603. int tmp;
  604. uint8_t code = OP_READ_ID;
  605. uint8_t id[3];
  606. uint32_t jedec;
  607. struct flash_info *info;
  608. int status;
  609. /* JEDEC also defines an optional "extended device information"
  610. * string for after vendor-specific data, after the three bytes
  611. * we use here. Supporting some chips might require using it.
  612. *
  613. * If the vendor ID isn't Atmel's (0x1f), assume this call failed.
  614. * That's not an error; only rev C and newer chips handle it, and
  615. * only Atmel sells these chips.
  616. */
  617. tmp = spi_write_then_read(spi, &code, 1, id, 3);
  618. if (tmp < 0) {
  619. pr_debug("%s: error %d reading JEDEC ID\n",
  620. dev_name(&spi->dev), tmp);
  621. return ERR_PTR(tmp);
  622. }
  623. if (id[0] != 0x1f)
  624. return NULL;
  625. jedec = id[0];
  626. jedec = jedec << 8;
  627. jedec |= id[1];
  628. jedec = jedec << 8;
  629. jedec |= id[2];
  630. for (tmp = 0, info = dataflash_data;
  631. tmp < ARRAY_SIZE(dataflash_data);
  632. tmp++, info++) {
  633. if (info->jedec_id == jedec) {
  634. pr_debug("%s: OTP, sector protect%s\n",
  635. dev_name(&spi->dev),
  636. (info->flags & SUP_POW2PS)
  637. ? ", binary pagesize" : ""
  638. );
  639. if (info->flags & SUP_POW2PS) {
  640. status = dataflash_status(spi);
  641. if (status < 0) {
  642. pr_debug("%s: status error %d\n",
  643. dev_name(&spi->dev), status);
  644. return ERR_PTR(status);
  645. }
  646. if (status & 0x1) {
  647. if (info->flags & IS_POW2PS)
  648. return info;
  649. } else {
  650. if (!(info->flags & IS_POW2PS))
  651. return info;
  652. }
  653. } else
  654. return info;
  655. }
  656. }
  657. /*
  658. * Treat other chips as errors ... we won't know the right page
  659. * size (it might be binary) even when we can tell which density
  660. * class is involved (legacy chip id scheme).
  661. */
  662. dev_warn(&spi->dev, "JEDEC id %06x not handled\n", jedec);
  663. return ERR_PTR(-ENODEV);
  664. }
  665. /*
  666. * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
  667. * or else the ID code embedded in the status bits:
  668. *
  669. * Device Density ID code #Pages PageSize Offset
  670. * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
  671. * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9
  672. * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
  673. * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
  674. * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
  675. * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
  676. * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11
  677. * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
  678. */
  679. static int dataflash_probe(struct spi_device *spi)
  680. {
  681. int status;
  682. struct flash_info *info;
  683. /*
  684. * Try to detect dataflash by JEDEC ID.
  685. * If it succeeds we know we have either a C or D part.
  686. * D will support power of 2 pagesize option.
  687. * Both support the security register, though with different
  688. * write procedures.
  689. */
  690. info = jedec_probe(spi);
  691. if (IS_ERR(info))
  692. return PTR_ERR(info);
  693. if (info != NULL)
  694. return add_dataflash_otp(spi, info->name, info->nr_pages,
  695. info->pagesize, info->pageoffset,
  696. (info->flags & SUP_POW2PS) ? 'd' : 'c');
  697. /*
  698. * Older chips support only legacy commands, identifing
  699. * capacity using bits in the status byte.
  700. */
  701. status = dataflash_status(spi);
  702. if (status <= 0 || status == 0xff) {
  703. pr_debug("%s: status error %d\n",
  704. dev_name(&spi->dev), status);
  705. if (status == 0 || status == 0xff)
  706. status = -ENODEV;
  707. return status;
  708. }
  709. /* if there's a device there, assume it's dataflash.
  710. * board setup should have set spi->max_speed_max to
  711. * match f(car) for continuous reads, mode 0 or 3.
  712. */
  713. switch (status & 0x3c) {
  714. case 0x0c: /* 0 0 1 1 x x */
  715. status = add_dataflash(spi, "AT45DB011B", 512, 264, 9);
  716. break;
  717. case 0x14: /* 0 1 0 1 x x */
  718. status = add_dataflash(spi, "AT45DB021B", 1024, 264, 9);
  719. break;
  720. case 0x1c: /* 0 1 1 1 x x */
  721. status = add_dataflash(spi, "AT45DB041x", 2048, 264, 9);
  722. break;
  723. case 0x24: /* 1 0 0 1 x x */
  724. status = add_dataflash(spi, "AT45DB081B", 4096, 264, 9);
  725. break;
  726. case 0x2c: /* 1 0 1 1 x x */
  727. status = add_dataflash(spi, "AT45DB161x", 4096, 528, 10);
  728. break;
  729. case 0x34: /* 1 1 0 1 x x */
  730. status = add_dataflash(spi, "AT45DB321x", 8192, 528, 10);
  731. break;
  732. case 0x38: /* 1 1 1 x x x */
  733. case 0x3c:
  734. status = add_dataflash(spi, "AT45DB642x", 8192, 1056, 11);
  735. break;
  736. /* obsolete AT45DB1282 not (yet?) supported */
  737. default:
  738. dev_info(&spi->dev, "unsupported device (%x)\n",
  739. status & 0x3c);
  740. status = -ENODEV;
  741. }
  742. if (status < 0)
  743. pr_debug("%s: add_dataflash --> %d\n", dev_name(&spi->dev),
  744. status);
  745. return status;
  746. }
  747. static int dataflash_remove(struct spi_device *spi)
  748. {
  749. struct dataflash *flash = spi_get_drvdata(spi);
  750. int status;
  751. pr_debug("%s: remove\n", dev_name(&spi->dev));
  752. status = mtd_device_unregister(&flash->mtd);
  753. if (status == 0)
  754. kfree(flash);
  755. return status;
  756. }
  757. static struct spi_driver dataflash_driver = {
  758. .driver = {
  759. .name = "mtd_dataflash",
  760. .owner = THIS_MODULE,
  761. .of_match_table = of_match_ptr(dataflash_dt_ids),
  762. },
  763. .probe = dataflash_probe,
  764. .remove = dataflash_remove,
  765. /* FIXME: investigate suspend and resume... */
  766. };
  767. module_spi_driver(dataflash_driver);
  768. MODULE_LICENSE("GPL");
  769. MODULE_AUTHOR("Andrew Victor, David Brownell");
  770. MODULE_DESCRIPTION("MTD DataFlash driver");
  771. MODULE_ALIAS("spi:mtd_dataflash");