sdhci-of-arasan.c 5.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228
  1. /*
  2. * Arasan Secure Digital Host Controller Interface.
  3. * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
  4. * Copyright (c) 2012 Wind River Systems, Inc.
  5. * Copyright (C) 2013 Pengutronix e.K.
  6. * Copyright (C) 2013 Xilinx Inc.
  7. *
  8. * Based on sdhci-of-esdhc.c
  9. *
  10. * Copyright (c) 2007 Freescale Semiconductor, Inc.
  11. * Copyright (c) 2009 MontaVista Software, Inc.
  12. *
  13. * Authors: Xiaobo Xie <X.Xie@freescale.com>
  14. * Anton Vorontsov <avorontsov@ru.mvista.com>
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License as published by
  18. * the Free Software Foundation; either version 2 of the License, or (at
  19. * your option) any later version.
  20. */
  21. #include <linux/module.h>
  22. #include "sdhci-pltfm.h"
  23. #define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c
  24. #define CLK_CTRL_TIMEOUT_SHIFT 16
  25. #define CLK_CTRL_TIMEOUT_MASK (0xf << CLK_CTRL_TIMEOUT_SHIFT)
  26. #define CLK_CTRL_TIMEOUT_MIN_EXP 13
  27. /**
  28. * struct sdhci_arasan_data
  29. * @clk_ahb: Pointer to the AHB clock
  30. */
  31. struct sdhci_arasan_data {
  32. struct clk *clk_ahb;
  33. };
  34. static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
  35. {
  36. u32 div;
  37. unsigned long freq;
  38. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  39. div = readl(host->ioaddr + SDHCI_ARASAN_CLK_CTRL_OFFSET);
  40. div = (div & CLK_CTRL_TIMEOUT_MASK) >> CLK_CTRL_TIMEOUT_SHIFT;
  41. freq = clk_get_rate(pltfm_host->clk);
  42. freq /= 1 << (CLK_CTRL_TIMEOUT_MIN_EXP + div);
  43. return freq;
  44. }
  45. static struct sdhci_ops sdhci_arasan_ops = {
  46. .set_clock = sdhci_set_clock,
  47. .get_max_clock = sdhci_pltfm_clk_get_max_clock,
  48. .get_timeout_clock = sdhci_arasan_get_timeout_clock,
  49. .set_bus_width = sdhci_set_bus_width,
  50. .reset = sdhci_reset,
  51. .set_uhs_signaling = sdhci_set_uhs_signaling,
  52. };
  53. static struct sdhci_pltfm_data sdhci_arasan_pdata = {
  54. .ops = &sdhci_arasan_ops,
  55. };
  56. #ifdef CONFIG_PM_SLEEP
  57. /**
  58. * sdhci_arasan_suspend - Suspend method for the driver
  59. * @dev: Address of the device structure
  60. * Returns 0 on success and error value on error
  61. *
  62. * Put the device in a low power state.
  63. */
  64. static int sdhci_arasan_suspend(struct device *dev)
  65. {
  66. struct platform_device *pdev = to_platform_device(dev);
  67. struct sdhci_host *host = platform_get_drvdata(pdev);
  68. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  69. struct sdhci_arasan_data *sdhci_arasan = pltfm_host->priv;
  70. int ret;
  71. ret = sdhci_suspend_host(host);
  72. if (ret)
  73. return ret;
  74. clk_disable(pltfm_host->clk);
  75. clk_disable(sdhci_arasan->clk_ahb);
  76. return 0;
  77. }
  78. /**
  79. * sdhci_arasan_resume - Resume method for the driver
  80. * @dev: Address of the device structure
  81. * Returns 0 on success and error value on error
  82. *
  83. * Resume operation after suspend
  84. */
  85. static int sdhci_arasan_resume(struct device *dev)
  86. {
  87. struct platform_device *pdev = to_platform_device(dev);
  88. struct sdhci_host *host = platform_get_drvdata(pdev);
  89. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  90. struct sdhci_arasan_data *sdhci_arasan = pltfm_host->priv;
  91. int ret;
  92. ret = clk_enable(sdhci_arasan->clk_ahb);
  93. if (ret) {
  94. dev_err(dev, "Cannot enable AHB clock.\n");
  95. return ret;
  96. }
  97. ret = clk_enable(pltfm_host->clk);
  98. if (ret) {
  99. dev_err(dev, "Cannot enable SD clock.\n");
  100. clk_disable(sdhci_arasan->clk_ahb);
  101. return ret;
  102. }
  103. return sdhci_resume_host(host);
  104. }
  105. #endif /* ! CONFIG_PM_SLEEP */
  106. static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
  107. sdhci_arasan_resume);
  108. static int sdhci_arasan_probe(struct platform_device *pdev)
  109. {
  110. int ret;
  111. struct clk *clk_xin;
  112. struct sdhci_host *host;
  113. struct sdhci_pltfm_host *pltfm_host;
  114. struct sdhci_arasan_data *sdhci_arasan;
  115. sdhci_arasan = devm_kzalloc(&pdev->dev, sizeof(*sdhci_arasan),
  116. GFP_KERNEL);
  117. if (!sdhci_arasan)
  118. return -ENOMEM;
  119. sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
  120. if (IS_ERR(sdhci_arasan->clk_ahb)) {
  121. dev_err(&pdev->dev, "clk_ahb clock not found.\n");
  122. return PTR_ERR(sdhci_arasan->clk_ahb);
  123. }
  124. clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
  125. if (IS_ERR(clk_xin)) {
  126. dev_err(&pdev->dev, "clk_xin clock not found.\n");
  127. return PTR_ERR(clk_xin);
  128. }
  129. ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
  130. if (ret) {
  131. dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
  132. return ret;
  133. }
  134. ret = clk_prepare_enable(clk_xin);
  135. if (ret) {
  136. dev_err(&pdev->dev, "Unable to enable SD clock.\n");
  137. goto clk_dis_ahb;
  138. }
  139. host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata, 0);
  140. if (IS_ERR(host)) {
  141. ret = PTR_ERR(host);
  142. dev_err(&pdev->dev, "platform init failed (%u)\n", ret);
  143. goto clk_disable_all;
  144. }
  145. sdhci_get_of_property(pdev);
  146. pltfm_host = sdhci_priv(host);
  147. pltfm_host->priv = sdhci_arasan;
  148. pltfm_host->clk = clk_xin;
  149. ret = sdhci_add_host(host);
  150. if (ret) {
  151. dev_err(&pdev->dev, "platform register failed (%u)\n", ret);
  152. goto err_pltfm_free;
  153. }
  154. return 0;
  155. err_pltfm_free:
  156. sdhci_pltfm_free(pdev);
  157. clk_disable_all:
  158. clk_disable_unprepare(clk_xin);
  159. clk_dis_ahb:
  160. clk_disable_unprepare(sdhci_arasan->clk_ahb);
  161. return ret;
  162. }
  163. static int sdhci_arasan_remove(struct platform_device *pdev)
  164. {
  165. struct sdhci_host *host = platform_get_drvdata(pdev);
  166. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  167. struct sdhci_arasan_data *sdhci_arasan = pltfm_host->priv;
  168. clk_disable_unprepare(pltfm_host->clk);
  169. clk_disable_unprepare(sdhci_arasan->clk_ahb);
  170. return sdhci_pltfm_unregister(pdev);
  171. }
  172. static const struct of_device_id sdhci_arasan_of_match[] = {
  173. { .compatible = "arasan,sdhci-8.9a" },
  174. { }
  175. };
  176. MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
  177. static struct platform_driver sdhci_arasan_driver = {
  178. .driver = {
  179. .name = "sdhci-arasan",
  180. .owner = THIS_MODULE,
  181. .of_match_table = sdhci_arasan_of_match,
  182. .pm = &sdhci_arasan_dev_pm_ops,
  183. },
  184. .probe = sdhci_arasan_probe,
  185. .remove = sdhci_arasan_remove,
  186. };
  187. module_platform_driver(sdhci_arasan_driver);
  188. MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
  189. MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
  190. MODULE_LICENSE("GPL");