pci-me.c 12 KB

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  1. /*
  2. *
  3. * Intel Management Engine Interface (Intel MEI) Linux driver
  4. * Copyright (c) 2003-2012, Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. */
  16. #include <linux/module.h>
  17. #include <linux/moduleparam.h>
  18. #include <linux/kernel.h>
  19. #include <linux/device.h>
  20. #include <linux/fs.h>
  21. #include <linux/errno.h>
  22. #include <linux/types.h>
  23. #include <linux/fcntl.h>
  24. #include <linux/aio.h>
  25. #include <linux/pci.h>
  26. #include <linux/poll.h>
  27. #include <linux/ioctl.h>
  28. #include <linux/cdev.h>
  29. #include <linux/sched.h>
  30. #include <linux/uuid.h>
  31. #include <linux/compat.h>
  32. #include <linux/jiffies.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/miscdevice.h>
  35. #include <linux/pm_runtime.h>
  36. #include <linux/mei.h>
  37. #include "mei_dev.h"
  38. #include "client.h"
  39. #include "hw-me-regs.h"
  40. #include "hw-me.h"
  41. /* mei_pci_tbl - PCI Device ID Table */
  42. static const struct pci_device_id mei_me_pci_tbl[] = {
  43. {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, mei_me_legacy_cfg)},
  44. {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, mei_me_legacy_cfg)},
  45. {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, mei_me_legacy_cfg)},
  46. {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, mei_me_legacy_cfg)},
  47. {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, mei_me_legacy_cfg)},
  48. {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, mei_me_legacy_cfg)},
  49. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, mei_me_legacy_cfg)},
  50. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, mei_me_legacy_cfg)},
  51. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, mei_me_legacy_cfg)},
  52. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, mei_me_legacy_cfg)},
  53. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, mei_me_legacy_cfg)},
  54. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, mei_me_legacy_cfg)},
  55. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, mei_me_legacy_cfg)},
  56. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, mei_me_legacy_cfg)},
  57. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, mei_me_legacy_cfg)},
  58. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, mei_me_legacy_cfg)},
  59. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, mei_me_legacy_cfg)},
  60. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, mei_me_legacy_cfg)},
  61. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, mei_me_legacy_cfg)},
  62. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, mei_me_legacy_cfg)},
  63. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, mei_me_ich_cfg)},
  64. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, mei_me_ich_cfg)},
  65. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, mei_me_ich_cfg)},
  66. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, mei_me_ich_cfg)},
  67. {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, mei_me_pch_cfg)},
  68. {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, mei_me_pch_cfg)},
  69. {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, mei_me_pch_cpt_pbg_cfg)},
  70. {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, mei_me_pch_cpt_pbg_cfg)},
  71. {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, mei_me_pch_cfg)},
  72. {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, mei_me_pch_cfg)},
  73. {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, mei_me_pch_cfg)},
  74. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, mei_me_lpt_cfg)},
  75. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, mei_me_lpt_cfg)},
  76. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, mei_me_pch_cfg)},
  77. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, mei_me_lpt_cfg)},
  78. {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, mei_me_pch_cfg)},
  79. /* required last entry */
  80. {0, }
  81. };
  82. MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
  83. #ifdef CONFIG_PM_RUNTIME
  84. static inline void mei_me_set_pm_domain(struct mei_device *dev);
  85. static inline void mei_me_unset_pm_domain(struct mei_device *dev);
  86. #else
  87. static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
  88. static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
  89. #endif /* CONFIG_PM_RUNTIME */
  90. /**
  91. * mei_quirk_probe - probe for devices that doesn't valid ME interface
  92. *
  93. * @pdev: PCI device structure
  94. * @cfg: per generation config
  95. *
  96. * returns true if ME Interface is valid, false otherwise
  97. */
  98. static bool mei_me_quirk_probe(struct pci_dev *pdev,
  99. const struct mei_cfg *cfg)
  100. {
  101. if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
  102. dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
  103. return false;
  104. }
  105. return true;
  106. }
  107. /**
  108. * mei_probe - Device Initialization Routine
  109. *
  110. * @pdev: PCI device structure
  111. * @ent: entry in kcs_pci_tbl
  112. *
  113. * returns 0 on success, <0 on failure.
  114. */
  115. static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  116. {
  117. const struct mei_cfg *cfg = (struct mei_cfg *)(ent->driver_data);
  118. struct mei_device *dev;
  119. struct mei_me_hw *hw;
  120. int err;
  121. if (!mei_me_quirk_probe(pdev, cfg))
  122. return -ENODEV;
  123. /* enable pci dev */
  124. err = pci_enable_device(pdev);
  125. if (err) {
  126. dev_err(&pdev->dev, "failed to enable pci device.\n");
  127. goto end;
  128. }
  129. /* set PCI host mastering */
  130. pci_set_master(pdev);
  131. /* pci request regions for mei driver */
  132. err = pci_request_regions(pdev, KBUILD_MODNAME);
  133. if (err) {
  134. dev_err(&pdev->dev, "failed to get pci regions.\n");
  135. goto disable_device;
  136. }
  137. if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
  138. dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
  139. err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
  140. if (err)
  141. err = dma_set_coherent_mask(&pdev->dev,
  142. DMA_BIT_MASK(32));
  143. }
  144. if (err) {
  145. dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
  146. goto release_regions;
  147. }
  148. /* allocates and initializes the mei dev structure */
  149. dev = mei_me_dev_init(pdev, cfg);
  150. if (!dev) {
  151. err = -ENOMEM;
  152. goto release_regions;
  153. }
  154. hw = to_me_hw(dev);
  155. /* mapping IO device memory */
  156. hw->mem_addr = pci_iomap(pdev, 0, 0);
  157. if (!hw->mem_addr) {
  158. dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
  159. err = -ENOMEM;
  160. goto free_device;
  161. }
  162. pci_enable_msi(pdev);
  163. /* request and enable interrupt */
  164. if (pci_dev_msi_enabled(pdev))
  165. err = request_threaded_irq(pdev->irq,
  166. NULL,
  167. mei_me_irq_thread_handler,
  168. IRQF_ONESHOT, KBUILD_MODNAME, dev);
  169. else
  170. err = request_threaded_irq(pdev->irq,
  171. mei_me_irq_quick_handler,
  172. mei_me_irq_thread_handler,
  173. IRQF_SHARED, KBUILD_MODNAME, dev);
  174. if (err) {
  175. dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
  176. pdev->irq);
  177. goto disable_msi;
  178. }
  179. if (mei_start(dev)) {
  180. dev_err(&pdev->dev, "init hw failure.\n");
  181. err = -ENODEV;
  182. goto release_irq;
  183. }
  184. pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
  185. pm_runtime_use_autosuspend(&pdev->dev);
  186. err = mei_register(dev);
  187. if (err)
  188. goto release_irq;
  189. pci_set_drvdata(pdev, dev);
  190. schedule_delayed_work(&dev->timer_work, HZ);
  191. /*
  192. * For not wake-able HW runtime pm framework
  193. * can't be used on pci device level.
  194. * Use domain runtime pm callbacks instead.
  195. */
  196. if (!pci_dev_run_wake(pdev))
  197. mei_me_set_pm_domain(dev);
  198. if (mei_pg_is_enabled(dev))
  199. pm_runtime_put_noidle(&pdev->dev);
  200. dev_dbg(&pdev->dev, "initialization successful.\n");
  201. return 0;
  202. release_irq:
  203. mei_cancel_work(dev);
  204. mei_disable_interrupts(dev);
  205. free_irq(pdev->irq, dev);
  206. disable_msi:
  207. pci_disable_msi(pdev);
  208. pci_iounmap(pdev, hw->mem_addr);
  209. free_device:
  210. kfree(dev);
  211. release_regions:
  212. pci_release_regions(pdev);
  213. disable_device:
  214. pci_disable_device(pdev);
  215. end:
  216. dev_err(&pdev->dev, "initialization failed.\n");
  217. return err;
  218. }
  219. /**
  220. * mei_remove - Device Removal Routine
  221. *
  222. * @pdev: PCI device structure
  223. *
  224. * mei_remove is called by the PCI subsystem to alert the driver
  225. * that it should release a PCI device.
  226. */
  227. static void mei_me_remove(struct pci_dev *pdev)
  228. {
  229. struct mei_device *dev;
  230. struct mei_me_hw *hw;
  231. dev = pci_get_drvdata(pdev);
  232. if (!dev)
  233. return;
  234. if (mei_pg_is_enabled(dev))
  235. pm_runtime_get_noresume(&pdev->dev);
  236. hw = to_me_hw(dev);
  237. dev_dbg(&pdev->dev, "stop\n");
  238. mei_stop(dev);
  239. if (!pci_dev_run_wake(pdev))
  240. mei_me_unset_pm_domain(dev);
  241. /* disable interrupts */
  242. mei_disable_interrupts(dev);
  243. free_irq(pdev->irq, dev);
  244. pci_disable_msi(pdev);
  245. if (hw->mem_addr)
  246. pci_iounmap(pdev, hw->mem_addr);
  247. mei_deregister(dev);
  248. kfree(dev);
  249. pci_release_regions(pdev);
  250. pci_disable_device(pdev);
  251. }
  252. #ifdef CONFIG_PM_SLEEP
  253. static int mei_me_pci_suspend(struct device *device)
  254. {
  255. struct pci_dev *pdev = to_pci_dev(device);
  256. struct mei_device *dev = pci_get_drvdata(pdev);
  257. if (!dev)
  258. return -ENODEV;
  259. dev_dbg(&pdev->dev, "suspend\n");
  260. mei_stop(dev);
  261. mei_disable_interrupts(dev);
  262. free_irq(pdev->irq, dev);
  263. pci_disable_msi(pdev);
  264. return 0;
  265. }
  266. static int mei_me_pci_resume(struct device *device)
  267. {
  268. struct pci_dev *pdev = to_pci_dev(device);
  269. struct mei_device *dev;
  270. int err;
  271. dev = pci_get_drvdata(pdev);
  272. if (!dev)
  273. return -ENODEV;
  274. pci_enable_msi(pdev);
  275. /* request and enable interrupt */
  276. if (pci_dev_msi_enabled(pdev))
  277. err = request_threaded_irq(pdev->irq,
  278. NULL,
  279. mei_me_irq_thread_handler,
  280. IRQF_ONESHOT, KBUILD_MODNAME, dev);
  281. else
  282. err = request_threaded_irq(pdev->irq,
  283. mei_me_irq_quick_handler,
  284. mei_me_irq_thread_handler,
  285. IRQF_SHARED, KBUILD_MODNAME, dev);
  286. if (err) {
  287. dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
  288. pdev->irq);
  289. return err;
  290. }
  291. err = mei_restart(dev);
  292. if (err)
  293. return err;
  294. /* Start timer if stopped in suspend */
  295. schedule_delayed_work(&dev->timer_work, HZ);
  296. return 0;
  297. }
  298. #endif /* CONFIG_PM_SLEEP */
  299. #ifdef CONFIG_PM_RUNTIME
  300. static int mei_me_pm_runtime_idle(struct device *device)
  301. {
  302. struct pci_dev *pdev = to_pci_dev(device);
  303. struct mei_device *dev;
  304. dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
  305. dev = pci_get_drvdata(pdev);
  306. if (!dev)
  307. return -ENODEV;
  308. if (mei_write_is_idle(dev))
  309. pm_schedule_suspend(device, MEI_ME_RPM_TIMEOUT * 2);
  310. return -EBUSY;
  311. }
  312. static int mei_me_pm_runtime_suspend(struct device *device)
  313. {
  314. struct pci_dev *pdev = to_pci_dev(device);
  315. struct mei_device *dev;
  316. int ret;
  317. dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
  318. dev = pci_get_drvdata(pdev);
  319. if (!dev)
  320. return -ENODEV;
  321. mutex_lock(&dev->device_lock);
  322. if (mei_write_is_idle(dev))
  323. ret = mei_me_pg_set_sync(dev);
  324. else
  325. ret = -EAGAIN;
  326. mutex_unlock(&dev->device_lock);
  327. dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
  328. return ret;
  329. }
  330. static int mei_me_pm_runtime_resume(struct device *device)
  331. {
  332. struct pci_dev *pdev = to_pci_dev(device);
  333. struct mei_device *dev;
  334. int ret;
  335. dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
  336. dev = pci_get_drvdata(pdev);
  337. if (!dev)
  338. return -ENODEV;
  339. mutex_lock(&dev->device_lock);
  340. ret = mei_me_pg_unset_sync(dev);
  341. mutex_unlock(&dev->device_lock);
  342. dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
  343. return ret;
  344. }
  345. /**
  346. * mei_me_set_pm_domain - fill and set pm domian stucture for device
  347. *
  348. * @dev: mei_device
  349. */
  350. static inline void mei_me_set_pm_domain(struct mei_device *dev)
  351. {
  352. struct pci_dev *pdev = dev->pdev;
  353. if (pdev->dev.bus && pdev->dev.bus->pm) {
  354. dev->pg_domain.ops = *pdev->dev.bus->pm;
  355. dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
  356. dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
  357. dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
  358. pdev->dev.pm_domain = &dev->pg_domain;
  359. }
  360. }
  361. /**
  362. * mei_me_unset_pm_domain - clean pm domian stucture for device
  363. *
  364. * @dev: mei_device
  365. */
  366. static inline void mei_me_unset_pm_domain(struct mei_device *dev)
  367. {
  368. /* stop using pm callbacks if any */
  369. dev->pdev->dev.pm_domain = NULL;
  370. }
  371. #endif /* CONFIG_PM_RUNTIME */
  372. #ifdef CONFIG_PM
  373. static const struct dev_pm_ops mei_me_pm_ops = {
  374. SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
  375. mei_me_pci_resume)
  376. SET_RUNTIME_PM_OPS(
  377. mei_me_pm_runtime_suspend,
  378. mei_me_pm_runtime_resume,
  379. mei_me_pm_runtime_idle)
  380. };
  381. #define MEI_ME_PM_OPS (&mei_me_pm_ops)
  382. #else
  383. #define MEI_ME_PM_OPS NULL
  384. #endif /* CONFIG_PM */
  385. /*
  386. * PCI driver structure
  387. */
  388. static struct pci_driver mei_me_driver = {
  389. .name = KBUILD_MODNAME,
  390. .id_table = mei_me_pci_tbl,
  391. .probe = mei_me_probe,
  392. .remove = mei_me_remove,
  393. .shutdown = mei_me_remove,
  394. .driver.pm = MEI_ME_PM_OPS,
  395. };
  396. module_pci_driver(mei_me_driver);
  397. MODULE_AUTHOR("Intel Corporation");
  398. MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
  399. MODULE_LICENSE("GPL v2");