hw-txe.h 2.2 KB

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  1. /*
  2. *
  3. * Intel Management Engine Interface (Intel MEI) Linux driver
  4. * Copyright (c) 2013-2014, Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. */
  16. #ifndef _MEI_HW_TXE_H_
  17. #define _MEI_HW_TXE_H_
  18. #include <linux/irqreturn.h>
  19. #include "hw.h"
  20. #include "hw-txe-regs.h"
  21. #define MEI_TXI_RPM_TIMEOUT 500 /* ms */
  22. /* Flatten Hierarchy interrupt cause */
  23. #define TXE_INTR_READINESS_BIT 0 /* HISR_INT_0_STS */
  24. #define TXE_INTR_READINESS HISR_INT_0_STS
  25. #define TXE_INTR_ALIVENESS_BIT 1 /* HISR_INT_1_STS */
  26. #define TXE_INTR_ALIVENESS HISR_INT_1_STS
  27. #define TXE_INTR_OUT_DB_BIT 2 /* HISR_INT_2_STS */
  28. #define TXE_INTR_OUT_DB HISR_INT_2_STS
  29. #define TXE_INTR_IN_READY_BIT 8 /* beyond HISR */
  30. #define TXE_INTR_IN_READY BIT(8)
  31. /**
  32. * struct mei_txe_hw - txe hardware specifics
  33. *
  34. * @mem_addr: SeC and BRIDGE bars
  35. * @aliveness: aliveness (power gating) state of the hardware
  36. * @readiness: readiness state of the hardware
  37. * @wait_aliveness_resp: aliveness wait queue
  38. * @intr_cause: translated interrupt cause
  39. */
  40. struct mei_txe_hw {
  41. void __iomem *mem_addr[NUM_OF_MEM_BARS];
  42. u32 aliveness;
  43. u32 readiness;
  44. u32 slots;
  45. wait_queue_head_t wait_aliveness_resp;
  46. unsigned long intr_cause;
  47. };
  48. #define to_txe_hw(dev) (struct mei_txe_hw *)((dev)->hw)
  49. static inline struct mei_device *hw_txe_to_mei(struct mei_txe_hw *hw)
  50. {
  51. return container_of((void *)hw, struct mei_device, hw);
  52. }
  53. extern const struct mei_cfg mei_txe_cfg;
  54. struct mei_device *mei_txe_dev_init(struct pci_dev *pdev,
  55. const struct mei_cfg *cfg);
  56. irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id);
  57. irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id);
  58. int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req);
  59. int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range);
  60. #endif /* _MEI_HW_TXE_H_ */