ad525x_dpot.c 20 KB

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  1. /*
  2. * ad525x_dpot: Driver for the Analog Devices digital potentiometers
  3. * Copyright (c) 2009-2010 Analog Devices, Inc.
  4. * Author: Michael Hennerich <hennerich@blackfin.uclinux.org>
  5. *
  6. * DEVID #Wipers #Positions Resistor Options (kOhm)
  7. * AD5258 1 64 1, 10, 50, 100
  8. * AD5259 1 256 5, 10, 50, 100
  9. * AD5251 2 64 1, 10, 50, 100
  10. * AD5252 2 256 1, 10, 50, 100
  11. * AD5255 3 512 25, 250
  12. * AD5253 4 64 1, 10, 50, 100
  13. * AD5254 4 256 1, 10, 50, 100
  14. * AD5160 1 256 5, 10, 50, 100
  15. * AD5161 1 256 5, 10, 50, 100
  16. * AD5162 2 256 2.5, 10, 50, 100
  17. * AD5165 1 256 100
  18. * AD5200 1 256 10, 50
  19. * AD5201 1 33 10, 50
  20. * AD5203 4 64 10, 100
  21. * AD5204 4 256 10, 50, 100
  22. * AD5206 6 256 10, 50, 100
  23. * AD5207 2 256 10, 50, 100
  24. * AD5231 1 1024 10, 50, 100
  25. * AD5232 2 256 10, 50, 100
  26. * AD5233 4 64 10, 50, 100
  27. * AD5235 2 1024 25, 250
  28. * AD5260 1 256 20, 50, 200
  29. * AD5262 2 256 20, 50, 200
  30. * AD5263 4 256 20, 50, 200
  31. * AD5290 1 256 10, 50, 100
  32. * AD5291 1 256 20, 50, 100 (20-TP)
  33. * AD5292 1 1024 20, 50, 100 (20-TP)
  34. * AD5293 1 1024 20, 50, 100
  35. * AD7376 1 128 10, 50, 100, 1M
  36. * AD8400 1 256 1, 10, 50, 100
  37. * AD8402 2 256 1, 10, 50, 100
  38. * AD8403 4 256 1, 10, 50, 100
  39. * ADN2850 3 512 25, 250
  40. * AD5241 1 256 10, 100, 1M
  41. * AD5246 1 128 5, 10, 50, 100
  42. * AD5247 1 128 5, 10, 50, 100
  43. * AD5245 1 256 5, 10, 50, 100
  44. * AD5243 2 256 2.5, 10, 50, 100
  45. * AD5248 2 256 2.5, 10, 50, 100
  46. * AD5242 2 256 20, 50, 200
  47. * AD5280 1 256 20, 50, 200
  48. * AD5282 2 256 20, 50, 200
  49. * ADN2860 3 512 25, 250
  50. * AD5273 1 64 1, 10, 50, 100 (OTP)
  51. * AD5171 1 64 5, 10, 50, 100 (OTP)
  52. * AD5170 1 256 2.5, 10, 50, 100 (OTP)
  53. * AD5172 2 256 2.5, 10, 50, 100 (OTP)
  54. * AD5173 2 256 2.5, 10, 50, 100 (OTP)
  55. * AD5270 1 1024 20, 50, 100 (50-TP)
  56. * AD5271 1 256 20, 50, 100 (50-TP)
  57. * AD5272 1 1024 20, 50, 100 (50-TP)
  58. * AD5274 1 256 20, 50, 100 (50-TP)
  59. *
  60. * See Documentation/misc-devices/ad525x_dpot.txt for more info.
  61. *
  62. * derived from ad5258.c
  63. * Copyright (c) 2009 Cyber Switching, Inc.
  64. * Author: Chris Verges <chrisv@cyberswitching.com>
  65. *
  66. * derived from ad5252.c
  67. * Copyright (c) 2006-2011 Michael Hennerich <hennerich@blackfin.uclinux.org>
  68. *
  69. * Licensed under the GPL-2 or later.
  70. */
  71. #include <linux/module.h>
  72. #include <linux/device.h>
  73. #include <linux/kernel.h>
  74. #include <linux/delay.h>
  75. #include <linux/slab.h>
  76. #include "ad525x_dpot.h"
  77. /*
  78. * Client data (each client gets its own)
  79. */
  80. struct dpot_data {
  81. struct ad_dpot_bus_data bdata;
  82. struct mutex update_lock;
  83. unsigned rdac_mask;
  84. unsigned max_pos;
  85. unsigned long devid;
  86. unsigned uid;
  87. unsigned feat;
  88. unsigned wipers;
  89. u16 rdac_cache[MAX_RDACS];
  90. DECLARE_BITMAP(otp_en_mask, MAX_RDACS);
  91. };
  92. static inline int dpot_read_d8(struct dpot_data *dpot)
  93. {
  94. return dpot->bdata.bops->read_d8(dpot->bdata.client);
  95. }
  96. static inline int dpot_read_r8d8(struct dpot_data *dpot, u8 reg)
  97. {
  98. return dpot->bdata.bops->read_r8d8(dpot->bdata.client, reg);
  99. }
  100. static inline int dpot_read_r8d16(struct dpot_data *dpot, u8 reg)
  101. {
  102. return dpot->bdata.bops->read_r8d16(dpot->bdata.client, reg);
  103. }
  104. static inline int dpot_write_d8(struct dpot_data *dpot, u8 val)
  105. {
  106. return dpot->bdata.bops->write_d8(dpot->bdata.client, val);
  107. }
  108. static inline int dpot_write_r8d8(struct dpot_data *dpot, u8 reg, u16 val)
  109. {
  110. return dpot->bdata.bops->write_r8d8(dpot->bdata.client, reg, val);
  111. }
  112. static inline int dpot_write_r8d16(struct dpot_data *dpot, u8 reg, u16 val)
  113. {
  114. return dpot->bdata.bops->write_r8d16(dpot->bdata.client, reg, val);
  115. }
  116. static s32 dpot_read_spi(struct dpot_data *dpot, u8 reg)
  117. {
  118. unsigned ctrl = 0;
  119. int value;
  120. if (!(reg & (DPOT_ADDR_EEPROM | DPOT_ADDR_CMD))) {
  121. if (dpot->feat & F_RDACS_WONLY)
  122. return dpot->rdac_cache[reg & DPOT_RDAC_MASK];
  123. if (dpot->uid == DPOT_UID(AD5291_ID) ||
  124. dpot->uid == DPOT_UID(AD5292_ID) ||
  125. dpot->uid == DPOT_UID(AD5293_ID)) {
  126. value = dpot_read_r8d8(dpot,
  127. DPOT_AD5291_READ_RDAC << 2);
  128. if (dpot->uid == DPOT_UID(AD5291_ID))
  129. value = value >> 2;
  130. return value;
  131. } else if (dpot->uid == DPOT_UID(AD5270_ID) ||
  132. dpot->uid == DPOT_UID(AD5271_ID)) {
  133. value = dpot_read_r8d8(dpot,
  134. DPOT_AD5270_1_2_4_READ_RDAC << 2);
  135. if (value < 0)
  136. return value;
  137. if (dpot->uid == DPOT_UID(AD5271_ID))
  138. value = value >> 2;
  139. return value;
  140. }
  141. ctrl = DPOT_SPI_READ_RDAC;
  142. } else if (reg & DPOT_ADDR_EEPROM) {
  143. ctrl = DPOT_SPI_READ_EEPROM;
  144. }
  145. if (dpot->feat & F_SPI_16BIT)
  146. return dpot_read_r8d8(dpot, ctrl);
  147. else if (dpot->feat & F_SPI_24BIT)
  148. return dpot_read_r8d16(dpot, ctrl);
  149. return -EFAULT;
  150. }
  151. static s32 dpot_read_i2c(struct dpot_data *dpot, u8 reg)
  152. {
  153. int value;
  154. unsigned ctrl = 0;
  155. switch (dpot->uid) {
  156. case DPOT_UID(AD5246_ID):
  157. case DPOT_UID(AD5247_ID):
  158. return dpot_read_d8(dpot);
  159. case DPOT_UID(AD5245_ID):
  160. case DPOT_UID(AD5241_ID):
  161. case DPOT_UID(AD5242_ID):
  162. case DPOT_UID(AD5243_ID):
  163. case DPOT_UID(AD5248_ID):
  164. case DPOT_UID(AD5280_ID):
  165. case DPOT_UID(AD5282_ID):
  166. ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ?
  167. 0 : DPOT_AD5282_RDAC_AB;
  168. return dpot_read_r8d8(dpot, ctrl);
  169. case DPOT_UID(AD5170_ID):
  170. case DPOT_UID(AD5171_ID):
  171. case DPOT_UID(AD5273_ID):
  172. return dpot_read_d8(dpot);
  173. case DPOT_UID(AD5172_ID):
  174. case DPOT_UID(AD5173_ID):
  175. ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ?
  176. 0 : DPOT_AD5172_3_A0;
  177. return dpot_read_r8d8(dpot, ctrl);
  178. case DPOT_UID(AD5272_ID):
  179. case DPOT_UID(AD5274_ID):
  180. dpot_write_r8d8(dpot,
  181. (DPOT_AD5270_1_2_4_READ_RDAC << 2), 0);
  182. value = dpot_read_r8d16(dpot,
  183. DPOT_AD5270_1_2_4_RDAC << 2);
  184. if (value < 0)
  185. return value;
  186. /*
  187. * AD5272/AD5274 returns high byte first, however
  188. * underling smbus expects low byte first.
  189. */
  190. value = swab16(value);
  191. if (dpot->uid == DPOT_UID(AD5271_ID))
  192. value = value >> 2;
  193. return value;
  194. default:
  195. if ((reg & DPOT_REG_TOL) || (dpot->max_pos > 256))
  196. return dpot_read_r8d16(dpot, (reg & 0xF8) |
  197. ((reg & 0x7) << 1));
  198. else
  199. return dpot_read_r8d8(dpot, reg);
  200. }
  201. }
  202. static s32 dpot_read(struct dpot_data *dpot, u8 reg)
  203. {
  204. if (dpot->feat & F_SPI)
  205. return dpot_read_spi(dpot, reg);
  206. else
  207. return dpot_read_i2c(dpot, reg);
  208. }
  209. static s32 dpot_write_spi(struct dpot_data *dpot, u8 reg, u16 value)
  210. {
  211. unsigned val = 0;
  212. if (!(reg & (DPOT_ADDR_EEPROM | DPOT_ADDR_CMD | DPOT_ADDR_OTP))) {
  213. if (dpot->feat & F_RDACS_WONLY)
  214. dpot->rdac_cache[reg & DPOT_RDAC_MASK] = value;
  215. if (dpot->feat & F_AD_APPDATA) {
  216. if (dpot->feat & F_SPI_8BIT) {
  217. val = ((reg & DPOT_RDAC_MASK) <<
  218. DPOT_MAX_POS(dpot->devid)) |
  219. value;
  220. return dpot_write_d8(dpot, val);
  221. } else if (dpot->feat & F_SPI_16BIT) {
  222. val = ((reg & DPOT_RDAC_MASK) <<
  223. DPOT_MAX_POS(dpot->devid)) |
  224. value;
  225. return dpot_write_r8d8(dpot, val >> 8,
  226. val & 0xFF);
  227. } else
  228. BUG();
  229. } else {
  230. if (dpot->uid == DPOT_UID(AD5291_ID) ||
  231. dpot->uid == DPOT_UID(AD5292_ID) ||
  232. dpot->uid == DPOT_UID(AD5293_ID)) {
  233. dpot_write_r8d8(dpot, DPOT_AD5291_CTRLREG << 2,
  234. DPOT_AD5291_UNLOCK_CMD);
  235. if (dpot->uid == DPOT_UID(AD5291_ID))
  236. value = value << 2;
  237. return dpot_write_r8d8(dpot,
  238. (DPOT_AD5291_RDAC << 2) |
  239. (value >> 8), value & 0xFF);
  240. } else if (dpot->uid == DPOT_UID(AD5270_ID) ||
  241. dpot->uid == DPOT_UID(AD5271_ID)) {
  242. dpot_write_r8d8(dpot,
  243. DPOT_AD5270_1_2_4_CTRLREG << 2,
  244. DPOT_AD5270_1_2_4_UNLOCK_CMD);
  245. if (dpot->uid == DPOT_UID(AD5271_ID))
  246. value = value << 2;
  247. return dpot_write_r8d8(dpot,
  248. (DPOT_AD5270_1_2_4_RDAC << 2) |
  249. (value >> 8), value & 0xFF);
  250. }
  251. val = DPOT_SPI_RDAC | (reg & DPOT_RDAC_MASK);
  252. }
  253. } else if (reg & DPOT_ADDR_EEPROM) {
  254. val = DPOT_SPI_EEPROM | (reg & DPOT_RDAC_MASK);
  255. } else if (reg & DPOT_ADDR_CMD) {
  256. switch (reg) {
  257. case DPOT_DEC_ALL_6DB:
  258. val = DPOT_SPI_DEC_ALL_6DB;
  259. break;
  260. case DPOT_INC_ALL_6DB:
  261. val = DPOT_SPI_INC_ALL_6DB;
  262. break;
  263. case DPOT_DEC_ALL:
  264. val = DPOT_SPI_DEC_ALL;
  265. break;
  266. case DPOT_INC_ALL:
  267. val = DPOT_SPI_INC_ALL;
  268. break;
  269. }
  270. } else if (reg & DPOT_ADDR_OTP) {
  271. if (dpot->uid == DPOT_UID(AD5291_ID) ||
  272. dpot->uid == DPOT_UID(AD5292_ID)) {
  273. return dpot_write_r8d8(dpot,
  274. DPOT_AD5291_STORE_XTPM << 2, 0);
  275. } else if (dpot->uid == DPOT_UID(AD5270_ID) ||
  276. dpot->uid == DPOT_UID(AD5271_ID)) {
  277. return dpot_write_r8d8(dpot,
  278. DPOT_AD5270_1_2_4_STORE_XTPM << 2, 0);
  279. }
  280. } else
  281. BUG();
  282. if (dpot->feat & F_SPI_16BIT)
  283. return dpot_write_r8d8(dpot, val, value);
  284. else if (dpot->feat & F_SPI_24BIT)
  285. return dpot_write_r8d16(dpot, val, value);
  286. return -EFAULT;
  287. }
  288. static s32 dpot_write_i2c(struct dpot_data *dpot, u8 reg, u16 value)
  289. {
  290. /* Only write the instruction byte for certain commands */
  291. unsigned tmp = 0, ctrl = 0;
  292. switch (dpot->uid) {
  293. case DPOT_UID(AD5246_ID):
  294. case DPOT_UID(AD5247_ID):
  295. return dpot_write_d8(dpot, value);
  296. break;
  297. case DPOT_UID(AD5245_ID):
  298. case DPOT_UID(AD5241_ID):
  299. case DPOT_UID(AD5242_ID):
  300. case DPOT_UID(AD5243_ID):
  301. case DPOT_UID(AD5248_ID):
  302. case DPOT_UID(AD5280_ID):
  303. case DPOT_UID(AD5282_ID):
  304. ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ?
  305. 0 : DPOT_AD5282_RDAC_AB;
  306. return dpot_write_r8d8(dpot, ctrl, value);
  307. break;
  308. case DPOT_UID(AD5171_ID):
  309. case DPOT_UID(AD5273_ID):
  310. if (reg & DPOT_ADDR_OTP) {
  311. tmp = dpot_read_d8(dpot);
  312. if (tmp >> 6) /* Ready to Program? */
  313. return -EFAULT;
  314. ctrl = DPOT_AD5273_FUSE;
  315. }
  316. return dpot_write_r8d8(dpot, ctrl, value);
  317. break;
  318. case DPOT_UID(AD5172_ID):
  319. case DPOT_UID(AD5173_ID):
  320. ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ?
  321. 0 : DPOT_AD5172_3_A0;
  322. if (reg & DPOT_ADDR_OTP) {
  323. tmp = dpot_read_r8d16(dpot, ctrl);
  324. if (tmp >> 14) /* Ready to Program? */
  325. return -EFAULT;
  326. ctrl |= DPOT_AD5170_2_3_FUSE;
  327. }
  328. return dpot_write_r8d8(dpot, ctrl, value);
  329. break;
  330. case DPOT_UID(AD5170_ID):
  331. if (reg & DPOT_ADDR_OTP) {
  332. tmp = dpot_read_r8d16(dpot, tmp);
  333. if (tmp >> 14) /* Ready to Program? */
  334. return -EFAULT;
  335. ctrl = DPOT_AD5170_2_3_FUSE;
  336. }
  337. return dpot_write_r8d8(dpot, ctrl, value);
  338. break;
  339. case DPOT_UID(AD5272_ID):
  340. case DPOT_UID(AD5274_ID):
  341. dpot_write_r8d8(dpot, DPOT_AD5270_1_2_4_CTRLREG << 2,
  342. DPOT_AD5270_1_2_4_UNLOCK_CMD);
  343. if (reg & DPOT_ADDR_OTP)
  344. return dpot_write_r8d8(dpot,
  345. DPOT_AD5270_1_2_4_STORE_XTPM << 2, 0);
  346. if (dpot->uid == DPOT_UID(AD5274_ID))
  347. value = value << 2;
  348. return dpot_write_r8d8(dpot, (DPOT_AD5270_1_2_4_RDAC << 2) |
  349. (value >> 8), value & 0xFF);
  350. break;
  351. default:
  352. if (reg & DPOT_ADDR_CMD)
  353. return dpot_write_d8(dpot, reg);
  354. if (dpot->max_pos > 256)
  355. return dpot_write_r8d16(dpot, (reg & 0xF8) |
  356. ((reg & 0x7) << 1), value);
  357. else
  358. /* All other registers require instruction + data bytes */
  359. return dpot_write_r8d8(dpot, reg, value);
  360. }
  361. }
  362. static s32 dpot_write(struct dpot_data *dpot, u8 reg, u16 value)
  363. {
  364. if (dpot->feat & F_SPI)
  365. return dpot_write_spi(dpot, reg, value);
  366. else
  367. return dpot_write_i2c(dpot, reg, value);
  368. }
  369. /* sysfs functions */
  370. static ssize_t sysfs_show_reg(struct device *dev,
  371. struct device_attribute *attr,
  372. char *buf, u32 reg)
  373. {
  374. struct dpot_data *data = dev_get_drvdata(dev);
  375. s32 value;
  376. if (reg & DPOT_ADDR_OTP_EN)
  377. return sprintf(buf, "%s\n",
  378. test_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask) ?
  379. "enabled" : "disabled");
  380. mutex_lock(&data->update_lock);
  381. value = dpot_read(data, reg);
  382. mutex_unlock(&data->update_lock);
  383. if (value < 0)
  384. return -EINVAL;
  385. /*
  386. * Let someone else deal with converting this ...
  387. * the tolerance is a two-byte value where the MSB
  388. * is a sign + integer value, and the LSB is a
  389. * decimal value. See page 18 of the AD5258
  390. * datasheet (Rev. A) for more details.
  391. */
  392. if (reg & DPOT_REG_TOL)
  393. return sprintf(buf, "0x%04x\n", value & 0xFFFF);
  394. else
  395. return sprintf(buf, "%u\n", value & data->rdac_mask);
  396. }
  397. static ssize_t sysfs_set_reg(struct device *dev,
  398. struct device_attribute *attr,
  399. const char *buf, size_t count, u32 reg)
  400. {
  401. struct dpot_data *data = dev_get_drvdata(dev);
  402. unsigned long value;
  403. int err;
  404. if (reg & DPOT_ADDR_OTP_EN) {
  405. if (!strncmp(buf, "enabled", sizeof("enabled")))
  406. set_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask);
  407. else
  408. clear_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask);
  409. return count;
  410. }
  411. if ((reg & DPOT_ADDR_OTP) &&
  412. !test_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask))
  413. return -EPERM;
  414. err = kstrtoul(buf, 10, &value);
  415. if (err)
  416. return err;
  417. if (value > data->rdac_mask)
  418. value = data->rdac_mask;
  419. mutex_lock(&data->update_lock);
  420. dpot_write(data, reg, value);
  421. if (reg & DPOT_ADDR_EEPROM)
  422. msleep(26); /* Sleep while the EEPROM updates */
  423. else if (reg & DPOT_ADDR_OTP)
  424. msleep(400); /* Sleep while the OTP updates */
  425. mutex_unlock(&data->update_lock);
  426. return count;
  427. }
  428. static ssize_t sysfs_do_cmd(struct device *dev,
  429. struct device_attribute *attr,
  430. const char *buf, size_t count, u32 reg)
  431. {
  432. struct dpot_data *data = dev_get_drvdata(dev);
  433. mutex_lock(&data->update_lock);
  434. dpot_write(data, reg, 0);
  435. mutex_unlock(&data->update_lock);
  436. return count;
  437. }
  438. /* ------------------------------------------------------------------------- */
  439. #define DPOT_DEVICE_SHOW(_name, _reg) static ssize_t \
  440. show_##_name(struct device *dev, \
  441. struct device_attribute *attr, char *buf) \
  442. { \
  443. return sysfs_show_reg(dev, attr, buf, _reg); \
  444. }
  445. #define DPOT_DEVICE_SET(_name, _reg) static ssize_t \
  446. set_##_name(struct device *dev, \
  447. struct device_attribute *attr, \
  448. const char *buf, size_t count) \
  449. { \
  450. return sysfs_set_reg(dev, attr, buf, count, _reg); \
  451. }
  452. #define DPOT_DEVICE_SHOW_SET(name, reg) \
  453. DPOT_DEVICE_SHOW(name, reg) \
  454. DPOT_DEVICE_SET(name, reg) \
  455. static DEVICE_ATTR(name, S_IWUSR | S_IRUGO, show_##name, set_##name);
  456. #define DPOT_DEVICE_SHOW_ONLY(name, reg) \
  457. DPOT_DEVICE_SHOW(name, reg) \
  458. static DEVICE_ATTR(name, S_IWUSR | S_IRUGO, show_##name, NULL);
  459. DPOT_DEVICE_SHOW_SET(rdac0, DPOT_ADDR_RDAC | DPOT_RDAC0);
  460. DPOT_DEVICE_SHOW_SET(eeprom0, DPOT_ADDR_EEPROM | DPOT_RDAC0);
  461. DPOT_DEVICE_SHOW_ONLY(tolerance0, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC0);
  462. DPOT_DEVICE_SHOW_SET(otp0, DPOT_ADDR_OTP | DPOT_RDAC0);
  463. DPOT_DEVICE_SHOW_SET(otp0en, DPOT_ADDR_OTP_EN | DPOT_RDAC0);
  464. DPOT_DEVICE_SHOW_SET(rdac1, DPOT_ADDR_RDAC | DPOT_RDAC1);
  465. DPOT_DEVICE_SHOW_SET(eeprom1, DPOT_ADDR_EEPROM | DPOT_RDAC1);
  466. DPOT_DEVICE_SHOW_ONLY(tolerance1, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC1);
  467. DPOT_DEVICE_SHOW_SET(otp1, DPOT_ADDR_OTP | DPOT_RDAC1);
  468. DPOT_DEVICE_SHOW_SET(otp1en, DPOT_ADDR_OTP_EN | DPOT_RDAC1);
  469. DPOT_DEVICE_SHOW_SET(rdac2, DPOT_ADDR_RDAC | DPOT_RDAC2);
  470. DPOT_DEVICE_SHOW_SET(eeprom2, DPOT_ADDR_EEPROM | DPOT_RDAC2);
  471. DPOT_DEVICE_SHOW_ONLY(tolerance2, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC2);
  472. DPOT_DEVICE_SHOW_SET(otp2, DPOT_ADDR_OTP | DPOT_RDAC2);
  473. DPOT_DEVICE_SHOW_SET(otp2en, DPOT_ADDR_OTP_EN | DPOT_RDAC2);
  474. DPOT_DEVICE_SHOW_SET(rdac3, DPOT_ADDR_RDAC | DPOT_RDAC3);
  475. DPOT_DEVICE_SHOW_SET(eeprom3, DPOT_ADDR_EEPROM | DPOT_RDAC3);
  476. DPOT_DEVICE_SHOW_ONLY(tolerance3, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC3);
  477. DPOT_DEVICE_SHOW_SET(otp3, DPOT_ADDR_OTP | DPOT_RDAC3);
  478. DPOT_DEVICE_SHOW_SET(otp3en, DPOT_ADDR_OTP_EN | DPOT_RDAC3);
  479. DPOT_DEVICE_SHOW_SET(rdac4, DPOT_ADDR_RDAC | DPOT_RDAC4);
  480. DPOT_DEVICE_SHOW_SET(eeprom4, DPOT_ADDR_EEPROM | DPOT_RDAC4);
  481. DPOT_DEVICE_SHOW_ONLY(tolerance4, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC4);
  482. DPOT_DEVICE_SHOW_SET(otp4, DPOT_ADDR_OTP | DPOT_RDAC4);
  483. DPOT_DEVICE_SHOW_SET(otp4en, DPOT_ADDR_OTP_EN | DPOT_RDAC4);
  484. DPOT_DEVICE_SHOW_SET(rdac5, DPOT_ADDR_RDAC | DPOT_RDAC5);
  485. DPOT_DEVICE_SHOW_SET(eeprom5, DPOT_ADDR_EEPROM | DPOT_RDAC5);
  486. DPOT_DEVICE_SHOW_ONLY(tolerance5, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC5);
  487. DPOT_DEVICE_SHOW_SET(otp5, DPOT_ADDR_OTP | DPOT_RDAC5);
  488. DPOT_DEVICE_SHOW_SET(otp5en, DPOT_ADDR_OTP_EN | DPOT_RDAC5);
  489. static const struct attribute *dpot_attrib_wipers[] = {
  490. &dev_attr_rdac0.attr,
  491. &dev_attr_rdac1.attr,
  492. &dev_attr_rdac2.attr,
  493. &dev_attr_rdac3.attr,
  494. &dev_attr_rdac4.attr,
  495. &dev_attr_rdac5.attr,
  496. NULL
  497. };
  498. static const struct attribute *dpot_attrib_eeprom[] = {
  499. &dev_attr_eeprom0.attr,
  500. &dev_attr_eeprom1.attr,
  501. &dev_attr_eeprom2.attr,
  502. &dev_attr_eeprom3.attr,
  503. &dev_attr_eeprom4.attr,
  504. &dev_attr_eeprom5.attr,
  505. NULL
  506. };
  507. static const struct attribute *dpot_attrib_otp[] = {
  508. &dev_attr_otp0.attr,
  509. &dev_attr_otp1.attr,
  510. &dev_attr_otp2.attr,
  511. &dev_attr_otp3.attr,
  512. &dev_attr_otp4.attr,
  513. &dev_attr_otp5.attr,
  514. NULL
  515. };
  516. static const struct attribute *dpot_attrib_otp_en[] = {
  517. &dev_attr_otp0en.attr,
  518. &dev_attr_otp1en.attr,
  519. &dev_attr_otp2en.attr,
  520. &dev_attr_otp3en.attr,
  521. &dev_attr_otp4en.attr,
  522. &dev_attr_otp5en.attr,
  523. NULL
  524. };
  525. static const struct attribute *dpot_attrib_tolerance[] = {
  526. &dev_attr_tolerance0.attr,
  527. &dev_attr_tolerance1.attr,
  528. &dev_attr_tolerance2.attr,
  529. &dev_attr_tolerance3.attr,
  530. &dev_attr_tolerance4.attr,
  531. &dev_attr_tolerance5.attr,
  532. NULL
  533. };
  534. /* ------------------------------------------------------------------------- */
  535. #define DPOT_DEVICE_DO_CMD(_name, _cmd) static ssize_t \
  536. set_##_name(struct device *dev, \
  537. struct device_attribute *attr, \
  538. const char *buf, size_t count) \
  539. { \
  540. return sysfs_do_cmd(dev, attr, buf, count, _cmd); \
  541. } \
  542. static DEVICE_ATTR(_name, S_IWUSR | S_IRUGO, NULL, set_##_name);
  543. DPOT_DEVICE_DO_CMD(inc_all, DPOT_INC_ALL);
  544. DPOT_DEVICE_DO_CMD(dec_all, DPOT_DEC_ALL);
  545. DPOT_DEVICE_DO_CMD(inc_all_6db, DPOT_INC_ALL_6DB);
  546. DPOT_DEVICE_DO_CMD(dec_all_6db, DPOT_DEC_ALL_6DB);
  547. static struct attribute *ad525x_attributes_commands[] = {
  548. &dev_attr_inc_all.attr,
  549. &dev_attr_dec_all.attr,
  550. &dev_attr_inc_all_6db.attr,
  551. &dev_attr_dec_all_6db.attr,
  552. NULL
  553. };
  554. static const struct attribute_group ad525x_group_commands = {
  555. .attrs = ad525x_attributes_commands,
  556. };
  557. static int ad_dpot_add_files(struct device *dev,
  558. unsigned features, unsigned rdac)
  559. {
  560. int err = sysfs_create_file(&dev->kobj,
  561. dpot_attrib_wipers[rdac]);
  562. if (features & F_CMD_EEP)
  563. err |= sysfs_create_file(&dev->kobj,
  564. dpot_attrib_eeprom[rdac]);
  565. if (features & F_CMD_TOL)
  566. err |= sysfs_create_file(&dev->kobj,
  567. dpot_attrib_tolerance[rdac]);
  568. if (features & F_CMD_OTP) {
  569. err |= sysfs_create_file(&dev->kobj,
  570. dpot_attrib_otp_en[rdac]);
  571. err |= sysfs_create_file(&dev->kobj,
  572. dpot_attrib_otp[rdac]);
  573. }
  574. if (err)
  575. dev_err(dev, "failed to register sysfs hooks for RDAC%d\n",
  576. rdac);
  577. return err;
  578. }
  579. static inline void ad_dpot_remove_files(struct device *dev,
  580. unsigned features, unsigned rdac)
  581. {
  582. sysfs_remove_file(&dev->kobj,
  583. dpot_attrib_wipers[rdac]);
  584. if (features & F_CMD_EEP)
  585. sysfs_remove_file(&dev->kobj,
  586. dpot_attrib_eeprom[rdac]);
  587. if (features & F_CMD_TOL)
  588. sysfs_remove_file(&dev->kobj,
  589. dpot_attrib_tolerance[rdac]);
  590. if (features & F_CMD_OTP) {
  591. sysfs_remove_file(&dev->kobj,
  592. dpot_attrib_otp_en[rdac]);
  593. sysfs_remove_file(&dev->kobj,
  594. dpot_attrib_otp[rdac]);
  595. }
  596. }
  597. int ad_dpot_probe(struct device *dev,
  598. struct ad_dpot_bus_data *bdata, unsigned long devid,
  599. const char *name)
  600. {
  601. struct dpot_data *data;
  602. int i, err = 0;
  603. data = kzalloc(sizeof(struct dpot_data), GFP_KERNEL);
  604. if (!data) {
  605. err = -ENOMEM;
  606. goto exit;
  607. }
  608. dev_set_drvdata(dev, data);
  609. mutex_init(&data->update_lock);
  610. data->bdata = *bdata;
  611. data->devid = devid;
  612. data->max_pos = 1 << DPOT_MAX_POS(devid);
  613. data->rdac_mask = data->max_pos - 1;
  614. data->feat = DPOT_FEAT(devid);
  615. data->uid = DPOT_UID(devid);
  616. data->wipers = DPOT_WIPERS(devid);
  617. for (i = DPOT_RDAC0; i < MAX_RDACS; i++)
  618. if (data->wipers & (1 << i)) {
  619. err = ad_dpot_add_files(dev, data->feat, i);
  620. if (err)
  621. goto exit_remove_files;
  622. /* power-up midscale */
  623. if (data->feat & F_RDACS_WONLY)
  624. data->rdac_cache[i] = data->max_pos / 2;
  625. }
  626. if (data->feat & F_CMD_INC)
  627. err = sysfs_create_group(&dev->kobj, &ad525x_group_commands);
  628. if (err) {
  629. dev_err(dev, "failed to register sysfs hooks\n");
  630. goto exit_free;
  631. }
  632. dev_info(dev, "%s %d-Position Digital Potentiometer registered\n",
  633. name, data->max_pos);
  634. return 0;
  635. exit_remove_files:
  636. for (i = DPOT_RDAC0; i < MAX_RDACS; i++)
  637. if (data->wipers & (1 << i))
  638. ad_dpot_remove_files(dev, data->feat, i);
  639. exit_free:
  640. kfree(data);
  641. dev_set_drvdata(dev, NULL);
  642. exit:
  643. dev_err(dev, "failed to create client for %s ID 0x%lX\n",
  644. name, devid);
  645. return err;
  646. }
  647. EXPORT_SYMBOL(ad_dpot_probe);
  648. int ad_dpot_remove(struct device *dev)
  649. {
  650. struct dpot_data *data = dev_get_drvdata(dev);
  651. int i;
  652. for (i = DPOT_RDAC0; i < MAX_RDACS; i++)
  653. if (data->wipers & (1 << i))
  654. ad_dpot_remove_files(dev, data->feat, i);
  655. kfree(data);
  656. return 0;
  657. }
  658. EXPORT_SYMBOL(ad_dpot_remove);
  659. MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>, "
  660. "Michael Hennerich <hennerich@blackfin.uclinux.org>");
  661. MODULE_DESCRIPTION("Digital potentiometer driver");
  662. MODULE_LICENSE("GPL");