em28xx-core.c 27 KB

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  1. /*
  2. em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
  3. Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
  4. Markus Rechberger <mrechberger@gmail.com>
  5. Mauro Carvalho Chehab <mchehab@infradead.org>
  6. Sascha Sommer <saschasommer@freenet.de>
  7. Copyright (C) 2012 Frank Schäfer <fschaefer.oss@googlemail.com>
  8. This program is free software; you can redistribute it and/or modify
  9. it under the terms of the GNU General Public License as published by
  10. the Free Software Foundation; either version 2 of the License, or
  11. (at your option) any later version.
  12. This program is distributed in the hope that it will be useful,
  13. but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. GNU General Public License for more details.
  16. You should have received a copy of the GNU General Public License
  17. along with this program; if not, write to the Free Software
  18. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <linux/init.h>
  21. #include <linux/jiffies.h>
  22. #include <linux/list.h>
  23. #include <linux/module.h>
  24. #include <linux/slab.h>
  25. #include <linux/usb.h>
  26. #include <linux/vmalloc.h>
  27. #include <sound/ac97_codec.h>
  28. #include <media/v4l2-common.h>
  29. #include "em28xx.h"
  30. #define DRIVER_AUTHOR "Ludovico Cavedon <cavedon@sssup.it>, " \
  31. "Markus Rechberger <mrechberger@gmail.com>, " \
  32. "Mauro Carvalho Chehab <mchehab@infradead.org>, " \
  33. "Sascha Sommer <saschasommer@freenet.de>"
  34. MODULE_AUTHOR(DRIVER_AUTHOR);
  35. MODULE_DESCRIPTION(DRIVER_DESC);
  36. MODULE_LICENSE("GPL");
  37. MODULE_VERSION(EM28XX_VERSION);
  38. /* #define ENABLE_DEBUG_ISOC_FRAMES */
  39. static unsigned int core_debug;
  40. module_param(core_debug, int, 0644);
  41. MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
  42. #define em28xx_coredbg(fmt, arg...) do {\
  43. if (core_debug) \
  44. printk(KERN_INFO "%s %s :"fmt, \
  45. dev->name, __func__ , ##arg); } while (0)
  46. static unsigned int reg_debug;
  47. module_param(reg_debug, int, 0644);
  48. MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
  49. #define em28xx_regdbg(fmt, arg...) do {\
  50. if (reg_debug) \
  51. printk(KERN_INFO "%s %s :"fmt, \
  52. dev->name, __func__ , ##arg); } while (0)
  53. /* FIXME */
  54. #define em28xx_isocdbg(fmt, arg...) do {\
  55. if (core_debug) \
  56. printk(KERN_INFO "%s %s :"fmt, \
  57. dev->name, __func__ , ##arg); } while (0)
  58. /*
  59. * em28xx_read_reg_req()
  60. * reads data from the usb device specifying bRequest
  61. */
  62. int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
  63. char *buf, int len)
  64. {
  65. int ret;
  66. int pipe = usb_rcvctrlpipe(dev->udev, 0);
  67. if (dev->disconnected)
  68. return -ENODEV;
  69. if (len > URB_MAX_CTRL_SIZE)
  70. return -EINVAL;
  71. if (reg_debug) {
  72. printk(KERN_DEBUG "(pipe 0x%08x): "
  73. "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
  74. pipe,
  75. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  76. req, 0, 0,
  77. reg & 0xff, reg >> 8,
  78. len & 0xff, len >> 8);
  79. }
  80. mutex_lock(&dev->ctrl_urb_lock);
  81. ret = usb_control_msg(dev->udev, pipe, req,
  82. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  83. 0x0000, reg, dev->urb_buf, len, HZ);
  84. if (ret < 0) {
  85. if (reg_debug)
  86. printk(" failed!\n");
  87. mutex_unlock(&dev->ctrl_urb_lock);
  88. return usb_translate_errors(ret);
  89. }
  90. if (len)
  91. memcpy(buf, dev->urb_buf, len);
  92. mutex_unlock(&dev->ctrl_urb_lock);
  93. if (reg_debug) {
  94. int byte;
  95. printk("<<<");
  96. for (byte = 0; byte < len; byte++)
  97. printk(" %02x", (unsigned char)buf[byte]);
  98. printk("\n");
  99. }
  100. return ret;
  101. }
  102. /*
  103. * em28xx_read_reg_req()
  104. * reads data from the usb device specifying bRequest
  105. */
  106. int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
  107. {
  108. int ret;
  109. u8 val;
  110. ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
  111. if (ret < 0)
  112. return ret;
  113. return val;
  114. }
  115. int em28xx_read_reg(struct em28xx *dev, u16 reg)
  116. {
  117. return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
  118. }
  119. EXPORT_SYMBOL_GPL(em28xx_read_reg);
  120. /*
  121. * em28xx_write_regs_req()
  122. * sends data to the usb device, specifying bRequest
  123. */
  124. int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
  125. int len)
  126. {
  127. int ret;
  128. int pipe = usb_sndctrlpipe(dev->udev, 0);
  129. if (dev->disconnected)
  130. return -ENODEV;
  131. if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
  132. return -EINVAL;
  133. if (reg_debug) {
  134. int byte;
  135. printk(KERN_DEBUG "(pipe 0x%08x): "
  136. "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
  137. pipe,
  138. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  139. req, 0, 0,
  140. reg & 0xff, reg >> 8,
  141. len & 0xff, len >> 8);
  142. for (byte = 0; byte < len; byte++)
  143. printk(" %02x", (unsigned char)buf[byte]);
  144. printk("\n");
  145. }
  146. mutex_lock(&dev->ctrl_urb_lock);
  147. memcpy(dev->urb_buf, buf, len);
  148. ret = usb_control_msg(dev->udev, pipe, req,
  149. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  150. 0x0000, reg, dev->urb_buf, len, HZ);
  151. mutex_unlock(&dev->ctrl_urb_lock);
  152. if (ret < 0)
  153. return usb_translate_errors(ret);
  154. if (dev->wait_after_write)
  155. msleep(dev->wait_after_write);
  156. return ret;
  157. }
  158. int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
  159. {
  160. return em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
  161. }
  162. EXPORT_SYMBOL_GPL(em28xx_write_regs);
  163. /* Write a single register */
  164. int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
  165. {
  166. return em28xx_write_regs(dev, reg, &val, 1);
  167. }
  168. EXPORT_SYMBOL_GPL(em28xx_write_reg);
  169. /*
  170. * em28xx_write_reg_bits()
  171. * sets only some bits (specified by bitmask) of a register, by first reading
  172. * the actual value
  173. */
  174. int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
  175. u8 bitmask)
  176. {
  177. int oldval;
  178. u8 newval;
  179. oldval = em28xx_read_reg(dev, reg);
  180. if (oldval < 0)
  181. return oldval;
  182. newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
  183. return em28xx_write_regs(dev, reg, &newval, 1);
  184. }
  185. EXPORT_SYMBOL_GPL(em28xx_write_reg_bits);
  186. /*
  187. * em28xx_toggle_reg_bits()
  188. * toggles/inverts the bits (specified by bitmask) of a register
  189. */
  190. int em28xx_toggle_reg_bits(struct em28xx *dev, u16 reg, u8 bitmask)
  191. {
  192. int oldval;
  193. u8 newval;
  194. oldval = em28xx_read_reg(dev, reg);
  195. if (oldval < 0)
  196. return oldval;
  197. newval = (~oldval & bitmask) | (oldval & ~bitmask);
  198. return em28xx_write_reg(dev, reg, newval);
  199. }
  200. EXPORT_SYMBOL_GPL(em28xx_toggle_reg_bits);
  201. /*
  202. * em28xx_is_ac97_ready()
  203. * Checks if ac97 is ready
  204. */
  205. static int em28xx_is_ac97_ready(struct em28xx *dev)
  206. {
  207. unsigned long timeout = jiffies + msecs_to_jiffies(EM28XX_AC97_XFER_TIMEOUT);
  208. int ret;
  209. /* Wait up to 50 ms for AC97 command to complete */
  210. while (time_is_after_jiffies(timeout)) {
  211. ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
  212. if (ret < 0)
  213. return ret;
  214. if (!(ret & 0x01))
  215. return 0;
  216. msleep(5);
  217. }
  218. em28xx_warn("AC97 command still being executed: not handled properly!\n");
  219. return -EBUSY;
  220. }
  221. /*
  222. * em28xx_read_ac97()
  223. * write a 16 bit value to the specified AC97 address (LSB first!)
  224. */
  225. int em28xx_read_ac97(struct em28xx *dev, u8 reg)
  226. {
  227. int ret;
  228. u8 addr = (reg & 0x7f) | 0x80;
  229. u16 val;
  230. ret = em28xx_is_ac97_ready(dev);
  231. if (ret < 0)
  232. return ret;
  233. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  234. if (ret < 0)
  235. return ret;
  236. ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
  237. (u8 *)&val, sizeof(val));
  238. if (ret < 0)
  239. return ret;
  240. return le16_to_cpu(val);
  241. }
  242. EXPORT_SYMBOL_GPL(em28xx_read_ac97);
  243. /*
  244. * em28xx_write_ac97()
  245. * write a 16 bit value to the specified AC97 address (LSB first!)
  246. */
  247. int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
  248. {
  249. int ret;
  250. u8 addr = reg & 0x7f;
  251. __le16 value;
  252. value = cpu_to_le16(val);
  253. ret = em28xx_is_ac97_ready(dev);
  254. if (ret < 0)
  255. return ret;
  256. ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
  257. if (ret < 0)
  258. return ret;
  259. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  260. if (ret < 0)
  261. return ret;
  262. return 0;
  263. }
  264. EXPORT_SYMBOL_GPL(em28xx_write_ac97);
  265. struct em28xx_vol_itable {
  266. enum em28xx_amux mux;
  267. u8 reg;
  268. };
  269. static struct em28xx_vol_itable inputs[] = {
  270. { EM28XX_AMUX_VIDEO, AC97_VIDEO },
  271. { EM28XX_AMUX_LINE_IN, AC97_LINE },
  272. { EM28XX_AMUX_PHONE, AC97_PHONE },
  273. { EM28XX_AMUX_MIC, AC97_MIC },
  274. { EM28XX_AMUX_CD, AC97_CD },
  275. { EM28XX_AMUX_AUX, AC97_AUX },
  276. { EM28XX_AMUX_PCM_OUT, AC97_PCM },
  277. };
  278. static int set_ac97_input(struct em28xx *dev)
  279. {
  280. int ret, i;
  281. enum em28xx_amux amux = dev->ctl_ainput;
  282. /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
  283. em28xx should point to LINE IN, while AC97 should use VIDEO
  284. */
  285. if (amux == EM28XX_AMUX_VIDEO2)
  286. amux = EM28XX_AMUX_VIDEO;
  287. /* Mute all entres but the one that were selected */
  288. for (i = 0; i < ARRAY_SIZE(inputs); i++) {
  289. if (amux == inputs[i].mux)
  290. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
  291. else
  292. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
  293. if (ret < 0)
  294. em28xx_warn("couldn't setup AC97 register %d\n",
  295. inputs[i].reg);
  296. }
  297. return 0;
  298. }
  299. static int em28xx_set_audio_source(struct em28xx *dev)
  300. {
  301. int ret;
  302. u8 input;
  303. if (dev->board.is_em2800) {
  304. if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
  305. input = EM2800_AUDIO_SRC_TUNER;
  306. else
  307. input = EM2800_AUDIO_SRC_LINE;
  308. ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
  309. if (ret < 0)
  310. return ret;
  311. }
  312. if (dev->board.has_msp34xx)
  313. input = EM28XX_AUDIO_SRC_TUNER;
  314. else {
  315. switch (dev->ctl_ainput) {
  316. case EM28XX_AMUX_VIDEO:
  317. input = EM28XX_AUDIO_SRC_TUNER;
  318. break;
  319. default:
  320. input = EM28XX_AUDIO_SRC_LINE;
  321. break;
  322. }
  323. }
  324. if (dev->board.mute_gpio && dev->mute)
  325. em28xx_gpio_set(dev, dev->board.mute_gpio);
  326. else
  327. em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  328. ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
  329. if (ret < 0)
  330. return ret;
  331. msleep(5);
  332. switch (dev->audio_mode.ac97) {
  333. case EM28XX_NO_AC97:
  334. break;
  335. default:
  336. ret = set_ac97_input(dev);
  337. }
  338. return ret;
  339. }
  340. struct em28xx_vol_otable {
  341. enum em28xx_aout mux;
  342. u8 reg;
  343. };
  344. static const struct em28xx_vol_otable outputs[] = {
  345. { EM28XX_AOUT_MASTER, AC97_MASTER },
  346. { EM28XX_AOUT_LINE, AC97_HEADPHONE },
  347. { EM28XX_AOUT_MONO, AC97_MASTER_MONO },
  348. { EM28XX_AOUT_LFE, AC97_CENTER_LFE_MASTER },
  349. { EM28XX_AOUT_SURR, AC97_SURROUND_MASTER },
  350. };
  351. int em28xx_audio_analog_set(struct em28xx *dev)
  352. {
  353. int ret, i;
  354. u8 xclk;
  355. if (!dev->audio_mode.has_audio)
  356. return 0;
  357. /* It is assumed that all devices use master volume for output.
  358. It would be possible to use also line output.
  359. */
  360. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  361. /* Mute all outputs */
  362. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  363. ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
  364. if (ret < 0)
  365. em28xx_warn("couldn't setup AC97 register %d\n",
  366. outputs[i].reg);
  367. }
  368. }
  369. xclk = dev->board.xclk & 0x7f;
  370. if (!dev->mute)
  371. xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
  372. ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
  373. if (ret < 0)
  374. return ret;
  375. msleep(10);
  376. /* Selects the proper audio input */
  377. ret = em28xx_set_audio_source(dev);
  378. /* Sets volume */
  379. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  380. int vol;
  381. em28xx_write_ac97(dev, AC97_POWERDOWN, 0x4200);
  382. em28xx_write_ac97(dev, AC97_EXTENDED_STATUS, 0x0031);
  383. em28xx_write_ac97(dev, AC97_PCM_LR_ADC_RATE, 0xbb80);
  384. /* LSB: left channel - both channels with the same level */
  385. vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
  386. /* Mute device, if needed */
  387. if (dev->mute)
  388. vol |= 0x8000;
  389. /* Sets volume */
  390. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  391. if (dev->ctl_aoutput & outputs[i].mux)
  392. ret = em28xx_write_ac97(dev, outputs[i].reg,
  393. vol);
  394. if (ret < 0)
  395. em28xx_warn("couldn't setup AC97 register %d\n",
  396. outputs[i].reg);
  397. }
  398. if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
  399. int sel = ac97_return_record_select(dev->ctl_aoutput);
  400. /* Use the same input for both left and right
  401. channels */
  402. sel |= (sel << 8);
  403. em28xx_write_ac97(dev, AC97_REC_SEL, sel);
  404. }
  405. }
  406. return ret;
  407. }
  408. EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
  409. int em28xx_audio_setup(struct em28xx *dev)
  410. {
  411. int vid1, vid2, feat, cfg;
  412. u32 vid;
  413. if (!dev->audio_mode.has_audio)
  414. return 0;
  415. /* See how this device is configured */
  416. cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
  417. em28xx_info("Config register raw data: 0x%02x\n", cfg);
  418. if (cfg < 0) {
  419. /* Register read error? */
  420. cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
  421. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
  422. /* The device doesn't have vendor audio at all */
  423. dev->has_alsa_audio = false;
  424. dev->audio_mode.has_audio = false;
  425. return 0;
  426. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
  427. if (dev->chip_id < CHIP_ID_EM2860 &&
  428. (cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  429. EM2820_CHIPCFG_I2S_1_SAMPRATE)
  430. dev->audio_mode.i2s_samplerates = 1;
  431. else if (dev->chip_id >= CHIP_ID_EM2860 &&
  432. (cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  433. EM2860_CHIPCFG_I2S_5_SAMPRATES)
  434. dev->audio_mode.i2s_samplerates = 5;
  435. else
  436. dev->audio_mode.i2s_samplerates = 3;
  437. em28xx_info("I2S Audio (%d sample rate(s))\n",
  438. dev->audio_mode.i2s_samplerates);
  439. /* Skip the code that does AC97 vendor detection */
  440. dev->audio_mode.ac97 = EM28XX_NO_AC97;
  441. goto init_audio;
  442. }
  443. dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
  444. vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
  445. if (vid1 < 0) {
  446. /*
  447. * Device likely doesn't support AC97
  448. * Note: (some) em2800 devices without eeprom reports 0x91 on
  449. * CHIPCFG register, even not having an AC97 chip
  450. */
  451. em28xx_warn("AC97 chip type couldn't be determined\n");
  452. dev->audio_mode.ac97 = EM28XX_NO_AC97;
  453. dev->has_alsa_audio = false;
  454. dev->audio_mode.has_audio = false;
  455. goto init_audio;
  456. }
  457. vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
  458. if (vid2 < 0)
  459. goto init_audio;
  460. vid = vid1 << 16 | vid2;
  461. dev->audio_mode.ac97_vendor_id = vid;
  462. em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
  463. feat = em28xx_read_ac97(dev, AC97_RESET);
  464. if (feat < 0)
  465. goto init_audio;
  466. dev->audio_mode.ac97_feat = feat;
  467. em28xx_warn("AC97 features = 0x%04x\n", feat);
  468. /* Try to identify what audio processor we have */
  469. if (((vid == 0xffffffff) || (vid == 0x83847650)) && (feat == 0x6a90))
  470. dev->audio_mode.ac97 = EM28XX_AC97_EM202;
  471. else if ((vid >> 8) == 0x838476)
  472. dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
  473. init_audio:
  474. /* Reports detected AC97 processor */
  475. switch (dev->audio_mode.ac97) {
  476. case EM28XX_NO_AC97:
  477. em28xx_info("No AC97 audio processor\n");
  478. break;
  479. case EM28XX_AC97_EM202:
  480. em28xx_info("Empia 202 AC97 audio processor detected\n");
  481. break;
  482. case EM28XX_AC97_SIGMATEL:
  483. em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
  484. dev->audio_mode.ac97_vendor_id & 0xff);
  485. break;
  486. case EM28XX_AC97_OTHER:
  487. em28xx_warn("Unknown AC97 audio processor detected!\n");
  488. break;
  489. default:
  490. break;
  491. }
  492. return em28xx_audio_analog_set(dev);
  493. }
  494. EXPORT_SYMBOL_GPL(em28xx_audio_setup);
  495. const struct em28xx_led *em28xx_find_led(struct em28xx *dev,
  496. enum em28xx_led_role role)
  497. {
  498. if (dev->board.leds) {
  499. u8 k = 0;
  500. while (dev->board.leds[k].role >= 0 &&
  501. dev->board.leds[k].role < EM28XX_NUM_LED_ROLES) {
  502. if (dev->board.leds[k].role == role)
  503. return &dev->board.leds[k];
  504. k++;
  505. }
  506. }
  507. return NULL;
  508. }
  509. EXPORT_SYMBOL_GPL(em28xx_find_led);
  510. int em28xx_capture_start(struct em28xx *dev, int start)
  511. {
  512. int rc;
  513. const struct em28xx_led *led = NULL;
  514. if (dev->chip_id == CHIP_ID_EM2874 ||
  515. dev->chip_id == CHIP_ID_EM2884 ||
  516. dev->chip_id == CHIP_ID_EM28174 ||
  517. dev->chip_id == CHIP_ID_EM28178) {
  518. /* The Transport Stream Enable Register moved in em2874 */
  519. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  520. start ?
  521. EM2874_TS1_CAPTURE_ENABLE : 0x00,
  522. EM2874_TS1_CAPTURE_ENABLE);
  523. } else {
  524. /* FIXME: which is the best order? */
  525. /* video registers are sampled by VREF */
  526. rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
  527. start ? 0x10 : 0x00, 0x10);
  528. if (rc < 0)
  529. return rc;
  530. if (start) {
  531. if (dev->board.is_webcam)
  532. rc = em28xx_write_reg(dev, 0x13, 0x0c);
  533. /* Enable video capture */
  534. rc = em28xx_write_reg(dev, 0x48, 0x00);
  535. if (rc < 0)
  536. return rc;
  537. if (dev->mode == EM28XX_ANALOG_MODE)
  538. rc = em28xx_write_reg(dev,
  539. EM28XX_R12_VINENABLE, 0x67);
  540. else
  541. rc = em28xx_write_reg(dev,
  542. EM28XX_R12_VINENABLE, 0x37);
  543. if (rc < 0)
  544. return rc;
  545. msleep(6);
  546. } else {
  547. /* disable video capture */
  548. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
  549. }
  550. }
  551. if (dev->mode == EM28XX_ANALOG_MODE)
  552. led = em28xx_find_led(dev, EM28XX_LED_ANALOG_CAPTURING);
  553. else
  554. led = em28xx_find_led(dev, EM28XX_LED_DIGITAL_CAPTURING);
  555. if (led)
  556. em28xx_write_reg_bits(dev, led->gpio_reg,
  557. (!start ^ led->inverted) ?
  558. ~led->gpio_mask : led->gpio_mask,
  559. led->gpio_mask);
  560. return rc;
  561. }
  562. int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
  563. {
  564. int rc = 0;
  565. if (!gpio)
  566. return rc;
  567. if (dev->mode != EM28XX_SUSPEND) {
  568. em28xx_write_reg(dev, 0x48, 0x00);
  569. if (dev->mode == EM28XX_ANALOG_MODE)
  570. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
  571. else
  572. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
  573. msleep(6);
  574. }
  575. /* Send GPIO reset sequences specified at board entry */
  576. while (gpio->sleep >= 0) {
  577. if (gpio->reg >= 0) {
  578. rc = em28xx_write_reg_bits(dev,
  579. gpio->reg,
  580. gpio->val,
  581. gpio->mask);
  582. if (rc < 0)
  583. return rc;
  584. }
  585. if (gpio->sleep > 0)
  586. msleep(gpio->sleep);
  587. gpio++;
  588. }
  589. return rc;
  590. }
  591. EXPORT_SYMBOL_GPL(em28xx_gpio_set);
  592. int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
  593. {
  594. if (dev->mode == set_mode)
  595. return 0;
  596. if (set_mode == EM28XX_SUSPEND) {
  597. dev->mode = set_mode;
  598. /* FIXME: add suspend support for ac97 */
  599. return em28xx_gpio_set(dev, dev->board.suspend_gpio);
  600. }
  601. dev->mode = set_mode;
  602. if (dev->mode == EM28XX_DIGITAL_MODE)
  603. return em28xx_gpio_set(dev, dev->board.dvb_gpio);
  604. else
  605. return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  606. }
  607. EXPORT_SYMBOL_GPL(em28xx_set_mode);
  608. /* ------------------------------------------------------------------
  609. URB control
  610. ------------------------------------------------------------------*/
  611. /*
  612. * URB completion handler for isoc/bulk transfers
  613. */
  614. static void em28xx_irq_callback(struct urb *urb)
  615. {
  616. struct em28xx *dev = urb->context;
  617. int i;
  618. switch (urb->status) {
  619. case 0: /* success */
  620. case -ETIMEDOUT: /* NAK */
  621. break;
  622. case -ECONNRESET: /* kill */
  623. case -ENOENT:
  624. case -ESHUTDOWN:
  625. return;
  626. default: /* error */
  627. em28xx_isocdbg("urb completition error %d.\n", urb->status);
  628. break;
  629. }
  630. /* Copy data from URB */
  631. spin_lock(&dev->slock);
  632. dev->usb_ctl.urb_data_copy(dev, urb);
  633. spin_unlock(&dev->slock);
  634. /* Reset urb buffers */
  635. for (i = 0; i < urb->number_of_packets; i++) {
  636. /* isoc only (bulk: number_of_packets = 0) */
  637. urb->iso_frame_desc[i].status = 0;
  638. urb->iso_frame_desc[i].actual_length = 0;
  639. }
  640. urb->status = 0;
  641. urb->status = usb_submit_urb(urb, GFP_ATOMIC);
  642. if (urb->status) {
  643. em28xx_isocdbg("urb resubmit failed (error=%i)\n",
  644. urb->status);
  645. }
  646. }
  647. /*
  648. * Stop and Deallocate URBs
  649. */
  650. void em28xx_uninit_usb_xfer(struct em28xx *dev, enum em28xx_mode mode)
  651. {
  652. struct urb *urb;
  653. struct em28xx_usb_bufs *usb_bufs;
  654. int i;
  655. em28xx_isocdbg("em28xx: called em28xx_uninit_usb_xfer in mode %d\n",
  656. mode);
  657. if (mode == EM28XX_DIGITAL_MODE)
  658. usb_bufs = &dev->usb_ctl.digital_bufs;
  659. else
  660. usb_bufs = &dev->usb_ctl.analog_bufs;
  661. for (i = 0; i < usb_bufs->num_bufs; i++) {
  662. urb = usb_bufs->urb[i];
  663. if (urb) {
  664. if (!irqs_disabled())
  665. usb_kill_urb(urb);
  666. else
  667. usb_unlink_urb(urb);
  668. if (usb_bufs->transfer_buffer[i]) {
  669. usb_free_coherent(dev->udev,
  670. urb->transfer_buffer_length,
  671. usb_bufs->transfer_buffer[i],
  672. urb->transfer_dma);
  673. }
  674. usb_free_urb(urb);
  675. usb_bufs->urb[i] = NULL;
  676. }
  677. usb_bufs->transfer_buffer[i] = NULL;
  678. }
  679. kfree(usb_bufs->urb);
  680. kfree(usb_bufs->transfer_buffer);
  681. usb_bufs->urb = NULL;
  682. usb_bufs->transfer_buffer = NULL;
  683. usb_bufs->num_bufs = 0;
  684. em28xx_capture_start(dev, 0);
  685. }
  686. EXPORT_SYMBOL_GPL(em28xx_uninit_usb_xfer);
  687. /*
  688. * Stop URBs
  689. */
  690. void em28xx_stop_urbs(struct em28xx *dev)
  691. {
  692. int i;
  693. struct urb *urb;
  694. struct em28xx_usb_bufs *isoc_bufs = &dev->usb_ctl.digital_bufs;
  695. em28xx_isocdbg("em28xx: called em28xx_stop_urbs\n");
  696. for (i = 0; i < isoc_bufs->num_bufs; i++) {
  697. urb = isoc_bufs->urb[i];
  698. if (urb) {
  699. if (!irqs_disabled())
  700. usb_kill_urb(urb);
  701. else
  702. usb_unlink_urb(urb);
  703. }
  704. }
  705. em28xx_capture_start(dev, 0);
  706. }
  707. EXPORT_SYMBOL_GPL(em28xx_stop_urbs);
  708. /*
  709. * Allocate URBs
  710. */
  711. int em28xx_alloc_urbs(struct em28xx *dev, enum em28xx_mode mode, int xfer_bulk,
  712. int num_bufs, int max_pkt_size, int packet_multiplier)
  713. {
  714. struct em28xx_usb_bufs *usb_bufs;
  715. int i;
  716. int sb_size, pipe;
  717. struct urb *urb;
  718. int j, k;
  719. em28xx_isocdbg("em28xx: called em28xx_alloc_isoc in mode %d\n", mode);
  720. /* Check mode and if we have an endpoint for the selected
  721. transfer type, select buffer */
  722. if (mode == EM28XX_DIGITAL_MODE) {
  723. if ((xfer_bulk && !dev->dvb_ep_bulk) ||
  724. (!xfer_bulk && !dev->dvb_ep_isoc)) {
  725. em28xx_errdev("no endpoint for DVB mode and transfer type %d\n",
  726. xfer_bulk > 0);
  727. return -EINVAL;
  728. }
  729. usb_bufs = &dev->usb_ctl.digital_bufs;
  730. } else if (mode == EM28XX_ANALOG_MODE) {
  731. if ((xfer_bulk && !dev->analog_ep_bulk) ||
  732. (!xfer_bulk && !dev->analog_ep_isoc)) {
  733. em28xx_errdev("no endpoint for analog mode and transfer type %d\n",
  734. xfer_bulk > 0);
  735. return -EINVAL;
  736. }
  737. usb_bufs = &dev->usb_ctl.analog_bufs;
  738. } else {
  739. em28xx_errdev("invalid mode selected\n");
  740. return -EINVAL;
  741. }
  742. /* De-allocates all pending stuff */
  743. em28xx_uninit_usb_xfer(dev, mode);
  744. usb_bufs->num_bufs = num_bufs;
  745. usb_bufs->urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
  746. if (!usb_bufs->urb) {
  747. em28xx_errdev("cannot alloc memory for usb buffers\n");
  748. return -ENOMEM;
  749. }
  750. usb_bufs->transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
  751. GFP_KERNEL);
  752. if (!usb_bufs->transfer_buffer) {
  753. em28xx_errdev("cannot allocate memory for usb transfer\n");
  754. kfree(usb_bufs->urb);
  755. return -ENOMEM;
  756. }
  757. usb_bufs->max_pkt_size = max_pkt_size;
  758. if (xfer_bulk)
  759. usb_bufs->num_packets = 0;
  760. else
  761. usb_bufs->num_packets = packet_multiplier;
  762. dev->usb_ctl.vid_buf = NULL;
  763. dev->usb_ctl.vbi_buf = NULL;
  764. sb_size = packet_multiplier * usb_bufs->max_pkt_size;
  765. /* allocate urbs and transfer buffers */
  766. for (i = 0; i < usb_bufs->num_bufs; i++) {
  767. urb = usb_alloc_urb(usb_bufs->num_packets, GFP_KERNEL);
  768. if (!urb) {
  769. em28xx_err("cannot alloc usb_ctl.urb %i\n", i);
  770. em28xx_uninit_usb_xfer(dev, mode);
  771. return -ENOMEM;
  772. }
  773. usb_bufs->urb[i] = urb;
  774. usb_bufs->transfer_buffer[i] = usb_alloc_coherent(dev->udev,
  775. sb_size, GFP_KERNEL, &urb->transfer_dma);
  776. if (!usb_bufs->transfer_buffer[i]) {
  777. em28xx_err("unable to allocate %i bytes for transfer"
  778. " buffer %i%s\n",
  779. sb_size, i,
  780. in_interrupt() ? " while in int" : "");
  781. em28xx_uninit_usb_xfer(dev, mode);
  782. return -ENOMEM;
  783. }
  784. memset(usb_bufs->transfer_buffer[i], 0, sb_size);
  785. if (xfer_bulk) { /* bulk */
  786. pipe = usb_rcvbulkpipe(dev->udev,
  787. mode == EM28XX_ANALOG_MODE ?
  788. dev->analog_ep_bulk :
  789. dev->dvb_ep_bulk);
  790. usb_fill_bulk_urb(urb, dev->udev, pipe,
  791. usb_bufs->transfer_buffer[i], sb_size,
  792. em28xx_irq_callback, dev);
  793. urb->transfer_flags = URB_NO_TRANSFER_DMA_MAP;
  794. } else { /* isoc */
  795. pipe = usb_rcvisocpipe(dev->udev,
  796. mode == EM28XX_ANALOG_MODE ?
  797. dev->analog_ep_isoc :
  798. dev->dvb_ep_isoc);
  799. usb_fill_int_urb(urb, dev->udev, pipe,
  800. usb_bufs->transfer_buffer[i], sb_size,
  801. em28xx_irq_callback, dev, 1);
  802. urb->transfer_flags = URB_ISO_ASAP |
  803. URB_NO_TRANSFER_DMA_MAP;
  804. k = 0;
  805. for (j = 0; j < usb_bufs->num_packets; j++) {
  806. urb->iso_frame_desc[j].offset = k;
  807. urb->iso_frame_desc[j].length =
  808. usb_bufs->max_pkt_size;
  809. k += usb_bufs->max_pkt_size;
  810. }
  811. }
  812. urb->number_of_packets = usb_bufs->num_packets;
  813. }
  814. return 0;
  815. }
  816. EXPORT_SYMBOL_GPL(em28xx_alloc_urbs);
  817. /*
  818. * Allocate URBs and start IRQ
  819. */
  820. int em28xx_init_usb_xfer(struct em28xx *dev, enum em28xx_mode mode,
  821. int xfer_bulk, int num_bufs, int max_pkt_size,
  822. int packet_multiplier,
  823. int (*urb_data_copy) (struct em28xx *dev, struct urb *urb))
  824. {
  825. struct em28xx_dmaqueue *dma_q = &dev->vidq;
  826. struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq;
  827. struct em28xx_usb_bufs *usb_bufs;
  828. int i;
  829. int rc;
  830. int alloc;
  831. em28xx_isocdbg("em28xx: called em28xx_init_usb_xfer in mode %d\n",
  832. mode);
  833. dev->usb_ctl.urb_data_copy = urb_data_copy;
  834. if (mode == EM28XX_DIGITAL_MODE) {
  835. usb_bufs = &dev->usb_ctl.digital_bufs;
  836. /* no need to free/alloc usb buffers in digital mode */
  837. alloc = 0;
  838. } else {
  839. usb_bufs = &dev->usb_ctl.analog_bufs;
  840. alloc = 1;
  841. }
  842. if (alloc) {
  843. rc = em28xx_alloc_urbs(dev, mode, xfer_bulk, num_bufs,
  844. max_pkt_size, packet_multiplier);
  845. if (rc)
  846. return rc;
  847. }
  848. if (xfer_bulk) {
  849. rc = usb_clear_halt(dev->udev, usb_bufs->urb[0]->pipe);
  850. if (rc < 0) {
  851. em28xx_err("failed to clear USB bulk endpoint stall/halt condition (error=%i)\n",
  852. rc);
  853. em28xx_uninit_usb_xfer(dev, mode);
  854. return rc;
  855. }
  856. }
  857. init_waitqueue_head(&dma_q->wq);
  858. init_waitqueue_head(&vbi_dma_q->wq);
  859. em28xx_capture_start(dev, 1);
  860. /* submit urbs and enables IRQ */
  861. for (i = 0; i < usb_bufs->num_bufs; i++) {
  862. rc = usb_submit_urb(usb_bufs->urb[i], GFP_ATOMIC);
  863. if (rc) {
  864. em28xx_err("submit of urb %i failed (error=%i)\n", i,
  865. rc);
  866. em28xx_uninit_usb_xfer(dev, mode);
  867. return rc;
  868. }
  869. }
  870. return 0;
  871. }
  872. EXPORT_SYMBOL_GPL(em28xx_init_usb_xfer);
  873. /*
  874. * Device control list
  875. */
  876. static LIST_HEAD(em28xx_devlist);
  877. static DEFINE_MUTEX(em28xx_devlist_mutex);
  878. /*
  879. * Extension interface
  880. */
  881. static LIST_HEAD(em28xx_extension_devlist);
  882. int em28xx_register_extension(struct em28xx_ops *ops)
  883. {
  884. struct em28xx *dev = NULL;
  885. mutex_lock(&em28xx_devlist_mutex);
  886. list_add_tail(&ops->next, &em28xx_extension_devlist);
  887. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  888. ops->init(dev);
  889. }
  890. mutex_unlock(&em28xx_devlist_mutex);
  891. printk(KERN_INFO "em28xx: Registered (%s) extension\n", ops->name);
  892. return 0;
  893. }
  894. EXPORT_SYMBOL(em28xx_register_extension);
  895. void em28xx_unregister_extension(struct em28xx_ops *ops)
  896. {
  897. struct em28xx *dev = NULL;
  898. mutex_lock(&em28xx_devlist_mutex);
  899. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  900. ops->fini(dev);
  901. }
  902. list_del(&ops->next);
  903. mutex_unlock(&em28xx_devlist_mutex);
  904. printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
  905. }
  906. EXPORT_SYMBOL(em28xx_unregister_extension);
  907. void em28xx_init_extension(struct em28xx *dev)
  908. {
  909. const struct em28xx_ops *ops = NULL;
  910. mutex_lock(&em28xx_devlist_mutex);
  911. list_add_tail(&dev->devlist, &em28xx_devlist);
  912. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  913. if (ops->init)
  914. ops->init(dev);
  915. }
  916. mutex_unlock(&em28xx_devlist_mutex);
  917. }
  918. void em28xx_close_extension(struct em28xx *dev)
  919. {
  920. const struct em28xx_ops *ops = NULL;
  921. mutex_lock(&em28xx_devlist_mutex);
  922. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  923. if (ops->fini)
  924. ops->fini(dev);
  925. }
  926. list_del(&dev->devlist);
  927. mutex_unlock(&em28xx_devlist_mutex);
  928. }
  929. int em28xx_suspend_extension(struct em28xx *dev)
  930. {
  931. const struct em28xx_ops *ops = NULL;
  932. em28xx_info("Suspending extensions");
  933. mutex_lock(&em28xx_devlist_mutex);
  934. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  935. if (ops->suspend)
  936. ops->suspend(dev);
  937. }
  938. mutex_unlock(&em28xx_devlist_mutex);
  939. return 0;
  940. }
  941. int em28xx_resume_extension(struct em28xx *dev)
  942. {
  943. const struct em28xx_ops *ops = NULL;
  944. em28xx_info("Resuming extensions");
  945. mutex_lock(&em28xx_devlist_mutex);
  946. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  947. if (ops->resume)
  948. ops->resume(dev);
  949. }
  950. mutex_unlock(&em28xx_devlist_mutex);
  951. return 0;
  952. }