adv7604.c 88 KB

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  1. /*
  2. * adv7604 - Analog Devices ADV7604 video decoder driver
  3. *
  4. * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
  5. *
  6. * This program is free software; you may redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; version 2 of the License.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17. * SOFTWARE.
  18. *
  19. */
  20. /*
  21. * References (c = chapter, p = page):
  22. * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
  23. * Revision 2.5, June 2010
  24. * REF_02 - Analog devices, Register map documentation, Documentation of
  25. * the register maps, Software manual, Rev. F, June 2010
  26. * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
  27. */
  28. #include <linux/delay.h>
  29. #include <linux/gpio/consumer.h>
  30. #include <linux/i2c.h>
  31. #include <linux/kernel.h>
  32. #include <linux/module.h>
  33. #include <linux/slab.h>
  34. #include <linux/v4l2-dv-timings.h>
  35. #include <linux/videodev2.h>
  36. #include <linux/workqueue.h>
  37. #include <media/adv7604.h>
  38. #include <media/v4l2-ctrls.h>
  39. #include <media/v4l2-device.h>
  40. #include <media/v4l2-dv-timings.h>
  41. #include <media/v4l2-of.h>
  42. static int debug;
  43. module_param(debug, int, 0644);
  44. MODULE_PARM_DESC(debug, "debug level (0-2)");
  45. MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
  46. MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  47. MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  48. MODULE_LICENSE("GPL");
  49. /* ADV7604 system clock frequency */
  50. #define ADV7604_fsc (28636360)
  51. #define ADV7604_RGB_OUT (1 << 1)
  52. #define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0)
  53. #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
  54. #define ADV7604_OP_FORMAT_SEL_12BIT (2 << 0)
  55. #define ADV7604_OP_MODE_SEL_SDR_422 (0 << 5)
  56. #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
  57. #define ADV7604_OP_MODE_SEL_SDR_444 (2 << 5)
  58. #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
  59. #define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5)
  60. #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
  61. #define ADV7604_OP_CH_SEL_GBR (0 << 5)
  62. #define ADV7604_OP_CH_SEL_GRB (1 << 5)
  63. #define ADV7604_OP_CH_SEL_BGR (2 << 5)
  64. #define ADV7604_OP_CH_SEL_RGB (3 << 5)
  65. #define ADV7604_OP_CH_SEL_BRG (4 << 5)
  66. #define ADV7604_OP_CH_SEL_RBG (5 << 5)
  67. #define ADV7604_OP_SWAP_CB_CR (1 << 0)
  68. enum adv7604_type {
  69. ADV7604,
  70. ADV7611,
  71. };
  72. struct adv7604_reg_seq {
  73. unsigned int reg;
  74. u8 val;
  75. };
  76. struct adv7604_format_info {
  77. enum v4l2_mbus_pixelcode code;
  78. u8 op_ch_sel;
  79. bool rgb_out;
  80. bool swap_cb_cr;
  81. u8 op_format_sel;
  82. };
  83. struct adv7604_chip_info {
  84. enum adv7604_type type;
  85. bool has_afe;
  86. unsigned int max_port;
  87. unsigned int num_dv_ports;
  88. unsigned int edid_enable_reg;
  89. unsigned int edid_status_reg;
  90. unsigned int lcf_reg;
  91. unsigned int cable_det_mask;
  92. unsigned int tdms_lock_mask;
  93. unsigned int fmt_change_digital_mask;
  94. const struct adv7604_format_info *formats;
  95. unsigned int nformats;
  96. void (*set_termination)(struct v4l2_subdev *sd, bool enable);
  97. void (*setup_irqs)(struct v4l2_subdev *sd);
  98. unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
  99. unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
  100. /* 0 = AFE, 1 = HDMI */
  101. const struct adv7604_reg_seq *recommended_settings[2];
  102. unsigned int num_recommended_settings[2];
  103. unsigned long page_mask;
  104. };
  105. /*
  106. **********************************************************************
  107. *
  108. * Arrays with configuration parameters for the ADV7604
  109. *
  110. **********************************************************************
  111. */
  112. struct adv7604_state {
  113. const struct adv7604_chip_info *info;
  114. struct adv7604_platform_data pdata;
  115. struct gpio_desc *hpd_gpio[4];
  116. struct v4l2_subdev sd;
  117. struct media_pad pads[ADV7604_PAD_MAX];
  118. unsigned int source_pad;
  119. struct v4l2_ctrl_handler hdl;
  120. enum adv7604_pad selected_input;
  121. struct v4l2_dv_timings timings;
  122. const struct adv7604_format_info *format;
  123. struct {
  124. u8 edid[256];
  125. u32 present;
  126. unsigned blocks;
  127. } edid;
  128. u16 spa_port_a[2];
  129. struct v4l2_fract aspect_ratio;
  130. u32 rgb_quantization_range;
  131. struct workqueue_struct *work_queues;
  132. struct delayed_work delayed_work_enable_hotplug;
  133. bool restart_stdi_once;
  134. /* i2c clients */
  135. struct i2c_client *i2c_clients[ADV7604_PAGE_MAX];
  136. /* controls */
  137. struct v4l2_ctrl *detect_tx_5v_ctrl;
  138. struct v4l2_ctrl *analog_sampling_phase_ctrl;
  139. struct v4l2_ctrl *free_run_color_manual_ctrl;
  140. struct v4l2_ctrl *free_run_color_ctrl;
  141. struct v4l2_ctrl *rgb_quantization_range_ctrl;
  142. };
  143. static bool adv7604_has_afe(struct adv7604_state *state)
  144. {
  145. return state->info->has_afe;
  146. }
  147. /* Supported CEA and DMT timings */
  148. static const struct v4l2_dv_timings adv7604_timings[] = {
  149. V4L2_DV_BT_CEA_720X480P59_94,
  150. V4L2_DV_BT_CEA_720X576P50,
  151. V4L2_DV_BT_CEA_1280X720P24,
  152. V4L2_DV_BT_CEA_1280X720P25,
  153. V4L2_DV_BT_CEA_1280X720P50,
  154. V4L2_DV_BT_CEA_1280X720P60,
  155. V4L2_DV_BT_CEA_1920X1080P24,
  156. V4L2_DV_BT_CEA_1920X1080P25,
  157. V4L2_DV_BT_CEA_1920X1080P30,
  158. V4L2_DV_BT_CEA_1920X1080P50,
  159. V4L2_DV_BT_CEA_1920X1080P60,
  160. /* sorted by DMT ID */
  161. V4L2_DV_BT_DMT_640X350P85,
  162. V4L2_DV_BT_DMT_640X400P85,
  163. V4L2_DV_BT_DMT_720X400P85,
  164. V4L2_DV_BT_DMT_640X480P60,
  165. V4L2_DV_BT_DMT_640X480P72,
  166. V4L2_DV_BT_DMT_640X480P75,
  167. V4L2_DV_BT_DMT_640X480P85,
  168. V4L2_DV_BT_DMT_800X600P56,
  169. V4L2_DV_BT_DMT_800X600P60,
  170. V4L2_DV_BT_DMT_800X600P72,
  171. V4L2_DV_BT_DMT_800X600P75,
  172. V4L2_DV_BT_DMT_800X600P85,
  173. V4L2_DV_BT_DMT_848X480P60,
  174. V4L2_DV_BT_DMT_1024X768P60,
  175. V4L2_DV_BT_DMT_1024X768P70,
  176. V4L2_DV_BT_DMT_1024X768P75,
  177. V4L2_DV_BT_DMT_1024X768P85,
  178. V4L2_DV_BT_DMT_1152X864P75,
  179. V4L2_DV_BT_DMT_1280X768P60_RB,
  180. V4L2_DV_BT_DMT_1280X768P60,
  181. V4L2_DV_BT_DMT_1280X768P75,
  182. V4L2_DV_BT_DMT_1280X768P85,
  183. V4L2_DV_BT_DMT_1280X800P60_RB,
  184. V4L2_DV_BT_DMT_1280X800P60,
  185. V4L2_DV_BT_DMT_1280X800P75,
  186. V4L2_DV_BT_DMT_1280X800P85,
  187. V4L2_DV_BT_DMT_1280X960P60,
  188. V4L2_DV_BT_DMT_1280X960P85,
  189. V4L2_DV_BT_DMT_1280X1024P60,
  190. V4L2_DV_BT_DMT_1280X1024P75,
  191. V4L2_DV_BT_DMT_1280X1024P85,
  192. V4L2_DV_BT_DMT_1360X768P60,
  193. V4L2_DV_BT_DMT_1400X1050P60_RB,
  194. V4L2_DV_BT_DMT_1400X1050P60,
  195. V4L2_DV_BT_DMT_1400X1050P75,
  196. V4L2_DV_BT_DMT_1400X1050P85,
  197. V4L2_DV_BT_DMT_1440X900P60_RB,
  198. V4L2_DV_BT_DMT_1440X900P60,
  199. V4L2_DV_BT_DMT_1600X1200P60,
  200. V4L2_DV_BT_DMT_1680X1050P60_RB,
  201. V4L2_DV_BT_DMT_1680X1050P60,
  202. V4L2_DV_BT_DMT_1792X1344P60,
  203. V4L2_DV_BT_DMT_1856X1392P60,
  204. V4L2_DV_BT_DMT_1920X1200P60_RB,
  205. V4L2_DV_BT_DMT_1366X768P60_RB,
  206. V4L2_DV_BT_DMT_1366X768P60,
  207. V4L2_DV_BT_DMT_1920X1080P60,
  208. { },
  209. };
  210. struct adv7604_video_standards {
  211. struct v4l2_dv_timings timings;
  212. u8 vid_std;
  213. u8 v_freq;
  214. };
  215. /* sorted by number of lines */
  216. static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
  217. /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
  218. { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
  219. { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
  220. { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
  221. { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
  222. { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
  223. { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
  224. { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
  225. { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
  226. /* TODO add 1920x1080P60_RB (CVT timing) */
  227. { },
  228. };
  229. /* sorted by number of lines */
  230. static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
  231. { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
  232. { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
  233. { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
  234. { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
  235. { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
  236. { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
  237. { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
  238. { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
  239. { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
  240. { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
  241. { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
  242. { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
  243. { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
  244. { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
  245. { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
  246. { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
  247. { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
  248. { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
  249. { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
  250. { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
  251. /* TODO add 1600X1200P60_RB (not a DMT timing) */
  252. { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
  253. { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
  254. { },
  255. };
  256. /* sorted by number of lines */
  257. static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
  258. { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
  259. { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
  260. { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
  261. { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
  262. { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
  263. { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
  264. { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
  265. { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
  266. { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
  267. { },
  268. };
  269. /* sorted by number of lines */
  270. static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
  271. { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
  272. { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
  273. { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
  274. { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
  275. { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
  276. { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
  277. { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
  278. { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
  279. { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
  280. { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
  281. { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
  282. { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
  283. { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
  284. { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
  285. { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
  286. { },
  287. };
  288. /* ----------------------------------------------------------------------- */
  289. static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
  290. {
  291. return container_of(sd, struct adv7604_state, sd);
  292. }
  293. static inline unsigned hblanking(const struct v4l2_bt_timings *t)
  294. {
  295. return V4L2_DV_BT_BLANKING_WIDTH(t);
  296. }
  297. static inline unsigned htotal(const struct v4l2_bt_timings *t)
  298. {
  299. return V4L2_DV_BT_FRAME_WIDTH(t);
  300. }
  301. static inline unsigned vblanking(const struct v4l2_bt_timings *t)
  302. {
  303. return V4L2_DV_BT_BLANKING_HEIGHT(t);
  304. }
  305. static inline unsigned vtotal(const struct v4l2_bt_timings *t)
  306. {
  307. return V4L2_DV_BT_FRAME_HEIGHT(t);
  308. }
  309. /* ----------------------------------------------------------------------- */
  310. static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
  311. u8 command, bool check)
  312. {
  313. union i2c_smbus_data data;
  314. if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
  315. I2C_SMBUS_READ, command,
  316. I2C_SMBUS_BYTE_DATA, &data))
  317. return data.byte;
  318. if (check)
  319. v4l_err(client, "error reading %02x, %02x\n",
  320. client->addr, command);
  321. return -EIO;
  322. }
  323. static s32 adv_smbus_read_byte_data(struct adv7604_state *state,
  324. enum adv7604_page page, u8 command)
  325. {
  326. return adv_smbus_read_byte_data_check(state->i2c_clients[page],
  327. command, true);
  328. }
  329. static s32 adv_smbus_write_byte_data(struct adv7604_state *state,
  330. enum adv7604_page page, u8 command,
  331. u8 value)
  332. {
  333. struct i2c_client *client = state->i2c_clients[page];
  334. union i2c_smbus_data data;
  335. int err;
  336. int i;
  337. data.byte = value;
  338. for (i = 0; i < 3; i++) {
  339. err = i2c_smbus_xfer(client->adapter, client->addr,
  340. client->flags,
  341. I2C_SMBUS_WRITE, command,
  342. I2C_SMBUS_BYTE_DATA, &data);
  343. if (!err)
  344. break;
  345. }
  346. if (err < 0)
  347. v4l_err(client, "error writing %02x, %02x, %02x\n",
  348. client->addr, command, value);
  349. return err;
  350. }
  351. static s32 adv_smbus_write_i2c_block_data(struct adv7604_state *state,
  352. enum adv7604_page page, u8 command,
  353. unsigned length, const u8 *values)
  354. {
  355. struct i2c_client *client = state->i2c_clients[page];
  356. union i2c_smbus_data data;
  357. if (length > I2C_SMBUS_BLOCK_MAX)
  358. length = I2C_SMBUS_BLOCK_MAX;
  359. data.block[0] = length;
  360. memcpy(data.block + 1, values, length);
  361. return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
  362. I2C_SMBUS_WRITE, command,
  363. I2C_SMBUS_I2C_BLOCK_DATA, &data);
  364. }
  365. /* ----------------------------------------------------------------------- */
  366. static inline int io_read(struct v4l2_subdev *sd, u8 reg)
  367. {
  368. struct adv7604_state *state = to_state(sd);
  369. return adv_smbus_read_byte_data(state, ADV7604_PAGE_IO, reg);
  370. }
  371. static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  372. {
  373. struct adv7604_state *state = to_state(sd);
  374. return adv_smbus_write_byte_data(state, ADV7604_PAGE_IO, reg, val);
  375. }
  376. static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
  377. {
  378. return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
  379. }
  380. static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
  381. {
  382. struct adv7604_state *state = to_state(sd);
  383. return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg);
  384. }
  385. static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  386. {
  387. struct adv7604_state *state = to_state(sd);
  388. return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val);
  389. }
  390. static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
  391. {
  392. struct adv7604_state *state = to_state(sd);
  393. return adv_smbus_read_byte_data(state, ADV7604_PAGE_CEC, reg);
  394. }
  395. static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  396. {
  397. struct adv7604_state *state = to_state(sd);
  398. return adv_smbus_write_byte_data(state, ADV7604_PAGE_CEC, reg, val);
  399. }
  400. static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
  401. {
  402. return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
  403. }
  404. static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
  405. {
  406. struct adv7604_state *state = to_state(sd);
  407. return adv_smbus_read_byte_data(state, ADV7604_PAGE_INFOFRAME, reg);
  408. }
  409. static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  410. {
  411. struct adv7604_state *state = to_state(sd);
  412. return adv_smbus_write_byte_data(state, ADV7604_PAGE_INFOFRAME,
  413. reg, val);
  414. }
  415. static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
  416. {
  417. struct adv7604_state *state = to_state(sd);
  418. return adv_smbus_read_byte_data(state, ADV7604_PAGE_ESDP, reg);
  419. }
  420. static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  421. {
  422. struct adv7604_state *state = to_state(sd);
  423. return adv_smbus_write_byte_data(state, ADV7604_PAGE_ESDP, reg, val);
  424. }
  425. static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
  426. {
  427. struct adv7604_state *state = to_state(sd);
  428. return adv_smbus_read_byte_data(state, ADV7604_PAGE_DPP, reg);
  429. }
  430. static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  431. {
  432. struct adv7604_state *state = to_state(sd);
  433. return adv_smbus_write_byte_data(state, ADV7604_PAGE_DPP, reg, val);
  434. }
  435. static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
  436. {
  437. struct adv7604_state *state = to_state(sd);
  438. return adv_smbus_read_byte_data(state, ADV7604_PAGE_AFE, reg);
  439. }
  440. static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  441. {
  442. struct adv7604_state *state = to_state(sd);
  443. return adv_smbus_write_byte_data(state, ADV7604_PAGE_AFE, reg, val);
  444. }
  445. static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
  446. {
  447. struct adv7604_state *state = to_state(sd);
  448. return adv_smbus_read_byte_data(state, ADV7604_PAGE_REP, reg);
  449. }
  450. static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  451. {
  452. struct adv7604_state *state = to_state(sd);
  453. return adv_smbus_write_byte_data(state, ADV7604_PAGE_REP, reg, val);
  454. }
  455. static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
  456. {
  457. return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
  458. }
  459. static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
  460. {
  461. struct adv7604_state *state = to_state(sd);
  462. return adv_smbus_read_byte_data(state, ADV7604_PAGE_EDID, reg);
  463. }
  464. static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  465. {
  466. struct adv7604_state *state = to_state(sd);
  467. return adv_smbus_write_byte_data(state, ADV7604_PAGE_EDID, reg, val);
  468. }
  469. static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
  470. {
  471. struct adv7604_state *state = to_state(sd);
  472. struct i2c_client *client = state->i2c_clients[ADV7604_PAGE_EDID];
  473. u8 msgbuf0[1] = { 0 };
  474. u8 msgbuf1[256];
  475. struct i2c_msg msg[2] = {
  476. {
  477. .addr = client->addr,
  478. .len = 1,
  479. .buf = msgbuf0
  480. },
  481. {
  482. .addr = client->addr,
  483. .flags = I2C_M_RD,
  484. .len = len,
  485. .buf = msgbuf1
  486. },
  487. };
  488. if (i2c_transfer(client->adapter, msg, 2) < 0)
  489. return -EIO;
  490. memcpy(val, msgbuf1, len);
  491. return 0;
  492. }
  493. static inline int edid_write_block(struct v4l2_subdev *sd,
  494. unsigned len, const u8 *val)
  495. {
  496. struct adv7604_state *state = to_state(sd);
  497. int err = 0;
  498. int i;
  499. v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
  500. for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
  501. err = adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_EDID,
  502. i, I2C_SMBUS_BLOCK_MAX, val + i);
  503. return err;
  504. }
  505. static void adv7604_set_hpd(struct adv7604_state *state, unsigned int hpd)
  506. {
  507. unsigned int i;
  508. for (i = 0; i < state->info->num_dv_ports; ++i) {
  509. if (IS_ERR(state->hpd_gpio[i]))
  510. continue;
  511. gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
  512. }
  513. v4l2_subdev_notify(&state->sd, ADV7604_HOTPLUG, &hpd);
  514. }
  515. static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
  516. {
  517. struct delayed_work *dwork = to_delayed_work(work);
  518. struct adv7604_state *state = container_of(dwork, struct adv7604_state,
  519. delayed_work_enable_hotplug);
  520. struct v4l2_subdev *sd = &state->sd;
  521. v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
  522. adv7604_set_hpd(state, state->edid.present);
  523. }
  524. static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
  525. {
  526. struct adv7604_state *state = to_state(sd);
  527. return adv_smbus_read_byte_data(state, ADV7604_PAGE_HDMI, reg);
  528. }
  529. static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
  530. {
  531. return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
  532. }
  533. static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  534. {
  535. struct adv7604_state *state = to_state(sd);
  536. return adv_smbus_write_byte_data(state, ADV7604_PAGE_HDMI, reg, val);
  537. }
  538. static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
  539. {
  540. return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
  541. }
  542. static inline int test_read(struct v4l2_subdev *sd, u8 reg)
  543. {
  544. struct adv7604_state *state = to_state(sd);
  545. return adv_smbus_read_byte_data(state, ADV7604_PAGE_TEST, reg);
  546. }
  547. static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  548. {
  549. struct adv7604_state *state = to_state(sd);
  550. return adv_smbus_write_byte_data(state, ADV7604_PAGE_TEST, reg, val);
  551. }
  552. static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
  553. {
  554. struct adv7604_state *state = to_state(sd);
  555. return adv_smbus_read_byte_data(state, ADV7604_PAGE_CP, reg);
  556. }
  557. static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
  558. {
  559. return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
  560. }
  561. static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  562. {
  563. struct adv7604_state *state = to_state(sd);
  564. return adv_smbus_write_byte_data(state, ADV7604_PAGE_CP, reg, val);
  565. }
  566. static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
  567. {
  568. return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
  569. }
  570. static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
  571. {
  572. struct adv7604_state *state = to_state(sd);
  573. return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg);
  574. }
  575. static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  576. {
  577. struct adv7604_state *state = to_state(sd);
  578. return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val);
  579. }
  580. #define ADV7604_REG(page, offset) (((page) << 8) | (offset))
  581. #define ADV7604_REG_SEQ_TERM 0xffff
  582. #ifdef CONFIG_VIDEO_ADV_DEBUG
  583. static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg)
  584. {
  585. struct adv7604_state *state = to_state(sd);
  586. unsigned int page = reg >> 8;
  587. if (!(BIT(page) & state->info->page_mask))
  588. return -EINVAL;
  589. reg &= 0xff;
  590. return adv_smbus_read_byte_data(state, page, reg);
  591. }
  592. #endif
  593. static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
  594. {
  595. struct adv7604_state *state = to_state(sd);
  596. unsigned int page = reg >> 8;
  597. if (!(BIT(page) & state->info->page_mask))
  598. return -EINVAL;
  599. reg &= 0xff;
  600. return adv_smbus_write_byte_data(state, page, reg, val);
  601. }
  602. static void adv7604_write_reg_seq(struct v4l2_subdev *sd,
  603. const struct adv7604_reg_seq *reg_seq)
  604. {
  605. unsigned int i;
  606. for (i = 0; reg_seq[i].reg != ADV7604_REG_SEQ_TERM; i++)
  607. adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
  608. }
  609. /* -----------------------------------------------------------------------------
  610. * Format helpers
  611. */
  612. static const struct adv7604_format_info adv7604_formats[] = {
  613. { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false,
  614. ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT },
  615. { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false,
  616. ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
  617. { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true,
  618. ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
  619. { V4L2_MBUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false,
  620. ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
  621. { V4L2_MBUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true,
  622. ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
  623. { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false,
  624. ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
  625. { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true,
  626. ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
  627. { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false,
  628. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
  629. { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true,
  630. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
  631. { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false,
  632. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
  633. { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true,
  634. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
  635. { V4L2_MBUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false,
  636. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
  637. { V4L2_MBUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true,
  638. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
  639. { V4L2_MBUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false,
  640. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
  641. { V4L2_MBUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true,
  642. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
  643. { V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false,
  644. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
  645. { V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true,
  646. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
  647. { V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false,
  648. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
  649. { V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true,
  650. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
  651. };
  652. static const struct adv7604_format_info adv7611_formats[] = {
  653. { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false,
  654. ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT },
  655. { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false,
  656. ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
  657. { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true,
  658. ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
  659. { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false,
  660. ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
  661. { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true,
  662. ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
  663. { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false,
  664. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
  665. { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true,
  666. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
  667. { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false,
  668. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
  669. { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true,
  670. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
  671. { V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false,
  672. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
  673. { V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true,
  674. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
  675. { V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false,
  676. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
  677. { V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true,
  678. ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
  679. };
  680. static const struct adv7604_format_info *
  681. adv7604_format_info(struct adv7604_state *state, enum v4l2_mbus_pixelcode code)
  682. {
  683. unsigned int i;
  684. for (i = 0; i < state->info->nformats; ++i) {
  685. if (state->info->formats[i].code == code)
  686. return &state->info->formats[i];
  687. }
  688. return NULL;
  689. }
  690. /* ----------------------------------------------------------------------- */
  691. static inline bool is_analog_input(struct v4l2_subdev *sd)
  692. {
  693. struct adv7604_state *state = to_state(sd);
  694. return state->selected_input == ADV7604_PAD_VGA_RGB ||
  695. state->selected_input == ADV7604_PAD_VGA_COMP;
  696. }
  697. static inline bool is_digital_input(struct v4l2_subdev *sd)
  698. {
  699. struct adv7604_state *state = to_state(sd);
  700. return state->selected_input == ADV7604_PAD_HDMI_PORT_A ||
  701. state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
  702. state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
  703. state->selected_input == ADV7604_PAD_HDMI_PORT_D;
  704. }
  705. /* ----------------------------------------------------------------------- */
  706. #ifdef CONFIG_VIDEO_ADV_DEBUG
  707. static void adv7604_inv_register(struct v4l2_subdev *sd)
  708. {
  709. v4l2_info(sd, "0x000-0x0ff: IO Map\n");
  710. v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
  711. v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
  712. v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
  713. v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
  714. v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
  715. v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
  716. v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
  717. v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
  718. v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
  719. v4l2_info(sd, "0xa00-0xaff: Test Map\n");
  720. v4l2_info(sd, "0xb00-0xbff: CP Map\n");
  721. v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
  722. }
  723. static int adv7604_g_register(struct v4l2_subdev *sd,
  724. struct v4l2_dbg_register *reg)
  725. {
  726. int ret;
  727. ret = adv7604_read_reg(sd, reg->reg);
  728. if (ret < 0) {
  729. v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
  730. adv7604_inv_register(sd);
  731. return ret;
  732. }
  733. reg->size = 1;
  734. reg->val = ret;
  735. return 0;
  736. }
  737. static int adv7604_s_register(struct v4l2_subdev *sd,
  738. const struct v4l2_dbg_register *reg)
  739. {
  740. int ret;
  741. ret = adv7604_write_reg(sd, reg->reg, reg->val);
  742. if (ret < 0) {
  743. v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
  744. adv7604_inv_register(sd);
  745. return ret;
  746. }
  747. return 0;
  748. }
  749. #endif
  750. static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
  751. {
  752. u8 value = io_read(sd, 0x6f);
  753. return ((value & 0x10) >> 4)
  754. | ((value & 0x08) >> 2)
  755. | ((value & 0x04) << 0)
  756. | ((value & 0x02) << 2);
  757. }
  758. static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
  759. {
  760. u8 value = io_read(sd, 0x6f);
  761. return value & 1;
  762. }
  763. static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
  764. {
  765. struct adv7604_state *state = to_state(sd);
  766. const struct adv7604_chip_info *info = state->info;
  767. return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
  768. info->read_cable_det(sd));
  769. }
  770. static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
  771. u8 prim_mode,
  772. const struct adv7604_video_standards *predef_vid_timings,
  773. const struct v4l2_dv_timings *timings)
  774. {
  775. int i;
  776. for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
  777. if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
  778. is_digital_input(sd) ? 250000 : 1000000))
  779. continue;
  780. io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
  781. io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
  782. prim_mode); /* v_freq and prim mode */
  783. return 0;
  784. }
  785. return -1;
  786. }
  787. static int configure_predefined_video_timings(struct v4l2_subdev *sd,
  788. struct v4l2_dv_timings *timings)
  789. {
  790. struct adv7604_state *state = to_state(sd);
  791. int err;
  792. v4l2_dbg(1, debug, sd, "%s", __func__);
  793. if (adv7604_has_afe(state)) {
  794. /* reset to default values */
  795. io_write(sd, 0x16, 0x43);
  796. io_write(sd, 0x17, 0x5a);
  797. }
  798. /* disable embedded syncs for auto graphics mode */
  799. cp_write_clr_set(sd, 0x81, 0x10, 0x00);
  800. cp_write(sd, 0x8f, 0x00);
  801. cp_write(sd, 0x90, 0x00);
  802. cp_write(sd, 0xa2, 0x00);
  803. cp_write(sd, 0xa3, 0x00);
  804. cp_write(sd, 0xa4, 0x00);
  805. cp_write(sd, 0xa5, 0x00);
  806. cp_write(sd, 0xa6, 0x00);
  807. cp_write(sd, 0xa7, 0x00);
  808. cp_write(sd, 0xab, 0x00);
  809. cp_write(sd, 0xac, 0x00);
  810. if (is_analog_input(sd)) {
  811. err = find_and_set_predefined_video_timings(sd,
  812. 0x01, adv7604_prim_mode_comp, timings);
  813. if (err)
  814. err = find_and_set_predefined_video_timings(sd,
  815. 0x02, adv7604_prim_mode_gr, timings);
  816. } else if (is_digital_input(sd)) {
  817. err = find_and_set_predefined_video_timings(sd,
  818. 0x05, adv7604_prim_mode_hdmi_comp, timings);
  819. if (err)
  820. err = find_and_set_predefined_video_timings(sd,
  821. 0x06, adv7604_prim_mode_hdmi_gr, timings);
  822. } else {
  823. v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
  824. __func__, state->selected_input);
  825. err = -1;
  826. }
  827. return err;
  828. }
  829. static void configure_custom_video_timings(struct v4l2_subdev *sd,
  830. const struct v4l2_bt_timings *bt)
  831. {
  832. struct adv7604_state *state = to_state(sd);
  833. u32 width = htotal(bt);
  834. u32 height = vtotal(bt);
  835. u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
  836. u16 cp_start_eav = width - bt->hfrontporch;
  837. u16 cp_start_vbi = height - bt->vfrontporch;
  838. u16 cp_end_vbi = bt->vsync + bt->vbackporch;
  839. u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
  840. ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
  841. const u8 pll[2] = {
  842. 0xc0 | ((width >> 8) & 0x1f),
  843. width & 0xff
  844. };
  845. v4l2_dbg(2, debug, sd, "%s\n", __func__);
  846. if (is_analog_input(sd)) {
  847. /* auto graphics */
  848. io_write(sd, 0x00, 0x07); /* video std */
  849. io_write(sd, 0x01, 0x02); /* prim mode */
  850. /* enable embedded syncs for auto graphics mode */
  851. cp_write_clr_set(sd, 0x81, 0x10, 0x10);
  852. /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
  853. /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
  854. /* IO-map reg. 0x16 and 0x17 should be written in sequence */
  855. if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_IO,
  856. 0x16, 2, pll))
  857. v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
  858. /* active video - horizontal timing */
  859. cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
  860. cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
  861. ((cp_start_eav >> 8) & 0x0f));
  862. cp_write(sd, 0xa4, cp_start_eav & 0xff);
  863. /* active video - vertical timing */
  864. cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
  865. cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
  866. ((cp_end_vbi >> 8) & 0xf));
  867. cp_write(sd, 0xa7, cp_end_vbi & 0xff);
  868. } else if (is_digital_input(sd)) {
  869. /* set default prim_mode/vid_std for HDMI
  870. according to [REF_03, c. 4.2] */
  871. io_write(sd, 0x00, 0x02); /* video std */
  872. io_write(sd, 0x01, 0x06); /* prim mode */
  873. } else {
  874. v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
  875. __func__, state->selected_input);
  876. }
  877. cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
  878. cp_write(sd, 0x90, ch1_fr_ll & 0xff);
  879. cp_write(sd, 0xab, (height >> 4) & 0xff);
  880. cp_write(sd, 0xac, (height & 0x0f) << 4);
  881. }
  882. static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
  883. {
  884. struct adv7604_state *state = to_state(sd);
  885. u8 offset_buf[4];
  886. if (auto_offset) {
  887. offset_a = 0x3ff;
  888. offset_b = 0x3ff;
  889. offset_c = 0x3ff;
  890. }
  891. v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
  892. __func__, auto_offset ? "Auto" : "Manual",
  893. offset_a, offset_b, offset_c);
  894. offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
  895. offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
  896. offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
  897. offset_buf[3] = offset_c & 0x0ff;
  898. /* Registers must be written in this order with no i2c access in between */
  899. if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP,
  900. 0x77, 4, offset_buf))
  901. v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
  902. }
  903. static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
  904. {
  905. struct adv7604_state *state = to_state(sd);
  906. u8 gain_buf[4];
  907. u8 gain_man = 1;
  908. u8 agc_mode_man = 1;
  909. if (auto_gain) {
  910. gain_man = 0;
  911. agc_mode_man = 0;
  912. gain_a = 0x100;
  913. gain_b = 0x100;
  914. gain_c = 0x100;
  915. }
  916. v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
  917. __func__, auto_gain ? "Auto" : "Manual",
  918. gain_a, gain_b, gain_c);
  919. gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
  920. gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
  921. gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
  922. gain_buf[3] = ((gain_c & 0x0ff));
  923. /* Registers must be written in this order with no i2c access in between */
  924. if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP,
  925. 0x73, 4, gain_buf))
  926. v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
  927. }
  928. static void set_rgb_quantization_range(struct v4l2_subdev *sd)
  929. {
  930. struct adv7604_state *state = to_state(sd);
  931. bool rgb_output = io_read(sd, 0x02) & 0x02;
  932. bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
  933. v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
  934. __func__, state->rgb_quantization_range,
  935. rgb_output, hdmi_signal);
  936. adv7604_set_gain(sd, true, 0x0, 0x0, 0x0);
  937. adv7604_set_offset(sd, true, 0x0, 0x0, 0x0);
  938. switch (state->rgb_quantization_range) {
  939. case V4L2_DV_RGB_RANGE_AUTO:
  940. if (state->selected_input == ADV7604_PAD_VGA_RGB) {
  941. /* Receiving analog RGB signal
  942. * Set RGB full range (0-255) */
  943. io_write_clr_set(sd, 0x02, 0xf0, 0x10);
  944. break;
  945. }
  946. if (state->selected_input == ADV7604_PAD_VGA_COMP) {
  947. /* Receiving analog YPbPr signal
  948. * Set automode */
  949. io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
  950. break;
  951. }
  952. if (hdmi_signal) {
  953. /* Receiving HDMI signal
  954. * Set automode */
  955. io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
  956. break;
  957. }
  958. /* Receiving DVI-D signal
  959. * ADV7604 selects RGB limited range regardless of
  960. * input format (CE/IT) in automatic mode */
  961. if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
  962. /* RGB limited range (16-235) */
  963. io_write_clr_set(sd, 0x02, 0xf0, 0x00);
  964. } else {
  965. /* RGB full range (0-255) */
  966. io_write_clr_set(sd, 0x02, 0xf0, 0x10);
  967. if (is_digital_input(sd) && rgb_output) {
  968. adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
  969. } else {
  970. adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
  971. adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
  972. }
  973. }
  974. break;
  975. case V4L2_DV_RGB_RANGE_LIMITED:
  976. if (state->selected_input == ADV7604_PAD_VGA_COMP) {
  977. /* YCrCb limited range (16-235) */
  978. io_write_clr_set(sd, 0x02, 0xf0, 0x20);
  979. break;
  980. }
  981. /* RGB limited range (16-235) */
  982. io_write_clr_set(sd, 0x02, 0xf0, 0x00);
  983. break;
  984. case V4L2_DV_RGB_RANGE_FULL:
  985. if (state->selected_input == ADV7604_PAD_VGA_COMP) {
  986. /* YCrCb full range (0-255) */
  987. io_write_clr_set(sd, 0x02, 0xf0, 0x60);
  988. break;
  989. }
  990. /* RGB full range (0-255) */
  991. io_write_clr_set(sd, 0x02, 0xf0, 0x10);
  992. if (is_analog_input(sd) || hdmi_signal)
  993. break;
  994. /* Adjust gain/offset for DVI-D signals only */
  995. if (rgb_output) {
  996. adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
  997. } else {
  998. adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
  999. adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
  1000. }
  1001. break;
  1002. }
  1003. }
  1004. static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
  1005. {
  1006. struct v4l2_subdev *sd =
  1007. &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
  1008. struct adv7604_state *state = to_state(sd);
  1009. switch (ctrl->id) {
  1010. case V4L2_CID_BRIGHTNESS:
  1011. cp_write(sd, 0x3c, ctrl->val);
  1012. return 0;
  1013. case V4L2_CID_CONTRAST:
  1014. cp_write(sd, 0x3a, ctrl->val);
  1015. return 0;
  1016. case V4L2_CID_SATURATION:
  1017. cp_write(sd, 0x3b, ctrl->val);
  1018. return 0;
  1019. case V4L2_CID_HUE:
  1020. cp_write(sd, 0x3d, ctrl->val);
  1021. return 0;
  1022. case V4L2_CID_DV_RX_RGB_RANGE:
  1023. state->rgb_quantization_range = ctrl->val;
  1024. set_rgb_quantization_range(sd);
  1025. return 0;
  1026. case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
  1027. if (!adv7604_has_afe(state))
  1028. return -EINVAL;
  1029. /* Set the analog sampling phase. This is needed to find the
  1030. best sampling phase for analog video: an application or
  1031. driver has to try a number of phases and analyze the picture
  1032. quality before settling on the best performing phase. */
  1033. afe_write(sd, 0xc8, ctrl->val);
  1034. return 0;
  1035. case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
  1036. /* Use the default blue color for free running mode,
  1037. or supply your own. */
  1038. cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
  1039. return 0;
  1040. case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
  1041. cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
  1042. cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
  1043. cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
  1044. return 0;
  1045. }
  1046. return -EINVAL;
  1047. }
  1048. /* ----------------------------------------------------------------------- */
  1049. static inline bool no_power(struct v4l2_subdev *sd)
  1050. {
  1051. /* Entire chip or CP powered off */
  1052. return io_read(sd, 0x0c) & 0x24;
  1053. }
  1054. static inline bool no_signal_tmds(struct v4l2_subdev *sd)
  1055. {
  1056. struct adv7604_state *state = to_state(sd);
  1057. return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
  1058. }
  1059. static inline bool no_lock_tmds(struct v4l2_subdev *sd)
  1060. {
  1061. struct adv7604_state *state = to_state(sd);
  1062. const struct adv7604_chip_info *info = state->info;
  1063. return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
  1064. }
  1065. static inline bool is_hdmi(struct v4l2_subdev *sd)
  1066. {
  1067. return hdmi_read(sd, 0x05) & 0x80;
  1068. }
  1069. static inline bool no_lock_sspd(struct v4l2_subdev *sd)
  1070. {
  1071. struct adv7604_state *state = to_state(sd);
  1072. /*
  1073. * Chips without a AFE don't expose registers for the SSPD, so just assume
  1074. * that we have a lock.
  1075. */
  1076. if (adv7604_has_afe(state))
  1077. return false;
  1078. /* TODO channel 2 */
  1079. return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
  1080. }
  1081. static inline bool no_lock_stdi(struct v4l2_subdev *sd)
  1082. {
  1083. /* TODO channel 2 */
  1084. return !(cp_read(sd, 0xb1) & 0x80);
  1085. }
  1086. static inline bool no_signal(struct v4l2_subdev *sd)
  1087. {
  1088. bool ret;
  1089. ret = no_power(sd);
  1090. ret |= no_lock_stdi(sd);
  1091. ret |= no_lock_sspd(sd);
  1092. if (is_digital_input(sd)) {
  1093. ret |= no_lock_tmds(sd);
  1094. ret |= no_signal_tmds(sd);
  1095. }
  1096. return ret;
  1097. }
  1098. static inline bool no_lock_cp(struct v4l2_subdev *sd)
  1099. {
  1100. struct adv7604_state *state = to_state(sd);
  1101. if (!adv7604_has_afe(state))
  1102. return false;
  1103. /* CP has detected a non standard number of lines on the incoming
  1104. video compared to what it is configured to receive by s_dv_timings */
  1105. return io_read(sd, 0x12) & 0x01;
  1106. }
  1107. static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
  1108. {
  1109. *status = 0;
  1110. *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
  1111. *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
  1112. if (no_lock_cp(sd))
  1113. *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
  1114. v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
  1115. return 0;
  1116. }
  1117. /* ----------------------------------------------------------------------- */
  1118. struct stdi_readback {
  1119. u16 bl, lcf, lcvs;
  1120. u8 hs_pol, vs_pol;
  1121. bool interlaced;
  1122. };
  1123. static int stdi2dv_timings(struct v4l2_subdev *sd,
  1124. struct stdi_readback *stdi,
  1125. struct v4l2_dv_timings *timings)
  1126. {
  1127. struct adv7604_state *state = to_state(sd);
  1128. u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
  1129. u32 pix_clk;
  1130. int i;
  1131. for (i = 0; adv7604_timings[i].bt.height; i++) {
  1132. if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
  1133. continue;
  1134. if (adv7604_timings[i].bt.vsync != stdi->lcvs)
  1135. continue;
  1136. pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
  1137. if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
  1138. (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
  1139. *timings = adv7604_timings[i];
  1140. return 0;
  1141. }
  1142. }
  1143. if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
  1144. (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
  1145. (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
  1146. timings))
  1147. return 0;
  1148. if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
  1149. (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
  1150. (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
  1151. state->aspect_ratio, timings))
  1152. return 0;
  1153. v4l2_dbg(2, debug, sd,
  1154. "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
  1155. __func__, stdi->lcvs, stdi->lcf, stdi->bl,
  1156. stdi->hs_pol, stdi->vs_pol);
  1157. return -1;
  1158. }
  1159. static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
  1160. {
  1161. struct adv7604_state *state = to_state(sd);
  1162. const struct adv7604_chip_info *info = state->info;
  1163. u8 polarity;
  1164. if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
  1165. v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
  1166. return -1;
  1167. }
  1168. /* read STDI */
  1169. stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
  1170. stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
  1171. stdi->lcvs = cp_read(sd, 0xb3) >> 3;
  1172. stdi->interlaced = io_read(sd, 0x12) & 0x10;
  1173. if (adv7604_has_afe(state)) {
  1174. /* read SSPD */
  1175. polarity = cp_read(sd, 0xb5);
  1176. if ((polarity & 0x03) == 0x01) {
  1177. stdi->hs_pol = polarity & 0x10
  1178. ? (polarity & 0x08 ? '+' : '-') : 'x';
  1179. stdi->vs_pol = polarity & 0x40
  1180. ? (polarity & 0x20 ? '+' : '-') : 'x';
  1181. } else {
  1182. stdi->hs_pol = 'x';
  1183. stdi->vs_pol = 'x';
  1184. }
  1185. } else {
  1186. polarity = hdmi_read(sd, 0x05);
  1187. stdi->hs_pol = polarity & 0x20 ? '+' : '-';
  1188. stdi->vs_pol = polarity & 0x10 ? '+' : '-';
  1189. }
  1190. if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
  1191. v4l2_dbg(2, debug, sd,
  1192. "%s: signal lost during readout of STDI/SSPD\n", __func__);
  1193. return -1;
  1194. }
  1195. if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
  1196. v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
  1197. memset(stdi, 0, sizeof(struct stdi_readback));
  1198. return -1;
  1199. }
  1200. v4l2_dbg(2, debug, sd,
  1201. "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
  1202. __func__, stdi->lcf, stdi->bl, stdi->lcvs,
  1203. stdi->hs_pol, stdi->vs_pol,
  1204. stdi->interlaced ? "interlaced" : "progressive");
  1205. return 0;
  1206. }
  1207. static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
  1208. struct v4l2_enum_dv_timings *timings)
  1209. {
  1210. struct adv7604_state *state = to_state(sd);
  1211. if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
  1212. return -EINVAL;
  1213. if (timings->pad >= state->source_pad)
  1214. return -EINVAL;
  1215. memset(timings->reserved, 0, sizeof(timings->reserved));
  1216. timings->timings = adv7604_timings[timings->index];
  1217. return 0;
  1218. }
  1219. static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
  1220. struct v4l2_dv_timings_cap *cap)
  1221. {
  1222. struct adv7604_state *state = to_state(sd);
  1223. if (cap->pad >= state->source_pad)
  1224. return -EINVAL;
  1225. cap->type = V4L2_DV_BT_656_1120;
  1226. cap->bt.max_width = 1920;
  1227. cap->bt.max_height = 1200;
  1228. cap->bt.min_pixelclock = 25000000;
  1229. switch (cap->pad) {
  1230. case ADV7604_PAD_HDMI_PORT_A:
  1231. case ADV7604_PAD_HDMI_PORT_B:
  1232. case ADV7604_PAD_HDMI_PORT_C:
  1233. case ADV7604_PAD_HDMI_PORT_D:
  1234. cap->bt.max_pixelclock = 225000000;
  1235. break;
  1236. case ADV7604_PAD_VGA_RGB:
  1237. case ADV7604_PAD_VGA_COMP:
  1238. default:
  1239. cap->bt.max_pixelclock = 170000000;
  1240. break;
  1241. }
  1242. cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
  1243. V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
  1244. cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
  1245. V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
  1246. return 0;
  1247. }
  1248. /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
  1249. if the format is listed in adv7604_timings[] */
  1250. static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
  1251. struct v4l2_dv_timings *timings)
  1252. {
  1253. int i;
  1254. for (i = 0; adv7604_timings[i].bt.width; i++) {
  1255. if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
  1256. is_digital_input(sd) ? 250000 : 1000000)) {
  1257. *timings = adv7604_timings[i];
  1258. break;
  1259. }
  1260. }
  1261. }
  1262. static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
  1263. {
  1264. unsigned int freq;
  1265. int a, b;
  1266. a = hdmi_read(sd, 0x06);
  1267. b = hdmi_read(sd, 0x3b);
  1268. if (a < 0 || b < 0)
  1269. return 0;
  1270. freq = a * 1000000 + ((b & 0x30) >> 4) * 250000;
  1271. if (is_hdmi(sd)) {
  1272. /* adjust for deep color mode */
  1273. unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
  1274. freq = freq * 8 / bits_per_channel;
  1275. }
  1276. return freq;
  1277. }
  1278. static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
  1279. {
  1280. int a, b;
  1281. a = hdmi_read(sd, 0x51);
  1282. b = hdmi_read(sd, 0x52);
  1283. if (a < 0 || b < 0)
  1284. return 0;
  1285. return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
  1286. }
  1287. static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
  1288. struct v4l2_dv_timings *timings)
  1289. {
  1290. struct adv7604_state *state = to_state(sd);
  1291. const struct adv7604_chip_info *info = state->info;
  1292. struct v4l2_bt_timings *bt = &timings->bt;
  1293. struct stdi_readback stdi;
  1294. if (!timings)
  1295. return -EINVAL;
  1296. memset(timings, 0, sizeof(struct v4l2_dv_timings));
  1297. if (no_signal(sd)) {
  1298. state->restart_stdi_once = true;
  1299. v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
  1300. return -ENOLINK;
  1301. }
  1302. /* read STDI */
  1303. if (read_stdi(sd, &stdi)) {
  1304. v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
  1305. return -ENOLINK;
  1306. }
  1307. bt->interlaced = stdi.interlaced ?
  1308. V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
  1309. if (is_digital_input(sd)) {
  1310. timings->type = V4L2_DV_BT_656_1120;
  1311. /* FIXME: All masks are incorrect for ADV7611 */
  1312. bt->width = hdmi_read16(sd, 0x07, 0xfff);
  1313. bt->height = hdmi_read16(sd, 0x09, 0xfff);
  1314. bt->pixelclock = info->read_hdmi_pixelclock(sd);
  1315. bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff);
  1316. bt->hsync = hdmi_read16(sd, 0x22, 0x3ff);
  1317. bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff);
  1318. bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2;
  1319. bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2;
  1320. bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2;
  1321. bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
  1322. ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
  1323. if (bt->interlaced == V4L2_DV_INTERLACED) {
  1324. bt->height += hdmi_read16(sd, 0x0b, 0xfff);
  1325. bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2;
  1326. bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2;
  1327. bt->vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2;
  1328. }
  1329. adv7604_fill_optional_dv_timings_fields(sd, timings);
  1330. } else {
  1331. /* find format
  1332. * Since LCVS values are inaccurate [REF_03, p. 275-276],
  1333. * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
  1334. */
  1335. if (!stdi2dv_timings(sd, &stdi, timings))
  1336. goto found;
  1337. stdi.lcvs += 1;
  1338. v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
  1339. if (!stdi2dv_timings(sd, &stdi, timings))
  1340. goto found;
  1341. stdi.lcvs -= 2;
  1342. v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
  1343. if (stdi2dv_timings(sd, &stdi, timings)) {
  1344. /*
  1345. * The STDI block may measure wrong values, especially
  1346. * for lcvs and lcf. If the driver can not find any
  1347. * valid timing, the STDI block is restarted to measure
  1348. * the video timings again. The function will return an
  1349. * error, but the restart of STDI will generate a new
  1350. * STDI interrupt and the format detection process will
  1351. * restart.
  1352. */
  1353. if (state->restart_stdi_once) {
  1354. v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
  1355. /* TODO restart STDI for Sync Channel 2 */
  1356. /* enter one-shot mode */
  1357. cp_write_clr_set(sd, 0x86, 0x06, 0x00);
  1358. /* trigger STDI restart */
  1359. cp_write_clr_set(sd, 0x86, 0x06, 0x04);
  1360. /* reset to continuous mode */
  1361. cp_write_clr_set(sd, 0x86, 0x06, 0x02);
  1362. state->restart_stdi_once = false;
  1363. return -ENOLINK;
  1364. }
  1365. v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
  1366. return -ERANGE;
  1367. }
  1368. state->restart_stdi_once = true;
  1369. }
  1370. found:
  1371. if (no_signal(sd)) {
  1372. v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
  1373. memset(timings, 0, sizeof(struct v4l2_dv_timings));
  1374. return -ENOLINK;
  1375. }
  1376. if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
  1377. (is_digital_input(sd) && bt->pixelclock > 225000000)) {
  1378. v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
  1379. __func__, (u32)bt->pixelclock);
  1380. return -ERANGE;
  1381. }
  1382. if (debug > 1)
  1383. v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
  1384. timings, true);
  1385. return 0;
  1386. }
  1387. static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
  1388. struct v4l2_dv_timings *timings)
  1389. {
  1390. struct adv7604_state *state = to_state(sd);
  1391. struct v4l2_bt_timings *bt;
  1392. int err;
  1393. if (!timings)
  1394. return -EINVAL;
  1395. if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
  1396. v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
  1397. return 0;
  1398. }
  1399. bt = &timings->bt;
  1400. if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
  1401. (is_digital_input(sd) && bt->pixelclock > 225000000)) {
  1402. v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
  1403. __func__, (u32)bt->pixelclock);
  1404. return -ERANGE;
  1405. }
  1406. adv7604_fill_optional_dv_timings_fields(sd, timings);
  1407. state->timings = *timings;
  1408. cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
  1409. /* Use prim_mode and vid_std when available */
  1410. err = configure_predefined_video_timings(sd, timings);
  1411. if (err) {
  1412. /* custom settings when the video format
  1413. does not have prim_mode/vid_std */
  1414. configure_custom_video_timings(sd, bt);
  1415. }
  1416. set_rgb_quantization_range(sd);
  1417. if (debug > 1)
  1418. v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
  1419. timings, true);
  1420. return 0;
  1421. }
  1422. static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
  1423. struct v4l2_dv_timings *timings)
  1424. {
  1425. struct adv7604_state *state = to_state(sd);
  1426. *timings = state->timings;
  1427. return 0;
  1428. }
  1429. static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
  1430. {
  1431. hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
  1432. }
  1433. static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
  1434. {
  1435. hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
  1436. }
  1437. static void enable_input(struct v4l2_subdev *sd)
  1438. {
  1439. struct adv7604_state *state = to_state(sd);
  1440. if (is_analog_input(sd)) {
  1441. io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
  1442. } else if (is_digital_input(sd)) {
  1443. hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
  1444. state->info->set_termination(sd, true);
  1445. io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
  1446. hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
  1447. } else {
  1448. v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
  1449. __func__, state->selected_input);
  1450. }
  1451. }
  1452. static void disable_input(struct v4l2_subdev *sd)
  1453. {
  1454. struct adv7604_state *state = to_state(sd);
  1455. hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
  1456. msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
  1457. io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
  1458. state->info->set_termination(sd, false);
  1459. }
  1460. static void select_input(struct v4l2_subdev *sd)
  1461. {
  1462. struct adv7604_state *state = to_state(sd);
  1463. const struct adv7604_chip_info *info = state->info;
  1464. if (is_analog_input(sd)) {
  1465. adv7604_write_reg_seq(sd, info->recommended_settings[0]);
  1466. afe_write(sd, 0x00, 0x08); /* power up ADC */
  1467. afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
  1468. afe_write(sd, 0xc8, 0x00); /* phase control */
  1469. } else if (is_digital_input(sd)) {
  1470. hdmi_write(sd, 0x00, state->selected_input & 0x03);
  1471. adv7604_write_reg_seq(sd, info->recommended_settings[1]);
  1472. if (adv7604_has_afe(state)) {
  1473. afe_write(sd, 0x00, 0xff); /* power down ADC */
  1474. afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
  1475. afe_write(sd, 0xc8, 0x40); /* phase control */
  1476. }
  1477. cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
  1478. cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
  1479. cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
  1480. } else {
  1481. v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
  1482. __func__, state->selected_input);
  1483. }
  1484. }
  1485. static int adv7604_s_routing(struct v4l2_subdev *sd,
  1486. u32 input, u32 output, u32 config)
  1487. {
  1488. struct adv7604_state *state = to_state(sd);
  1489. v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
  1490. __func__, input, state->selected_input);
  1491. if (input == state->selected_input)
  1492. return 0;
  1493. if (input > state->info->max_port)
  1494. return -EINVAL;
  1495. state->selected_input = input;
  1496. disable_input(sd);
  1497. select_input(sd);
  1498. enable_input(sd);
  1499. return 0;
  1500. }
  1501. static int adv7604_enum_mbus_code(struct v4l2_subdev *sd,
  1502. struct v4l2_subdev_fh *fh,
  1503. struct v4l2_subdev_mbus_code_enum *code)
  1504. {
  1505. struct adv7604_state *state = to_state(sd);
  1506. if (code->index >= state->info->nformats)
  1507. return -EINVAL;
  1508. code->code = state->info->formats[code->index].code;
  1509. return 0;
  1510. }
  1511. static void adv7604_fill_format(struct adv7604_state *state,
  1512. struct v4l2_mbus_framefmt *format)
  1513. {
  1514. memset(format, 0, sizeof(*format));
  1515. format->width = state->timings.bt.width;
  1516. format->height = state->timings.bt.height;
  1517. format->field = V4L2_FIELD_NONE;
  1518. if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861)
  1519. format->colorspace = (state->timings.bt.height <= 576) ?
  1520. V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
  1521. }
  1522. /*
  1523. * Compute the op_ch_sel value required to obtain on the bus the component order
  1524. * corresponding to the selected format taking into account bus reordering
  1525. * applied by the board at the output of the device.
  1526. *
  1527. * The following table gives the op_ch_value from the format component order
  1528. * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
  1529. * adv7604_bus_order value in row).
  1530. *
  1531. * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
  1532. * ----------+-------------------------------------------------
  1533. * RGB (NOP) | GBR GRB BGR RGB BRG RBG
  1534. * GRB (1-2) | BGR RGB GBR GRB RBG BRG
  1535. * RBG (2-3) | GRB GBR BRG RBG BGR RGB
  1536. * BGR (1-3) | RBG BRG RGB BGR GRB GBR
  1537. * BRG (ROR) | BRG RBG GRB GBR RGB BGR
  1538. * GBR (ROL) | RGB BGR RBG BRG GBR GRB
  1539. */
  1540. static unsigned int adv7604_op_ch_sel(struct adv7604_state *state)
  1541. {
  1542. #define _SEL(a,b,c,d,e,f) { \
  1543. ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, \
  1544. ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f }
  1545. #define _BUS(x) [ADV7604_BUS_ORDER_##x]
  1546. static const unsigned int op_ch_sel[6][6] = {
  1547. _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
  1548. _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
  1549. _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
  1550. _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
  1551. _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
  1552. _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
  1553. };
  1554. return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
  1555. }
  1556. static void adv7604_setup_format(struct adv7604_state *state)
  1557. {
  1558. struct v4l2_subdev *sd = &state->sd;
  1559. io_write_clr_set(sd, 0x02, 0x02,
  1560. state->format->rgb_out ? ADV7604_RGB_OUT : 0);
  1561. io_write(sd, 0x03, state->format->op_format_sel |
  1562. state->pdata.op_format_mode_sel);
  1563. io_write_clr_set(sd, 0x04, 0xe0, adv7604_op_ch_sel(state));
  1564. io_write_clr_set(sd, 0x05, 0x01,
  1565. state->format->swap_cb_cr ? ADV7604_OP_SWAP_CB_CR : 0);
  1566. }
  1567. static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
  1568. struct v4l2_subdev_format *format)
  1569. {
  1570. struct adv7604_state *state = to_state(sd);
  1571. if (format->pad != state->source_pad)
  1572. return -EINVAL;
  1573. adv7604_fill_format(state, &format->format);
  1574. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  1575. struct v4l2_mbus_framefmt *fmt;
  1576. fmt = v4l2_subdev_get_try_format(fh, format->pad);
  1577. format->format.code = fmt->code;
  1578. } else {
  1579. format->format.code = state->format->code;
  1580. }
  1581. return 0;
  1582. }
  1583. static int adv7604_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
  1584. struct v4l2_subdev_format *format)
  1585. {
  1586. struct adv7604_state *state = to_state(sd);
  1587. const struct adv7604_format_info *info;
  1588. if (format->pad != state->source_pad)
  1589. return -EINVAL;
  1590. info = adv7604_format_info(state, format->format.code);
  1591. if (info == NULL)
  1592. info = adv7604_format_info(state, V4L2_MBUS_FMT_YUYV8_2X8);
  1593. adv7604_fill_format(state, &format->format);
  1594. format->format.code = info->code;
  1595. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  1596. struct v4l2_mbus_framefmt *fmt;
  1597. fmt = v4l2_subdev_get_try_format(fh, format->pad);
  1598. fmt->code = format->format.code;
  1599. } else {
  1600. state->format = info;
  1601. adv7604_setup_format(state);
  1602. }
  1603. return 0;
  1604. }
  1605. static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
  1606. {
  1607. struct adv7604_state *state = to_state(sd);
  1608. const struct adv7604_chip_info *info = state->info;
  1609. const u8 irq_reg_0x43 = io_read(sd, 0x43);
  1610. const u8 irq_reg_0x6b = io_read(sd, 0x6b);
  1611. const u8 irq_reg_0x70 = io_read(sd, 0x70);
  1612. u8 fmt_change_digital;
  1613. u8 fmt_change;
  1614. u8 tx_5v;
  1615. if (irq_reg_0x43)
  1616. io_write(sd, 0x44, irq_reg_0x43);
  1617. if (irq_reg_0x70)
  1618. io_write(sd, 0x71, irq_reg_0x70);
  1619. if (irq_reg_0x6b)
  1620. io_write(sd, 0x6c, irq_reg_0x6b);
  1621. v4l2_dbg(2, debug, sd, "%s: ", __func__);
  1622. /* format change */
  1623. fmt_change = irq_reg_0x43 & 0x98;
  1624. fmt_change_digital = is_digital_input(sd)
  1625. ? irq_reg_0x6b & info->fmt_change_digital_mask
  1626. : 0;
  1627. if (fmt_change || fmt_change_digital) {
  1628. v4l2_dbg(1, debug, sd,
  1629. "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
  1630. __func__, fmt_change, fmt_change_digital);
  1631. v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
  1632. if (handled)
  1633. *handled = true;
  1634. }
  1635. /* HDMI/DVI mode */
  1636. if (irq_reg_0x6b & 0x01) {
  1637. v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
  1638. (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
  1639. set_rgb_quantization_range(sd);
  1640. if (handled)
  1641. *handled = true;
  1642. }
  1643. /* tx 5v detect */
  1644. tx_5v = io_read(sd, 0x70) & info->cable_det_mask;
  1645. if (tx_5v) {
  1646. v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
  1647. io_write(sd, 0x71, tx_5v);
  1648. adv7604_s_detect_tx_5v_ctrl(sd);
  1649. if (handled)
  1650. *handled = true;
  1651. }
  1652. return 0;
  1653. }
  1654. static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
  1655. {
  1656. struct adv7604_state *state = to_state(sd);
  1657. u8 *data = NULL;
  1658. if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
  1659. return -EINVAL;
  1660. if (edid->blocks == 0)
  1661. return -EINVAL;
  1662. if (edid->blocks > 2)
  1663. return -EINVAL;
  1664. if (edid->start_block > 1)
  1665. return -EINVAL;
  1666. if (edid->start_block == 1)
  1667. edid->blocks = 1;
  1668. if (edid->blocks > state->edid.blocks)
  1669. edid->blocks = state->edid.blocks;
  1670. switch (edid->pad) {
  1671. case ADV7604_PAD_HDMI_PORT_A:
  1672. case ADV7604_PAD_HDMI_PORT_B:
  1673. case ADV7604_PAD_HDMI_PORT_C:
  1674. case ADV7604_PAD_HDMI_PORT_D:
  1675. if (state->edid.present & (1 << edid->pad))
  1676. data = state->edid.edid;
  1677. break;
  1678. default:
  1679. return -EINVAL;
  1680. break;
  1681. }
  1682. if (!data)
  1683. return -ENODATA;
  1684. memcpy(edid->edid,
  1685. data + edid->start_block * 128,
  1686. edid->blocks * 128);
  1687. return 0;
  1688. }
  1689. static int get_edid_spa_location(const u8 *edid)
  1690. {
  1691. u8 d;
  1692. if ((edid[0x7e] != 1) ||
  1693. (edid[0x80] != 0x02) ||
  1694. (edid[0x81] != 0x03)) {
  1695. return -1;
  1696. }
  1697. /* search Vendor Specific Data Block (tag 3) */
  1698. d = edid[0x82] & 0x7f;
  1699. if (d > 4) {
  1700. int i = 0x84;
  1701. int end = 0x80 + d;
  1702. do {
  1703. u8 tag = edid[i] >> 5;
  1704. u8 len = edid[i] & 0x1f;
  1705. if ((tag == 3) && (len >= 5))
  1706. return i + 4;
  1707. i += len + 1;
  1708. } while (i < end);
  1709. }
  1710. return -1;
  1711. }
  1712. static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
  1713. {
  1714. struct adv7604_state *state = to_state(sd);
  1715. const struct adv7604_chip_info *info = state->info;
  1716. int spa_loc;
  1717. int err;
  1718. int i;
  1719. if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
  1720. return -EINVAL;
  1721. if (edid->start_block != 0)
  1722. return -EINVAL;
  1723. if (edid->blocks == 0) {
  1724. /* Disable hotplug and I2C access to EDID RAM from DDC port */
  1725. state->edid.present &= ~(1 << edid->pad);
  1726. adv7604_set_hpd(state, state->edid.present);
  1727. rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
  1728. /* Fall back to a 16:9 aspect ratio */
  1729. state->aspect_ratio.numerator = 16;
  1730. state->aspect_ratio.denominator = 9;
  1731. if (!state->edid.present)
  1732. state->edid.blocks = 0;
  1733. v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
  1734. __func__, edid->pad, state->edid.present);
  1735. return 0;
  1736. }
  1737. if (edid->blocks > 2) {
  1738. edid->blocks = 2;
  1739. return -E2BIG;
  1740. }
  1741. v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
  1742. __func__, edid->pad, state->edid.present);
  1743. /* Disable hotplug and I2C access to EDID RAM from DDC port */
  1744. cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
  1745. adv7604_set_hpd(state, 0);
  1746. rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
  1747. spa_loc = get_edid_spa_location(edid->edid);
  1748. if (spa_loc < 0)
  1749. spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
  1750. switch (edid->pad) {
  1751. case ADV7604_PAD_HDMI_PORT_A:
  1752. state->spa_port_a[0] = edid->edid[spa_loc];
  1753. state->spa_port_a[1] = edid->edid[spa_loc + 1];
  1754. break;
  1755. case ADV7604_PAD_HDMI_PORT_B:
  1756. rep_write(sd, 0x70, edid->edid[spa_loc]);
  1757. rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
  1758. break;
  1759. case ADV7604_PAD_HDMI_PORT_C:
  1760. rep_write(sd, 0x72, edid->edid[spa_loc]);
  1761. rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
  1762. break;
  1763. case ADV7604_PAD_HDMI_PORT_D:
  1764. rep_write(sd, 0x74, edid->edid[spa_loc]);
  1765. rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
  1766. break;
  1767. default:
  1768. return -EINVAL;
  1769. }
  1770. if (info->type == ADV7604) {
  1771. rep_write(sd, 0x76, spa_loc & 0xff);
  1772. rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
  1773. } else {
  1774. /* FIXME: Where is the SPA location LSB register ? */
  1775. rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
  1776. }
  1777. edid->edid[spa_loc] = state->spa_port_a[0];
  1778. edid->edid[spa_loc + 1] = state->spa_port_a[1];
  1779. memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
  1780. state->edid.blocks = edid->blocks;
  1781. state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
  1782. edid->edid[0x16]);
  1783. state->edid.present |= 1 << edid->pad;
  1784. err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
  1785. if (err < 0) {
  1786. v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
  1787. return err;
  1788. }
  1789. /* adv7604 calculates the checksums and enables I2C access to internal
  1790. EDID RAM from DDC port. */
  1791. rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
  1792. for (i = 0; i < 1000; i++) {
  1793. if (rep_read(sd, info->edid_status_reg) & state->edid.present)
  1794. break;
  1795. mdelay(1);
  1796. }
  1797. if (i == 1000) {
  1798. v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
  1799. return -EIO;
  1800. }
  1801. /* enable hotplug after 100 ms */
  1802. queue_delayed_work(state->work_queues,
  1803. &state->delayed_work_enable_hotplug, HZ / 10);
  1804. return 0;
  1805. }
  1806. /*********** avi info frame CEA-861-E **************/
  1807. static void print_avi_infoframe(struct v4l2_subdev *sd)
  1808. {
  1809. int i;
  1810. u8 buf[14];
  1811. u8 avi_len;
  1812. u8 avi_ver;
  1813. if (!is_hdmi(sd)) {
  1814. v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
  1815. return;
  1816. }
  1817. if (!(io_read(sd, 0x60) & 0x01)) {
  1818. v4l2_info(sd, "AVI infoframe not received\n");
  1819. return;
  1820. }
  1821. if (io_read(sd, 0x83) & 0x01) {
  1822. v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
  1823. io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
  1824. if (io_read(sd, 0x83) & 0x01) {
  1825. v4l2_info(sd, "AVI infoframe checksum error still present\n");
  1826. io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
  1827. }
  1828. }
  1829. avi_len = infoframe_read(sd, 0xe2);
  1830. avi_ver = infoframe_read(sd, 0xe1);
  1831. v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
  1832. avi_ver, avi_len);
  1833. if (avi_ver != 0x02)
  1834. return;
  1835. for (i = 0; i < 14; i++)
  1836. buf[i] = infoframe_read(sd, i);
  1837. v4l2_info(sd,
  1838. "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
  1839. buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
  1840. buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
  1841. }
  1842. static int adv7604_log_status(struct v4l2_subdev *sd)
  1843. {
  1844. struct adv7604_state *state = to_state(sd);
  1845. const struct adv7604_chip_info *info = state->info;
  1846. struct v4l2_dv_timings timings;
  1847. struct stdi_readback stdi;
  1848. u8 reg_io_0x02 = io_read(sd, 0x02);
  1849. u8 edid_enabled;
  1850. u8 cable_det;
  1851. static const char * const csc_coeff_sel_rb[16] = {
  1852. "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
  1853. "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
  1854. "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
  1855. "reserved", "reserved", "reserved", "reserved", "manual"
  1856. };
  1857. static const char * const input_color_space_txt[16] = {
  1858. "RGB limited range (16-235)", "RGB full range (0-255)",
  1859. "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
  1860. "xvYCC Bt.601", "xvYCC Bt.709",
  1861. "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
  1862. "invalid", "invalid", "invalid", "invalid", "invalid",
  1863. "invalid", "invalid", "automatic"
  1864. };
  1865. static const char * const rgb_quantization_range_txt[] = {
  1866. "Automatic",
  1867. "RGB limited range (16-235)",
  1868. "RGB full range (0-255)",
  1869. };
  1870. static const char * const deep_color_mode_txt[4] = {
  1871. "8-bits per channel",
  1872. "10-bits per channel",
  1873. "12-bits per channel",
  1874. "16-bits per channel (not supported)"
  1875. };
  1876. v4l2_info(sd, "-----Chip status-----\n");
  1877. v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
  1878. edid_enabled = rep_read(sd, info->edid_status_reg);
  1879. v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
  1880. ((edid_enabled & 0x01) ? "Yes" : "No"),
  1881. ((edid_enabled & 0x02) ? "Yes" : "No"),
  1882. ((edid_enabled & 0x04) ? "Yes" : "No"),
  1883. ((edid_enabled & 0x08) ? "Yes" : "No"));
  1884. v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
  1885. "enabled" : "disabled");
  1886. v4l2_info(sd, "-----Signal status-----\n");
  1887. cable_det = info->read_cable_det(sd);
  1888. v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
  1889. ((cable_det & 0x01) ? "Yes" : "No"),
  1890. ((cable_det & 0x02) ? "Yes" : "No"),
  1891. ((cable_det & 0x04) ? "Yes" : "No"),
  1892. ((cable_det & 0x08) ? "Yes" : "No"));
  1893. v4l2_info(sd, "TMDS signal detected: %s\n",
  1894. no_signal_tmds(sd) ? "false" : "true");
  1895. v4l2_info(sd, "TMDS signal locked: %s\n",
  1896. no_lock_tmds(sd) ? "false" : "true");
  1897. v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
  1898. v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
  1899. v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
  1900. v4l2_info(sd, "CP free run: %s\n",
  1901. (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
  1902. v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
  1903. io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
  1904. (io_read(sd, 0x01) & 0x70) >> 4);
  1905. v4l2_info(sd, "-----Video Timings-----\n");
  1906. if (read_stdi(sd, &stdi))
  1907. v4l2_info(sd, "STDI: not locked\n");
  1908. else
  1909. v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
  1910. stdi.lcf, stdi.bl, stdi.lcvs,
  1911. stdi.interlaced ? "interlaced" : "progressive",
  1912. stdi.hs_pol, stdi.vs_pol);
  1913. if (adv7604_query_dv_timings(sd, &timings))
  1914. v4l2_info(sd, "No video detected\n");
  1915. else
  1916. v4l2_print_dv_timings(sd->name, "Detected format: ",
  1917. &timings, true);
  1918. v4l2_print_dv_timings(sd->name, "Configured format: ",
  1919. &state->timings, true);
  1920. if (no_signal(sd))
  1921. return 0;
  1922. v4l2_info(sd, "-----Color space-----\n");
  1923. v4l2_info(sd, "RGB quantization range ctrl: %s\n",
  1924. rgb_quantization_range_txt[state->rgb_quantization_range]);
  1925. v4l2_info(sd, "Input color space: %s\n",
  1926. input_color_space_txt[reg_io_0x02 >> 4]);
  1927. v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
  1928. (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
  1929. (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
  1930. ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
  1931. "enabled" : "disabled");
  1932. v4l2_info(sd, "Color space conversion: %s\n",
  1933. csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
  1934. if (!is_digital_input(sd))
  1935. return 0;
  1936. v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
  1937. v4l2_info(sd, "Digital video port selected: %c\n",
  1938. (hdmi_read(sd, 0x00) & 0x03) + 'A');
  1939. v4l2_info(sd, "HDCP encrypted content: %s\n",
  1940. (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
  1941. v4l2_info(sd, "HDCP keys read: %s%s\n",
  1942. (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
  1943. (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
  1944. if (!is_hdmi(sd)) {
  1945. bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
  1946. bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
  1947. bool audio_mute = io_read(sd, 0x65) & 0x40;
  1948. v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
  1949. audio_pll_locked ? "locked" : "not locked",
  1950. audio_sample_packet_detect ? "detected" : "not detected",
  1951. audio_mute ? "muted" : "enabled");
  1952. if (audio_pll_locked && audio_sample_packet_detect) {
  1953. v4l2_info(sd, "Audio format: %s\n",
  1954. (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
  1955. }
  1956. v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
  1957. (hdmi_read(sd, 0x5c) << 8) +
  1958. (hdmi_read(sd, 0x5d) & 0xf0));
  1959. v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
  1960. (hdmi_read(sd, 0x5e) << 8) +
  1961. hdmi_read(sd, 0x5f));
  1962. v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
  1963. v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
  1964. print_avi_infoframe(sd);
  1965. }
  1966. return 0;
  1967. }
  1968. /* ----------------------------------------------------------------------- */
  1969. static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
  1970. .s_ctrl = adv7604_s_ctrl,
  1971. };
  1972. static const struct v4l2_subdev_core_ops adv7604_core_ops = {
  1973. .log_status = adv7604_log_status,
  1974. .interrupt_service_routine = adv7604_isr,
  1975. #ifdef CONFIG_VIDEO_ADV_DEBUG
  1976. .g_register = adv7604_g_register,
  1977. .s_register = adv7604_s_register,
  1978. #endif
  1979. };
  1980. static const struct v4l2_subdev_video_ops adv7604_video_ops = {
  1981. .s_routing = adv7604_s_routing,
  1982. .g_input_status = adv7604_g_input_status,
  1983. .s_dv_timings = adv7604_s_dv_timings,
  1984. .g_dv_timings = adv7604_g_dv_timings,
  1985. .query_dv_timings = adv7604_query_dv_timings,
  1986. };
  1987. static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
  1988. .enum_mbus_code = adv7604_enum_mbus_code,
  1989. .get_fmt = adv7604_get_format,
  1990. .set_fmt = adv7604_set_format,
  1991. .get_edid = adv7604_get_edid,
  1992. .set_edid = adv7604_set_edid,
  1993. .dv_timings_cap = adv7604_dv_timings_cap,
  1994. .enum_dv_timings = adv7604_enum_dv_timings,
  1995. };
  1996. static const struct v4l2_subdev_ops adv7604_ops = {
  1997. .core = &adv7604_core_ops,
  1998. .video = &adv7604_video_ops,
  1999. .pad = &adv7604_pad_ops,
  2000. };
  2001. /* -------------------------- custom ctrls ---------------------------------- */
  2002. static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
  2003. .ops = &adv7604_ctrl_ops,
  2004. .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
  2005. .name = "Analog Sampling Phase",
  2006. .type = V4L2_CTRL_TYPE_INTEGER,
  2007. .min = 0,
  2008. .max = 0x1f,
  2009. .step = 1,
  2010. .def = 0,
  2011. };
  2012. static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
  2013. .ops = &adv7604_ctrl_ops,
  2014. .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
  2015. .name = "Free Running Color, Manual",
  2016. .type = V4L2_CTRL_TYPE_BOOLEAN,
  2017. .min = false,
  2018. .max = true,
  2019. .step = 1,
  2020. .def = false,
  2021. };
  2022. static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
  2023. .ops = &adv7604_ctrl_ops,
  2024. .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
  2025. .name = "Free Running Color",
  2026. .type = V4L2_CTRL_TYPE_INTEGER,
  2027. .min = 0x0,
  2028. .max = 0xffffff,
  2029. .step = 0x1,
  2030. .def = 0x0,
  2031. };
  2032. /* ----------------------------------------------------------------------- */
  2033. static int adv7604_core_init(struct v4l2_subdev *sd)
  2034. {
  2035. struct adv7604_state *state = to_state(sd);
  2036. const struct adv7604_chip_info *info = state->info;
  2037. struct adv7604_platform_data *pdata = &state->pdata;
  2038. hdmi_write(sd, 0x48,
  2039. (pdata->disable_pwrdnb ? 0x80 : 0) |
  2040. (pdata->disable_cable_det_rst ? 0x40 : 0));
  2041. disable_input(sd);
  2042. if (pdata->default_input >= 0 &&
  2043. pdata->default_input < state->source_pad) {
  2044. state->selected_input = pdata->default_input;
  2045. select_input(sd);
  2046. enable_input(sd);
  2047. }
  2048. /* power */
  2049. io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
  2050. io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
  2051. cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
  2052. /* video format */
  2053. io_write_clr_set(sd, 0x02, 0x0f,
  2054. pdata->alt_gamma << 3 |
  2055. pdata->op_656_range << 2 |
  2056. pdata->alt_data_sat << 0);
  2057. io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
  2058. pdata->insert_av_codes << 2 |
  2059. pdata->replicate_av_codes << 1);
  2060. adv7604_setup_format(state);
  2061. cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
  2062. /* VS, HS polarities */
  2063. io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
  2064. pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
  2065. /* Adjust drive strength */
  2066. io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
  2067. pdata->dr_str_clk << 2 |
  2068. pdata->dr_str_sync);
  2069. cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
  2070. cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
  2071. cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
  2072. ADI recommended setting [REF_01, c. 2.3.3] */
  2073. cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
  2074. ADI recommended setting [REF_01, c. 2.3.3] */
  2075. cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
  2076. for digital formats */
  2077. /* HDMI audio */
  2078. hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
  2079. hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
  2080. hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
  2081. /* TODO from platform data */
  2082. afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
  2083. if (adv7604_has_afe(state)) {
  2084. afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
  2085. io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
  2086. }
  2087. /* interrupts */
  2088. io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
  2089. io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
  2090. io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
  2091. io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
  2092. info->setup_irqs(sd);
  2093. return v4l2_ctrl_handler_setup(sd->ctrl_handler);
  2094. }
  2095. static void adv7604_setup_irqs(struct v4l2_subdev *sd)
  2096. {
  2097. io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
  2098. }
  2099. static void adv7611_setup_irqs(struct v4l2_subdev *sd)
  2100. {
  2101. io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
  2102. }
  2103. static void adv7604_unregister_clients(struct adv7604_state *state)
  2104. {
  2105. unsigned int i;
  2106. for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
  2107. if (state->i2c_clients[i])
  2108. i2c_unregister_device(state->i2c_clients[i]);
  2109. }
  2110. }
  2111. static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
  2112. u8 addr, u8 io_reg)
  2113. {
  2114. struct i2c_client *client = v4l2_get_subdevdata(sd);
  2115. if (addr)
  2116. io_write(sd, io_reg, addr << 1);
  2117. return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
  2118. }
  2119. static const struct adv7604_reg_seq adv7604_recommended_settings_afe[] = {
  2120. /* reset ADI recommended settings for HDMI: */
  2121. /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
  2122. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
  2123. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
  2124. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
  2125. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
  2126. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
  2127. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
  2128. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
  2129. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
  2130. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
  2131. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
  2132. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
  2133. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
  2134. /* set ADI recommended settings for digitizer */
  2135. /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
  2136. { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
  2137. { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
  2138. { ADV7604_REG(ADV7604_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
  2139. { ADV7604_REG(ADV7604_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
  2140. { ADV7604_REG(ADV7604_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
  2141. { ADV7604_REG_SEQ_TERM, 0 },
  2142. };
  2143. static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi[] = {
  2144. /* set ADI recommended settings for HDMI: */
  2145. /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
  2146. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
  2147. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
  2148. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
  2149. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
  2150. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
  2151. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
  2152. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
  2153. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
  2154. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
  2155. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
  2156. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
  2157. /* reset ADI recommended settings for digitizer */
  2158. /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
  2159. { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
  2160. { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
  2161. { ADV7604_REG_SEQ_TERM, 0 },
  2162. };
  2163. static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi[] = {
  2164. { ADV7604_REG(ADV7604_PAGE_CP, 0x6c), 0x00 },
  2165. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x6f), 0x0c },
  2166. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x87), 0x70 },
  2167. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xda },
  2168. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x01 },
  2169. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x03), 0x98 },
  2170. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4c), 0x44 },
  2171. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x04 },
  2172. { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x1e },
  2173. { ADV7604_REG_SEQ_TERM, 0 },
  2174. };
  2175. static const struct adv7604_chip_info adv7604_chip_info[] = {
  2176. [ADV7604] = {
  2177. .type = ADV7604,
  2178. .has_afe = true,
  2179. .max_port = ADV7604_PAD_VGA_COMP,
  2180. .num_dv_ports = 4,
  2181. .edid_enable_reg = 0x77,
  2182. .edid_status_reg = 0x7d,
  2183. .lcf_reg = 0xb3,
  2184. .tdms_lock_mask = 0xe0,
  2185. .cable_det_mask = 0x1e,
  2186. .fmt_change_digital_mask = 0xc1,
  2187. .formats = adv7604_formats,
  2188. .nformats = ARRAY_SIZE(adv7604_formats),
  2189. .set_termination = adv7604_set_termination,
  2190. .setup_irqs = adv7604_setup_irqs,
  2191. .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
  2192. .read_cable_det = adv7604_read_cable_det,
  2193. .recommended_settings = {
  2194. [0] = adv7604_recommended_settings_afe,
  2195. [1] = adv7604_recommended_settings_hdmi,
  2196. },
  2197. .num_recommended_settings = {
  2198. [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
  2199. [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
  2200. },
  2201. .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
  2202. BIT(ADV7604_PAGE_CEC) | BIT(ADV7604_PAGE_INFOFRAME) |
  2203. BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
  2204. BIT(ADV7604_PAGE_AFE) | BIT(ADV7604_PAGE_REP) |
  2205. BIT(ADV7604_PAGE_EDID) | BIT(ADV7604_PAGE_HDMI) |
  2206. BIT(ADV7604_PAGE_TEST) | BIT(ADV7604_PAGE_CP) |
  2207. BIT(ADV7604_PAGE_VDP),
  2208. },
  2209. [ADV7611] = {
  2210. .type = ADV7611,
  2211. .has_afe = false,
  2212. .max_port = ADV7604_PAD_HDMI_PORT_A,
  2213. .num_dv_ports = 1,
  2214. .edid_enable_reg = 0x74,
  2215. .edid_status_reg = 0x76,
  2216. .lcf_reg = 0xa3,
  2217. .tdms_lock_mask = 0x43,
  2218. .cable_det_mask = 0x01,
  2219. .fmt_change_digital_mask = 0x03,
  2220. .formats = adv7611_formats,
  2221. .nformats = ARRAY_SIZE(adv7611_formats),
  2222. .set_termination = adv7611_set_termination,
  2223. .setup_irqs = adv7611_setup_irqs,
  2224. .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
  2225. .read_cable_det = adv7611_read_cable_det,
  2226. .recommended_settings = {
  2227. [1] = adv7611_recommended_settings_hdmi,
  2228. },
  2229. .num_recommended_settings = {
  2230. [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
  2231. },
  2232. .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_CEC) |
  2233. BIT(ADV7604_PAGE_INFOFRAME) | BIT(ADV7604_PAGE_AFE) |
  2234. BIT(ADV7604_PAGE_REP) | BIT(ADV7604_PAGE_EDID) |
  2235. BIT(ADV7604_PAGE_HDMI) | BIT(ADV7604_PAGE_CP),
  2236. },
  2237. };
  2238. static struct i2c_device_id adv7604_i2c_id[] = {
  2239. { "adv7604", (kernel_ulong_t)&adv7604_chip_info[ADV7604] },
  2240. { "adv7611", (kernel_ulong_t)&adv7604_chip_info[ADV7611] },
  2241. { }
  2242. };
  2243. MODULE_DEVICE_TABLE(i2c, adv7604_i2c_id);
  2244. static struct of_device_id adv7604_of_id[] __maybe_unused = {
  2245. { .compatible = "adi,adv7611", .data = &adv7604_chip_info[ADV7611] },
  2246. { }
  2247. };
  2248. MODULE_DEVICE_TABLE(of, adv7604_of_id);
  2249. static int adv7604_parse_dt(struct adv7604_state *state)
  2250. {
  2251. struct v4l2_of_endpoint bus_cfg;
  2252. struct device_node *endpoint;
  2253. struct device_node *np;
  2254. unsigned int flags;
  2255. np = state->i2c_clients[ADV7604_PAGE_IO]->dev.of_node;
  2256. /* Parse the endpoint. */
  2257. endpoint = of_graph_get_next_endpoint(np, NULL);
  2258. if (!endpoint)
  2259. return -EINVAL;
  2260. v4l2_of_parse_endpoint(endpoint, &bus_cfg);
  2261. of_node_put(endpoint);
  2262. flags = bus_cfg.bus.parallel.flags;
  2263. if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
  2264. state->pdata.inv_hs_pol = 1;
  2265. if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
  2266. state->pdata.inv_vs_pol = 1;
  2267. if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
  2268. state->pdata.inv_llc_pol = 1;
  2269. if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
  2270. state->pdata.insert_av_codes = 1;
  2271. state->pdata.op_656_range = 1;
  2272. }
  2273. /* Disable the interrupt for now as no DT-based board uses it. */
  2274. state->pdata.int1_config = ADV7604_INT1_CONFIG_DISABLED;
  2275. /* Use the default I2C addresses. */
  2276. state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
  2277. state->pdata.i2c_addresses[ADV7604_PAGE_CEC] = 0x40;
  2278. state->pdata.i2c_addresses[ADV7604_PAGE_INFOFRAME] = 0x3e;
  2279. state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
  2280. state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
  2281. state->pdata.i2c_addresses[ADV7604_PAGE_AFE] = 0x26;
  2282. state->pdata.i2c_addresses[ADV7604_PAGE_REP] = 0x32;
  2283. state->pdata.i2c_addresses[ADV7604_PAGE_EDID] = 0x36;
  2284. state->pdata.i2c_addresses[ADV7604_PAGE_HDMI] = 0x34;
  2285. state->pdata.i2c_addresses[ADV7604_PAGE_TEST] = 0x30;
  2286. state->pdata.i2c_addresses[ADV7604_PAGE_CP] = 0x22;
  2287. state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
  2288. /* Hardcode the remaining platform data fields. */
  2289. state->pdata.disable_pwrdnb = 0;
  2290. state->pdata.disable_cable_det_rst = 0;
  2291. state->pdata.default_input = -1;
  2292. state->pdata.blank_data = 1;
  2293. state->pdata.alt_data_sat = 1;
  2294. state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
  2295. state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
  2296. return 0;
  2297. }
  2298. static int adv7604_probe(struct i2c_client *client,
  2299. const struct i2c_device_id *id)
  2300. {
  2301. static const struct v4l2_dv_timings cea640x480 =
  2302. V4L2_DV_BT_CEA_640X480P59_94;
  2303. struct adv7604_state *state;
  2304. struct v4l2_ctrl_handler *hdl;
  2305. struct v4l2_subdev *sd;
  2306. unsigned int i;
  2307. u16 val;
  2308. int err;
  2309. /* Check if the adapter supports the needed features */
  2310. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  2311. return -EIO;
  2312. v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
  2313. client->addr << 1);
  2314. state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
  2315. if (!state) {
  2316. v4l_err(client, "Could not allocate adv7604_state memory!\n");
  2317. return -ENOMEM;
  2318. }
  2319. state->i2c_clients[ADV7604_PAGE_IO] = client;
  2320. /* initialize variables */
  2321. state->restart_stdi_once = true;
  2322. state->selected_input = ~0;
  2323. if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
  2324. const struct of_device_id *oid;
  2325. oid = of_match_node(adv7604_of_id, client->dev.of_node);
  2326. state->info = oid->data;
  2327. err = adv7604_parse_dt(state);
  2328. if (err < 0) {
  2329. v4l_err(client, "DT parsing error\n");
  2330. return err;
  2331. }
  2332. } else if (client->dev.platform_data) {
  2333. struct adv7604_platform_data *pdata = client->dev.platform_data;
  2334. state->info = (const struct adv7604_chip_info *)id->driver_data;
  2335. state->pdata = *pdata;
  2336. } else {
  2337. v4l_err(client, "No platform data!\n");
  2338. return -ENODEV;
  2339. }
  2340. /* Request GPIOs. */
  2341. for (i = 0; i < state->info->num_dv_ports; ++i) {
  2342. state->hpd_gpio[i] =
  2343. devm_gpiod_get_index(&client->dev, "hpd", i);
  2344. if (IS_ERR(state->hpd_gpio[i]))
  2345. continue;
  2346. gpiod_direction_output(state->hpd_gpio[i], 0);
  2347. v4l_info(client, "Handling HPD %u GPIO\n", i);
  2348. }
  2349. state->timings = cea640x480;
  2350. state->format = adv7604_format_info(state, V4L2_MBUS_FMT_YUYV8_2X8);
  2351. sd = &state->sd;
  2352. v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
  2353. snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
  2354. id->name, i2c_adapter_id(client->adapter),
  2355. client->addr);
  2356. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  2357. /*
  2358. * Verify that the chip is present. On ADV7604 the RD_INFO register only
  2359. * identifies the revision, while on ADV7611 it identifies the model as
  2360. * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
  2361. */
  2362. if (state->info->type == ADV7604) {
  2363. val = adv_smbus_read_byte_data_check(client, 0xfb, false);
  2364. if (val != 0x68) {
  2365. v4l2_info(sd, "not an adv7604 on address 0x%x\n",
  2366. client->addr << 1);
  2367. return -ENODEV;
  2368. }
  2369. } else {
  2370. val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8)
  2371. | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0);
  2372. if (val != 0x2051) {
  2373. v4l2_info(sd, "not an adv7611 on address 0x%x\n",
  2374. client->addr << 1);
  2375. return -ENODEV;
  2376. }
  2377. }
  2378. /* control handlers */
  2379. hdl = &state->hdl;
  2380. v4l2_ctrl_handler_init(hdl, adv7604_has_afe(state) ? 9 : 8);
  2381. v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
  2382. V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
  2383. v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
  2384. V4L2_CID_CONTRAST, 0, 255, 1, 128);
  2385. v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
  2386. V4L2_CID_SATURATION, 0, 255, 1, 128);
  2387. v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
  2388. V4L2_CID_HUE, 0, 128, 1, 0);
  2389. /* private controls */
  2390. state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
  2391. V4L2_CID_DV_RX_POWER_PRESENT, 0,
  2392. (1 << state->info->num_dv_ports) - 1, 0, 0);
  2393. state->rgb_quantization_range_ctrl =
  2394. v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
  2395. V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
  2396. 0, V4L2_DV_RGB_RANGE_AUTO);
  2397. /* custom controls */
  2398. if (adv7604_has_afe(state))
  2399. state->analog_sampling_phase_ctrl =
  2400. v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
  2401. state->free_run_color_manual_ctrl =
  2402. v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
  2403. state->free_run_color_ctrl =
  2404. v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
  2405. sd->ctrl_handler = hdl;
  2406. if (hdl->error) {
  2407. err = hdl->error;
  2408. goto err_hdl;
  2409. }
  2410. state->detect_tx_5v_ctrl->is_private = true;
  2411. state->rgb_quantization_range_ctrl->is_private = true;
  2412. if (adv7604_has_afe(state))
  2413. state->analog_sampling_phase_ctrl->is_private = true;
  2414. state->free_run_color_manual_ctrl->is_private = true;
  2415. state->free_run_color_ctrl->is_private = true;
  2416. if (adv7604_s_detect_tx_5v_ctrl(sd)) {
  2417. err = -ENODEV;
  2418. goto err_hdl;
  2419. }
  2420. for (i = 1; i < ADV7604_PAGE_MAX; ++i) {
  2421. if (!(BIT(i) & state->info->page_mask))
  2422. continue;
  2423. state->i2c_clients[i] =
  2424. adv7604_dummy_client(sd, state->pdata.i2c_addresses[i],
  2425. 0xf2 + i);
  2426. if (state->i2c_clients[i] == NULL) {
  2427. err = -ENOMEM;
  2428. v4l2_err(sd, "failed to create i2c client %u\n", i);
  2429. goto err_i2c;
  2430. }
  2431. }
  2432. /* work queues */
  2433. state->work_queues = create_singlethread_workqueue(client->name);
  2434. if (!state->work_queues) {
  2435. v4l2_err(sd, "Could not create work queue\n");
  2436. err = -ENOMEM;
  2437. goto err_i2c;
  2438. }
  2439. INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
  2440. adv7604_delayed_work_enable_hotplug);
  2441. state->source_pad = state->info->num_dv_ports
  2442. + (state->info->has_afe ? 2 : 0);
  2443. for (i = 0; i < state->source_pad; ++i)
  2444. state->pads[i].flags = MEDIA_PAD_FL_SINK;
  2445. state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
  2446. err = media_entity_init(&sd->entity, state->source_pad + 1,
  2447. state->pads, 0);
  2448. if (err)
  2449. goto err_work_queues;
  2450. err = adv7604_core_init(sd);
  2451. if (err)
  2452. goto err_entity;
  2453. v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
  2454. client->addr << 1, client->adapter->name);
  2455. err = v4l2_async_register_subdev(sd);
  2456. if (err)
  2457. goto err_entity;
  2458. return 0;
  2459. err_entity:
  2460. media_entity_cleanup(&sd->entity);
  2461. err_work_queues:
  2462. cancel_delayed_work(&state->delayed_work_enable_hotplug);
  2463. destroy_workqueue(state->work_queues);
  2464. err_i2c:
  2465. adv7604_unregister_clients(state);
  2466. err_hdl:
  2467. v4l2_ctrl_handler_free(hdl);
  2468. return err;
  2469. }
  2470. /* ----------------------------------------------------------------------- */
  2471. static int adv7604_remove(struct i2c_client *client)
  2472. {
  2473. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  2474. struct adv7604_state *state = to_state(sd);
  2475. cancel_delayed_work(&state->delayed_work_enable_hotplug);
  2476. destroy_workqueue(state->work_queues);
  2477. v4l2_async_unregister_subdev(sd);
  2478. v4l2_device_unregister_subdev(sd);
  2479. media_entity_cleanup(&sd->entity);
  2480. adv7604_unregister_clients(to_state(sd));
  2481. v4l2_ctrl_handler_free(sd->ctrl_handler);
  2482. return 0;
  2483. }
  2484. /* ----------------------------------------------------------------------- */
  2485. static struct i2c_driver adv7604_driver = {
  2486. .driver = {
  2487. .owner = THIS_MODULE,
  2488. .name = "adv7604",
  2489. .of_match_table = of_match_ptr(adv7604_of_id),
  2490. },
  2491. .probe = adv7604_probe,
  2492. .remove = adv7604_remove,
  2493. .id_table = adv7604_i2c_id,
  2494. };
  2495. module_i2c_driver(adv7604_driver);