ocrdma_verbs.c 80 KB

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  1. /*******************************************************************
  2. * This file is part of the Emulex RoCE Device Driver for *
  3. * RoCE (RDMA over Converged Ethernet) adapters. *
  4. * Copyright (C) 2008-2012 Emulex. All rights reserved. *
  5. * EMULEX and SLI are trademarks of Emulex. *
  6. * www.emulex.com *
  7. * *
  8. * This program is free software; you can redistribute it and/or *
  9. * modify it under the terms of version 2 of the GNU General *
  10. * Public License as published by the Free Software Foundation. *
  11. * This program is distributed in the hope that it will be useful. *
  12. * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
  13. * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
  14. * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
  15. * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16. * TO BE LEGALLY INVALID. See the GNU General Public License for *
  17. * more details, a copy of which can be found in the file COPYING *
  18. * included with this package. *
  19. *
  20. * Contact Information:
  21. * linux-drivers@emulex.com
  22. *
  23. * Emulex
  24. * 3333 Susan Street
  25. * Costa Mesa, CA 92626
  26. *******************************************************************/
  27. #include <linux/dma-mapping.h>
  28. #include <rdma/ib_verbs.h>
  29. #include <rdma/ib_user_verbs.h>
  30. #include <rdma/iw_cm.h>
  31. #include <rdma/ib_umem.h>
  32. #include <rdma/ib_addr.h>
  33. #include "ocrdma.h"
  34. #include "ocrdma_hw.h"
  35. #include "ocrdma_verbs.h"
  36. #include "ocrdma_abi.h"
  37. int ocrdma_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
  38. {
  39. if (index > 1)
  40. return -EINVAL;
  41. *pkey = 0xffff;
  42. return 0;
  43. }
  44. int ocrdma_query_gid(struct ib_device *ibdev, u8 port,
  45. int index, union ib_gid *sgid)
  46. {
  47. struct ocrdma_dev *dev;
  48. dev = get_ocrdma_dev(ibdev);
  49. memset(sgid, 0, sizeof(*sgid));
  50. if (index > OCRDMA_MAX_SGID)
  51. return -EINVAL;
  52. memcpy(sgid, &dev->sgid_tbl[index], sizeof(*sgid));
  53. return 0;
  54. }
  55. int ocrdma_query_device(struct ib_device *ibdev, struct ib_device_attr *attr)
  56. {
  57. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  58. memset(attr, 0, sizeof *attr);
  59. memcpy(&attr->fw_ver, &dev->attr.fw_ver[0],
  60. min(sizeof(dev->attr.fw_ver), sizeof(attr->fw_ver)));
  61. ocrdma_get_guid(dev, (u8 *)&attr->sys_image_guid);
  62. attr->max_mr_size = ~0ull;
  63. attr->page_size_cap = 0xffff000;
  64. attr->vendor_id = dev->nic_info.pdev->vendor;
  65. attr->vendor_part_id = dev->nic_info.pdev->device;
  66. attr->hw_ver = 0;
  67. attr->max_qp = dev->attr.max_qp;
  68. attr->max_ah = OCRDMA_MAX_AH;
  69. attr->max_qp_wr = dev->attr.max_wqe;
  70. attr->device_cap_flags = IB_DEVICE_CURR_QP_STATE_MOD |
  71. IB_DEVICE_RC_RNR_NAK_GEN |
  72. IB_DEVICE_SHUTDOWN_PORT |
  73. IB_DEVICE_SYS_IMAGE_GUID |
  74. IB_DEVICE_LOCAL_DMA_LKEY |
  75. IB_DEVICE_MEM_MGT_EXTENSIONS;
  76. attr->max_sge = min(dev->attr.max_send_sge, dev->attr.max_srq_sge);
  77. attr->max_sge_rd = 0;
  78. attr->max_cq = dev->attr.max_cq;
  79. attr->max_cqe = dev->attr.max_cqe;
  80. attr->max_mr = dev->attr.max_mr;
  81. attr->max_mw = dev->attr.max_mw;
  82. attr->max_pd = dev->attr.max_pd;
  83. attr->atomic_cap = 0;
  84. attr->max_fmr = 0;
  85. attr->max_map_per_fmr = 0;
  86. attr->max_qp_rd_atom =
  87. min(dev->attr.max_ord_per_qp, dev->attr.max_ird_per_qp);
  88. attr->max_qp_init_rd_atom = dev->attr.max_ord_per_qp;
  89. attr->max_srq = dev->attr.max_srq;
  90. attr->max_srq_sge = dev->attr.max_srq_sge;
  91. attr->max_srq_wr = dev->attr.max_rqe;
  92. attr->local_ca_ack_delay = dev->attr.local_ca_ack_delay;
  93. attr->max_fast_reg_page_list_len = 0;
  94. attr->max_pkeys = 1;
  95. return 0;
  96. }
  97. static inline void get_link_speed_and_width(struct ocrdma_dev *dev,
  98. u8 *ib_speed, u8 *ib_width)
  99. {
  100. int status;
  101. u8 speed;
  102. status = ocrdma_mbx_get_link_speed(dev, &speed);
  103. if (status)
  104. speed = OCRDMA_PHYS_LINK_SPEED_ZERO;
  105. switch (speed) {
  106. case OCRDMA_PHYS_LINK_SPEED_1GBPS:
  107. *ib_speed = IB_SPEED_SDR;
  108. *ib_width = IB_WIDTH_1X;
  109. break;
  110. case OCRDMA_PHYS_LINK_SPEED_10GBPS:
  111. *ib_speed = IB_SPEED_QDR;
  112. *ib_width = IB_WIDTH_1X;
  113. break;
  114. case OCRDMA_PHYS_LINK_SPEED_20GBPS:
  115. *ib_speed = IB_SPEED_DDR;
  116. *ib_width = IB_WIDTH_4X;
  117. break;
  118. case OCRDMA_PHYS_LINK_SPEED_40GBPS:
  119. *ib_speed = IB_SPEED_QDR;
  120. *ib_width = IB_WIDTH_4X;
  121. break;
  122. default:
  123. /* Unsupported */
  124. *ib_speed = IB_SPEED_SDR;
  125. *ib_width = IB_WIDTH_1X;
  126. }
  127. }
  128. int ocrdma_query_port(struct ib_device *ibdev,
  129. u8 port, struct ib_port_attr *props)
  130. {
  131. enum ib_port_state port_state;
  132. struct ocrdma_dev *dev;
  133. struct net_device *netdev;
  134. dev = get_ocrdma_dev(ibdev);
  135. if (port > 1) {
  136. pr_err("%s(%d) invalid_port=0x%x\n", __func__,
  137. dev->id, port);
  138. return -EINVAL;
  139. }
  140. netdev = dev->nic_info.netdev;
  141. if (netif_running(netdev) && netif_oper_up(netdev)) {
  142. port_state = IB_PORT_ACTIVE;
  143. props->phys_state = 5;
  144. } else {
  145. port_state = IB_PORT_DOWN;
  146. props->phys_state = 3;
  147. }
  148. props->max_mtu = IB_MTU_4096;
  149. props->active_mtu = iboe_get_mtu(netdev->mtu);
  150. props->lid = 0;
  151. props->lmc = 0;
  152. props->sm_lid = 0;
  153. props->sm_sl = 0;
  154. props->state = port_state;
  155. props->port_cap_flags =
  156. IB_PORT_CM_SUP |
  157. IB_PORT_REINIT_SUP |
  158. IB_PORT_DEVICE_MGMT_SUP | IB_PORT_VENDOR_CLASS_SUP | IB_PORT_IP_BASED_GIDS;
  159. props->gid_tbl_len = OCRDMA_MAX_SGID;
  160. props->pkey_tbl_len = 1;
  161. props->bad_pkey_cntr = 0;
  162. props->qkey_viol_cntr = 0;
  163. get_link_speed_and_width(dev, &props->active_speed,
  164. &props->active_width);
  165. props->max_msg_sz = 0x80000000;
  166. props->max_vl_num = 4;
  167. return 0;
  168. }
  169. int ocrdma_modify_port(struct ib_device *ibdev, u8 port, int mask,
  170. struct ib_port_modify *props)
  171. {
  172. struct ocrdma_dev *dev;
  173. dev = get_ocrdma_dev(ibdev);
  174. if (port > 1) {
  175. pr_err("%s(%d) invalid_port=0x%x\n", __func__, dev->id, port);
  176. return -EINVAL;
  177. }
  178. return 0;
  179. }
  180. static int ocrdma_add_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  181. unsigned long len)
  182. {
  183. struct ocrdma_mm *mm;
  184. mm = kzalloc(sizeof(*mm), GFP_KERNEL);
  185. if (mm == NULL)
  186. return -ENOMEM;
  187. mm->key.phy_addr = phy_addr;
  188. mm->key.len = len;
  189. INIT_LIST_HEAD(&mm->entry);
  190. mutex_lock(&uctx->mm_list_lock);
  191. list_add_tail(&mm->entry, &uctx->mm_head);
  192. mutex_unlock(&uctx->mm_list_lock);
  193. return 0;
  194. }
  195. static void ocrdma_del_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  196. unsigned long len)
  197. {
  198. struct ocrdma_mm *mm, *tmp;
  199. mutex_lock(&uctx->mm_list_lock);
  200. list_for_each_entry_safe(mm, tmp, &uctx->mm_head, entry) {
  201. if (len != mm->key.len && phy_addr != mm->key.phy_addr)
  202. continue;
  203. list_del(&mm->entry);
  204. kfree(mm);
  205. break;
  206. }
  207. mutex_unlock(&uctx->mm_list_lock);
  208. }
  209. static bool ocrdma_search_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  210. unsigned long len)
  211. {
  212. bool found = false;
  213. struct ocrdma_mm *mm;
  214. mutex_lock(&uctx->mm_list_lock);
  215. list_for_each_entry(mm, &uctx->mm_head, entry) {
  216. if (len != mm->key.len && phy_addr != mm->key.phy_addr)
  217. continue;
  218. found = true;
  219. break;
  220. }
  221. mutex_unlock(&uctx->mm_list_lock);
  222. return found;
  223. }
  224. static struct ocrdma_pd *_ocrdma_alloc_pd(struct ocrdma_dev *dev,
  225. struct ocrdma_ucontext *uctx,
  226. struct ib_udata *udata)
  227. {
  228. struct ocrdma_pd *pd = NULL;
  229. int status = 0;
  230. pd = kzalloc(sizeof(*pd), GFP_KERNEL);
  231. if (!pd)
  232. return ERR_PTR(-ENOMEM);
  233. if (udata && uctx) {
  234. pd->dpp_enabled =
  235. ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R;
  236. pd->num_dpp_qp =
  237. pd->dpp_enabled ? OCRDMA_PD_MAX_DPP_ENABLED_QP : 0;
  238. }
  239. retry:
  240. status = ocrdma_mbx_alloc_pd(dev, pd);
  241. if (status) {
  242. if (pd->dpp_enabled) {
  243. pd->dpp_enabled = false;
  244. pd->num_dpp_qp = 0;
  245. goto retry;
  246. } else {
  247. kfree(pd);
  248. return ERR_PTR(status);
  249. }
  250. }
  251. return pd;
  252. }
  253. static inline int is_ucontext_pd(struct ocrdma_ucontext *uctx,
  254. struct ocrdma_pd *pd)
  255. {
  256. return (uctx->cntxt_pd == pd ? true : false);
  257. }
  258. static int _ocrdma_dealloc_pd(struct ocrdma_dev *dev,
  259. struct ocrdma_pd *pd)
  260. {
  261. int status = 0;
  262. status = ocrdma_mbx_dealloc_pd(dev, pd);
  263. kfree(pd);
  264. return status;
  265. }
  266. static int ocrdma_alloc_ucontext_pd(struct ocrdma_dev *dev,
  267. struct ocrdma_ucontext *uctx,
  268. struct ib_udata *udata)
  269. {
  270. int status = 0;
  271. uctx->cntxt_pd = _ocrdma_alloc_pd(dev, uctx, udata);
  272. if (IS_ERR(uctx->cntxt_pd)) {
  273. status = PTR_ERR(uctx->cntxt_pd);
  274. uctx->cntxt_pd = NULL;
  275. goto err;
  276. }
  277. uctx->cntxt_pd->uctx = uctx;
  278. uctx->cntxt_pd->ibpd.device = &dev->ibdev;
  279. err:
  280. return status;
  281. }
  282. static int ocrdma_dealloc_ucontext_pd(struct ocrdma_ucontext *uctx)
  283. {
  284. int status = 0;
  285. struct ocrdma_pd *pd = uctx->cntxt_pd;
  286. struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
  287. BUG_ON(uctx->pd_in_use);
  288. uctx->cntxt_pd = NULL;
  289. status = _ocrdma_dealloc_pd(dev, pd);
  290. return status;
  291. }
  292. static struct ocrdma_pd *ocrdma_get_ucontext_pd(struct ocrdma_ucontext *uctx)
  293. {
  294. struct ocrdma_pd *pd = NULL;
  295. mutex_lock(&uctx->mm_list_lock);
  296. if (!uctx->pd_in_use) {
  297. uctx->pd_in_use = true;
  298. pd = uctx->cntxt_pd;
  299. }
  300. mutex_unlock(&uctx->mm_list_lock);
  301. return pd;
  302. }
  303. static void ocrdma_release_ucontext_pd(struct ocrdma_ucontext *uctx)
  304. {
  305. mutex_lock(&uctx->mm_list_lock);
  306. uctx->pd_in_use = false;
  307. mutex_unlock(&uctx->mm_list_lock);
  308. }
  309. struct ib_ucontext *ocrdma_alloc_ucontext(struct ib_device *ibdev,
  310. struct ib_udata *udata)
  311. {
  312. int status;
  313. struct ocrdma_ucontext *ctx;
  314. struct ocrdma_alloc_ucontext_resp resp;
  315. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  316. struct pci_dev *pdev = dev->nic_info.pdev;
  317. u32 map_len = roundup(sizeof(u32) * 2048, PAGE_SIZE);
  318. if (!udata)
  319. return ERR_PTR(-EFAULT);
  320. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  321. if (!ctx)
  322. return ERR_PTR(-ENOMEM);
  323. INIT_LIST_HEAD(&ctx->mm_head);
  324. mutex_init(&ctx->mm_list_lock);
  325. ctx->ah_tbl.va = dma_alloc_coherent(&pdev->dev, map_len,
  326. &ctx->ah_tbl.pa, GFP_KERNEL);
  327. if (!ctx->ah_tbl.va) {
  328. kfree(ctx);
  329. return ERR_PTR(-ENOMEM);
  330. }
  331. memset(ctx->ah_tbl.va, 0, map_len);
  332. ctx->ah_tbl.len = map_len;
  333. memset(&resp, 0, sizeof(resp));
  334. resp.ah_tbl_len = ctx->ah_tbl.len;
  335. resp.ah_tbl_page = ctx->ah_tbl.pa;
  336. status = ocrdma_add_mmap(ctx, resp.ah_tbl_page, resp.ah_tbl_len);
  337. if (status)
  338. goto map_err;
  339. status = ocrdma_alloc_ucontext_pd(dev, ctx, udata);
  340. if (status)
  341. goto pd_err;
  342. resp.dev_id = dev->id;
  343. resp.max_inline_data = dev->attr.max_inline_data;
  344. resp.wqe_size = dev->attr.wqe_size;
  345. resp.rqe_size = dev->attr.rqe_size;
  346. resp.dpp_wqe_size = dev->attr.wqe_size;
  347. memcpy(resp.fw_ver, dev->attr.fw_ver, sizeof(resp.fw_ver));
  348. status = ib_copy_to_udata(udata, &resp, sizeof(resp));
  349. if (status)
  350. goto cpy_err;
  351. return &ctx->ibucontext;
  352. cpy_err:
  353. pd_err:
  354. ocrdma_del_mmap(ctx, ctx->ah_tbl.pa, ctx->ah_tbl.len);
  355. map_err:
  356. dma_free_coherent(&pdev->dev, ctx->ah_tbl.len, ctx->ah_tbl.va,
  357. ctx->ah_tbl.pa);
  358. kfree(ctx);
  359. return ERR_PTR(status);
  360. }
  361. int ocrdma_dealloc_ucontext(struct ib_ucontext *ibctx)
  362. {
  363. int status = 0;
  364. struct ocrdma_mm *mm, *tmp;
  365. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ibctx);
  366. struct ocrdma_dev *dev = get_ocrdma_dev(ibctx->device);
  367. struct pci_dev *pdev = dev->nic_info.pdev;
  368. status = ocrdma_dealloc_ucontext_pd(uctx);
  369. ocrdma_del_mmap(uctx, uctx->ah_tbl.pa, uctx->ah_tbl.len);
  370. dma_free_coherent(&pdev->dev, uctx->ah_tbl.len, uctx->ah_tbl.va,
  371. uctx->ah_tbl.pa);
  372. list_for_each_entry_safe(mm, tmp, &uctx->mm_head, entry) {
  373. list_del(&mm->entry);
  374. kfree(mm);
  375. }
  376. kfree(uctx);
  377. return status;
  378. }
  379. int ocrdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  380. {
  381. struct ocrdma_ucontext *ucontext = get_ocrdma_ucontext(context);
  382. struct ocrdma_dev *dev = get_ocrdma_dev(context->device);
  383. unsigned long vm_page = vma->vm_pgoff << PAGE_SHIFT;
  384. u64 unmapped_db = (u64) dev->nic_info.unmapped_db;
  385. unsigned long len = (vma->vm_end - vma->vm_start);
  386. int status = 0;
  387. bool found;
  388. if (vma->vm_start & (PAGE_SIZE - 1))
  389. return -EINVAL;
  390. found = ocrdma_search_mmap(ucontext, vma->vm_pgoff << PAGE_SHIFT, len);
  391. if (!found)
  392. return -EINVAL;
  393. if ((vm_page >= unmapped_db) && (vm_page <= (unmapped_db +
  394. dev->nic_info.db_total_size)) &&
  395. (len <= dev->nic_info.db_page_size)) {
  396. if (vma->vm_flags & VM_READ)
  397. return -EPERM;
  398. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  399. status = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  400. len, vma->vm_page_prot);
  401. } else if (dev->nic_info.dpp_unmapped_len &&
  402. (vm_page >= (u64) dev->nic_info.dpp_unmapped_addr) &&
  403. (vm_page <= (u64) (dev->nic_info.dpp_unmapped_addr +
  404. dev->nic_info.dpp_unmapped_len)) &&
  405. (len <= dev->nic_info.dpp_unmapped_len)) {
  406. if (vma->vm_flags & VM_READ)
  407. return -EPERM;
  408. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  409. status = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  410. len, vma->vm_page_prot);
  411. } else {
  412. status = remap_pfn_range(vma, vma->vm_start,
  413. vma->vm_pgoff, len, vma->vm_page_prot);
  414. }
  415. return status;
  416. }
  417. static int ocrdma_copy_pd_uresp(struct ocrdma_dev *dev, struct ocrdma_pd *pd,
  418. struct ib_ucontext *ib_ctx,
  419. struct ib_udata *udata)
  420. {
  421. int status;
  422. u64 db_page_addr;
  423. u64 dpp_page_addr = 0;
  424. u32 db_page_size;
  425. struct ocrdma_alloc_pd_uresp rsp;
  426. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ib_ctx);
  427. memset(&rsp, 0, sizeof(rsp));
  428. rsp.id = pd->id;
  429. rsp.dpp_enabled = pd->dpp_enabled;
  430. db_page_addr = ocrdma_get_db_addr(dev, pd->id);
  431. db_page_size = dev->nic_info.db_page_size;
  432. status = ocrdma_add_mmap(uctx, db_page_addr, db_page_size);
  433. if (status)
  434. return status;
  435. if (pd->dpp_enabled) {
  436. dpp_page_addr = dev->nic_info.dpp_unmapped_addr +
  437. (pd->id * PAGE_SIZE);
  438. status = ocrdma_add_mmap(uctx, dpp_page_addr,
  439. PAGE_SIZE);
  440. if (status)
  441. goto dpp_map_err;
  442. rsp.dpp_page_addr_hi = upper_32_bits(dpp_page_addr);
  443. rsp.dpp_page_addr_lo = dpp_page_addr;
  444. }
  445. status = ib_copy_to_udata(udata, &rsp, sizeof(rsp));
  446. if (status)
  447. goto ucopy_err;
  448. pd->uctx = uctx;
  449. return 0;
  450. ucopy_err:
  451. if (pd->dpp_enabled)
  452. ocrdma_del_mmap(pd->uctx, dpp_page_addr, PAGE_SIZE);
  453. dpp_map_err:
  454. ocrdma_del_mmap(pd->uctx, db_page_addr, db_page_size);
  455. return status;
  456. }
  457. struct ib_pd *ocrdma_alloc_pd(struct ib_device *ibdev,
  458. struct ib_ucontext *context,
  459. struct ib_udata *udata)
  460. {
  461. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  462. struct ocrdma_pd *pd;
  463. struct ocrdma_ucontext *uctx = NULL;
  464. int status;
  465. u8 is_uctx_pd = false;
  466. if (udata && context) {
  467. uctx = get_ocrdma_ucontext(context);
  468. pd = ocrdma_get_ucontext_pd(uctx);
  469. if (pd) {
  470. is_uctx_pd = true;
  471. goto pd_mapping;
  472. }
  473. }
  474. pd = _ocrdma_alloc_pd(dev, uctx, udata);
  475. if (IS_ERR(pd)) {
  476. status = PTR_ERR(pd);
  477. goto exit;
  478. }
  479. pd_mapping:
  480. if (udata && context) {
  481. status = ocrdma_copy_pd_uresp(dev, pd, context, udata);
  482. if (status)
  483. goto err;
  484. }
  485. return &pd->ibpd;
  486. err:
  487. if (is_uctx_pd) {
  488. ocrdma_release_ucontext_pd(uctx);
  489. } else {
  490. status = ocrdma_mbx_dealloc_pd(dev, pd);
  491. kfree(pd);
  492. }
  493. exit:
  494. return ERR_PTR(status);
  495. }
  496. int ocrdma_dealloc_pd(struct ib_pd *ibpd)
  497. {
  498. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  499. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  500. struct ocrdma_ucontext *uctx = NULL;
  501. int status = 0;
  502. u64 usr_db;
  503. uctx = pd->uctx;
  504. if (uctx) {
  505. u64 dpp_db = dev->nic_info.dpp_unmapped_addr +
  506. (pd->id * PAGE_SIZE);
  507. if (pd->dpp_enabled)
  508. ocrdma_del_mmap(pd->uctx, dpp_db, PAGE_SIZE);
  509. usr_db = ocrdma_get_db_addr(dev, pd->id);
  510. ocrdma_del_mmap(pd->uctx, usr_db, dev->nic_info.db_page_size);
  511. if (is_ucontext_pd(uctx, pd)) {
  512. ocrdma_release_ucontext_pd(uctx);
  513. return status;
  514. }
  515. }
  516. status = _ocrdma_dealloc_pd(dev, pd);
  517. return status;
  518. }
  519. static int ocrdma_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  520. u32 pdid, int acc, u32 num_pbls, u32 addr_check)
  521. {
  522. int status;
  523. mr->hwmr.fr_mr = 0;
  524. mr->hwmr.local_rd = 1;
  525. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  526. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  527. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  528. mr->hwmr.mw_bind = (acc & IB_ACCESS_MW_BIND) ? 1 : 0;
  529. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  530. mr->hwmr.num_pbls = num_pbls;
  531. status = ocrdma_mbx_alloc_lkey(dev, &mr->hwmr, pdid, addr_check);
  532. if (status)
  533. return status;
  534. mr->ibmr.lkey = mr->hwmr.lkey;
  535. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  536. mr->ibmr.rkey = mr->hwmr.lkey;
  537. return 0;
  538. }
  539. struct ib_mr *ocrdma_get_dma_mr(struct ib_pd *ibpd, int acc)
  540. {
  541. int status;
  542. struct ocrdma_mr *mr;
  543. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  544. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  545. if (acc & IB_ACCESS_REMOTE_WRITE && !(acc & IB_ACCESS_LOCAL_WRITE)) {
  546. pr_err("%s err, invalid access rights\n", __func__);
  547. return ERR_PTR(-EINVAL);
  548. }
  549. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  550. if (!mr)
  551. return ERR_PTR(-ENOMEM);
  552. status = ocrdma_alloc_lkey(dev, mr, pd->id, acc, 0,
  553. OCRDMA_ADDR_CHECK_DISABLE);
  554. if (status) {
  555. kfree(mr);
  556. return ERR_PTR(status);
  557. }
  558. return &mr->ibmr;
  559. }
  560. static void ocrdma_free_mr_pbl_tbl(struct ocrdma_dev *dev,
  561. struct ocrdma_hw_mr *mr)
  562. {
  563. struct pci_dev *pdev = dev->nic_info.pdev;
  564. int i = 0;
  565. if (mr->pbl_table) {
  566. for (i = 0; i < mr->num_pbls; i++) {
  567. if (!mr->pbl_table[i].va)
  568. continue;
  569. dma_free_coherent(&pdev->dev, mr->pbl_size,
  570. mr->pbl_table[i].va,
  571. mr->pbl_table[i].pa);
  572. }
  573. kfree(mr->pbl_table);
  574. mr->pbl_table = NULL;
  575. }
  576. }
  577. static int ocrdma_get_pbl_info(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  578. u32 num_pbes)
  579. {
  580. u32 num_pbls = 0;
  581. u32 idx = 0;
  582. int status = 0;
  583. u32 pbl_size;
  584. do {
  585. pbl_size = OCRDMA_MIN_HPAGE_SIZE * (1 << idx);
  586. if (pbl_size > MAX_OCRDMA_PBL_SIZE) {
  587. status = -EFAULT;
  588. break;
  589. }
  590. num_pbls = roundup(num_pbes, (pbl_size / sizeof(u64)));
  591. num_pbls = num_pbls / (pbl_size / sizeof(u64));
  592. idx++;
  593. } while (num_pbls >= dev->attr.max_num_mr_pbl);
  594. mr->hwmr.num_pbes = num_pbes;
  595. mr->hwmr.num_pbls = num_pbls;
  596. mr->hwmr.pbl_size = pbl_size;
  597. return status;
  598. }
  599. static int ocrdma_build_pbl_tbl(struct ocrdma_dev *dev, struct ocrdma_hw_mr *mr)
  600. {
  601. int status = 0;
  602. int i;
  603. u32 dma_len = mr->pbl_size;
  604. struct pci_dev *pdev = dev->nic_info.pdev;
  605. void *va;
  606. dma_addr_t pa;
  607. mr->pbl_table = kzalloc(sizeof(struct ocrdma_pbl) *
  608. mr->num_pbls, GFP_KERNEL);
  609. if (!mr->pbl_table)
  610. return -ENOMEM;
  611. for (i = 0; i < mr->num_pbls; i++) {
  612. va = dma_alloc_coherent(&pdev->dev, dma_len, &pa, GFP_KERNEL);
  613. if (!va) {
  614. ocrdma_free_mr_pbl_tbl(dev, mr);
  615. status = -ENOMEM;
  616. break;
  617. }
  618. memset(va, 0, dma_len);
  619. mr->pbl_table[i].va = va;
  620. mr->pbl_table[i].pa = pa;
  621. }
  622. return status;
  623. }
  624. static void build_user_pbes(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  625. u32 num_pbes)
  626. {
  627. struct ocrdma_pbe *pbe;
  628. struct scatterlist *sg;
  629. struct ocrdma_pbl *pbl_tbl = mr->hwmr.pbl_table;
  630. struct ib_umem *umem = mr->umem;
  631. int shift, pg_cnt, pages, pbe_cnt, entry, total_num_pbes = 0;
  632. if (!mr->hwmr.num_pbes)
  633. return;
  634. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  635. pbe_cnt = 0;
  636. shift = ilog2(umem->page_size);
  637. for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
  638. pages = sg_dma_len(sg) >> shift;
  639. for (pg_cnt = 0; pg_cnt < pages; pg_cnt++) {
  640. /* store the page address in pbe */
  641. pbe->pa_lo =
  642. cpu_to_le32(sg_dma_address
  643. (sg) +
  644. (umem->page_size * pg_cnt));
  645. pbe->pa_hi =
  646. cpu_to_le32(upper_32_bits
  647. ((sg_dma_address
  648. (sg) +
  649. umem->page_size * pg_cnt)));
  650. pbe_cnt += 1;
  651. total_num_pbes += 1;
  652. pbe++;
  653. /* if done building pbes, issue the mbx cmd. */
  654. if (total_num_pbes == num_pbes)
  655. return;
  656. /* if the given pbl is full storing the pbes,
  657. * move to next pbl.
  658. */
  659. if (pbe_cnt ==
  660. (mr->hwmr.pbl_size / sizeof(u64))) {
  661. pbl_tbl++;
  662. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  663. pbe_cnt = 0;
  664. }
  665. }
  666. }
  667. }
  668. struct ib_mr *ocrdma_reg_user_mr(struct ib_pd *ibpd, u64 start, u64 len,
  669. u64 usr_addr, int acc, struct ib_udata *udata)
  670. {
  671. int status = -ENOMEM;
  672. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  673. struct ocrdma_mr *mr;
  674. struct ocrdma_pd *pd;
  675. u32 num_pbes;
  676. pd = get_ocrdma_pd(ibpd);
  677. if (acc & IB_ACCESS_REMOTE_WRITE && !(acc & IB_ACCESS_LOCAL_WRITE))
  678. return ERR_PTR(-EINVAL);
  679. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  680. if (!mr)
  681. return ERR_PTR(status);
  682. mr->umem = ib_umem_get(ibpd->uobject->context, start, len, acc, 0);
  683. if (IS_ERR(mr->umem)) {
  684. status = -EFAULT;
  685. goto umem_err;
  686. }
  687. num_pbes = ib_umem_page_count(mr->umem);
  688. status = ocrdma_get_pbl_info(dev, mr, num_pbes);
  689. if (status)
  690. goto umem_err;
  691. mr->hwmr.pbe_size = mr->umem->page_size;
  692. mr->hwmr.fbo = mr->umem->offset;
  693. mr->hwmr.va = usr_addr;
  694. mr->hwmr.len = len;
  695. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  696. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  697. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  698. mr->hwmr.local_rd = 1;
  699. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  700. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  701. if (status)
  702. goto umem_err;
  703. build_user_pbes(dev, mr, num_pbes);
  704. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, acc);
  705. if (status)
  706. goto mbx_err;
  707. mr->ibmr.lkey = mr->hwmr.lkey;
  708. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  709. mr->ibmr.rkey = mr->hwmr.lkey;
  710. return &mr->ibmr;
  711. mbx_err:
  712. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  713. umem_err:
  714. kfree(mr);
  715. return ERR_PTR(status);
  716. }
  717. int ocrdma_dereg_mr(struct ib_mr *ib_mr)
  718. {
  719. struct ocrdma_mr *mr = get_ocrdma_mr(ib_mr);
  720. struct ocrdma_dev *dev = get_ocrdma_dev(ib_mr->device);
  721. int status;
  722. status = ocrdma_mbx_dealloc_lkey(dev, mr->hwmr.fr_mr, mr->hwmr.lkey);
  723. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  724. /* it could be user registered memory. */
  725. if (mr->umem)
  726. ib_umem_release(mr->umem);
  727. kfree(mr);
  728. return status;
  729. }
  730. static int ocrdma_copy_cq_uresp(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
  731. struct ib_udata *udata,
  732. struct ib_ucontext *ib_ctx)
  733. {
  734. int status;
  735. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ib_ctx);
  736. struct ocrdma_create_cq_uresp uresp;
  737. memset(&uresp, 0, sizeof(uresp));
  738. uresp.cq_id = cq->id;
  739. uresp.page_size = PAGE_ALIGN(cq->len);
  740. uresp.num_pages = 1;
  741. uresp.max_hw_cqe = cq->max_hw_cqe;
  742. uresp.page_addr[0] = cq->pa;
  743. uresp.db_page_addr = ocrdma_get_db_addr(dev, uctx->cntxt_pd->id);
  744. uresp.db_page_size = dev->nic_info.db_page_size;
  745. uresp.phase_change = cq->phase_change ? 1 : 0;
  746. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  747. if (status) {
  748. pr_err("%s(%d) copy error cqid=0x%x.\n",
  749. __func__, dev->id, cq->id);
  750. goto err;
  751. }
  752. status = ocrdma_add_mmap(uctx, uresp.db_page_addr, uresp.db_page_size);
  753. if (status)
  754. goto err;
  755. status = ocrdma_add_mmap(uctx, uresp.page_addr[0], uresp.page_size);
  756. if (status) {
  757. ocrdma_del_mmap(uctx, uresp.db_page_addr, uresp.db_page_size);
  758. goto err;
  759. }
  760. cq->ucontext = uctx;
  761. err:
  762. return status;
  763. }
  764. struct ib_cq *ocrdma_create_cq(struct ib_device *ibdev, int entries, int vector,
  765. struct ib_ucontext *ib_ctx,
  766. struct ib_udata *udata)
  767. {
  768. struct ocrdma_cq *cq;
  769. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  770. struct ocrdma_ucontext *uctx = NULL;
  771. u16 pd_id = 0;
  772. int status;
  773. struct ocrdma_create_cq_ureq ureq;
  774. if (udata) {
  775. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  776. return ERR_PTR(-EFAULT);
  777. } else
  778. ureq.dpp_cq = 0;
  779. cq = kzalloc(sizeof(*cq), GFP_KERNEL);
  780. if (!cq)
  781. return ERR_PTR(-ENOMEM);
  782. spin_lock_init(&cq->cq_lock);
  783. spin_lock_init(&cq->comp_handler_lock);
  784. INIT_LIST_HEAD(&cq->sq_head);
  785. INIT_LIST_HEAD(&cq->rq_head);
  786. cq->first_arm = true;
  787. if (ib_ctx) {
  788. uctx = get_ocrdma_ucontext(ib_ctx);
  789. pd_id = uctx->cntxt_pd->id;
  790. }
  791. status = ocrdma_mbx_create_cq(dev, cq, entries, ureq.dpp_cq, pd_id);
  792. if (status) {
  793. kfree(cq);
  794. return ERR_PTR(status);
  795. }
  796. if (ib_ctx) {
  797. status = ocrdma_copy_cq_uresp(dev, cq, udata, ib_ctx);
  798. if (status)
  799. goto ctx_err;
  800. }
  801. cq->phase = OCRDMA_CQE_VALID;
  802. dev->cq_tbl[cq->id] = cq;
  803. return &cq->ibcq;
  804. ctx_err:
  805. ocrdma_mbx_destroy_cq(dev, cq);
  806. kfree(cq);
  807. return ERR_PTR(status);
  808. }
  809. int ocrdma_resize_cq(struct ib_cq *ibcq, int new_cnt,
  810. struct ib_udata *udata)
  811. {
  812. int status = 0;
  813. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  814. if (new_cnt < 1 || new_cnt > cq->max_hw_cqe) {
  815. status = -EINVAL;
  816. return status;
  817. }
  818. ibcq->cqe = new_cnt;
  819. return status;
  820. }
  821. static void ocrdma_flush_cq(struct ocrdma_cq *cq)
  822. {
  823. int cqe_cnt;
  824. int valid_count = 0;
  825. unsigned long flags;
  826. struct ocrdma_dev *dev = get_ocrdma_dev(cq->ibcq.device);
  827. struct ocrdma_cqe *cqe = NULL;
  828. cqe = cq->va;
  829. cqe_cnt = cq->cqe_cnt;
  830. /* Last irq might have scheduled a polling thread
  831. * sync-up with it before hard flushing.
  832. */
  833. spin_lock_irqsave(&cq->cq_lock, flags);
  834. while (cqe_cnt) {
  835. if (is_cqe_valid(cq, cqe))
  836. valid_count++;
  837. cqe++;
  838. cqe_cnt--;
  839. }
  840. ocrdma_ring_cq_db(dev, cq->id, false, false, valid_count);
  841. spin_unlock_irqrestore(&cq->cq_lock, flags);
  842. }
  843. int ocrdma_destroy_cq(struct ib_cq *ibcq)
  844. {
  845. int status;
  846. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  847. struct ocrdma_eq *eq = NULL;
  848. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  849. int pdid = 0;
  850. u32 irq, indx;
  851. dev->cq_tbl[cq->id] = NULL;
  852. indx = ocrdma_get_eq_table_index(dev, cq->eqn);
  853. if (indx == -EINVAL)
  854. BUG();
  855. eq = &dev->eq_tbl[indx];
  856. irq = ocrdma_get_irq(dev, eq);
  857. synchronize_irq(irq);
  858. ocrdma_flush_cq(cq);
  859. status = ocrdma_mbx_destroy_cq(dev, cq);
  860. if (cq->ucontext) {
  861. pdid = cq->ucontext->cntxt_pd->id;
  862. ocrdma_del_mmap(cq->ucontext, (u64) cq->pa,
  863. PAGE_ALIGN(cq->len));
  864. ocrdma_del_mmap(cq->ucontext,
  865. ocrdma_get_db_addr(dev, pdid),
  866. dev->nic_info.db_page_size);
  867. }
  868. kfree(cq);
  869. return status;
  870. }
  871. static int ocrdma_add_qpn_map(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
  872. {
  873. int status = -EINVAL;
  874. if (qp->id < OCRDMA_MAX_QP && dev->qp_tbl[qp->id] == NULL) {
  875. dev->qp_tbl[qp->id] = qp;
  876. status = 0;
  877. }
  878. return status;
  879. }
  880. static void ocrdma_del_qpn_map(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
  881. {
  882. dev->qp_tbl[qp->id] = NULL;
  883. }
  884. static int ocrdma_check_qp_params(struct ib_pd *ibpd, struct ocrdma_dev *dev,
  885. struct ib_qp_init_attr *attrs)
  886. {
  887. if ((attrs->qp_type != IB_QPT_GSI) &&
  888. (attrs->qp_type != IB_QPT_RC) &&
  889. (attrs->qp_type != IB_QPT_UC) &&
  890. (attrs->qp_type != IB_QPT_UD)) {
  891. pr_err("%s(%d) unsupported qp type=0x%x requested\n",
  892. __func__, dev->id, attrs->qp_type);
  893. return -EINVAL;
  894. }
  895. /* Skip the check for QP1 to support CM size of 128 */
  896. if ((attrs->qp_type != IB_QPT_GSI) &&
  897. (attrs->cap.max_send_wr > dev->attr.max_wqe)) {
  898. pr_err("%s(%d) unsupported send_wr=0x%x requested\n",
  899. __func__, dev->id, attrs->cap.max_send_wr);
  900. pr_err("%s(%d) supported send_wr=0x%x\n",
  901. __func__, dev->id, dev->attr.max_wqe);
  902. return -EINVAL;
  903. }
  904. if (!attrs->srq && (attrs->cap.max_recv_wr > dev->attr.max_rqe)) {
  905. pr_err("%s(%d) unsupported recv_wr=0x%x requested\n",
  906. __func__, dev->id, attrs->cap.max_recv_wr);
  907. pr_err("%s(%d) supported recv_wr=0x%x\n",
  908. __func__, dev->id, dev->attr.max_rqe);
  909. return -EINVAL;
  910. }
  911. if (attrs->cap.max_inline_data > dev->attr.max_inline_data) {
  912. pr_err("%s(%d) unsupported inline data size=0x%x requested\n",
  913. __func__, dev->id, attrs->cap.max_inline_data);
  914. pr_err("%s(%d) supported inline data size=0x%x\n",
  915. __func__, dev->id, dev->attr.max_inline_data);
  916. return -EINVAL;
  917. }
  918. if (attrs->cap.max_send_sge > dev->attr.max_send_sge) {
  919. pr_err("%s(%d) unsupported send_sge=0x%x requested\n",
  920. __func__, dev->id, attrs->cap.max_send_sge);
  921. pr_err("%s(%d) supported send_sge=0x%x\n",
  922. __func__, dev->id, dev->attr.max_send_sge);
  923. return -EINVAL;
  924. }
  925. if (attrs->cap.max_recv_sge > dev->attr.max_recv_sge) {
  926. pr_err("%s(%d) unsupported recv_sge=0x%x requested\n",
  927. __func__, dev->id, attrs->cap.max_recv_sge);
  928. pr_err("%s(%d) supported recv_sge=0x%x\n",
  929. __func__, dev->id, dev->attr.max_recv_sge);
  930. return -EINVAL;
  931. }
  932. /* unprivileged user space cannot create special QP */
  933. if (ibpd->uobject && attrs->qp_type == IB_QPT_GSI) {
  934. pr_err
  935. ("%s(%d) Userspace can't create special QPs of type=0x%x\n",
  936. __func__, dev->id, attrs->qp_type);
  937. return -EINVAL;
  938. }
  939. /* allow creating only one GSI type of QP */
  940. if (attrs->qp_type == IB_QPT_GSI && dev->gsi_qp_created) {
  941. pr_err("%s(%d) GSI special QPs already created.\n",
  942. __func__, dev->id);
  943. return -EINVAL;
  944. }
  945. /* verify consumer QPs are not trying to use GSI QP's CQ */
  946. if ((attrs->qp_type != IB_QPT_GSI) && (dev->gsi_qp_created)) {
  947. if ((dev->gsi_sqcq == get_ocrdma_cq(attrs->send_cq)) ||
  948. (dev->gsi_rqcq == get_ocrdma_cq(attrs->recv_cq))) {
  949. pr_err("%s(%d) Consumer QP cannot use GSI CQs.\n",
  950. __func__, dev->id);
  951. return -EINVAL;
  952. }
  953. }
  954. return 0;
  955. }
  956. static int ocrdma_copy_qp_uresp(struct ocrdma_qp *qp,
  957. struct ib_udata *udata, int dpp_offset,
  958. int dpp_credit_lmt, int srq)
  959. {
  960. int status = 0;
  961. u64 usr_db;
  962. struct ocrdma_create_qp_uresp uresp;
  963. struct ocrdma_dev *dev = qp->dev;
  964. struct ocrdma_pd *pd = qp->pd;
  965. memset(&uresp, 0, sizeof(uresp));
  966. usr_db = dev->nic_info.unmapped_db +
  967. (pd->id * dev->nic_info.db_page_size);
  968. uresp.qp_id = qp->id;
  969. uresp.sq_dbid = qp->sq.dbid;
  970. uresp.num_sq_pages = 1;
  971. uresp.sq_page_size = PAGE_ALIGN(qp->sq.len);
  972. uresp.sq_page_addr[0] = qp->sq.pa;
  973. uresp.num_wqe_allocated = qp->sq.max_cnt;
  974. if (!srq) {
  975. uresp.rq_dbid = qp->rq.dbid;
  976. uresp.num_rq_pages = 1;
  977. uresp.rq_page_size = PAGE_ALIGN(qp->rq.len);
  978. uresp.rq_page_addr[0] = qp->rq.pa;
  979. uresp.num_rqe_allocated = qp->rq.max_cnt;
  980. }
  981. uresp.db_page_addr = usr_db;
  982. uresp.db_page_size = dev->nic_info.db_page_size;
  983. uresp.db_sq_offset = OCRDMA_DB_GEN2_SQ_OFFSET;
  984. uresp.db_rq_offset = OCRDMA_DB_GEN2_RQ_OFFSET;
  985. uresp.db_shift = OCRDMA_DB_RQ_SHIFT;
  986. if (qp->dpp_enabled) {
  987. uresp.dpp_credit = dpp_credit_lmt;
  988. uresp.dpp_offset = dpp_offset;
  989. }
  990. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  991. if (status) {
  992. pr_err("%s(%d) user copy error.\n", __func__, dev->id);
  993. goto err;
  994. }
  995. status = ocrdma_add_mmap(pd->uctx, uresp.sq_page_addr[0],
  996. uresp.sq_page_size);
  997. if (status)
  998. goto err;
  999. if (!srq) {
  1000. status = ocrdma_add_mmap(pd->uctx, uresp.rq_page_addr[0],
  1001. uresp.rq_page_size);
  1002. if (status)
  1003. goto rq_map_err;
  1004. }
  1005. return status;
  1006. rq_map_err:
  1007. ocrdma_del_mmap(pd->uctx, uresp.sq_page_addr[0], uresp.sq_page_size);
  1008. err:
  1009. return status;
  1010. }
  1011. static void ocrdma_set_qp_db(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
  1012. struct ocrdma_pd *pd)
  1013. {
  1014. if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
  1015. qp->sq_db = dev->nic_info.db +
  1016. (pd->id * dev->nic_info.db_page_size) +
  1017. OCRDMA_DB_GEN2_SQ_OFFSET;
  1018. qp->rq_db = dev->nic_info.db +
  1019. (pd->id * dev->nic_info.db_page_size) +
  1020. OCRDMA_DB_GEN2_RQ_OFFSET;
  1021. } else {
  1022. qp->sq_db = dev->nic_info.db +
  1023. (pd->id * dev->nic_info.db_page_size) +
  1024. OCRDMA_DB_SQ_OFFSET;
  1025. qp->rq_db = dev->nic_info.db +
  1026. (pd->id * dev->nic_info.db_page_size) +
  1027. OCRDMA_DB_RQ_OFFSET;
  1028. }
  1029. }
  1030. static int ocrdma_alloc_wr_id_tbl(struct ocrdma_qp *qp)
  1031. {
  1032. qp->wqe_wr_id_tbl =
  1033. kzalloc(sizeof(*(qp->wqe_wr_id_tbl)) * qp->sq.max_cnt,
  1034. GFP_KERNEL);
  1035. if (qp->wqe_wr_id_tbl == NULL)
  1036. return -ENOMEM;
  1037. qp->rqe_wr_id_tbl =
  1038. kzalloc(sizeof(u64) * qp->rq.max_cnt, GFP_KERNEL);
  1039. if (qp->rqe_wr_id_tbl == NULL)
  1040. return -ENOMEM;
  1041. return 0;
  1042. }
  1043. static void ocrdma_set_qp_init_params(struct ocrdma_qp *qp,
  1044. struct ocrdma_pd *pd,
  1045. struct ib_qp_init_attr *attrs)
  1046. {
  1047. qp->pd = pd;
  1048. spin_lock_init(&qp->q_lock);
  1049. INIT_LIST_HEAD(&qp->sq_entry);
  1050. INIT_LIST_HEAD(&qp->rq_entry);
  1051. qp->qp_type = attrs->qp_type;
  1052. qp->cap_flags = OCRDMA_QP_INB_RD | OCRDMA_QP_INB_WR;
  1053. qp->max_inline_data = attrs->cap.max_inline_data;
  1054. qp->sq.max_sges = attrs->cap.max_send_sge;
  1055. qp->rq.max_sges = attrs->cap.max_recv_sge;
  1056. qp->state = OCRDMA_QPS_RST;
  1057. qp->signaled = (attrs->sq_sig_type == IB_SIGNAL_ALL_WR) ? true : false;
  1058. }
  1059. static void ocrdma_store_gsi_qp_cq(struct ocrdma_dev *dev,
  1060. struct ib_qp_init_attr *attrs)
  1061. {
  1062. if (attrs->qp_type == IB_QPT_GSI) {
  1063. dev->gsi_qp_created = 1;
  1064. dev->gsi_sqcq = get_ocrdma_cq(attrs->send_cq);
  1065. dev->gsi_rqcq = get_ocrdma_cq(attrs->recv_cq);
  1066. }
  1067. }
  1068. struct ib_qp *ocrdma_create_qp(struct ib_pd *ibpd,
  1069. struct ib_qp_init_attr *attrs,
  1070. struct ib_udata *udata)
  1071. {
  1072. int status;
  1073. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  1074. struct ocrdma_qp *qp;
  1075. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  1076. struct ocrdma_create_qp_ureq ureq;
  1077. u16 dpp_credit_lmt, dpp_offset;
  1078. status = ocrdma_check_qp_params(ibpd, dev, attrs);
  1079. if (status)
  1080. goto gen_err;
  1081. memset(&ureq, 0, sizeof(ureq));
  1082. if (udata) {
  1083. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  1084. return ERR_PTR(-EFAULT);
  1085. }
  1086. qp = kzalloc(sizeof(*qp), GFP_KERNEL);
  1087. if (!qp) {
  1088. status = -ENOMEM;
  1089. goto gen_err;
  1090. }
  1091. qp->dev = dev;
  1092. ocrdma_set_qp_init_params(qp, pd, attrs);
  1093. if (udata == NULL)
  1094. qp->cap_flags |= (OCRDMA_QP_MW_BIND | OCRDMA_QP_LKEY0 |
  1095. OCRDMA_QP_FAST_REG);
  1096. mutex_lock(&dev->dev_lock);
  1097. status = ocrdma_mbx_create_qp(qp, attrs, ureq.enable_dpp_cq,
  1098. ureq.dpp_cq_id,
  1099. &dpp_offset, &dpp_credit_lmt);
  1100. if (status)
  1101. goto mbx_err;
  1102. /* user space QP's wr_id table are managed in library */
  1103. if (udata == NULL) {
  1104. status = ocrdma_alloc_wr_id_tbl(qp);
  1105. if (status)
  1106. goto map_err;
  1107. }
  1108. status = ocrdma_add_qpn_map(dev, qp);
  1109. if (status)
  1110. goto map_err;
  1111. ocrdma_set_qp_db(dev, qp, pd);
  1112. if (udata) {
  1113. status = ocrdma_copy_qp_uresp(qp, udata, dpp_offset,
  1114. dpp_credit_lmt,
  1115. (attrs->srq != NULL));
  1116. if (status)
  1117. goto cpy_err;
  1118. }
  1119. ocrdma_store_gsi_qp_cq(dev, attrs);
  1120. qp->ibqp.qp_num = qp->id;
  1121. mutex_unlock(&dev->dev_lock);
  1122. return &qp->ibqp;
  1123. cpy_err:
  1124. ocrdma_del_qpn_map(dev, qp);
  1125. map_err:
  1126. ocrdma_mbx_destroy_qp(dev, qp);
  1127. mbx_err:
  1128. mutex_unlock(&dev->dev_lock);
  1129. kfree(qp->wqe_wr_id_tbl);
  1130. kfree(qp->rqe_wr_id_tbl);
  1131. kfree(qp);
  1132. pr_err("%s(%d) error=%d\n", __func__, dev->id, status);
  1133. gen_err:
  1134. return ERR_PTR(status);
  1135. }
  1136. int _ocrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1137. int attr_mask)
  1138. {
  1139. int status = 0;
  1140. struct ocrdma_qp *qp;
  1141. struct ocrdma_dev *dev;
  1142. enum ib_qp_state old_qps;
  1143. qp = get_ocrdma_qp(ibqp);
  1144. dev = qp->dev;
  1145. if (attr_mask & IB_QP_STATE)
  1146. status = ocrdma_qp_state_change(qp, attr->qp_state, &old_qps);
  1147. /* if new and previous states are same hw doesn't need to
  1148. * know about it.
  1149. */
  1150. if (status < 0)
  1151. return status;
  1152. status = ocrdma_mbx_modify_qp(dev, qp, attr, attr_mask);
  1153. return status;
  1154. }
  1155. int ocrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1156. int attr_mask, struct ib_udata *udata)
  1157. {
  1158. unsigned long flags;
  1159. int status = -EINVAL;
  1160. struct ocrdma_qp *qp;
  1161. struct ocrdma_dev *dev;
  1162. enum ib_qp_state old_qps, new_qps;
  1163. qp = get_ocrdma_qp(ibqp);
  1164. dev = qp->dev;
  1165. /* syncronize with multiple context trying to change, retrive qps */
  1166. mutex_lock(&dev->dev_lock);
  1167. /* syncronize with wqe, rqe posting and cqe processing contexts */
  1168. spin_lock_irqsave(&qp->q_lock, flags);
  1169. old_qps = get_ibqp_state(qp->state);
  1170. if (attr_mask & IB_QP_STATE)
  1171. new_qps = attr->qp_state;
  1172. else
  1173. new_qps = old_qps;
  1174. spin_unlock_irqrestore(&qp->q_lock, flags);
  1175. if (!ib_modify_qp_is_ok(old_qps, new_qps, ibqp->qp_type, attr_mask,
  1176. IB_LINK_LAYER_ETHERNET)) {
  1177. pr_err("%s(%d) invalid attribute mask=0x%x specified for\n"
  1178. "qpn=0x%x of type=0x%x old_qps=0x%x, new_qps=0x%x\n",
  1179. __func__, dev->id, attr_mask, qp->id, ibqp->qp_type,
  1180. old_qps, new_qps);
  1181. goto param_err;
  1182. }
  1183. status = _ocrdma_modify_qp(ibqp, attr, attr_mask);
  1184. if (status > 0)
  1185. status = 0;
  1186. param_err:
  1187. mutex_unlock(&dev->dev_lock);
  1188. return status;
  1189. }
  1190. static enum ib_mtu ocrdma_mtu_int_to_enum(u16 mtu)
  1191. {
  1192. switch (mtu) {
  1193. case 256:
  1194. return IB_MTU_256;
  1195. case 512:
  1196. return IB_MTU_512;
  1197. case 1024:
  1198. return IB_MTU_1024;
  1199. case 2048:
  1200. return IB_MTU_2048;
  1201. case 4096:
  1202. return IB_MTU_4096;
  1203. default:
  1204. return IB_MTU_1024;
  1205. }
  1206. }
  1207. static int ocrdma_to_ib_qp_acc_flags(int qp_cap_flags)
  1208. {
  1209. int ib_qp_acc_flags = 0;
  1210. if (qp_cap_flags & OCRDMA_QP_INB_WR)
  1211. ib_qp_acc_flags |= IB_ACCESS_REMOTE_WRITE;
  1212. if (qp_cap_flags & OCRDMA_QP_INB_RD)
  1213. ib_qp_acc_flags |= IB_ACCESS_LOCAL_WRITE;
  1214. return ib_qp_acc_flags;
  1215. }
  1216. int ocrdma_query_qp(struct ib_qp *ibqp,
  1217. struct ib_qp_attr *qp_attr,
  1218. int attr_mask, struct ib_qp_init_attr *qp_init_attr)
  1219. {
  1220. int status;
  1221. u32 qp_state;
  1222. struct ocrdma_qp_params params;
  1223. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1224. struct ocrdma_dev *dev = qp->dev;
  1225. memset(&params, 0, sizeof(params));
  1226. mutex_lock(&dev->dev_lock);
  1227. status = ocrdma_mbx_query_qp(dev, qp, &params);
  1228. mutex_unlock(&dev->dev_lock);
  1229. if (status)
  1230. goto mbx_err;
  1231. qp_attr->qp_state = get_ibqp_state(IB_QPS_INIT);
  1232. qp_attr->cur_qp_state = get_ibqp_state(IB_QPS_INIT);
  1233. qp_attr->path_mtu =
  1234. ocrdma_mtu_int_to_enum(params.path_mtu_pkey_indx &
  1235. OCRDMA_QP_PARAMS_PATH_MTU_MASK) >>
  1236. OCRDMA_QP_PARAMS_PATH_MTU_SHIFT;
  1237. qp_attr->path_mig_state = IB_MIG_MIGRATED;
  1238. qp_attr->rq_psn = params.hop_lmt_rq_psn & OCRDMA_QP_PARAMS_RQ_PSN_MASK;
  1239. qp_attr->sq_psn = params.tclass_sq_psn & OCRDMA_QP_PARAMS_SQ_PSN_MASK;
  1240. qp_attr->dest_qp_num =
  1241. params.ack_to_rnr_rtc_dest_qpn & OCRDMA_QP_PARAMS_DEST_QPN_MASK;
  1242. qp_attr->qp_access_flags = ocrdma_to_ib_qp_acc_flags(qp->cap_flags);
  1243. qp_attr->cap.max_send_wr = qp->sq.max_cnt - 1;
  1244. qp_attr->cap.max_recv_wr = qp->rq.max_cnt - 1;
  1245. qp_attr->cap.max_send_sge = qp->sq.max_sges;
  1246. qp_attr->cap.max_recv_sge = qp->rq.max_sges;
  1247. qp_attr->cap.max_inline_data = qp->max_inline_data;
  1248. qp_init_attr->cap = qp_attr->cap;
  1249. memcpy(&qp_attr->ah_attr.grh.dgid, &params.dgid[0],
  1250. sizeof(params.dgid));
  1251. qp_attr->ah_attr.grh.flow_label = params.rnt_rc_sl_fl &
  1252. OCRDMA_QP_PARAMS_FLOW_LABEL_MASK;
  1253. qp_attr->ah_attr.grh.sgid_index = qp->sgid_idx;
  1254. qp_attr->ah_attr.grh.hop_limit = (params.hop_lmt_rq_psn &
  1255. OCRDMA_QP_PARAMS_HOP_LMT_MASK) >>
  1256. OCRDMA_QP_PARAMS_HOP_LMT_SHIFT;
  1257. qp_attr->ah_attr.grh.traffic_class = (params.tclass_sq_psn &
  1258. OCRDMA_QP_PARAMS_TCLASS_MASK) >>
  1259. OCRDMA_QP_PARAMS_TCLASS_SHIFT;
  1260. qp_attr->ah_attr.ah_flags = IB_AH_GRH;
  1261. qp_attr->ah_attr.port_num = 1;
  1262. qp_attr->ah_attr.sl = (params.rnt_rc_sl_fl &
  1263. OCRDMA_QP_PARAMS_SL_MASK) >>
  1264. OCRDMA_QP_PARAMS_SL_SHIFT;
  1265. qp_attr->timeout = (params.ack_to_rnr_rtc_dest_qpn &
  1266. OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK) >>
  1267. OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
  1268. qp_attr->rnr_retry = (params.ack_to_rnr_rtc_dest_qpn &
  1269. OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK) >>
  1270. OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT;
  1271. qp_attr->retry_cnt =
  1272. (params.rnt_rc_sl_fl & OCRDMA_QP_PARAMS_RETRY_CNT_MASK) >>
  1273. OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT;
  1274. qp_attr->min_rnr_timer = 0;
  1275. qp_attr->pkey_index = 0;
  1276. qp_attr->port_num = 1;
  1277. qp_attr->ah_attr.src_path_bits = 0;
  1278. qp_attr->ah_attr.static_rate = 0;
  1279. qp_attr->alt_pkey_index = 0;
  1280. qp_attr->alt_port_num = 0;
  1281. qp_attr->alt_timeout = 0;
  1282. memset(&qp_attr->alt_ah_attr, 0, sizeof(qp_attr->alt_ah_attr));
  1283. qp_state = (params.max_sge_recv_flags & OCRDMA_QP_PARAMS_STATE_MASK) >>
  1284. OCRDMA_QP_PARAMS_STATE_SHIFT;
  1285. qp_attr->sq_draining = (qp_state == OCRDMA_QPS_SQ_DRAINING) ? 1 : 0;
  1286. qp_attr->max_dest_rd_atomic =
  1287. params.max_ord_ird >> OCRDMA_QP_PARAMS_MAX_ORD_SHIFT;
  1288. qp_attr->max_rd_atomic =
  1289. params.max_ord_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK;
  1290. qp_attr->en_sqd_async_notify = (params.max_sge_recv_flags &
  1291. OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC) ? 1 : 0;
  1292. mbx_err:
  1293. return status;
  1294. }
  1295. static void ocrdma_srq_toggle_bit(struct ocrdma_srq *srq, int idx)
  1296. {
  1297. int i = idx / 32;
  1298. unsigned int mask = (1 << (idx % 32));
  1299. if (srq->idx_bit_fields[i] & mask)
  1300. srq->idx_bit_fields[i] &= ~mask;
  1301. else
  1302. srq->idx_bit_fields[i] |= mask;
  1303. }
  1304. static int ocrdma_hwq_free_cnt(struct ocrdma_qp_hwq_info *q)
  1305. {
  1306. return ((q->max_wqe_idx - q->head) + q->tail) % q->max_cnt;
  1307. }
  1308. static int is_hw_sq_empty(struct ocrdma_qp *qp)
  1309. {
  1310. return (qp->sq.tail == qp->sq.head);
  1311. }
  1312. static int is_hw_rq_empty(struct ocrdma_qp *qp)
  1313. {
  1314. return (qp->rq.tail == qp->rq.head);
  1315. }
  1316. static void *ocrdma_hwq_head(struct ocrdma_qp_hwq_info *q)
  1317. {
  1318. return q->va + (q->head * q->entry_size);
  1319. }
  1320. static void *ocrdma_hwq_head_from_idx(struct ocrdma_qp_hwq_info *q,
  1321. u32 idx)
  1322. {
  1323. return q->va + (idx * q->entry_size);
  1324. }
  1325. static void ocrdma_hwq_inc_head(struct ocrdma_qp_hwq_info *q)
  1326. {
  1327. q->head = (q->head + 1) & q->max_wqe_idx;
  1328. }
  1329. static void ocrdma_hwq_inc_tail(struct ocrdma_qp_hwq_info *q)
  1330. {
  1331. q->tail = (q->tail + 1) & q->max_wqe_idx;
  1332. }
  1333. /* discard the cqe for a given QP */
  1334. static void ocrdma_discard_cqes(struct ocrdma_qp *qp, struct ocrdma_cq *cq)
  1335. {
  1336. unsigned long cq_flags;
  1337. unsigned long flags;
  1338. int discard_cnt = 0;
  1339. u32 cur_getp, stop_getp;
  1340. struct ocrdma_cqe *cqe;
  1341. u32 qpn = 0, wqe_idx = 0;
  1342. spin_lock_irqsave(&cq->cq_lock, cq_flags);
  1343. /* traverse through the CQEs in the hw CQ,
  1344. * find the matching CQE for a given qp,
  1345. * mark the matching one discarded by clearing qpn.
  1346. * ring the doorbell in the poll_cq() as
  1347. * we don't complete out of order cqe.
  1348. */
  1349. cur_getp = cq->getp;
  1350. /* find upto when do we reap the cq. */
  1351. stop_getp = cur_getp;
  1352. do {
  1353. if (is_hw_sq_empty(qp) && (!qp->srq && is_hw_rq_empty(qp)))
  1354. break;
  1355. cqe = cq->va + cur_getp;
  1356. /* if (a) done reaping whole hw cq, or
  1357. * (b) qp_xq becomes empty.
  1358. * then exit
  1359. */
  1360. qpn = cqe->cmn.qpn & OCRDMA_CQE_QPN_MASK;
  1361. /* if previously discarded cqe found, skip that too. */
  1362. /* check for matching qp */
  1363. if (qpn == 0 || qpn != qp->id)
  1364. goto skip_cqe;
  1365. if (is_cqe_for_sq(cqe)) {
  1366. ocrdma_hwq_inc_tail(&qp->sq);
  1367. } else {
  1368. if (qp->srq) {
  1369. wqe_idx = (le32_to_cpu(cqe->rq.buftag_qpn) >>
  1370. OCRDMA_CQE_BUFTAG_SHIFT) &
  1371. qp->srq->rq.max_wqe_idx;
  1372. if (wqe_idx < 1)
  1373. BUG();
  1374. spin_lock_irqsave(&qp->srq->q_lock, flags);
  1375. ocrdma_hwq_inc_tail(&qp->srq->rq);
  1376. ocrdma_srq_toggle_bit(qp->srq, wqe_idx - 1);
  1377. spin_unlock_irqrestore(&qp->srq->q_lock, flags);
  1378. } else {
  1379. ocrdma_hwq_inc_tail(&qp->rq);
  1380. }
  1381. }
  1382. /* mark cqe discarded so that it is not picked up later
  1383. * in the poll_cq().
  1384. */
  1385. discard_cnt += 1;
  1386. cqe->cmn.qpn = 0;
  1387. skip_cqe:
  1388. cur_getp = (cur_getp + 1) % cq->max_hw_cqe;
  1389. } while (cur_getp != stop_getp);
  1390. spin_unlock_irqrestore(&cq->cq_lock, cq_flags);
  1391. }
  1392. void ocrdma_del_flush_qp(struct ocrdma_qp *qp)
  1393. {
  1394. int found = false;
  1395. unsigned long flags;
  1396. struct ocrdma_dev *dev = qp->dev;
  1397. /* sync with any active CQ poll */
  1398. spin_lock_irqsave(&dev->flush_q_lock, flags);
  1399. found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
  1400. if (found)
  1401. list_del(&qp->sq_entry);
  1402. if (!qp->srq) {
  1403. found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
  1404. if (found)
  1405. list_del(&qp->rq_entry);
  1406. }
  1407. spin_unlock_irqrestore(&dev->flush_q_lock, flags);
  1408. }
  1409. int ocrdma_destroy_qp(struct ib_qp *ibqp)
  1410. {
  1411. int status;
  1412. struct ocrdma_pd *pd;
  1413. struct ocrdma_qp *qp;
  1414. struct ocrdma_dev *dev;
  1415. struct ib_qp_attr attrs;
  1416. int attr_mask = IB_QP_STATE;
  1417. unsigned long flags;
  1418. qp = get_ocrdma_qp(ibqp);
  1419. dev = qp->dev;
  1420. attrs.qp_state = IB_QPS_ERR;
  1421. pd = qp->pd;
  1422. /* change the QP state to ERROR */
  1423. _ocrdma_modify_qp(ibqp, &attrs, attr_mask);
  1424. /* ensure that CQEs for newly created QP (whose id may be same with
  1425. * one which just getting destroyed are same), dont get
  1426. * discarded until the old CQEs are discarded.
  1427. */
  1428. mutex_lock(&dev->dev_lock);
  1429. status = ocrdma_mbx_destroy_qp(dev, qp);
  1430. /*
  1431. * acquire CQ lock while destroy is in progress, in order to
  1432. * protect against proessing in-flight CQEs for this QP.
  1433. */
  1434. spin_lock_irqsave(&qp->sq_cq->cq_lock, flags);
  1435. if (qp->rq_cq && (qp->rq_cq != qp->sq_cq))
  1436. spin_lock(&qp->rq_cq->cq_lock);
  1437. ocrdma_del_qpn_map(dev, qp);
  1438. if (qp->rq_cq && (qp->rq_cq != qp->sq_cq))
  1439. spin_unlock(&qp->rq_cq->cq_lock);
  1440. spin_unlock_irqrestore(&qp->sq_cq->cq_lock, flags);
  1441. if (!pd->uctx) {
  1442. ocrdma_discard_cqes(qp, qp->sq_cq);
  1443. ocrdma_discard_cqes(qp, qp->rq_cq);
  1444. }
  1445. mutex_unlock(&dev->dev_lock);
  1446. if (pd->uctx) {
  1447. ocrdma_del_mmap(pd->uctx, (u64) qp->sq.pa,
  1448. PAGE_ALIGN(qp->sq.len));
  1449. if (!qp->srq)
  1450. ocrdma_del_mmap(pd->uctx, (u64) qp->rq.pa,
  1451. PAGE_ALIGN(qp->rq.len));
  1452. }
  1453. ocrdma_del_flush_qp(qp);
  1454. kfree(qp->wqe_wr_id_tbl);
  1455. kfree(qp->rqe_wr_id_tbl);
  1456. kfree(qp);
  1457. return status;
  1458. }
  1459. static int ocrdma_copy_srq_uresp(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
  1460. struct ib_udata *udata)
  1461. {
  1462. int status;
  1463. struct ocrdma_create_srq_uresp uresp;
  1464. memset(&uresp, 0, sizeof(uresp));
  1465. uresp.rq_dbid = srq->rq.dbid;
  1466. uresp.num_rq_pages = 1;
  1467. uresp.rq_page_addr[0] = srq->rq.pa;
  1468. uresp.rq_page_size = srq->rq.len;
  1469. uresp.db_page_addr = dev->nic_info.unmapped_db +
  1470. (srq->pd->id * dev->nic_info.db_page_size);
  1471. uresp.db_page_size = dev->nic_info.db_page_size;
  1472. uresp.num_rqe_allocated = srq->rq.max_cnt;
  1473. if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
  1474. uresp.db_rq_offset = OCRDMA_DB_GEN2_RQ_OFFSET;
  1475. uresp.db_shift = 24;
  1476. } else {
  1477. uresp.db_rq_offset = OCRDMA_DB_RQ_OFFSET;
  1478. uresp.db_shift = 16;
  1479. }
  1480. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  1481. if (status)
  1482. return status;
  1483. status = ocrdma_add_mmap(srq->pd->uctx, uresp.rq_page_addr[0],
  1484. uresp.rq_page_size);
  1485. if (status)
  1486. return status;
  1487. return status;
  1488. }
  1489. struct ib_srq *ocrdma_create_srq(struct ib_pd *ibpd,
  1490. struct ib_srq_init_attr *init_attr,
  1491. struct ib_udata *udata)
  1492. {
  1493. int status = -ENOMEM;
  1494. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  1495. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  1496. struct ocrdma_srq *srq;
  1497. if (init_attr->attr.max_sge > dev->attr.max_recv_sge)
  1498. return ERR_PTR(-EINVAL);
  1499. if (init_attr->attr.max_wr > dev->attr.max_rqe)
  1500. return ERR_PTR(-EINVAL);
  1501. srq = kzalloc(sizeof(*srq), GFP_KERNEL);
  1502. if (!srq)
  1503. return ERR_PTR(status);
  1504. spin_lock_init(&srq->q_lock);
  1505. srq->pd = pd;
  1506. srq->db = dev->nic_info.db + (pd->id * dev->nic_info.db_page_size);
  1507. status = ocrdma_mbx_create_srq(dev, srq, init_attr, pd);
  1508. if (status)
  1509. goto err;
  1510. if (udata == NULL) {
  1511. srq->rqe_wr_id_tbl = kzalloc(sizeof(u64) * srq->rq.max_cnt,
  1512. GFP_KERNEL);
  1513. if (srq->rqe_wr_id_tbl == NULL)
  1514. goto arm_err;
  1515. srq->bit_fields_len = (srq->rq.max_cnt / 32) +
  1516. (srq->rq.max_cnt % 32 ? 1 : 0);
  1517. srq->idx_bit_fields =
  1518. kmalloc(srq->bit_fields_len * sizeof(u32), GFP_KERNEL);
  1519. if (srq->idx_bit_fields == NULL)
  1520. goto arm_err;
  1521. memset(srq->idx_bit_fields, 0xff,
  1522. srq->bit_fields_len * sizeof(u32));
  1523. }
  1524. if (init_attr->attr.srq_limit) {
  1525. status = ocrdma_mbx_modify_srq(srq, &init_attr->attr);
  1526. if (status)
  1527. goto arm_err;
  1528. }
  1529. if (udata) {
  1530. status = ocrdma_copy_srq_uresp(dev, srq, udata);
  1531. if (status)
  1532. goto arm_err;
  1533. }
  1534. return &srq->ibsrq;
  1535. arm_err:
  1536. ocrdma_mbx_destroy_srq(dev, srq);
  1537. err:
  1538. kfree(srq->rqe_wr_id_tbl);
  1539. kfree(srq->idx_bit_fields);
  1540. kfree(srq);
  1541. return ERR_PTR(status);
  1542. }
  1543. int ocrdma_modify_srq(struct ib_srq *ibsrq,
  1544. struct ib_srq_attr *srq_attr,
  1545. enum ib_srq_attr_mask srq_attr_mask,
  1546. struct ib_udata *udata)
  1547. {
  1548. int status = 0;
  1549. struct ocrdma_srq *srq;
  1550. srq = get_ocrdma_srq(ibsrq);
  1551. if (srq_attr_mask & IB_SRQ_MAX_WR)
  1552. status = -EINVAL;
  1553. else
  1554. status = ocrdma_mbx_modify_srq(srq, srq_attr);
  1555. return status;
  1556. }
  1557. int ocrdma_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr)
  1558. {
  1559. int status;
  1560. struct ocrdma_srq *srq;
  1561. srq = get_ocrdma_srq(ibsrq);
  1562. status = ocrdma_mbx_query_srq(srq, srq_attr);
  1563. return status;
  1564. }
  1565. int ocrdma_destroy_srq(struct ib_srq *ibsrq)
  1566. {
  1567. int status;
  1568. struct ocrdma_srq *srq;
  1569. struct ocrdma_dev *dev = get_ocrdma_dev(ibsrq->device);
  1570. srq = get_ocrdma_srq(ibsrq);
  1571. status = ocrdma_mbx_destroy_srq(dev, srq);
  1572. if (srq->pd->uctx)
  1573. ocrdma_del_mmap(srq->pd->uctx, (u64) srq->rq.pa,
  1574. PAGE_ALIGN(srq->rq.len));
  1575. kfree(srq->idx_bit_fields);
  1576. kfree(srq->rqe_wr_id_tbl);
  1577. kfree(srq);
  1578. return status;
  1579. }
  1580. /* unprivileged verbs and their support functions. */
  1581. static void ocrdma_build_ud_hdr(struct ocrdma_qp *qp,
  1582. struct ocrdma_hdr_wqe *hdr,
  1583. struct ib_send_wr *wr)
  1584. {
  1585. struct ocrdma_ewqe_ud_hdr *ud_hdr =
  1586. (struct ocrdma_ewqe_ud_hdr *)(hdr + 1);
  1587. struct ocrdma_ah *ah = get_ocrdma_ah(wr->wr.ud.ah);
  1588. ud_hdr->rsvd_dest_qpn = wr->wr.ud.remote_qpn;
  1589. if (qp->qp_type == IB_QPT_GSI)
  1590. ud_hdr->qkey = qp->qkey;
  1591. else
  1592. ud_hdr->qkey = wr->wr.ud.remote_qkey;
  1593. ud_hdr->rsvd_ahid = ah->id;
  1594. }
  1595. static void ocrdma_build_sges(struct ocrdma_hdr_wqe *hdr,
  1596. struct ocrdma_sge *sge, int num_sge,
  1597. struct ib_sge *sg_list)
  1598. {
  1599. int i;
  1600. for (i = 0; i < num_sge; i++) {
  1601. sge[i].lrkey = sg_list[i].lkey;
  1602. sge[i].addr_lo = sg_list[i].addr;
  1603. sge[i].addr_hi = upper_32_bits(sg_list[i].addr);
  1604. sge[i].len = sg_list[i].length;
  1605. hdr->total_len += sg_list[i].length;
  1606. }
  1607. if (num_sge == 0)
  1608. memset(sge, 0, sizeof(*sge));
  1609. }
  1610. static inline uint32_t ocrdma_sglist_len(struct ib_sge *sg_list, int num_sge)
  1611. {
  1612. uint32_t total_len = 0, i;
  1613. for (i = 0; i < num_sge; i++)
  1614. total_len += sg_list[i].length;
  1615. return total_len;
  1616. }
  1617. static int ocrdma_build_inline_sges(struct ocrdma_qp *qp,
  1618. struct ocrdma_hdr_wqe *hdr,
  1619. struct ocrdma_sge *sge,
  1620. struct ib_send_wr *wr, u32 wqe_size)
  1621. {
  1622. int i;
  1623. char *dpp_addr;
  1624. if (wr->send_flags & IB_SEND_INLINE && qp->qp_type != IB_QPT_UD) {
  1625. hdr->total_len = ocrdma_sglist_len(wr->sg_list, wr->num_sge);
  1626. if (unlikely(hdr->total_len > qp->max_inline_data)) {
  1627. pr_err("%s() supported_len=0x%x,\n"
  1628. " unspported len req=0x%x\n", __func__,
  1629. qp->max_inline_data, hdr->total_len);
  1630. return -EINVAL;
  1631. }
  1632. dpp_addr = (char *)sge;
  1633. for (i = 0; i < wr->num_sge; i++) {
  1634. memcpy(dpp_addr,
  1635. (void *)(unsigned long)wr->sg_list[i].addr,
  1636. wr->sg_list[i].length);
  1637. dpp_addr += wr->sg_list[i].length;
  1638. }
  1639. wqe_size += roundup(hdr->total_len, OCRDMA_WQE_ALIGN_BYTES);
  1640. if (0 == hdr->total_len)
  1641. wqe_size += sizeof(struct ocrdma_sge);
  1642. hdr->cw |= (OCRDMA_TYPE_INLINE << OCRDMA_WQE_TYPE_SHIFT);
  1643. } else {
  1644. ocrdma_build_sges(hdr, sge, wr->num_sge, wr->sg_list);
  1645. if (wr->num_sge)
  1646. wqe_size += (wr->num_sge * sizeof(struct ocrdma_sge));
  1647. else
  1648. wqe_size += sizeof(struct ocrdma_sge);
  1649. hdr->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1650. }
  1651. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1652. return 0;
  1653. }
  1654. static int ocrdma_build_send(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1655. struct ib_send_wr *wr)
  1656. {
  1657. int status;
  1658. struct ocrdma_sge *sge;
  1659. u32 wqe_size = sizeof(*hdr);
  1660. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  1661. ocrdma_build_ud_hdr(qp, hdr, wr);
  1662. sge = (struct ocrdma_sge *)(hdr + 2);
  1663. wqe_size += sizeof(struct ocrdma_ewqe_ud_hdr);
  1664. } else {
  1665. sge = (struct ocrdma_sge *)(hdr + 1);
  1666. }
  1667. status = ocrdma_build_inline_sges(qp, hdr, sge, wr, wqe_size);
  1668. return status;
  1669. }
  1670. static int ocrdma_build_write(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1671. struct ib_send_wr *wr)
  1672. {
  1673. int status;
  1674. struct ocrdma_sge *ext_rw = (struct ocrdma_sge *)(hdr + 1);
  1675. struct ocrdma_sge *sge = ext_rw + 1;
  1676. u32 wqe_size = sizeof(*hdr) + sizeof(*ext_rw);
  1677. status = ocrdma_build_inline_sges(qp, hdr, sge, wr, wqe_size);
  1678. if (status)
  1679. return status;
  1680. ext_rw->addr_lo = wr->wr.rdma.remote_addr;
  1681. ext_rw->addr_hi = upper_32_bits(wr->wr.rdma.remote_addr);
  1682. ext_rw->lrkey = wr->wr.rdma.rkey;
  1683. ext_rw->len = hdr->total_len;
  1684. return 0;
  1685. }
  1686. static void ocrdma_build_read(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1687. struct ib_send_wr *wr)
  1688. {
  1689. struct ocrdma_sge *ext_rw = (struct ocrdma_sge *)(hdr + 1);
  1690. struct ocrdma_sge *sge = ext_rw + 1;
  1691. u32 wqe_size = ((wr->num_sge + 1) * sizeof(struct ocrdma_sge)) +
  1692. sizeof(struct ocrdma_hdr_wqe);
  1693. ocrdma_build_sges(hdr, sge, wr->num_sge, wr->sg_list);
  1694. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1695. hdr->cw |= (OCRDMA_READ << OCRDMA_WQE_OPCODE_SHIFT);
  1696. hdr->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1697. ext_rw->addr_lo = wr->wr.rdma.remote_addr;
  1698. ext_rw->addr_hi = upper_32_bits(wr->wr.rdma.remote_addr);
  1699. ext_rw->lrkey = wr->wr.rdma.rkey;
  1700. ext_rw->len = hdr->total_len;
  1701. }
  1702. static void build_frmr_pbes(struct ib_send_wr *wr, struct ocrdma_pbl *pbl_tbl,
  1703. struct ocrdma_hw_mr *hwmr)
  1704. {
  1705. int i;
  1706. u64 buf_addr = 0;
  1707. int num_pbes;
  1708. struct ocrdma_pbe *pbe;
  1709. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  1710. num_pbes = 0;
  1711. /* go through the OS phy regions & fill hw pbe entries into pbls. */
  1712. for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
  1713. /* number of pbes can be more for one OS buf, when
  1714. * buffers are of different sizes.
  1715. * split the ib_buf to one or more pbes.
  1716. */
  1717. buf_addr = wr->wr.fast_reg.page_list->page_list[i];
  1718. pbe->pa_lo = cpu_to_le32((u32) (buf_addr & PAGE_MASK));
  1719. pbe->pa_hi = cpu_to_le32((u32) upper_32_bits(buf_addr));
  1720. num_pbes += 1;
  1721. pbe++;
  1722. /* if the pbl is full storing the pbes,
  1723. * move to next pbl.
  1724. */
  1725. if (num_pbes == (hwmr->pbl_size/sizeof(u64))) {
  1726. pbl_tbl++;
  1727. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  1728. }
  1729. }
  1730. return;
  1731. }
  1732. static int get_encoded_page_size(int pg_sz)
  1733. {
  1734. /* Max size is 256M 4096 << 16 */
  1735. int i = 0;
  1736. for (; i < 17; i++)
  1737. if (pg_sz == (4096 << i))
  1738. break;
  1739. return i;
  1740. }
  1741. static int ocrdma_build_fr(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1742. struct ib_send_wr *wr)
  1743. {
  1744. u64 fbo;
  1745. struct ocrdma_ewqe_fr *fast_reg = (struct ocrdma_ewqe_fr *)(hdr + 1);
  1746. struct ocrdma_mr *mr;
  1747. u32 wqe_size = sizeof(*fast_reg) + sizeof(*hdr);
  1748. wqe_size = roundup(wqe_size, OCRDMA_WQE_ALIGN_BYTES);
  1749. if (wr->wr.fast_reg.page_list_len > qp->dev->attr.max_pages_per_frmr)
  1750. return -EINVAL;
  1751. hdr->cw |= (OCRDMA_FR_MR << OCRDMA_WQE_OPCODE_SHIFT);
  1752. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1753. if (wr->wr.fast_reg.page_list_len == 0)
  1754. BUG();
  1755. if (wr->wr.fast_reg.access_flags & IB_ACCESS_LOCAL_WRITE)
  1756. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_LOCAL_WR;
  1757. if (wr->wr.fast_reg.access_flags & IB_ACCESS_REMOTE_WRITE)
  1758. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_REMOTE_WR;
  1759. if (wr->wr.fast_reg.access_flags & IB_ACCESS_REMOTE_READ)
  1760. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_REMOTE_RD;
  1761. hdr->lkey = wr->wr.fast_reg.rkey;
  1762. hdr->total_len = wr->wr.fast_reg.length;
  1763. fbo = wr->wr.fast_reg.iova_start -
  1764. (wr->wr.fast_reg.page_list->page_list[0] & PAGE_MASK);
  1765. fast_reg->va_hi = upper_32_bits(wr->wr.fast_reg.iova_start);
  1766. fast_reg->va_lo = (u32) (wr->wr.fast_reg.iova_start & 0xffffffff);
  1767. fast_reg->fbo_hi = upper_32_bits(fbo);
  1768. fast_reg->fbo_lo = (u32) fbo & 0xffffffff;
  1769. fast_reg->num_sges = wr->wr.fast_reg.page_list_len;
  1770. fast_reg->size_sge =
  1771. get_encoded_page_size(1 << wr->wr.fast_reg.page_shift);
  1772. mr = (struct ocrdma_mr *) (unsigned long)
  1773. qp->dev->stag_arr[(hdr->lkey >> 8) & (OCRDMA_MAX_STAG - 1)];
  1774. build_frmr_pbes(wr, mr->hwmr.pbl_table, &mr->hwmr);
  1775. return 0;
  1776. }
  1777. static void ocrdma_ring_sq_db(struct ocrdma_qp *qp)
  1778. {
  1779. u32 val = qp->sq.dbid | (1 << OCRDMA_DB_SQ_SHIFT);
  1780. iowrite32(val, qp->sq_db);
  1781. }
  1782. int ocrdma_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  1783. struct ib_send_wr **bad_wr)
  1784. {
  1785. int status = 0;
  1786. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1787. struct ocrdma_hdr_wqe *hdr;
  1788. unsigned long flags;
  1789. spin_lock_irqsave(&qp->q_lock, flags);
  1790. if (qp->state != OCRDMA_QPS_RTS && qp->state != OCRDMA_QPS_SQD) {
  1791. spin_unlock_irqrestore(&qp->q_lock, flags);
  1792. *bad_wr = wr;
  1793. return -EINVAL;
  1794. }
  1795. while (wr) {
  1796. if (ocrdma_hwq_free_cnt(&qp->sq) == 0 ||
  1797. wr->num_sge > qp->sq.max_sges) {
  1798. *bad_wr = wr;
  1799. status = -ENOMEM;
  1800. break;
  1801. }
  1802. hdr = ocrdma_hwq_head(&qp->sq);
  1803. hdr->cw = 0;
  1804. if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
  1805. hdr->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
  1806. if (wr->send_flags & IB_SEND_FENCE)
  1807. hdr->cw |=
  1808. (OCRDMA_FLAG_FENCE_L << OCRDMA_WQE_FLAGS_SHIFT);
  1809. if (wr->send_flags & IB_SEND_SOLICITED)
  1810. hdr->cw |=
  1811. (OCRDMA_FLAG_SOLICIT << OCRDMA_WQE_FLAGS_SHIFT);
  1812. hdr->total_len = 0;
  1813. switch (wr->opcode) {
  1814. case IB_WR_SEND_WITH_IMM:
  1815. hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
  1816. hdr->immdt = ntohl(wr->ex.imm_data);
  1817. case IB_WR_SEND:
  1818. hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
  1819. ocrdma_build_send(qp, hdr, wr);
  1820. break;
  1821. case IB_WR_SEND_WITH_INV:
  1822. hdr->cw |= (OCRDMA_FLAG_INV << OCRDMA_WQE_FLAGS_SHIFT);
  1823. hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
  1824. hdr->lkey = wr->ex.invalidate_rkey;
  1825. status = ocrdma_build_send(qp, hdr, wr);
  1826. break;
  1827. case IB_WR_RDMA_WRITE_WITH_IMM:
  1828. hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
  1829. hdr->immdt = ntohl(wr->ex.imm_data);
  1830. case IB_WR_RDMA_WRITE:
  1831. hdr->cw |= (OCRDMA_WRITE << OCRDMA_WQE_OPCODE_SHIFT);
  1832. status = ocrdma_build_write(qp, hdr, wr);
  1833. break;
  1834. case IB_WR_RDMA_READ_WITH_INV:
  1835. hdr->cw |= (OCRDMA_FLAG_INV << OCRDMA_WQE_FLAGS_SHIFT);
  1836. case IB_WR_RDMA_READ:
  1837. ocrdma_build_read(qp, hdr, wr);
  1838. break;
  1839. case IB_WR_LOCAL_INV:
  1840. hdr->cw |=
  1841. (OCRDMA_LKEY_INV << OCRDMA_WQE_OPCODE_SHIFT);
  1842. hdr->cw |= ((sizeof(struct ocrdma_hdr_wqe) +
  1843. sizeof(struct ocrdma_sge)) /
  1844. OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT;
  1845. hdr->lkey = wr->ex.invalidate_rkey;
  1846. break;
  1847. case IB_WR_FAST_REG_MR:
  1848. status = ocrdma_build_fr(qp, hdr, wr);
  1849. break;
  1850. default:
  1851. status = -EINVAL;
  1852. break;
  1853. }
  1854. if (status) {
  1855. *bad_wr = wr;
  1856. break;
  1857. }
  1858. if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
  1859. qp->wqe_wr_id_tbl[qp->sq.head].signaled = 1;
  1860. else
  1861. qp->wqe_wr_id_tbl[qp->sq.head].signaled = 0;
  1862. qp->wqe_wr_id_tbl[qp->sq.head].wrid = wr->wr_id;
  1863. ocrdma_cpu_to_le32(hdr, ((hdr->cw >> OCRDMA_WQE_SIZE_SHIFT) &
  1864. OCRDMA_WQE_SIZE_MASK) * OCRDMA_WQE_STRIDE);
  1865. /* make sure wqe is written before adapter can access it */
  1866. wmb();
  1867. /* inform hw to start processing it */
  1868. ocrdma_ring_sq_db(qp);
  1869. /* update pointer, counter for next wr */
  1870. ocrdma_hwq_inc_head(&qp->sq);
  1871. wr = wr->next;
  1872. }
  1873. spin_unlock_irqrestore(&qp->q_lock, flags);
  1874. return status;
  1875. }
  1876. static void ocrdma_ring_rq_db(struct ocrdma_qp *qp)
  1877. {
  1878. u32 val = qp->rq.dbid | (1 << OCRDMA_DB_RQ_SHIFT);
  1879. iowrite32(val, qp->rq_db);
  1880. }
  1881. static void ocrdma_build_rqe(struct ocrdma_hdr_wqe *rqe, struct ib_recv_wr *wr,
  1882. u16 tag)
  1883. {
  1884. u32 wqe_size = 0;
  1885. struct ocrdma_sge *sge;
  1886. if (wr->num_sge)
  1887. wqe_size = (wr->num_sge * sizeof(*sge)) + sizeof(*rqe);
  1888. else
  1889. wqe_size = sizeof(*sge) + sizeof(*rqe);
  1890. rqe->cw = ((wqe_size / OCRDMA_WQE_STRIDE) <<
  1891. OCRDMA_WQE_SIZE_SHIFT);
  1892. rqe->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
  1893. rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1894. rqe->total_len = 0;
  1895. rqe->rsvd_tag = tag;
  1896. sge = (struct ocrdma_sge *)(rqe + 1);
  1897. ocrdma_build_sges(rqe, sge, wr->num_sge, wr->sg_list);
  1898. ocrdma_cpu_to_le32(rqe, wqe_size);
  1899. }
  1900. int ocrdma_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
  1901. struct ib_recv_wr **bad_wr)
  1902. {
  1903. int status = 0;
  1904. unsigned long flags;
  1905. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1906. struct ocrdma_hdr_wqe *rqe;
  1907. spin_lock_irqsave(&qp->q_lock, flags);
  1908. if (qp->state == OCRDMA_QPS_RST || qp->state == OCRDMA_QPS_ERR) {
  1909. spin_unlock_irqrestore(&qp->q_lock, flags);
  1910. *bad_wr = wr;
  1911. return -EINVAL;
  1912. }
  1913. while (wr) {
  1914. if (ocrdma_hwq_free_cnt(&qp->rq) == 0 ||
  1915. wr->num_sge > qp->rq.max_sges) {
  1916. *bad_wr = wr;
  1917. status = -ENOMEM;
  1918. break;
  1919. }
  1920. rqe = ocrdma_hwq_head(&qp->rq);
  1921. ocrdma_build_rqe(rqe, wr, 0);
  1922. qp->rqe_wr_id_tbl[qp->rq.head] = wr->wr_id;
  1923. /* make sure rqe is written before adapter can access it */
  1924. wmb();
  1925. /* inform hw to start processing it */
  1926. ocrdma_ring_rq_db(qp);
  1927. /* update pointer, counter for next wr */
  1928. ocrdma_hwq_inc_head(&qp->rq);
  1929. wr = wr->next;
  1930. }
  1931. spin_unlock_irqrestore(&qp->q_lock, flags);
  1932. return status;
  1933. }
  1934. /* cqe for srq's rqe can potentially arrive out of order.
  1935. * index gives the entry in the shadow table where to store
  1936. * the wr_id. tag/index is returned in cqe to reference back
  1937. * for a given rqe.
  1938. */
  1939. static int ocrdma_srq_get_idx(struct ocrdma_srq *srq)
  1940. {
  1941. int row = 0;
  1942. int indx = 0;
  1943. for (row = 0; row < srq->bit_fields_len; row++) {
  1944. if (srq->idx_bit_fields[row]) {
  1945. indx = ffs(srq->idx_bit_fields[row]);
  1946. indx = (row * 32) + (indx - 1);
  1947. if (indx >= srq->rq.max_cnt)
  1948. BUG();
  1949. ocrdma_srq_toggle_bit(srq, indx);
  1950. break;
  1951. }
  1952. }
  1953. if (row == srq->bit_fields_len)
  1954. BUG();
  1955. return indx + 1; /* Use from index 1 */
  1956. }
  1957. static void ocrdma_ring_srq_db(struct ocrdma_srq *srq)
  1958. {
  1959. u32 val = srq->rq.dbid | (1 << 16);
  1960. iowrite32(val, srq->db + OCRDMA_DB_GEN2_SRQ_OFFSET);
  1961. }
  1962. int ocrdma_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
  1963. struct ib_recv_wr **bad_wr)
  1964. {
  1965. int status = 0;
  1966. unsigned long flags;
  1967. struct ocrdma_srq *srq;
  1968. struct ocrdma_hdr_wqe *rqe;
  1969. u16 tag;
  1970. srq = get_ocrdma_srq(ibsrq);
  1971. spin_lock_irqsave(&srq->q_lock, flags);
  1972. while (wr) {
  1973. if (ocrdma_hwq_free_cnt(&srq->rq) == 0 ||
  1974. wr->num_sge > srq->rq.max_sges) {
  1975. status = -ENOMEM;
  1976. *bad_wr = wr;
  1977. break;
  1978. }
  1979. tag = ocrdma_srq_get_idx(srq);
  1980. rqe = ocrdma_hwq_head(&srq->rq);
  1981. ocrdma_build_rqe(rqe, wr, tag);
  1982. srq->rqe_wr_id_tbl[tag] = wr->wr_id;
  1983. /* make sure rqe is written before adapter can perform DMA */
  1984. wmb();
  1985. /* inform hw to start processing it */
  1986. ocrdma_ring_srq_db(srq);
  1987. /* update pointer, counter for next wr */
  1988. ocrdma_hwq_inc_head(&srq->rq);
  1989. wr = wr->next;
  1990. }
  1991. spin_unlock_irqrestore(&srq->q_lock, flags);
  1992. return status;
  1993. }
  1994. static enum ib_wc_status ocrdma_to_ibwc_err(u16 status)
  1995. {
  1996. enum ib_wc_status ibwc_status;
  1997. switch (status) {
  1998. case OCRDMA_CQE_GENERAL_ERR:
  1999. ibwc_status = IB_WC_GENERAL_ERR;
  2000. break;
  2001. case OCRDMA_CQE_LOC_LEN_ERR:
  2002. ibwc_status = IB_WC_LOC_LEN_ERR;
  2003. break;
  2004. case OCRDMA_CQE_LOC_QP_OP_ERR:
  2005. ibwc_status = IB_WC_LOC_QP_OP_ERR;
  2006. break;
  2007. case OCRDMA_CQE_LOC_EEC_OP_ERR:
  2008. ibwc_status = IB_WC_LOC_EEC_OP_ERR;
  2009. break;
  2010. case OCRDMA_CQE_LOC_PROT_ERR:
  2011. ibwc_status = IB_WC_LOC_PROT_ERR;
  2012. break;
  2013. case OCRDMA_CQE_WR_FLUSH_ERR:
  2014. ibwc_status = IB_WC_WR_FLUSH_ERR;
  2015. break;
  2016. case OCRDMA_CQE_MW_BIND_ERR:
  2017. ibwc_status = IB_WC_MW_BIND_ERR;
  2018. break;
  2019. case OCRDMA_CQE_BAD_RESP_ERR:
  2020. ibwc_status = IB_WC_BAD_RESP_ERR;
  2021. break;
  2022. case OCRDMA_CQE_LOC_ACCESS_ERR:
  2023. ibwc_status = IB_WC_LOC_ACCESS_ERR;
  2024. break;
  2025. case OCRDMA_CQE_REM_INV_REQ_ERR:
  2026. ibwc_status = IB_WC_REM_INV_REQ_ERR;
  2027. break;
  2028. case OCRDMA_CQE_REM_ACCESS_ERR:
  2029. ibwc_status = IB_WC_REM_ACCESS_ERR;
  2030. break;
  2031. case OCRDMA_CQE_REM_OP_ERR:
  2032. ibwc_status = IB_WC_REM_OP_ERR;
  2033. break;
  2034. case OCRDMA_CQE_RETRY_EXC_ERR:
  2035. ibwc_status = IB_WC_RETRY_EXC_ERR;
  2036. break;
  2037. case OCRDMA_CQE_RNR_RETRY_EXC_ERR:
  2038. ibwc_status = IB_WC_RNR_RETRY_EXC_ERR;
  2039. break;
  2040. case OCRDMA_CQE_LOC_RDD_VIOL_ERR:
  2041. ibwc_status = IB_WC_LOC_RDD_VIOL_ERR;
  2042. break;
  2043. case OCRDMA_CQE_REM_INV_RD_REQ_ERR:
  2044. ibwc_status = IB_WC_REM_INV_RD_REQ_ERR;
  2045. break;
  2046. case OCRDMA_CQE_REM_ABORT_ERR:
  2047. ibwc_status = IB_WC_REM_ABORT_ERR;
  2048. break;
  2049. case OCRDMA_CQE_INV_EECN_ERR:
  2050. ibwc_status = IB_WC_INV_EECN_ERR;
  2051. break;
  2052. case OCRDMA_CQE_INV_EEC_STATE_ERR:
  2053. ibwc_status = IB_WC_INV_EEC_STATE_ERR;
  2054. break;
  2055. case OCRDMA_CQE_FATAL_ERR:
  2056. ibwc_status = IB_WC_FATAL_ERR;
  2057. break;
  2058. case OCRDMA_CQE_RESP_TIMEOUT_ERR:
  2059. ibwc_status = IB_WC_RESP_TIMEOUT_ERR;
  2060. break;
  2061. default:
  2062. ibwc_status = IB_WC_GENERAL_ERR;
  2063. break;
  2064. }
  2065. return ibwc_status;
  2066. }
  2067. static void ocrdma_update_wc(struct ocrdma_qp *qp, struct ib_wc *ibwc,
  2068. u32 wqe_idx)
  2069. {
  2070. struct ocrdma_hdr_wqe *hdr;
  2071. struct ocrdma_sge *rw;
  2072. int opcode;
  2073. hdr = ocrdma_hwq_head_from_idx(&qp->sq, wqe_idx);
  2074. ibwc->wr_id = qp->wqe_wr_id_tbl[wqe_idx].wrid;
  2075. /* Undo the hdr->cw swap */
  2076. opcode = le32_to_cpu(hdr->cw) & OCRDMA_WQE_OPCODE_MASK;
  2077. switch (opcode) {
  2078. case OCRDMA_WRITE:
  2079. ibwc->opcode = IB_WC_RDMA_WRITE;
  2080. break;
  2081. case OCRDMA_READ:
  2082. rw = (struct ocrdma_sge *)(hdr + 1);
  2083. ibwc->opcode = IB_WC_RDMA_READ;
  2084. ibwc->byte_len = rw->len;
  2085. break;
  2086. case OCRDMA_SEND:
  2087. ibwc->opcode = IB_WC_SEND;
  2088. break;
  2089. case OCRDMA_FR_MR:
  2090. ibwc->opcode = IB_WC_FAST_REG_MR;
  2091. break;
  2092. case OCRDMA_LKEY_INV:
  2093. ibwc->opcode = IB_WC_LOCAL_INV;
  2094. break;
  2095. default:
  2096. ibwc->status = IB_WC_GENERAL_ERR;
  2097. pr_err("%s() invalid opcode received = 0x%x\n",
  2098. __func__, hdr->cw & OCRDMA_WQE_OPCODE_MASK);
  2099. break;
  2100. }
  2101. }
  2102. static void ocrdma_set_cqe_status_flushed(struct ocrdma_qp *qp,
  2103. struct ocrdma_cqe *cqe)
  2104. {
  2105. if (is_cqe_for_sq(cqe)) {
  2106. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2107. cqe->flags_status_srcqpn) &
  2108. ~OCRDMA_CQE_STATUS_MASK);
  2109. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2110. cqe->flags_status_srcqpn) |
  2111. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2112. OCRDMA_CQE_STATUS_SHIFT));
  2113. } else {
  2114. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  2115. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2116. cqe->flags_status_srcqpn) &
  2117. ~OCRDMA_CQE_UD_STATUS_MASK);
  2118. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2119. cqe->flags_status_srcqpn) |
  2120. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2121. OCRDMA_CQE_UD_STATUS_SHIFT));
  2122. } else {
  2123. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2124. cqe->flags_status_srcqpn) &
  2125. ~OCRDMA_CQE_STATUS_MASK);
  2126. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2127. cqe->flags_status_srcqpn) |
  2128. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2129. OCRDMA_CQE_STATUS_SHIFT));
  2130. }
  2131. }
  2132. }
  2133. static bool ocrdma_update_err_cqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2134. struct ocrdma_qp *qp, int status)
  2135. {
  2136. bool expand = false;
  2137. ibwc->byte_len = 0;
  2138. ibwc->qp = &qp->ibqp;
  2139. ibwc->status = ocrdma_to_ibwc_err(status);
  2140. ocrdma_flush_qp(qp);
  2141. ocrdma_qp_state_change(qp, IB_QPS_ERR, NULL);
  2142. /* if wqe/rqe pending for which cqe needs to be returned,
  2143. * trigger inflating it.
  2144. */
  2145. if (!is_hw_rq_empty(qp) || !is_hw_sq_empty(qp)) {
  2146. expand = true;
  2147. ocrdma_set_cqe_status_flushed(qp, cqe);
  2148. }
  2149. return expand;
  2150. }
  2151. static int ocrdma_update_err_rcqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2152. struct ocrdma_qp *qp, int status)
  2153. {
  2154. ibwc->opcode = IB_WC_RECV;
  2155. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2156. ocrdma_hwq_inc_tail(&qp->rq);
  2157. return ocrdma_update_err_cqe(ibwc, cqe, qp, status);
  2158. }
  2159. static int ocrdma_update_err_scqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2160. struct ocrdma_qp *qp, int status)
  2161. {
  2162. ocrdma_update_wc(qp, ibwc, qp->sq.tail);
  2163. ocrdma_hwq_inc_tail(&qp->sq);
  2164. return ocrdma_update_err_cqe(ibwc, cqe, qp, status);
  2165. }
  2166. static bool ocrdma_poll_err_scqe(struct ocrdma_qp *qp,
  2167. struct ocrdma_cqe *cqe, struct ib_wc *ibwc,
  2168. bool *polled, bool *stop)
  2169. {
  2170. bool expand;
  2171. int status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2172. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2173. /* when hw sq is empty, but rq is not empty, so we continue
  2174. * to keep the cqe in order to get the cq event again.
  2175. */
  2176. if (is_hw_sq_empty(qp) && !is_hw_rq_empty(qp)) {
  2177. /* when cq for rq and sq is same, it is safe to return
  2178. * flush cqe for RQEs.
  2179. */
  2180. if (!qp->srq && (qp->sq_cq == qp->rq_cq)) {
  2181. *polled = true;
  2182. status = OCRDMA_CQE_WR_FLUSH_ERR;
  2183. expand = ocrdma_update_err_rcqe(ibwc, cqe, qp, status);
  2184. } else {
  2185. /* stop processing further cqe as this cqe is used for
  2186. * triggering cq event on buddy cq of RQ.
  2187. * When QP is destroyed, this cqe will be removed
  2188. * from the cq's hardware q.
  2189. */
  2190. *polled = false;
  2191. *stop = true;
  2192. expand = false;
  2193. }
  2194. } else {
  2195. *polled = true;
  2196. expand = ocrdma_update_err_scqe(ibwc, cqe, qp, status);
  2197. }
  2198. return expand;
  2199. }
  2200. static bool ocrdma_poll_success_scqe(struct ocrdma_qp *qp,
  2201. struct ocrdma_cqe *cqe,
  2202. struct ib_wc *ibwc, bool *polled)
  2203. {
  2204. bool expand = false;
  2205. int tail = qp->sq.tail;
  2206. u32 wqe_idx;
  2207. if (!qp->wqe_wr_id_tbl[tail].signaled) {
  2208. *polled = false; /* WC cannot be consumed yet */
  2209. } else {
  2210. ibwc->status = IB_WC_SUCCESS;
  2211. ibwc->wc_flags = 0;
  2212. ibwc->qp = &qp->ibqp;
  2213. ocrdma_update_wc(qp, ibwc, tail);
  2214. *polled = true;
  2215. }
  2216. wqe_idx = (le32_to_cpu(cqe->wq.wqeidx) &
  2217. OCRDMA_CQE_WQEIDX_MASK) & qp->sq.max_wqe_idx;
  2218. if (tail != wqe_idx)
  2219. expand = true; /* Coalesced CQE can't be consumed yet */
  2220. ocrdma_hwq_inc_tail(&qp->sq);
  2221. return expand;
  2222. }
  2223. static bool ocrdma_poll_scqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2224. struct ib_wc *ibwc, bool *polled, bool *stop)
  2225. {
  2226. int status;
  2227. bool expand;
  2228. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2229. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2230. if (status == OCRDMA_CQE_SUCCESS)
  2231. expand = ocrdma_poll_success_scqe(qp, cqe, ibwc, polled);
  2232. else
  2233. expand = ocrdma_poll_err_scqe(qp, cqe, ibwc, polled, stop);
  2234. return expand;
  2235. }
  2236. static int ocrdma_update_ud_rcqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe)
  2237. {
  2238. int status;
  2239. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2240. OCRDMA_CQE_UD_STATUS_MASK) >> OCRDMA_CQE_UD_STATUS_SHIFT;
  2241. ibwc->src_qp = le32_to_cpu(cqe->flags_status_srcqpn) &
  2242. OCRDMA_CQE_SRCQP_MASK;
  2243. ibwc->pkey_index = le32_to_cpu(cqe->ud.rxlen_pkey) &
  2244. OCRDMA_CQE_PKEY_MASK;
  2245. ibwc->wc_flags = IB_WC_GRH;
  2246. ibwc->byte_len = (le32_to_cpu(cqe->ud.rxlen_pkey) >>
  2247. OCRDMA_CQE_UD_XFER_LEN_SHIFT);
  2248. return status;
  2249. }
  2250. static void ocrdma_update_free_srq_cqe(struct ib_wc *ibwc,
  2251. struct ocrdma_cqe *cqe,
  2252. struct ocrdma_qp *qp)
  2253. {
  2254. unsigned long flags;
  2255. struct ocrdma_srq *srq;
  2256. u32 wqe_idx;
  2257. srq = get_ocrdma_srq(qp->ibqp.srq);
  2258. wqe_idx = (le32_to_cpu(cqe->rq.buftag_qpn) >>
  2259. OCRDMA_CQE_BUFTAG_SHIFT) & srq->rq.max_wqe_idx;
  2260. if (wqe_idx < 1)
  2261. BUG();
  2262. ibwc->wr_id = srq->rqe_wr_id_tbl[wqe_idx];
  2263. spin_lock_irqsave(&srq->q_lock, flags);
  2264. ocrdma_srq_toggle_bit(srq, wqe_idx - 1);
  2265. spin_unlock_irqrestore(&srq->q_lock, flags);
  2266. ocrdma_hwq_inc_tail(&srq->rq);
  2267. }
  2268. static bool ocrdma_poll_err_rcqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2269. struct ib_wc *ibwc, bool *polled, bool *stop,
  2270. int status)
  2271. {
  2272. bool expand;
  2273. /* when hw_rq is empty, but wq is not empty, so continue
  2274. * to keep the cqe to get the cq event again.
  2275. */
  2276. if (is_hw_rq_empty(qp) && !is_hw_sq_empty(qp)) {
  2277. if (!qp->srq && (qp->sq_cq == qp->rq_cq)) {
  2278. *polled = true;
  2279. status = OCRDMA_CQE_WR_FLUSH_ERR;
  2280. expand = ocrdma_update_err_scqe(ibwc, cqe, qp, status);
  2281. } else {
  2282. *polled = false;
  2283. *stop = true;
  2284. expand = false;
  2285. }
  2286. } else {
  2287. *polled = true;
  2288. expand = ocrdma_update_err_rcqe(ibwc, cqe, qp, status);
  2289. }
  2290. return expand;
  2291. }
  2292. static void ocrdma_poll_success_rcqe(struct ocrdma_qp *qp,
  2293. struct ocrdma_cqe *cqe, struct ib_wc *ibwc)
  2294. {
  2295. ibwc->opcode = IB_WC_RECV;
  2296. ibwc->qp = &qp->ibqp;
  2297. ibwc->status = IB_WC_SUCCESS;
  2298. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI)
  2299. ocrdma_update_ud_rcqe(ibwc, cqe);
  2300. else
  2301. ibwc->byte_len = le32_to_cpu(cqe->rq.rxlen);
  2302. if (is_cqe_imm(cqe)) {
  2303. ibwc->ex.imm_data = htonl(le32_to_cpu(cqe->rq.lkey_immdt));
  2304. ibwc->wc_flags |= IB_WC_WITH_IMM;
  2305. } else if (is_cqe_wr_imm(cqe)) {
  2306. ibwc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  2307. ibwc->ex.imm_data = htonl(le32_to_cpu(cqe->rq.lkey_immdt));
  2308. ibwc->wc_flags |= IB_WC_WITH_IMM;
  2309. } else if (is_cqe_invalidated(cqe)) {
  2310. ibwc->ex.invalidate_rkey = le32_to_cpu(cqe->rq.lkey_immdt);
  2311. ibwc->wc_flags |= IB_WC_WITH_INVALIDATE;
  2312. }
  2313. if (qp->ibqp.srq) {
  2314. ocrdma_update_free_srq_cqe(ibwc, cqe, qp);
  2315. } else {
  2316. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2317. ocrdma_hwq_inc_tail(&qp->rq);
  2318. }
  2319. }
  2320. static bool ocrdma_poll_rcqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2321. struct ib_wc *ibwc, bool *polled, bool *stop)
  2322. {
  2323. int status;
  2324. bool expand = false;
  2325. ibwc->wc_flags = 0;
  2326. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  2327. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2328. OCRDMA_CQE_UD_STATUS_MASK) >>
  2329. OCRDMA_CQE_UD_STATUS_SHIFT;
  2330. } else {
  2331. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2332. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2333. }
  2334. if (status == OCRDMA_CQE_SUCCESS) {
  2335. *polled = true;
  2336. ocrdma_poll_success_rcqe(qp, cqe, ibwc);
  2337. } else {
  2338. expand = ocrdma_poll_err_rcqe(qp, cqe, ibwc, polled, stop,
  2339. status);
  2340. }
  2341. return expand;
  2342. }
  2343. static void ocrdma_change_cq_phase(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe,
  2344. u16 cur_getp)
  2345. {
  2346. if (cq->phase_change) {
  2347. if (cur_getp == 0)
  2348. cq->phase = (~cq->phase & OCRDMA_CQE_VALID);
  2349. } else {
  2350. /* clear valid bit */
  2351. cqe->flags_status_srcqpn = 0;
  2352. }
  2353. }
  2354. static int ocrdma_poll_hwcq(struct ocrdma_cq *cq, int num_entries,
  2355. struct ib_wc *ibwc)
  2356. {
  2357. u16 qpn = 0;
  2358. int i = 0;
  2359. bool expand = false;
  2360. int polled_hw_cqes = 0;
  2361. struct ocrdma_qp *qp = NULL;
  2362. struct ocrdma_dev *dev = get_ocrdma_dev(cq->ibcq.device);
  2363. struct ocrdma_cqe *cqe;
  2364. u16 cur_getp; bool polled = false; bool stop = false;
  2365. cur_getp = cq->getp;
  2366. while (num_entries) {
  2367. cqe = cq->va + cur_getp;
  2368. /* check whether valid cqe or not */
  2369. if (!is_cqe_valid(cq, cqe))
  2370. break;
  2371. qpn = (le32_to_cpu(cqe->cmn.qpn) & OCRDMA_CQE_QPN_MASK);
  2372. /* ignore discarded cqe */
  2373. if (qpn == 0)
  2374. goto skip_cqe;
  2375. qp = dev->qp_tbl[qpn];
  2376. BUG_ON(qp == NULL);
  2377. if (is_cqe_for_sq(cqe)) {
  2378. expand = ocrdma_poll_scqe(qp, cqe, ibwc, &polled,
  2379. &stop);
  2380. } else {
  2381. expand = ocrdma_poll_rcqe(qp, cqe, ibwc, &polled,
  2382. &stop);
  2383. }
  2384. if (expand)
  2385. goto expand_cqe;
  2386. if (stop)
  2387. goto stop_cqe;
  2388. /* clear qpn to avoid duplicate processing by discard_cqe() */
  2389. cqe->cmn.qpn = 0;
  2390. skip_cqe:
  2391. polled_hw_cqes += 1;
  2392. cur_getp = (cur_getp + 1) % cq->max_hw_cqe;
  2393. ocrdma_change_cq_phase(cq, cqe, cur_getp);
  2394. expand_cqe:
  2395. if (polled) {
  2396. num_entries -= 1;
  2397. i += 1;
  2398. ibwc = ibwc + 1;
  2399. polled = false;
  2400. }
  2401. }
  2402. stop_cqe:
  2403. cq->getp = cur_getp;
  2404. if (cq->deferred_arm) {
  2405. ocrdma_ring_cq_db(dev, cq->id, true, cq->deferred_sol,
  2406. polled_hw_cqes);
  2407. cq->deferred_arm = false;
  2408. cq->deferred_sol = false;
  2409. } else {
  2410. /* We need to pop the CQE. No need to arm */
  2411. ocrdma_ring_cq_db(dev, cq->id, false, cq->deferred_sol,
  2412. polled_hw_cqes);
  2413. cq->deferred_sol = false;
  2414. }
  2415. return i;
  2416. }
  2417. /* insert error cqe if the QP's SQ or RQ's CQ matches the CQ under poll. */
  2418. static int ocrdma_add_err_cqe(struct ocrdma_cq *cq, int num_entries,
  2419. struct ocrdma_qp *qp, struct ib_wc *ibwc)
  2420. {
  2421. int err_cqes = 0;
  2422. while (num_entries) {
  2423. if (is_hw_sq_empty(qp) && is_hw_rq_empty(qp))
  2424. break;
  2425. if (!is_hw_sq_empty(qp) && qp->sq_cq == cq) {
  2426. ocrdma_update_wc(qp, ibwc, qp->sq.tail);
  2427. ocrdma_hwq_inc_tail(&qp->sq);
  2428. } else if (!is_hw_rq_empty(qp) && qp->rq_cq == cq) {
  2429. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2430. ocrdma_hwq_inc_tail(&qp->rq);
  2431. } else {
  2432. return err_cqes;
  2433. }
  2434. ibwc->byte_len = 0;
  2435. ibwc->status = IB_WC_WR_FLUSH_ERR;
  2436. ibwc = ibwc + 1;
  2437. err_cqes += 1;
  2438. num_entries -= 1;
  2439. }
  2440. return err_cqes;
  2441. }
  2442. int ocrdma_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
  2443. {
  2444. int cqes_to_poll = num_entries;
  2445. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  2446. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  2447. int num_os_cqe = 0, err_cqes = 0;
  2448. struct ocrdma_qp *qp;
  2449. unsigned long flags;
  2450. /* poll cqes from adapter CQ */
  2451. spin_lock_irqsave(&cq->cq_lock, flags);
  2452. num_os_cqe = ocrdma_poll_hwcq(cq, cqes_to_poll, wc);
  2453. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2454. cqes_to_poll -= num_os_cqe;
  2455. if (cqes_to_poll) {
  2456. wc = wc + num_os_cqe;
  2457. /* adapter returns single error cqe when qp moves to
  2458. * error state. So insert error cqes with wc_status as
  2459. * FLUSHED for pending WQEs and RQEs of QP's SQ and RQ
  2460. * respectively which uses this CQ.
  2461. */
  2462. spin_lock_irqsave(&dev->flush_q_lock, flags);
  2463. list_for_each_entry(qp, &cq->sq_head, sq_entry) {
  2464. if (cqes_to_poll == 0)
  2465. break;
  2466. err_cqes = ocrdma_add_err_cqe(cq, cqes_to_poll, qp, wc);
  2467. cqes_to_poll -= err_cqes;
  2468. num_os_cqe += err_cqes;
  2469. wc = wc + err_cqes;
  2470. }
  2471. spin_unlock_irqrestore(&dev->flush_q_lock, flags);
  2472. }
  2473. return num_os_cqe;
  2474. }
  2475. int ocrdma_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags cq_flags)
  2476. {
  2477. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  2478. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  2479. u16 cq_id;
  2480. unsigned long flags;
  2481. bool arm_needed = false, sol_needed = false;
  2482. cq_id = cq->id;
  2483. spin_lock_irqsave(&cq->cq_lock, flags);
  2484. if (cq_flags & IB_CQ_NEXT_COMP || cq_flags & IB_CQ_SOLICITED)
  2485. arm_needed = true;
  2486. if (cq_flags & IB_CQ_SOLICITED)
  2487. sol_needed = true;
  2488. if (cq->first_arm) {
  2489. ocrdma_ring_cq_db(dev, cq_id, arm_needed, sol_needed, 0);
  2490. cq->first_arm = false;
  2491. goto skip_defer;
  2492. }
  2493. cq->deferred_arm = true;
  2494. skip_defer:
  2495. cq->deferred_sol = sol_needed;
  2496. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2497. return 0;
  2498. }
  2499. struct ib_mr *ocrdma_alloc_frmr(struct ib_pd *ibpd, int max_page_list_len)
  2500. {
  2501. int status;
  2502. struct ocrdma_mr *mr;
  2503. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  2504. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  2505. if (max_page_list_len > dev->attr.max_pages_per_frmr)
  2506. return ERR_PTR(-EINVAL);
  2507. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  2508. if (!mr)
  2509. return ERR_PTR(-ENOMEM);
  2510. status = ocrdma_get_pbl_info(dev, mr, max_page_list_len);
  2511. if (status)
  2512. goto pbl_err;
  2513. mr->hwmr.fr_mr = 1;
  2514. mr->hwmr.remote_rd = 0;
  2515. mr->hwmr.remote_wr = 0;
  2516. mr->hwmr.local_rd = 0;
  2517. mr->hwmr.local_wr = 0;
  2518. mr->hwmr.mw_bind = 0;
  2519. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  2520. if (status)
  2521. goto pbl_err;
  2522. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, 0);
  2523. if (status)
  2524. goto mbx_err;
  2525. mr->ibmr.rkey = mr->hwmr.lkey;
  2526. mr->ibmr.lkey = mr->hwmr.lkey;
  2527. dev->stag_arr[(mr->hwmr.lkey >> 8) & (OCRDMA_MAX_STAG - 1)] =
  2528. (unsigned long) mr;
  2529. return &mr->ibmr;
  2530. mbx_err:
  2531. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  2532. pbl_err:
  2533. kfree(mr);
  2534. return ERR_PTR(-ENOMEM);
  2535. }
  2536. struct ib_fast_reg_page_list *ocrdma_alloc_frmr_page_list(struct ib_device
  2537. *ibdev,
  2538. int page_list_len)
  2539. {
  2540. struct ib_fast_reg_page_list *frmr_list;
  2541. int size;
  2542. size = sizeof(*frmr_list) + (page_list_len * sizeof(u64));
  2543. frmr_list = kzalloc(size, GFP_KERNEL);
  2544. if (!frmr_list)
  2545. return ERR_PTR(-ENOMEM);
  2546. frmr_list->page_list = (u64 *)(frmr_list + 1);
  2547. return frmr_list;
  2548. }
  2549. void ocrdma_free_frmr_page_list(struct ib_fast_reg_page_list *page_list)
  2550. {
  2551. kfree(page_list);
  2552. }
  2553. #define MAX_KERNEL_PBE_SIZE 65536
  2554. static inline int count_kernel_pbes(struct ib_phys_buf *buf_list,
  2555. int buf_cnt, u32 *pbe_size)
  2556. {
  2557. u64 total_size = 0;
  2558. u64 buf_size = 0;
  2559. int i;
  2560. *pbe_size = roundup(buf_list[0].size, PAGE_SIZE);
  2561. *pbe_size = roundup_pow_of_two(*pbe_size);
  2562. /* find the smallest PBE size that we can have */
  2563. for (i = 0; i < buf_cnt; i++) {
  2564. /* first addr may not be page aligned, so ignore checking */
  2565. if ((i != 0) && ((buf_list[i].addr & ~PAGE_MASK) ||
  2566. (buf_list[i].size & ~PAGE_MASK))) {
  2567. return 0;
  2568. }
  2569. /* if configured PBE size is greater then the chosen one,
  2570. * reduce the PBE size.
  2571. */
  2572. buf_size = roundup(buf_list[i].size, PAGE_SIZE);
  2573. /* pbe_size has to be even multiple of 4K 1,2,4,8...*/
  2574. buf_size = roundup_pow_of_two(buf_size);
  2575. if (*pbe_size > buf_size)
  2576. *pbe_size = buf_size;
  2577. total_size += buf_size;
  2578. }
  2579. *pbe_size = *pbe_size > MAX_KERNEL_PBE_SIZE ?
  2580. (MAX_KERNEL_PBE_SIZE) : (*pbe_size);
  2581. /* num_pbes = total_size / (*pbe_size); this is implemented below. */
  2582. return total_size >> ilog2(*pbe_size);
  2583. }
  2584. static void build_kernel_pbes(struct ib_phys_buf *buf_list, int ib_buf_cnt,
  2585. u32 pbe_size, struct ocrdma_pbl *pbl_tbl,
  2586. struct ocrdma_hw_mr *hwmr)
  2587. {
  2588. int i;
  2589. int idx;
  2590. int pbes_per_buf = 0;
  2591. u64 buf_addr = 0;
  2592. int num_pbes;
  2593. struct ocrdma_pbe *pbe;
  2594. int total_num_pbes = 0;
  2595. if (!hwmr->num_pbes)
  2596. return;
  2597. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  2598. num_pbes = 0;
  2599. /* go through the OS phy regions & fill hw pbe entries into pbls. */
  2600. for (i = 0; i < ib_buf_cnt; i++) {
  2601. buf_addr = buf_list[i].addr;
  2602. pbes_per_buf =
  2603. roundup_pow_of_two(roundup(buf_list[i].size, PAGE_SIZE)) /
  2604. pbe_size;
  2605. hwmr->len += buf_list[i].size;
  2606. /* number of pbes can be more for one OS buf, when
  2607. * buffers are of different sizes.
  2608. * split the ib_buf to one or more pbes.
  2609. */
  2610. for (idx = 0; idx < pbes_per_buf; idx++) {
  2611. /* we program always page aligned addresses,
  2612. * first unaligned address is taken care by fbo.
  2613. */
  2614. if (i == 0) {
  2615. /* for non zero fbo, assign the
  2616. * start of the page.
  2617. */
  2618. pbe->pa_lo =
  2619. cpu_to_le32((u32) (buf_addr & PAGE_MASK));
  2620. pbe->pa_hi =
  2621. cpu_to_le32((u32) upper_32_bits(buf_addr));
  2622. } else {
  2623. pbe->pa_lo =
  2624. cpu_to_le32((u32) (buf_addr & 0xffffffff));
  2625. pbe->pa_hi =
  2626. cpu_to_le32((u32) upper_32_bits(buf_addr));
  2627. }
  2628. buf_addr += pbe_size;
  2629. num_pbes += 1;
  2630. total_num_pbes += 1;
  2631. pbe++;
  2632. if (total_num_pbes == hwmr->num_pbes)
  2633. goto mr_tbl_done;
  2634. /* if the pbl is full storing the pbes,
  2635. * move to next pbl.
  2636. */
  2637. if (num_pbes == (hwmr->pbl_size/sizeof(u64))) {
  2638. pbl_tbl++;
  2639. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  2640. num_pbes = 0;
  2641. }
  2642. }
  2643. }
  2644. mr_tbl_done:
  2645. return;
  2646. }
  2647. struct ib_mr *ocrdma_reg_kernel_mr(struct ib_pd *ibpd,
  2648. struct ib_phys_buf *buf_list,
  2649. int buf_cnt, int acc, u64 *iova_start)
  2650. {
  2651. int status = -ENOMEM;
  2652. struct ocrdma_mr *mr;
  2653. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  2654. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  2655. u32 num_pbes;
  2656. u32 pbe_size = 0;
  2657. if ((acc & IB_ACCESS_REMOTE_WRITE) && !(acc & IB_ACCESS_LOCAL_WRITE))
  2658. return ERR_PTR(-EINVAL);
  2659. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  2660. if (!mr)
  2661. return ERR_PTR(status);
  2662. num_pbes = count_kernel_pbes(buf_list, buf_cnt, &pbe_size);
  2663. if (num_pbes == 0) {
  2664. status = -EINVAL;
  2665. goto pbl_err;
  2666. }
  2667. status = ocrdma_get_pbl_info(dev, mr, num_pbes);
  2668. if (status)
  2669. goto pbl_err;
  2670. mr->hwmr.pbe_size = pbe_size;
  2671. mr->hwmr.fbo = *iova_start - (buf_list[0].addr & PAGE_MASK);
  2672. mr->hwmr.va = *iova_start;
  2673. mr->hwmr.local_rd = 1;
  2674. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  2675. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  2676. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  2677. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  2678. mr->hwmr.mw_bind = (acc & IB_ACCESS_MW_BIND) ? 1 : 0;
  2679. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  2680. if (status)
  2681. goto pbl_err;
  2682. build_kernel_pbes(buf_list, buf_cnt, pbe_size, mr->hwmr.pbl_table,
  2683. &mr->hwmr);
  2684. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, acc);
  2685. if (status)
  2686. goto mbx_err;
  2687. mr->ibmr.lkey = mr->hwmr.lkey;
  2688. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  2689. mr->ibmr.rkey = mr->hwmr.lkey;
  2690. return &mr->ibmr;
  2691. mbx_err:
  2692. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  2693. pbl_err:
  2694. kfree(mr);
  2695. return ERR_PTR(status);
  2696. }