mr.c 28 KB

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  1. /*
  2. * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/kref.h>
  33. #include <linux/random.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/export.h>
  36. #include <linux/delay.h>
  37. #include <rdma/ib_umem.h>
  38. #include "mlx5_ib.h"
  39. enum {
  40. MAX_PENDING_REG_MR = 8,
  41. };
  42. enum {
  43. MLX5_UMR_ALIGN = 2048
  44. };
  45. static __be64 *mr_align(__be64 *ptr, int align)
  46. {
  47. unsigned long mask = align - 1;
  48. return (__be64 *)(((unsigned long)ptr + mask) & ~mask);
  49. }
  50. static int order2idx(struct mlx5_ib_dev *dev, int order)
  51. {
  52. struct mlx5_mr_cache *cache = &dev->cache;
  53. if (order < cache->ent[0].order)
  54. return 0;
  55. else
  56. return order - cache->ent[0].order;
  57. }
  58. static void reg_mr_callback(int status, void *context)
  59. {
  60. struct mlx5_ib_mr *mr = context;
  61. struct mlx5_ib_dev *dev = mr->dev;
  62. struct mlx5_mr_cache *cache = &dev->cache;
  63. int c = order2idx(dev, mr->order);
  64. struct mlx5_cache_ent *ent = &cache->ent[c];
  65. u8 key;
  66. unsigned long flags;
  67. struct mlx5_mr_table *table = &dev->mdev.priv.mr_table;
  68. int err;
  69. spin_lock_irqsave(&ent->lock, flags);
  70. ent->pending--;
  71. spin_unlock_irqrestore(&ent->lock, flags);
  72. if (status) {
  73. mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status);
  74. kfree(mr);
  75. dev->fill_delay = 1;
  76. mod_timer(&dev->delay_timer, jiffies + HZ);
  77. return;
  78. }
  79. if (mr->out.hdr.status) {
  80. mlx5_ib_warn(dev, "failed - status %d, syndorme 0x%x\n",
  81. mr->out.hdr.status,
  82. be32_to_cpu(mr->out.hdr.syndrome));
  83. kfree(mr);
  84. dev->fill_delay = 1;
  85. mod_timer(&dev->delay_timer, jiffies + HZ);
  86. return;
  87. }
  88. spin_lock_irqsave(&dev->mdev.priv.mkey_lock, flags);
  89. key = dev->mdev.priv.mkey_key++;
  90. spin_unlock_irqrestore(&dev->mdev.priv.mkey_lock, flags);
  91. mr->mmr.key = mlx5_idx_to_mkey(be32_to_cpu(mr->out.mkey) & 0xffffff) | key;
  92. cache->last_add = jiffies;
  93. spin_lock_irqsave(&ent->lock, flags);
  94. list_add_tail(&mr->list, &ent->head);
  95. ent->cur++;
  96. ent->size++;
  97. spin_unlock_irqrestore(&ent->lock, flags);
  98. write_lock_irqsave(&table->lock, flags);
  99. err = radix_tree_insert(&table->tree, mlx5_base_mkey(mr->mmr.key),
  100. &mr->mmr);
  101. if (err)
  102. pr_err("Error inserting to mr tree. 0x%x\n", -err);
  103. write_unlock_irqrestore(&table->lock, flags);
  104. }
  105. static int add_keys(struct mlx5_ib_dev *dev, int c, int num)
  106. {
  107. struct mlx5_mr_cache *cache = &dev->cache;
  108. struct mlx5_cache_ent *ent = &cache->ent[c];
  109. struct mlx5_create_mkey_mbox_in *in;
  110. struct mlx5_ib_mr *mr;
  111. int npages = 1 << ent->order;
  112. int err = 0;
  113. int i;
  114. in = kzalloc(sizeof(*in), GFP_KERNEL);
  115. if (!in)
  116. return -ENOMEM;
  117. for (i = 0; i < num; i++) {
  118. if (ent->pending >= MAX_PENDING_REG_MR) {
  119. err = -EAGAIN;
  120. break;
  121. }
  122. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  123. if (!mr) {
  124. err = -ENOMEM;
  125. break;
  126. }
  127. mr->order = ent->order;
  128. mr->umred = 1;
  129. mr->dev = dev;
  130. in->seg.status = 1 << 6;
  131. in->seg.xlt_oct_size = cpu_to_be32((npages + 1) / 2);
  132. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  133. in->seg.flags = MLX5_ACCESS_MODE_MTT | MLX5_PERM_UMR_EN;
  134. in->seg.log2_page_size = 12;
  135. spin_lock_irq(&ent->lock);
  136. ent->pending++;
  137. spin_unlock_irq(&ent->lock);
  138. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in,
  139. sizeof(*in), reg_mr_callback,
  140. mr, &mr->out);
  141. if (err) {
  142. mlx5_ib_warn(dev, "create mkey failed %d\n", err);
  143. kfree(mr);
  144. break;
  145. }
  146. }
  147. kfree(in);
  148. return err;
  149. }
  150. static void remove_keys(struct mlx5_ib_dev *dev, int c, int num)
  151. {
  152. struct mlx5_mr_cache *cache = &dev->cache;
  153. struct mlx5_cache_ent *ent = &cache->ent[c];
  154. struct mlx5_ib_mr *mr;
  155. int err;
  156. int i;
  157. for (i = 0; i < num; i++) {
  158. spin_lock_irq(&ent->lock);
  159. if (list_empty(&ent->head)) {
  160. spin_unlock_irq(&ent->lock);
  161. return;
  162. }
  163. mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
  164. list_del(&mr->list);
  165. ent->cur--;
  166. ent->size--;
  167. spin_unlock_irq(&ent->lock);
  168. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  169. if (err)
  170. mlx5_ib_warn(dev, "failed destroy mkey\n");
  171. else
  172. kfree(mr);
  173. }
  174. }
  175. static ssize_t size_write(struct file *filp, const char __user *buf,
  176. size_t count, loff_t *pos)
  177. {
  178. struct mlx5_cache_ent *ent = filp->private_data;
  179. struct mlx5_ib_dev *dev = ent->dev;
  180. char lbuf[20];
  181. u32 var;
  182. int err;
  183. int c;
  184. if (copy_from_user(lbuf, buf, sizeof(lbuf)))
  185. return -EFAULT;
  186. c = order2idx(dev, ent->order);
  187. lbuf[sizeof(lbuf) - 1] = 0;
  188. if (sscanf(lbuf, "%u", &var) != 1)
  189. return -EINVAL;
  190. if (var < ent->limit)
  191. return -EINVAL;
  192. if (var > ent->size) {
  193. do {
  194. err = add_keys(dev, c, var - ent->size);
  195. if (err && err != -EAGAIN)
  196. return err;
  197. usleep_range(3000, 5000);
  198. } while (err);
  199. } else if (var < ent->size) {
  200. remove_keys(dev, c, ent->size - var);
  201. }
  202. return count;
  203. }
  204. static ssize_t size_read(struct file *filp, char __user *buf, size_t count,
  205. loff_t *pos)
  206. {
  207. struct mlx5_cache_ent *ent = filp->private_data;
  208. char lbuf[20];
  209. int err;
  210. if (*pos)
  211. return 0;
  212. err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size);
  213. if (err < 0)
  214. return err;
  215. if (copy_to_user(buf, lbuf, err))
  216. return -EFAULT;
  217. *pos += err;
  218. return err;
  219. }
  220. static const struct file_operations size_fops = {
  221. .owner = THIS_MODULE,
  222. .open = simple_open,
  223. .write = size_write,
  224. .read = size_read,
  225. };
  226. static ssize_t limit_write(struct file *filp, const char __user *buf,
  227. size_t count, loff_t *pos)
  228. {
  229. struct mlx5_cache_ent *ent = filp->private_data;
  230. struct mlx5_ib_dev *dev = ent->dev;
  231. char lbuf[20];
  232. u32 var;
  233. int err;
  234. int c;
  235. if (copy_from_user(lbuf, buf, sizeof(lbuf)))
  236. return -EFAULT;
  237. c = order2idx(dev, ent->order);
  238. lbuf[sizeof(lbuf) - 1] = 0;
  239. if (sscanf(lbuf, "%u", &var) != 1)
  240. return -EINVAL;
  241. if (var > ent->size)
  242. return -EINVAL;
  243. ent->limit = var;
  244. if (ent->cur < ent->limit) {
  245. err = add_keys(dev, c, 2 * ent->limit - ent->cur);
  246. if (err)
  247. return err;
  248. }
  249. return count;
  250. }
  251. static ssize_t limit_read(struct file *filp, char __user *buf, size_t count,
  252. loff_t *pos)
  253. {
  254. struct mlx5_cache_ent *ent = filp->private_data;
  255. char lbuf[20];
  256. int err;
  257. if (*pos)
  258. return 0;
  259. err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit);
  260. if (err < 0)
  261. return err;
  262. if (copy_to_user(buf, lbuf, err))
  263. return -EFAULT;
  264. *pos += err;
  265. return err;
  266. }
  267. static const struct file_operations limit_fops = {
  268. .owner = THIS_MODULE,
  269. .open = simple_open,
  270. .write = limit_write,
  271. .read = limit_read,
  272. };
  273. static int someone_adding(struct mlx5_mr_cache *cache)
  274. {
  275. int i;
  276. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  277. if (cache->ent[i].cur < cache->ent[i].limit)
  278. return 1;
  279. }
  280. return 0;
  281. }
  282. static void __cache_work_func(struct mlx5_cache_ent *ent)
  283. {
  284. struct mlx5_ib_dev *dev = ent->dev;
  285. struct mlx5_mr_cache *cache = &dev->cache;
  286. int i = order2idx(dev, ent->order);
  287. int err;
  288. if (cache->stopped)
  289. return;
  290. ent = &dev->cache.ent[i];
  291. if (ent->cur < 2 * ent->limit && !dev->fill_delay) {
  292. err = add_keys(dev, i, 1);
  293. if (ent->cur < 2 * ent->limit) {
  294. if (err == -EAGAIN) {
  295. mlx5_ib_dbg(dev, "returned eagain, order %d\n",
  296. i + 2);
  297. queue_delayed_work(cache->wq, &ent->dwork,
  298. msecs_to_jiffies(3));
  299. } else if (err) {
  300. mlx5_ib_warn(dev, "command failed order %d, err %d\n",
  301. i + 2, err);
  302. queue_delayed_work(cache->wq, &ent->dwork,
  303. msecs_to_jiffies(1000));
  304. } else {
  305. queue_work(cache->wq, &ent->work);
  306. }
  307. }
  308. } else if (ent->cur > 2 * ent->limit) {
  309. if (!someone_adding(cache) &&
  310. time_after(jiffies, cache->last_add + 300 * HZ)) {
  311. remove_keys(dev, i, 1);
  312. if (ent->cur > ent->limit)
  313. queue_work(cache->wq, &ent->work);
  314. } else {
  315. queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ);
  316. }
  317. }
  318. }
  319. static void delayed_cache_work_func(struct work_struct *work)
  320. {
  321. struct mlx5_cache_ent *ent;
  322. ent = container_of(work, struct mlx5_cache_ent, dwork.work);
  323. __cache_work_func(ent);
  324. }
  325. static void cache_work_func(struct work_struct *work)
  326. {
  327. struct mlx5_cache_ent *ent;
  328. ent = container_of(work, struct mlx5_cache_ent, work);
  329. __cache_work_func(ent);
  330. }
  331. static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order)
  332. {
  333. struct mlx5_mr_cache *cache = &dev->cache;
  334. struct mlx5_ib_mr *mr = NULL;
  335. struct mlx5_cache_ent *ent;
  336. int c;
  337. int i;
  338. c = order2idx(dev, order);
  339. if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) {
  340. mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c);
  341. return NULL;
  342. }
  343. for (i = c; i < MAX_MR_CACHE_ENTRIES; i++) {
  344. ent = &cache->ent[i];
  345. mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i);
  346. spin_lock_irq(&ent->lock);
  347. if (!list_empty(&ent->head)) {
  348. mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
  349. list);
  350. list_del(&mr->list);
  351. ent->cur--;
  352. spin_unlock_irq(&ent->lock);
  353. if (ent->cur < ent->limit)
  354. queue_work(cache->wq, &ent->work);
  355. break;
  356. }
  357. spin_unlock_irq(&ent->lock);
  358. queue_work(cache->wq, &ent->work);
  359. if (mr)
  360. break;
  361. }
  362. if (!mr)
  363. cache->ent[c].miss++;
  364. return mr;
  365. }
  366. static void free_cached_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
  367. {
  368. struct mlx5_mr_cache *cache = &dev->cache;
  369. struct mlx5_cache_ent *ent;
  370. int shrink = 0;
  371. int c;
  372. c = order2idx(dev, mr->order);
  373. if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) {
  374. mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c);
  375. return;
  376. }
  377. ent = &cache->ent[c];
  378. spin_lock_irq(&ent->lock);
  379. list_add_tail(&mr->list, &ent->head);
  380. ent->cur++;
  381. if (ent->cur > 2 * ent->limit)
  382. shrink = 1;
  383. spin_unlock_irq(&ent->lock);
  384. if (shrink)
  385. queue_work(cache->wq, &ent->work);
  386. }
  387. static void clean_keys(struct mlx5_ib_dev *dev, int c)
  388. {
  389. struct mlx5_mr_cache *cache = &dev->cache;
  390. struct mlx5_cache_ent *ent = &cache->ent[c];
  391. struct mlx5_ib_mr *mr;
  392. int err;
  393. cancel_delayed_work(&ent->dwork);
  394. while (1) {
  395. spin_lock_irq(&ent->lock);
  396. if (list_empty(&ent->head)) {
  397. spin_unlock_irq(&ent->lock);
  398. return;
  399. }
  400. mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
  401. list_del(&mr->list);
  402. ent->cur--;
  403. ent->size--;
  404. spin_unlock_irq(&ent->lock);
  405. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  406. if (err)
  407. mlx5_ib_warn(dev, "failed destroy mkey\n");
  408. else
  409. kfree(mr);
  410. }
  411. }
  412. static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev)
  413. {
  414. struct mlx5_mr_cache *cache = &dev->cache;
  415. struct mlx5_cache_ent *ent;
  416. int i;
  417. if (!mlx5_debugfs_root)
  418. return 0;
  419. cache->root = debugfs_create_dir("mr_cache", dev->mdev.priv.dbg_root);
  420. if (!cache->root)
  421. return -ENOMEM;
  422. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  423. ent = &cache->ent[i];
  424. sprintf(ent->name, "%d", ent->order);
  425. ent->dir = debugfs_create_dir(ent->name, cache->root);
  426. if (!ent->dir)
  427. return -ENOMEM;
  428. ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent,
  429. &size_fops);
  430. if (!ent->fsize)
  431. return -ENOMEM;
  432. ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent,
  433. &limit_fops);
  434. if (!ent->flimit)
  435. return -ENOMEM;
  436. ent->fcur = debugfs_create_u32("cur", 0400, ent->dir,
  437. &ent->cur);
  438. if (!ent->fcur)
  439. return -ENOMEM;
  440. ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir,
  441. &ent->miss);
  442. if (!ent->fmiss)
  443. return -ENOMEM;
  444. }
  445. return 0;
  446. }
  447. static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev)
  448. {
  449. if (!mlx5_debugfs_root)
  450. return;
  451. debugfs_remove_recursive(dev->cache.root);
  452. }
  453. static void delay_time_func(unsigned long ctx)
  454. {
  455. struct mlx5_ib_dev *dev = (struct mlx5_ib_dev *)ctx;
  456. dev->fill_delay = 0;
  457. }
  458. int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
  459. {
  460. struct mlx5_mr_cache *cache = &dev->cache;
  461. struct mlx5_cache_ent *ent;
  462. int limit;
  463. int err;
  464. int i;
  465. cache->wq = create_singlethread_workqueue("mkey_cache");
  466. if (!cache->wq) {
  467. mlx5_ib_warn(dev, "failed to create work queue\n");
  468. return -ENOMEM;
  469. }
  470. setup_timer(&dev->delay_timer, delay_time_func, (unsigned long)dev);
  471. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  472. INIT_LIST_HEAD(&cache->ent[i].head);
  473. spin_lock_init(&cache->ent[i].lock);
  474. ent = &cache->ent[i];
  475. INIT_LIST_HEAD(&ent->head);
  476. spin_lock_init(&ent->lock);
  477. ent->order = i + 2;
  478. ent->dev = dev;
  479. if (dev->mdev.profile->mask & MLX5_PROF_MASK_MR_CACHE)
  480. limit = dev->mdev.profile->mr_cache[i].limit;
  481. else
  482. limit = 0;
  483. INIT_WORK(&ent->work, cache_work_func);
  484. INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func);
  485. ent->limit = limit;
  486. queue_work(cache->wq, &ent->work);
  487. }
  488. err = mlx5_mr_cache_debugfs_init(dev);
  489. if (err)
  490. mlx5_ib_warn(dev, "cache debugfs failure\n");
  491. return 0;
  492. }
  493. int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev)
  494. {
  495. int i;
  496. dev->cache.stopped = 1;
  497. flush_workqueue(dev->cache.wq);
  498. mlx5_mr_cache_debugfs_cleanup(dev);
  499. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++)
  500. clean_keys(dev, i);
  501. destroy_workqueue(dev->cache.wq);
  502. del_timer_sync(&dev->delay_timer);
  503. return 0;
  504. }
  505. struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc)
  506. {
  507. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  508. struct mlx5_core_dev *mdev = &dev->mdev;
  509. struct mlx5_create_mkey_mbox_in *in;
  510. struct mlx5_mkey_seg *seg;
  511. struct mlx5_ib_mr *mr;
  512. int err;
  513. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  514. if (!mr)
  515. return ERR_PTR(-ENOMEM);
  516. in = kzalloc(sizeof(*in), GFP_KERNEL);
  517. if (!in) {
  518. err = -ENOMEM;
  519. goto err_free;
  520. }
  521. seg = &in->seg;
  522. seg->flags = convert_access(acc) | MLX5_ACCESS_MODE_PA;
  523. seg->flags_pd = cpu_to_be32(to_mpd(pd)->pdn | MLX5_MKEY_LEN64);
  524. seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  525. seg->start_addr = 0;
  526. err = mlx5_core_create_mkey(mdev, &mr->mmr, in, sizeof(*in), NULL, NULL,
  527. NULL);
  528. if (err)
  529. goto err_in;
  530. kfree(in);
  531. mr->ibmr.lkey = mr->mmr.key;
  532. mr->ibmr.rkey = mr->mmr.key;
  533. mr->umem = NULL;
  534. return &mr->ibmr;
  535. err_in:
  536. kfree(in);
  537. err_free:
  538. kfree(mr);
  539. return ERR_PTR(err);
  540. }
  541. static int get_octo_len(u64 addr, u64 len, int page_size)
  542. {
  543. u64 offset;
  544. int npages;
  545. offset = addr & (page_size - 1);
  546. npages = ALIGN(len + offset, page_size) >> ilog2(page_size);
  547. return (npages + 1) / 2;
  548. }
  549. static int use_umr(int order)
  550. {
  551. return order <= 17;
  552. }
  553. static void prep_umr_reg_wqe(struct ib_pd *pd, struct ib_send_wr *wr,
  554. struct ib_sge *sg, u64 dma, int n, u32 key,
  555. int page_shift, u64 virt_addr, u64 len,
  556. int access_flags)
  557. {
  558. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  559. struct ib_mr *mr = dev->umrc.mr;
  560. sg->addr = dma;
  561. sg->length = ALIGN(sizeof(u64) * n, 64);
  562. sg->lkey = mr->lkey;
  563. wr->next = NULL;
  564. wr->send_flags = 0;
  565. wr->sg_list = sg;
  566. if (n)
  567. wr->num_sge = 1;
  568. else
  569. wr->num_sge = 0;
  570. wr->opcode = MLX5_IB_WR_UMR;
  571. wr->wr.fast_reg.page_list_len = n;
  572. wr->wr.fast_reg.page_shift = page_shift;
  573. wr->wr.fast_reg.rkey = key;
  574. wr->wr.fast_reg.iova_start = virt_addr;
  575. wr->wr.fast_reg.length = len;
  576. wr->wr.fast_reg.access_flags = access_flags;
  577. wr->wr.fast_reg.page_list = (struct ib_fast_reg_page_list *)pd;
  578. }
  579. static void prep_umr_unreg_wqe(struct mlx5_ib_dev *dev,
  580. struct ib_send_wr *wr, u32 key)
  581. {
  582. wr->send_flags = MLX5_IB_SEND_UMR_UNREG;
  583. wr->opcode = MLX5_IB_WR_UMR;
  584. wr->wr.fast_reg.rkey = key;
  585. }
  586. void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context)
  587. {
  588. struct mlx5_ib_umr_context *context;
  589. struct ib_wc wc;
  590. int err;
  591. while (1) {
  592. err = ib_poll_cq(cq, 1, &wc);
  593. if (err < 0) {
  594. pr_warn("poll cq error %d\n", err);
  595. return;
  596. }
  597. if (err == 0)
  598. break;
  599. context = (struct mlx5_ib_umr_context *) (unsigned long) wc.wr_id;
  600. context->status = wc.status;
  601. complete(&context->done);
  602. }
  603. ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
  604. }
  605. static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem,
  606. u64 virt_addr, u64 len, int npages,
  607. int page_shift, int order, int access_flags)
  608. {
  609. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  610. struct device *ddev = dev->ib_dev.dma_device;
  611. struct umr_common *umrc = &dev->umrc;
  612. struct mlx5_ib_umr_context umr_context;
  613. struct ib_send_wr wr, *bad;
  614. struct mlx5_ib_mr *mr;
  615. struct ib_sge sg;
  616. int size = sizeof(u64) * npages;
  617. int err = 0;
  618. int i;
  619. for (i = 0; i < 1; i++) {
  620. mr = alloc_cached_mr(dev, order);
  621. if (mr)
  622. break;
  623. err = add_keys(dev, order2idx(dev, order), 1);
  624. if (err && err != -EAGAIN) {
  625. mlx5_ib_warn(dev, "add_keys failed, err %d\n", err);
  626. break;
  627. }
  628. }
  629. if (!mr)
  630. return ERR_PTR(-EAGAIN);
  631. mr->pas = kmalloc(size + MLX5_UMR_ALIGN - 1, GFP_KERNEL);
  632. if (!mr->pas) {
  633. err = -ENOMEM;
  634. goto free_mr;
  635. }
  636. mlx5_ib_populate_pas(dev, umem, page_shift,
  637. mr_align(mr->pas, MLX5_UMR_ALIGN), 1);
  638. mr->dma = dma_map_single(ddev, mr_align(mr->pas, MLX5_UMR_ALIGN), size,
  639. DMA_TO_DEVICE);
  640. if (dma_mapping_error(ddev, mr->dma)) {
  641. err = -ENOMEM;
  642. goto free_pas;
  643. }
  644. memset(&wr, 0, sizeof(wr));
  645. wr.wr_id = (u64)(unsigned long)&umr_context;
  646. prep_umr_reg_wqe(pd, &wr, &sg, mr->dma, npages, mr->mmr.key, page_shift, virt_addr, len, access_flags);
  647. mlx5_ib_init_umr_context(&umr_context);
  648. down(&umrc->sem);
  649. err = ib_post_send(umrc->qp, &wr, &bad);
  650. if (err) {
  651. mlx5_ib_warn(dev, "post send failed, err %d\n", err);
  652. goto unmap_dma;
  653. } else {
  654. wait_for_completion(&umr_context.done);
  655. if (umr_context.status != IB_WC_SUCCESS) {
  656. mlx5_ib_warn(dev, "reg umr failed\n");
  657. err = -EFAULT;
  658. }
  659. }
  660. mr->mmr.iova = virt_addr;
  661. mr->mmr.size = len;
  662. mr->mmr.pd = to_mpd(pd)->pdn;
  663. unmap_dma:
  664. up(&umrc->sem);
  665. dma_unmap_single(ddev, mr->dma, size, DMA_TO_DEVICE);
  666. free_pas:
  667. kfree(mr->pas);
  668. free_mr:
  669. if (err) {
  670. free_cached_mr(dev, mr);
  671. return ERR_PTR(err);
  672. }
  673. return mr;
  674. }
  675. static struct mlx5_ib_mr *reg_create(struct ib_pd *pd, u64 virt_addr,
  676. u64 length, struct ib_umem *umem,
  677. int npages, int page_shift,
  678. int access_flags)
  679. {
  680. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  681. struct mlx5_create_mkey_mbox_in *in;
  682. struct mlx5_ib_mr *mr;
  683. int inlen;
  684. int err;
  685. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  686. if (!mr)
  687. return ERR_PTR(-ENOMEM);
  688. inlen = sizeof(*in) + sizeof(*in->pas) * ((npages + 1) / 2) * 2;
  689. in = mlx5_vzalloc(inlen);
  690. if (!in) {
  691. err = -ENOMEM;
  692. goto err_1;
  693. }
  694. mlx5_ib_populate_pas(dev, umem, page_shift, in->pas, 0);
  695. in->seg.flags = convert_access(access_flags) |
  696. MLX5_ACCESS_MODE_MTT;
  697. in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn);
  698. in->seg.start_addr = cpu_to_be64(virt_addr);
  699. in->seg.len = cpu_to_be64(length);
  700. in->seg.bsfs_octo_size = 0;
  701. in->seg.xlt_oct_size = cpu_to_be32(get_octo_len(virt_addr, length, 1 << page_shift));
  702. in->seg.log2_page_size = page_shift;
  703. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  704. in->xlat_oct_act_size = cpu_to_be32(get_octo_len(virt_addr, length,
  705. 1 << page_shift));
  706. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in, inlen, NULL,
  707. NULL, NULL);
  708. if (err) {
  709. mlx5_ib_warn(dev, "create mkey failed\n");
  710. goto err_2;
  711. }
  712. mr->umem = umem;
  713. mlx5_vfree(in);
  714. mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmr.key);
  715. return mr;
  716. err_2:
  717. mlx5_vfree(in);
  718. err_1:
  719. kfree(mr);
  720. return ERR_PTR(err);
  721. }
  722. struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
  723. u64 virt_addr, int access_flags,
  724. struct ib_udata *udata)
  725. {
  726. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  727. struct mlx5_ib_mr *mr = NULL;
  728. struct ib_umem *umem;
  729. int page_shift;
  730. int npages;
  731. int ncont;
  732. int order;
  733. int err;
  734. mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx\n",
  735. start, virt_addr, length);
  736. umem = ib_umem_get(pd->uobject->context, start, length, access_flags,
  737. 0);
  738. if (IS_ERR(umem)) {
  739. mlx5_ib_dbg(dev, "umem get failed\n");
  740. return (void *)umem;
  741. }
  742. mlx5_ib_cont_pages(umem, start, &npages, &page_shift, &ncont, &order);
  743. if (!npages) {
  744. mlx5_ib_warn(dev, "avoid zero region\n");
  745. err = -EINVAL;
  746. goto error;
  747. }
  748. mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n",
  749. npages, ncont, order, page_shift);
  750. if (use_umr(order)) {
  751. mr = reg_umr(pd, umem, virt_addr, length, ncont, page_shift,
  752. order, access_flags);
  753. if (PTR_ERR(mr) == -EAGAIN) {
  754. mlx5_ib_dbg(dev, "cache empty for order %d", order);
  755. mr = NULL;
  756. }
  757. }
  758. if (!mr)
  759. mr = reg_create(pd, virt_addr, length, umem, ncont, page_shift,
  760. access_flags);
  761. if (IS_ERR(mr)) {
  762. err = PTR_ERR(mr);
  763. goto error;
  764. }
  765. mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmr.key);
  766. mr->umem = umem;
  767. mr->npages = npages;
  768. spin_lock(&dev->mr_lock);
  769. dev->mdev.priv.reg_pages += npages;
  770. spin_unlock(&dev->mr_lock);
  771. mr->ibmr.lkey = mr->mmr.key;
  772. mr->ibmr.rkey = mr->mmr.key;
  773. return &mr->ibmr;
  774. error:
  775. ib_umem_release(umem);
  776. return ERR_PTR(err);
  777. }
  778. static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
  779. {
  780. struct umr_common *umrc = &dev->umrc;
  781. struct mlx5_ib_umr_context umr_context;
  782. struct ib_send_wr wr, *bad;
  783. int err;
  784. memset(&wr, 0, sizeof(wr));
  785. wr.wr_id = (u64)(unsigned long)&umr_context;
  786. prep_umr_unreg_wqe(dev, &wr, mr->mmr.key);
  787. mlx5_ib_init_umr_context(&umr_context);
  788. down(&umrc->sem);
  789. err = ib_post_send(umrc->qp, &wr, &bad);
  790. if (err) {
  791. up(&umrc->sem);
  792. mlx5_ib_dbg(dev, "err %d\n", err);
  793. goto error;
  794. } else {
  795. wait_for_completion(&umr_context.done);
  796. up(&umrc->sem);
  797. }
  798. if (umr_context.status != IB_WC_SUCCESS) {
  799. mlx5_ib_warn(dev, "unreg umr failed\n");
  800. err = -EFAULT;
  801. goto error;
  802. }
  803. return 0;
  804. error:
  805. return err;
  806. }
  807. int mlx5_ib_dereg_mr(struct ib_mr *ibmr)
  808. {
  809. struct mlx5_ib_dev *dev = to_mdev(ibmr->device);
  810. struct mlx5_ib_mr *mr = to_mmr(ibmr);
  811. struct ib_umem *umem = mr->umem;
  812. int npages = mr->npages;
  813. int umred = mr->umred;
  814. int err;
  815. if (!umred) {
  816. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  817. if (err) {
  818. mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n",
  819. mr->mmr.key, err);
  820. return err;
  821. }
  822. } else {
  823. err = unreg_umr(dev, mr);
  824. if (err) {
  825. mlx5_ib_warn(dev, "failed unregister\n");
  826. return err;
  827. }
  828. free_cached_mr(dev, mr);
  829. }
  830. if (umem) {
  831. ib_umem_release(umem);
  832. spin_lock(&dev->mr_lock);
  833. dev->mdev.priv.reg_pages -= npages;
  834. spin_unlock(&dev->mr_lock);
  835. }
  836. if (!umred)
  837. kfree(mr);
  838. return 0;
  839. }
  840. struct ib_mr *mlx5_ib_create_mr(struct ib_pd *pd,
  841. struct ib_mr_init_attr *mr_init_attr)
  842. {
  843. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  844. struct mlx5_create_mkey_mbox_in *in;
  845. struct mlx5_ib_mr *mr;
  846. int access_mode, err;
  847. int ndescs = roundup(mr_init_attr->max_reg_descriptors, 4);
  848. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  849. if (!mr)
  850. return ERR_PTR(-ENOMEM);
  851. in = kzalloc(sizeof(*in), GFP_KERNEL);
  852. if (!in) {
  853. err = -ENOMEM;
  854. goto err_free;
  855. }
  856. in->seg.status = 1 << 6; /* free */
  857. in->seg.xlt_oct_size = cpu_to_be32(ndescs);
  858. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  859. in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn);
  860. access_mode = MLX5_ACCESS_MODE_MTT;
  861. if (mr_init_attr->flags & IB_MR_SIGNATURE_EN) {
  862. u32 psv_index[2];
  863. in->seg.flags_pd = cpu_to_be32(be32_to_cpu(in->seg.flags_pd) |
  864. MLX5_MKEY_BSF_EN);
  865. in->seg.bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
  866. mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL);
  867. if (!mr->sig) {
  868. err = -ENOMEM;
  869. goto err_free_in;
  870. }
  871. /* create mem & wire PSVs */
  872. err = mlx5_core_create_psv(&dev->mdev, to_mpd(pd)->pdn,
  873. 2, psv_index);
  874. if (err)
  875. goto err_free_sig;
  876. access_mode = MLX5_ACCESS_MODE_KLM;
  877. mr->sig->psv_memory.psv_idx = psv_index[0];
  878. mr->sig->psv_wire.psv_idx = psv_index[1];
  879. mr->sig->sig_status_checked = true;
  880. mr->sig->sig_err_exists = false;
  881. /* Next UMR, Arm SIGERR */
  882. ++mr->sig->sigerr_count;
  883. }
  884. in->seg.flags = MLX5_PERM_UMR_EN | access_mode;
  885. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in, sizeof(*in),
  886. NULL, NULL, NULL);
  887. if (err)
  888. goto err_destroy_psv;
  889. mr->ibmr.lkey = mr->mmr.key;
  890. mr->ibmr.rkey = mr->mmr.key;
  891. mr->umem = NULL;
  892. kfree(in);
  893. return &mr->ibmr;
  894. err_destroy_psv:
  895. if (mr->sig) {
  896. if (mlx5_core_destroy_psv(&dev->mdev,
  897. mr->sig->psv_memory.psv_idx))
  898. mlx5_ib_warn(dev, "failed to destroy mem psv %d\n",
  899. mr->sig->psv_memory.psv_idx);
  900. if (mlx5_core_destroy_psv(&dev->mdev,
  901. mr->sig->psv_wire.psv_idx))
  902. mlx5_ib_warn(dev, "failed to destroy wire psv %d\n",
  903. mr->sig->psv_wire.psv_idx);
  904. }
  905. err_free_sig:
  906. kfree(mr->sig);
  907. err_free_in:
  908. kfree(in);
  909. err_free:
  910. kfree(mr);
  911. return ERR_PTR(err);
  912. }
  913. int mlx5_ib_destroy_mr(struct ib_mr *ibmr)
  914. {
  915. struct mlx5_ib_dev *dev = to_mdev(ibmr->device);
  916. struct mlx5_ib_mr *mr = to_mmr(ibmr);
  917. int err;
  918. if (mr->sig) {
  919. if (mlx5_core_destroy_psv(&dev->mdev,
  920. mr->sig->psv_memory.psv_idx))
  921. mlx5_ib_warn(dev, "failed to destroy mem psv %d\n",
  922. mr->sig->psv_memory.psv_idx);
  923. if (mlx5_core_destroy_psv(&dev->mdev,
  924. mr->sig->psv_wire.psv_idx))
  925. mlx5_ib_warn(dev, "failed to destroy wire psv %d\n",
  926. mr->sig->psv_wire.psv_idx);
  927. kfree(mr->sig);
  928. }
  929. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  930. if (err) {
  931. mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n",
  932. mr->mmr.key, err);
  933. return err;
  934. }
  935. kfree(mr);
  936. return err;
  937. }
  938. struct ib_mr *mlx5_ib_alloc_fast_reg_mr(struct ib_pd *pd,
  939. int max_page_list_len)
  940. {
  941. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  942. struct mlx5_create_mkey_mbox_in *in;
  943. struct mlx5_ib_mr *mr;
  944. int err;
  945. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  946. if (!mr)
  947. return ERR_PTR(-ENOMEM);
  948. in = kzalloc(sizeof(*in), GFP_KERNEL);
  949. if (!in) {
  950. err = -ENOMEM;
  951. goto err_free;
  952. }
  953. in->seg.status = 1 << 6; /* free */
  954. in->seg.xlt_oct_size = cpu_to_be32((max_page_list_len + 1) / 2);
  955. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  956. in->seg.flags = MLX5_PERM_UMR_EN | MLX5_ACCESS_MODE_MTT;
  957. in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn);
  958. /*
  959. * TBD not needed - issue 197292 */
  960. in->seg.log2_page_size = PAGE_SHIFT;
  961. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in, sizeof(*in), NULL,
  962. NULL, NULL);
  963. kfree(in);
  964. if (err)
  965. goto err_free;
  966. mr->ibmr.lkey = mr->mmr.key;
  967. mr->ibmr.rkey = mr->mmr.key;
  968. mr->umem = NULL;
  969. return &mr->ibmr;
  970. err_free:
  971. kfree(mr);
  972. return ERR_PTR(err);
  973. }
  974. struct ib_fast_reg_page_list *mlx5_ib_alloc_fast_reg_page_list(struct ib_device *ibdev,
  975. int page_list_len)
  976. {
  977. struct mlx5_ib_fast_reg_page_list *mfrpl;
  978. int size = page_list_len * sizeof(u64);
  979. mfrpl = kmalloc(sizeof(*mfrpl), GFP_KERNEL);
  980. if (!mfrpl)
  981. return ERR_PTR(-ENOMEM);
  982. mfrpl->ibfrpl.page_list = kmalloc(size, GFP_KERNEL);
  983. if (!mfrpl->ibfrpl.page_list)
  984. goto err_free;
  985. mfrpl->mapped_page_list = dma_alloc_coherent(ibdev->dma_device,
  986. size, &mfrpl->map,
  987. GFP_KERNEL);
  988. if (!mfrpl->mapped_page_list)
  989. goto err_free;
  990. WARN_ON(mfrpl->map & 0x3f);
  991. return &mfrpl->ibfrpl;
  992. err_free:
  993. kfree(mfrpl->ibfrpl.page_list);
  994. kfree(mfrpl);
  995. return ERR_PTR(-ENOMEM);
  996. }
  997. void mlx5_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list)
  998. {
  999. struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(page_list);
  1000. struct mlx5_ib_dev *dev = to_mdev(page_list->device);
  1001. int size = page_list->max_page_list_len * sizeof(u64);
  1002. dma_free_coherent(&dev->mdev.pdev->dev, size, mfrpl->mapped_page_list,
  1003. mfrpl->map);
  1004. kfree(mfrpl->ibfrpl.page_list);
  1005. kfree(mfrpl);
  1006. }
  1007. int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
  1008. struct ib_mr_status *mr_status)
  1009. {
  1010. struct mlx5_ib_mr *mmr = to_mmr(ibmr);
  1011. int ret = 0;
  1012. if (check_mask & ~IB_MR_CHECK_SIG_STATUS) {
  1013. pr_err("Invalid status check mask\n");
  1014. ret = -EINVAL;
  1015. goto done;
  1016. }
  1017. mr_status->fail_status = 0;
  1018. if (check_mask & IB_MR_CHECK_SIG_STATUS) {
  1019. if (!mmr->sig) {
  1020. ret = -EINVAL;
  1021. pr_err("signature status check requested on a non-signature enabled MR\n");
  1022. goto done;
  1023. }
  1024. mmr->sig->sig_status_checked = true;
  1025. if (!mmr->sig->sig_err_exists)
  1026. goto done;
  1027. if (ibmr->lkey == mmr->sig->err_item.key)
  1028. memcpy(&mr_status->sig_err, &mmr->sig->err_item,
  1029. sizeof(mr_status->sig_err));
  1030. else {
  1031. mr_status->sig_err.err_type = IB_SIG_BAD_GUARD;
  1032. mr_status->sig_err.sig_err_offset = 0;
  1033. mr_status->sig_err.key = mmr->sig->err_item.key;
  1034. }
  1035. mmr->sig->sig_err_exists = false;
  1036. mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS;
  1037. }
  1038. done:
  1039. return ret;
  1040. }