device.c 36 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362
  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/vmalloc.h>
  36. #include <rdma/ib_verbs.h>
  37. #include "iw_cxgb4.h"
  38. #define DRV_VERSION "0.1"
  39. MODULE_AUTHOR("Steve Wise");
  40. MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver");
  41. MODULE_LICENSE("Dual BSD/GPL");
  42. MODULE_VERSION(DRV_VERSION);
  43. static int allow_db_fc_on_t5;
  44. module_param(allow_db_fc_on_t5, int, 0644);
  45. MODULE_PARM_DESC(allow_db_fc_on_t5,
  46. "Allow DB Flow Control on T5 (default = 0)");
  47. static int allow_db_coalescing_on_t5;
  48. module_param(allow_db_coalescing_on_t5, int, 0644);
  49. MODULE_PARM_DESC(allow_db_coalescing_on_t5,
  50. "Allow DB Coalescing on T5 (default = 0)");
  51. struct uld_ctx {
  52. struct list_head entry;
  53. struct cxgb4_lld_info lldi;
  54. struct c4iw_dev *dev;
  55. };
  56. static LIST_HEAD(uld_ctx_list);
  57. static DEFINE_MUTEX(dev_mutex);
  58. #define DB_FC_RESUME_SIZE 64
  59. #define DB_FC_RESUME_DELAY 1
  60. #define DB_FC_DRAIN_THRESH 0
  61. static struct dentry *c4iw_debugfs_root;
  62. struct c4iw_debugfs_data {
  63. struct c4iw_dev *devp;
  64. char *buf;
  65. int bufsize;
  66. int pos;
  67. };
  68. /* registered cxgb4 netlink callbacks */
  69. static struct ibnl_client_cbs c4iw_nl_cb_table[] = {
  70. [RDMA_NL_IWPM_REG_PID] = {.dump = iwpm_register_pid_cb},
  71. [RDMA_NL_IWPM_ADD_MAPPING] = {.dump = iwpm_add_mapping_cb},
  72. [RDMA_NL_IWPM_QUERY_MAPPING] = {.dump = iwpm_add_and_query_mapping_cb},
  73. [RDMA_NL_IWPM_HANDLE_ERR] = {.dump = iwpm_mapping_error_cb},
  74. [RDMA_NL_IWPM_MAPINFO] = {.dump = iwpm_mapping_info_cb},
  75. [RDMA_NL_IWPM_MAPINFO_NUM] = {.dump = iwpm_ack_mapping_info_cb}
  76. };
  77. static int count_idrs(int id, void *p, void *data)
  78. {
  79. int *countp = data;
  80. *countp = *countp + 1;
  81. return 0;
  82. }
  83. static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
  84. loff_t *ppos)
  85. {
  86. struct c4iw_debugfs_data *d = file->private_data;
  87. return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
  88. }
  89. static int dump_qp(int id, void *p, void *data)
  90. {
  91. struct c4iw_qp *qp = p;
  92. struct c4iw_debugfs_data *qpd = data;
  93. int space;
  94. int cc;
  95. if (id != qp->wq.sq.qid)
  96. return 0;
  97. space = qpd->bufsize - qpd->pos - 1;
  98. if (space == 0)
  99. return 1;
  100. if (qp->ep) {
  101. if (qp->ep->com.local_addr.ss_family == AF_INET) {
  102. struct sockaddr_in *lsin = (struct sockaddr_in *)
  103. &qp->ep->com.local_addr;
  104. struct sockaddr_in *rsin = (struct sockaddr_in *)
  105. &qp->ep->com.remote_addr;
  106. struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
  107. &qp->ep->com.mapped_local_addr;
  108. struct sockaddr_in *mapped_rsin = (struct sockaddr_in *)
  109. &qp->ep->com.mapped_remote_addr;
  110. cc = snprintf(qpd->buf + qpd->pos, space,
  111. "rc qp sq id %u rq id %u state %u "
  112. "onchip %u ep tid %u state %u "
  113. "%pI4:%u/%u->%pI4:%u/%u\n",
  114. qp->wq.sq.qid, qp->wq.rq.qid,
  115. (int)qp->attr.state,
  116. qp->wq.sq.flags & T4_SQ_ONCHIP,
  117. qp->ep->hwtid, (int)qp->ep->com.state,
  118. &lsin->sin_addr, ntohs(lsin->sin_port),
  119. ntohs(mapped_lsin->sin_port),
  120. &rsin->sin_addr, ntohs(rsin->sin_port),
  121. ntohs(mapped_rsin->sin_port));
  122. } else {
  123. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  124. &qp->ep->com.local_addr;
  125. struct sockaddr_in6 *rsin6 = (struct sockaddr_in6 *)
  126. &qp->ep->com.remote_addr;
  127. struct sockaddr_in6 *mapped_lsin6 =
  128. (struct sockaddr_in6 *)
  129. &qp->ep->com.mapped_local_addr;
  130. struct sockaddr_in6 *mapped_rsin6 =
  131. (struct sockaddr_in6 *)
  132. &qp->ep->com.mapped_remote_addr;
  133. cc = snprintf(qpd->buf + qpd->pos, space,
  134. "rc qp sq id %u rq id %u state %u "
  135. "onchip %u ep tid %u state %u "
  136. "%pI6:%u/%u->%pI6:%u/%u\n",
  137. qp->wq.sq.qid, qp->wq.rq.qid,
  138. (int)qp->attr.state,
  139. qp->wq.sq.flags & T4_SQ_ONCHIP,
  140. qp->ep->hwtid, (int)qp->ep->com.state,
  141. &lsin6->sin6_addr,
  142. ntohs(lsin6->sin6_port),
  143. ntohs(mapped_lsin6->sin6_port),
  144. &rsin6->sin6_addr,
  145. ntohs(rsin6->sin6_port),
  146. ntohs(mapped_rsin6->sin6_port));
  147. }
  148. } else
  149. cc = snprintf(qpd->buf + qpd->pos, space,
  150. "qp sq id %u rq id %u state %u onchip %u\n",
  151. qp->wq.sq.qid, qp->wq.rq.qid,
  152. (int)qp->attr.state,
  153. qp->wq.sq.flags & T4_SQ_ONCHIP);
  154. if (cc < space)
  155. qpd->pos += cc;
  156. return 0;
  157. }
  158. static int qp_release(struct inode *inode, struct file *file)
  159. {
  160. struct c4iw_debugfs_data *qpd = file->private_data;
  161. if (!qpd) {
  162. printk(KERN_INFO "%s null qpd?\n", __func__);
  163. return 0;
  164. }
  165. vfree(qpd->buf);
  166. kfree(qpd);
  167. return 0;
  168. }
  169. static int qp_open(struct inode *inode, struct file *file)
  170. {
  171. struct c4iw_debugfs_data *qpd;
  172. int ret = 0;
  173. int count = 1;
  174. qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
  175. if (!qpd) {
  176. ret = -ENOMEM;
  177. goto out;
  178. }
  179. qpd->devp = inode->i_private;
  180. qpd->pos = 0;
  181. spin_lock_irq(&qpd->devp->lock);
  182. idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
  183. spin_unlock_irq(&qpd->devp->lock);
  184. qpd->bufsize = count * 128;
  185. qpd->buf = vmalloc(qpd->bufsize);
  186. if (!qpd->buf) {
  187. ret = -ENOMEM;
  188. goto err1;
  189. }
  190. spin_lock_irq(&qpd->devp->lock);
  191. idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
  192. spin_unlock_irq(&qpd->devp->lock);
  193. qpd->buf[qpd->pos++] = 0;
  194. file->private_data = qpd;
  195. goto out;
  196. err1:
  197. kfree(qpd);
  198. out:
  199. return ret;
  200. }
  201. static const struct file_operations qp_debugfs_fops = {
  202. .owner = THIS_MODULE,
  203. .open = qp_open,
  204. .release = qp_release,
  205. .read = debugfs_read,
  206. .llseek = default_llseek,
  207. };
  208. static int dump_stag(int id, void *p, void *data)
  209. {
  210. struct c4iw_debugfs_data *stagd = data;
  211. int space;
  212. int cc;
  213. space = stagd->bufsize - stagd->pos - 1;
  214. if (space == 0)
  215. return 1;
  216. cc = snprintf(stagd->buf + stagd->pos, space, "0x%x\n", id<<8);
  217. if (cc < space)
  218. stagd->pos += cc;
  219. return 0;
  220. }
  221. static int stag_release(struct inode *inode, struct file *file)
  222. {
  223. struct c4iw_debugfs_data *stagd = file->private_data;
  224. if (!stagd) {
  225. printk(KERN_INFO "%s null stagd?\n", __func__);
  226. return 0;
  227. }
  228. kfree(stagd->buf);
  229. kfree(stagd);
  230. return 0;
  231. }
  232. static int stag_open(struct inode *inode, struct file *file)
  233. {
  234. struct c4iw_debugfs_data *stagd;
  235. int ret = 0;
  236. int count = 1;
  237. stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
  238. if (!stagd) {
  239. ret = -ENOMEM;
  240. goto out;
  241. }
  242. stagd->devp = inode->i_private;
  243. stagd->pos = 0;
  244. spin_lock_irq(&stagd->devp->lock);
  245. idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
  246. spin_unlock_irq(&stagd->devp->lock);
  247. stagd->bufsize = count * sizeof("0x12345678\n");
  248. stagd->buf = kmalloc(stagd->bufsize, GFP_KERNEL);
  249. if (!stagd->buf) {
  250. ret = -ENOMEM;
  251. goto err1;
  252. }
  253. spin_lock_irq(&stagd->devp->lock);
  254. idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
  255. spin_unlock_irq(&stagd->devp->lock);
  256. stagd->buf[stagd->pos++] = 0;
  257. file->private_data = stagd;
  258. goto out;
  259. err1:
  260. kfree(stagd);
  261. out:
  262. return ret;
  263. }
  264. static const struct file_operations stag_debugfs_fops = {
  265. .owner = THIS_MODULE,
  266. .open = stag_open,
  267. .release = stag_release,
  268. .read = debugfs_read,
  269. .llseek = default_llseek,
  270. };
  271. static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"};
  272. static int stats_show(struct seq_file *seq, void *v)
  273. {
  274. struct c4iw_dev *dev = seq->private;
  275. seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current",
  276. "Max", "Fail");
  277. seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n",
  278. dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
  279. dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail);
  280. seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n",
  281. dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
  282. dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail);
  283. seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n",
  284. dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
  285. dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail);
  286. seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n",
  287. dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
  288. dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail);
  289. seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n",
  290. dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
  291. dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail);
  292. seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n",
  293. dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
  294. dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail);
  295. seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
  296. seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
  297. seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
  298. seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n",
  299. db_state_str[dev->db_state],
  300. dev->rdev.stats.db_state_transitions,
  301. dev->rdev.stats.db_fc_interruptions);
  302. seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full);
  303. seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n",
  304. dev->rdev.stats.act_ofld_conn_fails);
  305. seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n",
  306. dev->rdev.stats.pas_ofld_conn_fails);
  307. return 0;
  308. }
  309. static int stats_open(struct inode *inode, struct file *file)
  310. {
  311. return single_open(file, stats_show, inode->i_private);
  312. }
  313. static ssize_t stats_clear(struct file *file, const char __user *buf,
  314. size_t count, loff_t *pos)
  315. {
  316. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  317. mutex_lock(&dev->rdev.stats.lock);
  318. dev->rdev.stats.pd.max = 0;
  319. dev->rdev.stats.pd.fail = 0;
  320. dev->rdev.stats.qid.max = 0;
  321. dev->rdev.stats.qid.fail = 0;
  322. dev->rdev.stats.stag.max = 0;
  323. dev->rdev.stats.stag.fail = 0;
  324. dev->rdev.stats.pbl.max = 0;
  325. dev->rdev.stats.pbl.fail = 0;
  326. dev->rdev.stats.rqt.max = 0;
  327. dev->rdev.stats.rqt.fail = 0;
  328. dev->rdev.stats.ocqp.max = 0;
  329. dev->rdev.stats.ocqp.fail = 0;
  330. dev->rdev.stats.db_full = 0;
  331. dev->rdev.stats.db_empty = 0;
  332. dev->rdev.stats.db_drop = 0;
  333. dev->rdev.stats.db_state_transitions = 0;
  334. dev->rdev.stats.tcam_full = 0;
  335. dev->rdev.stats.act_ofld_conn_fails = 0;
  336. dev->rdev.stats.pas_ofld_conn_fails = 0;
  337. mutex_unlock(&dev->rdev.stats.lock);
  338. return count;
  339. }
  340. static const struct file_operations stats_debugfs_fops = {
  341. .owner = THIS_MODULE,
  342. .open = stats_open,
  343. .release = single_release,
  344. .read = seq_read,
  345. .llseek = seq_lseek,
  346. .write = stats_clear,
  347. };
  348. static int dump_ep(int id, void *p, void *data)
  349. {
  350. struct c4iw_ep *ep = p;
  351. struct c4iw_debugfs_data *epd = data;
  352. int space;
  353. int cc;
  354. space = epd->bufsize - epd->pos - 1;
  355. if (space == 0)
  356. return 1;
  357. if (ep->com.local_addr.ss_family == AF_INET) {
  358. struct sockaddr_in *lsin = (struct sockaddr_in *)
  359. &ep->com.local_addr;
  360. struct sockaddr_in *rsin = (struct sockaddr_in *)
  361. &ep->com.remote_addr;
  362. struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
  363. &ep->com.mapped_local_addr;
  364. struct sockaddr_in *mapped_rsin = (struct sockaddr_in *)
  365. &ep->com.mapped_remote_addr;
  366. cc = snprintf(epd->buf + epd->pos, space,
  367. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  368. "history 0x%lx hwtid %d atid %d "
  369. "%pI4:%d/%d <-> %pI4:%d/%d\n",
  370. ep, ep->com.cm_id, ep->com.qp,
  371. (int)ep->com.state, ep->com.flags,
  372. ep->com.history, ep->hwtid, ep->atid,
  373. &lsin->sin_addr, ntohs(lsin->sin_port),
  374. ntohs(mapped_lsin->sin_port),
  375. &rsin->sin_addr, ntohs(rsin->sin_port),
  376. ntohs(mapped_rsin->sin_port));
  377. } else {
  378. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  379. &ep->com.local_addr;
  380. struct sockaddr_in6 *rsin6 = (struct sockaddr_in6 *)
  381. &ep->com.remote_addr;
  382. struct sockaddr_in6 *mapped_lsin6 = (struct sockaddr_in6 *)
  383. &ep->com.mapped_local_addr;
  384. struct sockaddr_in6 *mapped_rsin6 = (struct sockaddr_in6 *)
  385. &ep->com.mapped_remote_addr;
  386. cc = snprintf(epd->buf + epd->pos, space,
  387. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  388. "history 0x%lx hwtid %d atid %d "
  389. "%pI6:%d/%d <-> %pI6:%d/%d\n",
  390. ep, ep->com.cm_id, ep->com.qp,
  391. (int)ep->com.state, ep->com.flags,
  392. ep->com.history, ep->hwtid, ep->atid,
  393. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  394. ntohs(mapped_lsin6->sin6_port),
  395. &rsin6->sin6_addr, ntohs(rsin6->sin6_port),
  396. ntohs(mapped_rsin6->sin6_port));
  397. }
  398. if (cc < space)
  399. epd->pos += cc;
  400. return 0;
  401. }
  402. static int dump_listen_ep(int id, void *p, void *data)
  403. {
  404. struct c4iw_listen_ep *ep = p;
  405. struct c4iw_debugfs_data *epd = data;
  406. int space;
  407. int cc;
  408. space = epd->bufsize - epd->pos - 1;
  409. if (space == 0)
  410. return 1;
  411. if (ep->com.local_addr.ss_family == AF_INET) {
  412. struct sockaddr_in *lsin = (struct sockaddr_in *)
  413. &ep->com.local_addr;
  414. struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
  415. &ep->com.mapped_local_addr;
  416. cc = snprintf(epd->buf + epd->pos, space,
  417. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  418. "backlog %d %pI4:%d/%d\n",
  419. ep, ep->com.cm_id, (int)ep->com.state,
  420. ep->com.flags, ep->stid, ep->backlog,
  421. &lsin->sin_addr, ntohs(lsin->sin_port),
  422. ntohs(mapped_lsin->sin_port));
  423. } else {
  424. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  425. &ep->com.local_addr;
  426. struct sockaddr_in6 *mapped_lsin6 = (struct sockaddr_in6 *)
  427. &ep->com.mapped_local_addr;
  428. cc = snprintf(epd->buf + epd->pos, space,
  429. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  430. "backlog %d %pI6:%d/%d\n",
  431. ep, ep->com.cm_id, (int)ep->com.state,
  432. ep->com.flags, ep->stid, ep->backlog,
  433. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  434. ntohs(mapped_lsin6->sin6_port));
  435. }
  436. if (cc < space)
  437. epd->pos += cc;
  438. return 0;
  439. }
  440. static int ep_release(struct inode *inode, struct file *file)
  441. {
  442. struct c4iw_debugfs_data *epd = file->private_data;
  443. if (!epd) {
  444. pr_info("%s null qpd?\n", __func__);
  445. return 0;
  446. }
  447. vfree(epd->buf);
  448. kfree(epd);
  449. return 0;
  450. }
  451. static int ep_open(struct inode *inode, struct file *file)
  452. {
  453. struct c4iw_debugfs_data *epd;
  454. int ret = 0;
  455. int count = 1;
  456. epd = kmalloc(sizeof(*epd), GFP_KERNEL);
  457. if (!epd) {
  458. ret = -ENOMEM;
  459. goto out;
  460. }
  461. epd->devp = inode->i_private;
  462. epd->pos = 0;
  463. spin_lock_irq(&epd->devp->lock);
  464. idr_for_each(&epd->devp->hwtid_idr, count_idrs, &count);
  465. idr_for_each(&epd->devp->atid_idr, count_idrs, &count);
  466. idr_for_each(&epd->devp->stid_idr, count_idrs, &count);
  467. spin_unlock_irq(&epd->devp->lock);
  468. epd->bufsize = count * 160;
  469. epd->buf = vmalloc(epd->bufsize);
  470. if (!epd->buf) {
  471. ret = -ENOMEM;
  472. goto err1;
  473. }
  474. spin_lock_irq(&epd->devp->lock);
  475. idr_for_each(&epd->devp->hwtid_idr, dump_ep, epd);
  476. idr_for_each(&epd->devp->atid_idr, dump_ep, epd);
  477. idr_for_each(&epd->devp->stid_idr, dump_listen_ep, epd);
  478. spin_unlock_irq(&epd->devp->lock);
  479. file->private_data = epd;
  480. goto out;
  481. err1:
  482. kfree(epd);
  483. out:
  484. return ret;
  485. }
  486. static const struct file_operations ep_debugfs_fops = {
  487. .owner = THIS_MODULE,
  488. .open = ep_open,
  489. .release = ep_release,
  490. .read = debugfs_read,
  491. };
  492. static int setup_debugfs(struct c4iw_dev *devp)
  493. {
  494. struct dentry *de;
  495. if (!devp->debugfs_root)
  496. return -1;
  497. de = debugfs_create_file("qps", S_IWUSR, devp->debugfs_root,
  498. (void *)devp, &qp_debugfs_fops);
  499. if (de && de->d_inode)
  500. de->d_inode->i_size = 4096;
  501. de = debugfs_create_file("stags", S_IWUSR, devp->debugfs_root,
  502. (void *)devp, &stag_debugfs_fops);
  503. if (de && de->d_inode)
  504. de->d_inode->i_size = 4096;
  505. de = debugfs_create_file("stats", S_IWUSR, devp->debugfs_root,
  506. (void *)devp, &stats_debugfs_fops);
  507. if (de && de->d_inode)
  508. de->d_inode->i_size = 4096;
  509. de = debugfs_create_file("eps", S_IWUSR, devp->debugfs_root,
  510. (void *)devp, &ep_debugfs_fops);
  511. if (de && de->d_inode)
  512. de->d_inode->i_size = 4096;
  513. return 0;
  514. }
  515. void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
  516. struct c4iw_dev_ucontext *uctx)
  517. {
  518. struct list_head *pos, *nxt;
  519. struct c4iw_qid_list *entry;
  520. mutex_lock(&uctx->lock);
  521. list_for_each_safe(pos, nxt, &uctx->qpids) {
  522. entry = list_entry(pos, struct c4iw_qid_list, entry);
  523. list_del_init(&entry->entry);
  524. if (!(entry->qid & rdev->qpmask)) {
  525. c4iw_put_resource(&rdev->resource.qid_table,
  526. entry->qid);
  527. mutex_lock(&rdev->stats.lock);
  528. rdev->stats.qid.cur -= rdev->qpmask + 1;
  529. mutex_unlock(&rdev->stats.lock);
  530. }
  531. kfree(entry);
  532. }
  533. list_for_each_safe(pos, nxt, &uctx->qpids) {
  534. entry = list_entry(pos, struct c4iw_qid_list, entry);
  535. list_del_init(&entry->entry);
  536. kfree(entry);
  537. }
  538. mutex_unlock(&uctx->lock);
  539. }
  540. void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
  541. struct c4iw_dev_ucontext *uctx)
  542. {
  543. INIT_LIST_HEAD(&uctx->qpids);
  544. INIT_LIST_HEAD(&uctx->cqids);
  545. mutex_init(&uctx->lock);
  546. }
  547. /* Caller takes care of locking if needed */
  548. static int c4iw_rdev_open(struct c4iw_rdev *rdev)
  549. {
  550. int err;
  551. c4iw_init_dev_ucontext(rdev, &rdev->uctx);
  552. /*
  553. * qpshift is the number of bits to shift the qpid left in order
  554. * to get the correct address of the doorbell for that qp.
  555. */
  556. rdev->qpshift = PAGE_SHIFT - ilog2(rdev->lldi.udb_density);
  557. rdev->qpmask = rdev->lldi.udb_density - 1;
  558. rdev->cqshift = PAGE_SHIFT - ilog2(rdev->lldi.ucq_density);
  559. rdev->cqmask = rdev->lldi.ucq_density - 1;
  560. PDBG("%s dev %s stag start 0x%0x size 0x%0x num stags %d "
  561. "pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x "
  562. "qp qid start %u size %u cq qid start %u size %u\n",
  563. __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
  564. rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
  565. rdev->lldi.vr->pbl.start,
  566. rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
  567. rdev->lldi.vr->rq.size,
  568. rdev->lldi.vr->qp.start,
  569. rdev->lldi.vr->qp.size,
  570. rdev->lldi.vr->cq.start,
  571. rdev->lldi.vr->cq.size);
  572. PDBG("udb len 0x%x udb base %llx db_reg %p gts_reg %p qpshift %lu "
  573. "qpmask 0x%x cqshift %lu cqmask 0x%x\n",
  574. (unsigned)pci_resource_len(rdev->lldi.pdev, 2),
  575. (u64)pci_resource_start(rdev->lldi.pdev, 2),
  576. rdev->lldi.db_reg,
  577. rdev->lldi.gts_reg,
  578. rdev->qpshift, rdev->qpmask,
  579. rdev->cqshift, rdev->cqmask);
  580. if (c4iw_num_stags(rdev) == 0) {
  581. err = -EINVAL;
  582. goto err1;
  583. }
  584. rdev->stats.pd.total = T4_MAX_NUM_PD;
  585. rdev->stats.stag.total = rdev->lldi.vr->stag.size;
  586. rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
  587. rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
  588. rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
  589. rdev->stats.qid.total = rdev->lldi.vr->qp.size;
  590. err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
  591. if (err) {
  592. printk(KERN_ERR MOD "error %d initializing resources\n", err);
  593. goto err1;
  594. }
  595. err = c4iw_pblpool_create(rdev);
  596. if (err) {
  597. printk(KERN_ERR MOD "error %d initializing pbl pool\n", err);
  598. goto err2;
  599. }
  600. err = c4iw_rqtpool_create(rdev);
  601. if (err) {
  602. printk(KERN_ERR MOD "error %d initializing rqt pool\n", err);
  603. goto err3;
  604. }
  605. err = c4iw_ocqp_pool_create(rdev);
  606. if (err) {
  607. printk(KERN_ERR MOD "error %d initializing ocqp pool\n", err);
  608. goto err4;
  609. }
  610. rdev->status_page = (struct t4_dev_status_page *)
  611. __get_free_page(GFP_KERNEL);
  612. if (!rdev->status_page) {
  613. pr_err(MOD "error allocating status page\n");
  614. goto err4;
  615. }
  616. rdev->status_page->db_off = 0;
  617. return 0;
  618. err4:
  619. c4iw_rqtpool_destroy(rdev);
  620. err3:
  621. c4iw_pblpool_destroy(rdev);
  622. err2:
  623. c4iw_destroy_resource(&rdev->resource);
  624. err1:
  625. return err;
  626. }
  627. static void c4iw_rdev_close(struct c4iw_rdev *rdev)
  628. {
  629. free_page((unsigned long)rdev->status_page);
  630. c4iw_pblpool_destroy(rdev);
  631. c4iw_rqtpool_destroy(rdev);
  632. c4iw_destroy_resource(&rdev->resource);
  633. }
  634. static void c4iw_dealloc(struct uld_ctx *ctx)
  635. {
  636. c4iw_rdev_close(&ctx->dev->rdev);
  637. idr_destroy(&ctx->dev->cqidr);
  638. idr_destroy(&ctx->dev->qpidr);
  639. idr_destroy(&ctx->dev->mmidr);
  640. idr_destroy(&ctx->dev->hwtid_idr);
  641. idr_destroy(&ctx->dev->stid_idr);
  642. idr_destroy(&ctx->dev->atid_idr);
  643. if (ctx->dev->rdev.bar2_kva)
  644. iounmap(ctx->dev->rdev.bar2_kva);
  645. if (ctx->dev->rdev.oc_mw_kva)
  646. iounmap(ctx->dev->rdev.oc_mw_kva);
  647. ib_dealloc_device(&ctx->dev->ibdev);
  648. ctx->dev = NULL;
  649. }
  650. static void c4iw_remove(struct uld_ctx *ctx)
  651. {
  652. PDBG("%s c4iw_dev %p\n", __func__, ctx->dev);
  653. c4iw_unregister_device(ctx->dev);
  654. c4iw_dealloc(ctx);
  655. }
  656. static int rdma_supported(const struct cxgb4_lld_info *infop)
  657. {
  658. return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
  659. infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
  660. infop->vr->cq.size > 0;
  661. }
  662. static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
  663. {
  664. struct c4iw_dev *devp;
  665. int ret;
  666. if (!rdma_supported(infop)) {
  667. printk(KERN_INFO MOD "%s: RDMA not supported on this device.\n",
  668. pci_name(infop->pdev));
  669. return ERR_PTR(-ENOSYS);
  670. }
  671. if (!ocqp_supported(infop))
  672. pr_info("%s: On-Chip Queues not supported on this device.\n",
  673. pci_name(infop->pdev));
  674. devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
  675. if (!devp) {
  676. printk(KERN_ERR MOD "Cannot allocate ib device\n");
  677. return ERR_PTR(-ENOMEM);
  678. }
  679. devp->rdev.lldi = *infop;
  680. /*
  681. * For T5 devices, we map all of BAR2 with WC.
  682. * For T4 devices with onchip qp mem, we map only that part
  683. * of BAR2 with WC.
  684. */
  685. devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2);
  686. if (is_t5(devp->rdev.lldi.adapter_type)) {
  687. devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa,
  688. pci_resource_len(devp->rdev.lldi.pdev, 2));
  689. if (!devp->rdev.bar2_kva) {
  690. pr_err(MOD "Unable to ioremap BAR2\n");
  691. ib_dealloc_device(&devp->ibdev);
  692. return ERR_PTR(-EINVAL);
  693. }
  694. } else if (ocqp_supported(infop)) {
  695. devp->rdev.oc_mw_pa =
  696. pci_resource_start(devp->rdev.lldi.pdev, 2) +
  697. pci_resource_len(devp->rdev.lldi.pdev, 2) -
  698. roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size);
  699. devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
  700. devp->rdev.lldi.vr->ocq.size);
  701. if (!devp->rdev.oc_mw_kva) {
  702. pr_err(MOD "Unable to ioremap onchip mem\n");
  703. ib_dealloc_device(&devp->ibdev);
  704. return ERR_PTR(-EINVAL);
  705. }
  706. }
  707. PDBG(KERN_INFO MOD "ocq memory: "
  708. "hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
  709. devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
  710. devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
  711. ret = c4iw_rdev_open(&devp->rdev);
  712. if (ret) {
  713. printk(KERN_ERR MOD "Unable to open CXIO rdev err %d\n", ret);
  714. ib_dealloc_device(&devp->ibdev);
  715. return ERR_PTR(ret);
  716. }
  717. idr_init(&devp->cqidr);
  718. idr_init(&devp->qpidr);
  719. idr_init(&devp->mmidr);
  720. idr_init(&devp->hwtid_idr);
  721. idr_init(&devp->stid_idr);
  722. idr_init(&devp->atid_idr);
  723. spin_lock_init(&devp->lock);
  724. mutex_init(&devp->rdev.stats.lock);
  725. mutex_init(&devp->db_mutex);
  726. INIT_LIST_HEAD(&devp->db_fc_list);
  727. if (c4iw_debugfs_root) {
  728. devp->debugfs_root = debugfs_create_dir(
  729. pci_name(devp->rdev.lldi.pdev),
  730. c4iw_debugfs_root);
  731. setup_debugfs(devp);
  732. }
  733. return devp;
  734. }
  735. static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
  736. {
  737. struct uld_ctx *ctx;
  738. static int vers_printed;
  739. int i;
  740. if (!vers_printed++)
  741. pr_info("Chelsio T4/T5 RDMA Driver - version %s\n",
  742. DRV_VERSION);
  743. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  744. if (!ctx) {
  745. ctx = ERR_PTR(-ENOMEM);
  746. goto out;
  747. }
  748. ctx->lldi = *infop;
  749. PDBG("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n",
  750. __func__, pci_name(ctx->lldi.pdev),
  751. ctx->lldi.nchan, ctx->lldi.nrxq,
  752. ctx->lldi.ntxq, ctx->lldi.nports);
  753. mutex_lock(&dev_mutex);
  754. list_add_tail(&ctx->entry, &uld_ctx_list);
  755. mutex_unlock(&dev_mutex);
  756. for (i = 0; i < ctx->lldi.nrxq; i++)
  757. PDBG("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
  758. out:
  759. return ctx;
  760. }
  761. static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl,
  762. const __be64 *rsp,
  763. u32 pktshift)
  764. {
  765. struct sk_buff *skb;
  766. /*
  767. * Allocate space for cpl_pass_accept_req which will be synthesized by
  768. * driver. Once the driver synthesizes the request the skb will go
  769. * through the regular cpl_pass_accept_req processing.
  770. * The math here assumes sizeof cpl_pass_accept_req >= sizeof
  771. * cpl_rx_pkt.
  772. */
  773. skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  774. sizeof(struct rss_header) - pktshift, GFP_ATOMIC);
  775. if (unlikely(!skb))
  776. return NULL;
  777. __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  778. sizeof(struct rss_header) - pktshift);
  779. /*
  780. * This skb will contain:
  781. * rss_header from the rspq descriptor (1 flit)
  782. * cpl_rx_pkt struct from the rspq descriptor (2 flits)
  783. * space for the difference between the size of an
  784. * rx_pkt and pass_accept_req cpl (1 flit)
  785. * the packet data from the gl
  786. */
  787. skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) +
  788. sizeof(struct rss_header));
  789. skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) +
  790. sizeof(struct cpl_pass_accept_req),
  791. gl->va + pktshift,
  792. gl->tot_len - pktshift);
  793. return skb;
  794. }
  795. static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl,
  796. const __be64 *rsp)
  797. {
  798. unsigned int opcode = *(u8 *)rsp;
  799. struct sk_buff *skb;
  800. if (opcode != CPL_RX_PKT)
  801. goto out;
  802. skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift);
  803. if (skb == NULL)
  804. goto out;
  805. if (c4iw_handlers[opcode] == NULL) {
  806. pr_info("%s no handler opcode 0x%x...\n", __func__,
  807. opcode);
  808. kfree_skb(skb);
  809. goto out;
  810. }
  811. c4iw_handlers[opcode](dev, skb);
  812. return 1;
  813. out:
  814. return 0;
  815. }
  816. static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
  817. const struct pkt_gl *gl)
  818. {
  819. struct uld_ctx *ctx = handle;
  820. struct c4iw_dev *dev = ctx->dev;
  821. struct sk_buff *skb;
  822. u8 opcode;
  823. if (gl == NULL) {
  824. /* omit RSS and rsp_ctrl at end of descriptor */
  825. unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
  826. skb = alloc_skb(256, GFP_ATOMIC);
  827. if (!skb)
  828. goto nomem;
  829. __skb_put(skb, len);
  830. skb_copy_to_linear_data(skb, &rsp[1], len);
  831. } else if (gl == CXGB4_MSG_AN) {
  832. const struct rsp_ctrl *rc = (void *)rsp;
  833. u32 qid = be32_to_cpu(rc->pldbuflen_qid);
  834. c4iw_ev_handler(dev, qid);
  835. return 0;
  836. } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) {
  837. if (recv_rx_pkt(dev, gl, rsp))
  838. return 0;
  839. pr_info("%s: unexpected FL contents at %p, " \
  840. "RSS %#llx, FL %#llx, len %u\n",
  841. pci_name(ctx->lldi.pdev), gl->va,
  842. (unsigned long long)be64_to_cpu(*rsp),
  843. (unsigned long long)be64_to_cpu(
  844. *(__force __be64 *)gl->va),
  845. gl->tot_len);
  846. return 0;
  847. } else {
  848. skb = cxgb4_pktgl_to_skb(gl, 128, 128);
  849. if (unlikely(!skb))
  850. goto nomem;
  851. }
  852. opcode = *(u8 *)rsp;
  853. if (c4iw_handlers[opcode]) {
  854. c4iw_handlers[opcode](dev, skb);
  855. } else {
  856. pr_info("%s no handler opcode 0x%x...\n", __func__,
  857. opcode);
  858. kfree_skb(skb);
  859. }
  860. return 0;
  861. nomem:
  862. return -1;
  863. }
  864. static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
  865. {
  866. struct uld_ctx *ctx = handle;
  867. PDBG("%s new_state %u\n", __func__, new_state);
  868. switch (new_state) {
  869. case CXGB4_STATE_UP:
  870. printk(KERN_INFO MOD "%s: Up\n", pci_name(ctx->lldi.pdev));
  871. if (!ctx->dev) {
  872. int ret;
  873. ctx->dev = c4iw_alloc(&ctx->lldi);
  874. if (IS_ERR(ctx->dev)) {
  875. printk(KERN_ERR MOD
  876. "%s: initialization failed: %ld\n",
  877. pci_name(ctx->lldi.pdev),
  878. PTR_ERR(ctx->dev));
  879. ctx->dev = NULL;
  880. break;
  881. }
  882. ret = c4iw_register_device(ctx->dev);
  883. if (ret) {
  884. printk(KERN_ERR MOD
  885. "%s: RDMA registration failed: %d\n",
  886. pci_name(ctx->lldi.pdev), ret);
  887. c4iw_dealloc(ctx);
  888. }
  889. }
  890. break;
  891. case CXGB4_STATE_DOWN:
  892. printk(KERN_INFO MOD "%s: Down\n",
  893. pci_name(ctx->lldi.pdev));
  894. if (ctx->dev)
  895. c4iw_remove(ctx);
  896. break;
  897. case CXGB4_STATE_START_RECOVERY:
  898. printk(KERN_INFO MOD "%s: Fatal Error\n",
  899. pci_name(ctx->lldi.pdev));
  900. if (ctx->dev) {
  901. struct ib_event event;
  902. ctx->dev->rdev.flags |= T4_FATAL_ERROR;
  903. memset(&event, 0, sizeof event);
  904. event.event = IB_EVENT_DEVICE_FATAL;
  905. event.device = &ctx->dev->ibdev;
  906. ib_dispatch_event(&event);
  907. c4iw_remove(ctx);
  908. }
  909. break;
  910. case CXGB4_STATE_DETACH:
  911. printk(KERN_INFO MOD "%s: Detach\n",
  912. pci_name(ctx->lldi.pdev));
  913. if (ctx->dev)
  914. c4iw_remove(ctx);
  915. break;
  916. }
  917. return 0;
  918. }
  919. static int disable_qp_db(int id, void *p, void *data)
  920. {
  921. struct c4iw_qp *qp = p;
  922. t4_disable_wq_db(&qp->wq);
  923. return 0;
  924. }
  925. static void stop_queues(struct uld_ctx *ctx)
  926. {
  927. unsigned long flags;
  928. spin_lock_irqsave(&ctx->dev->lock, flags);
  929. ctx->dev->rdev.stats.db_state_transitions++;
  930. ctx->dev->db_state = STOPPED;
  931. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED)
  932. idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
  933. else
  934. ctx->dev->rdev.status_page->db_off = 1;
  935. spin_unlock_irqrestore(&ctx->dev->lock, flags);
  936. }
  937. static int enable_qp_db(int id, void *p, void *data)
  938. {
  939. struct c4iw_qp *qp = p;
  940. t4_enable_wq_db(&qp->wq);
  941. return 0;
  942. }
  943. static void resume_rc_qp(struct c4iw_qp *qp)
  944. {
  945. spin_lock(&qp->lock);
  946. t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc,
  947. is_t5(qp->rhp->rdev.lldi.adapter_type), NULL);
  948. qp->wq.sq.wq_pidx_inc = 0;
  949. t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc,
  950. is_t5(qp->rhp->rdev.lldi.adapter_type), NULL);
  951. qp->wq.rq.wq_pidx_inc = 0;
  952. spin_unlock(&qp->lock);
  953. }
  954. static void resume_a_chunk(struct uld_ctx *ctx)
  955. {
  956. int i;
  957. struct c4iw_qp *qp;
  958. for (i = 0; i < DB_FC_RESUME_SIZE; i++) {
  959. qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp,
  960. db_fc_entry);
  961. list_del_init(&qp->db_fc_entry);
  962. resume_rc_qp(qp);
  963. if (list_empty(&ctx->dev->db_fc_list))
  964. break;
  965. }
  966. }
  967. static void resume_queues(struct uld_ctx *ctx)
  968. {
  969. spin_lock_irq(&ctx->dev->lock);
  970. if (ctx->dev->db_state != STOPPED)
  971. goto out;
  972. ctx->dev->db_state = FLOW_CONTROL;
  973. while (1) {
  974. if (list_empty(&ctx->dev->db_fc_list)) {
  975. WARN_ON(ctx->dev->db_state != FLOW_CONTROL);
  976. ctx->dev->db_state = NORMAL;
  977. ctx->dev->rdev.stats.db_state_transitions++;
  978. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) {
  979. idr_for_each(&ctx->dev->qpidr, enable_qp_db,
  980. NULL);
  981. } else {
  982. ctx->dev->rdev.status_page->db_off = 0;
  983. }
  984. break;
  985. } else {
  986. if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1)
  987. < (ctx->dev->rdev.lldi.dbfifo_int_thresh <<
  988. DB_FC_DRAIN_THRESH)) {
  989. resume_a_chunk(ctx);
  990. }
  991. if (!list_empty(&ctx->dev->db_fc_list)) {
  992. spin_unlock_irq(&ctx->dev->lock);
  993. if (DB_FC_RESUME_DELAY) {
  994. set_current_state(TASK_UNINTERRUPTIBLE);
  995. schedule_timeout(DB_FC_RESUME_DELAY);
  996. }
  997. spin_lock_irq(&ctx->dev->lock);
  998. if (ctx->dev->db_state != FLOW_CONTROL)
  999. break;
  1000. }
  1001. }
  1002. }
  1003. out:
  1004. if (ctx->dev->db_state != NORMAL)
  1005. ctx->dev->rdev.stats.db_fc_interruptions++;
  1006. spin_unlock_irq(&ctx->dev->lock);
  1007. }
  1008. struct qp_list {
  1009. unsigned idx;
  1010. struct c4iw_qp **qps;
  1011. };
  1012. static int add_and_ref_qp(int id, void *p, void *data)
  1013. {
  1014. struct qp_list *qp_listp = data;
  1015. struct c4iw_qp *qp = p;
  1016. c4iw_qp_add_ref(&qp->ibqp);
  1017. qp_listp->qps[qp_listp->idx++] = qp;
  1018. return 0;
  1019. }
  1020. static int count_qps(int id, void *p, void *data)
  1021. {
  1022. unsigned *countp = data;
  1023. (*countp)++;
  1024. return 0;
  1025. }
  1026. static void deref_qps(struct qp_list *qp_list)
  1027. {
  1028. int idx;
  1029. for (idx = 0; idx < qp_list->idx; idx++)
  1030. c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp);
  1031. }
  1032. static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list)
  1033. {
  1034. int idx;
  1035. int ret;
  1036. for (idx = 0; idx < qp_list->idx; idx++) {
  1037. struct c4iw_qp *qp = qp_list->qps[idx];
  1038. spin_lock_irq(&qp->rhp->lock);
  1039. spin_lock(&qp->lock);
  1040. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1041. qp->wq.sq.qid,
  1042. t4_sq_host_wq_pidx(&qp->wq),
  1043. t4_sq_wq_size(&qp->wq));
  1044. if (ret) {
  1045. pr_err(KERN_ERR MOD "%s: Fatal error - "
  1046. "DB overflow recovery failed - "
  1047. "error syncing SQ qid %u\n",
  1048. pci_name(ctx->lldi.pdev), qp->wq.sq.qid);
  1049. spin_unlock(&qp->lock);
  1050. spin_unlock_irq(&qp->rhp->lock);
  1051. return;
  1052. }
  1053. qp->wq.sq.wq_pidx_inc = 0;
  1054. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1055. qp->wq.rq.qid,
  1056. t4_rq_host_wq_pidx(&qp->wq),
  1057. t4_rq_wq_size(&qp->wq));
  1058. if (ret) {
  1059. pr_err(KERN_ERR MOD "%s: Fatal error - "
  1060. "DB overflow recovery failed - "
  1061. "error syncing RQ qid %u\n",
  1062. pci_name(ctx->lldi.pdev), qp->wq.rq.qid);
  1063. spin_unlock(&qp->lock);
  1064. spin_unlock_irq(&qp->rhp->lock);
  1065. return;
  1066. }
  1067. qp->wq.rq.wq_pidx_inc = 0;
  1068. spin_unlock(&qp->lock);
  1069. spin_unlock_irq(&qp->rhp->lock);
  1070. /* Wait for the dbfifo to drain */
  1071. while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) {
  1072. set_current_state(TASK_UNINTERRUPTIBLE);
  1073. schedule_timeout(usecs_to_jiffies(10));
  1074. }
  1075. }
  1076. }
  1077. static void recover_queues(struct uld_ctx *ctx)
  1078. {
  1079. int count = 0;
  1080. struct qp_list qp_list;
  1081. int ret;
  1082. /* slow everybody down */
  1083. set_current_state(TASK_UNINTERRUPTIBLE);
  1084. schedule_timeout(usecs_to_jiffies(1000));
  1085. /* flush the SGE contexts */
  1086. ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]);
  1087. if (ret) {
  1088. printk(KERN_ERR MOD "%s: Fatal error - DB overflow recovery failed\n",
  1089. pci_name(ctx->lldi.pdev));
  1090. return;
  1091. }
  1092. /* Count active queues so we can build a list of queues to recover */
  1093. spin_lock_irq(&ctx->dev->lock);
  1094. WARN_ON(ctx->dev->db_state != STOPPED);
  1095. ctx->dev->db_state = RECOVERY;
  1096. idr_for_each(&ctx->dev->qpidr, count_qps, &count);
  1097. qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC);
  1098. if (!qp_list.qps) {
  1099. printk(KERN_ERR MOD "%s: Fatal error - DB overflow recovery failed\n",
  1100. pci_name(ctx->lldi.pdev));
  1101. spin_unlock_irq(&ctx->dev->lock);
  1102. return;
  1103. }
  1104. qp_list.idx = 0;
  1105. /* add and ref each qp so it doesn't get freed */
  1106. idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list);
  1107. spin_unlock_irq(&ctx->dev->lock);
  1108. /* now traverse the list in a safe context to recover the db state*/
  1109. recover_lost_dbs(ctx, &qp_list);
  1110. /* we're almost done! deref the qps and clean up */
  1111. deref_qps(&qp_list);
  1112. kfree(qp_list.qps);
  1113. spin_lock_irq(&ctx->dev->lock);
  1114. WARN_ON(ctx->dev->db_state != RECOVERY);
  1115. ctx->dev->db_state = STOPPED;
  1116. spin_unlock_irq(&ctx->dev->lock);
  1117. }
  1118. static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
  1119. {
  1120. struct uld_ctx *ctx = handle;
  1121. switch (control) {
  1122. case CXGB4_CONTROL_DB_FULL:
  1123. stop_queues(ctx);
  1124. ctx->dev->rdev.stats.db_full++;
  1125. break;
  1126. case CXGB4_CONTROL_DB_EMPTY:
  1127. resume_queues(ctx);
  1128. mutex_lock(&ctx->dev->rdev.stats.lock);
  1129. ctx->dev->rdev.stats.db_empty++;
  1130. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1131. break;
  1132. case CXGB4_CONTROL_DB_DROP:
  1133. recover_queues(ctx);
  1134. mutex_lock(&ctx->dev->rdev.stats.lock);
  1135. ctx->dev->rdev.stats.db_drop++;
  1136. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1137. break;
  1138. default:
  1139. printk(KERN_WARNING MOD "%s: unknown control cmd %u\n",
  1140. pci_name(ctx->lldi.pdev), control);
  1141. break;
  1142. }
  1143. return 0;
  1144. }
  1145. static struct cxgb4_uld_info c4iw_uld_info = {
  1146. .name = DRV_NAME,
  1147. .add = c4iw_uld_add,
  1148. .rx_handler = c4iw_uld_rx_handler,
  1149. .state_change = c4iw_uld_state_change,
  1150. .control = c4iw_uld_control,
  1151. };
  1152. static int __init c4iw_init_module(void)
  1153. {
  1154. int err;
  1155. err = c4iw_cm_init();
  1156. if (err)
  1157. return err;
  1158. c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
  1159. if (!c4iw_debugfs_root)
  1160. printk(KERN_WARNING MOD
  1161. "could not create debugfs entry, continuing\n");
  1162. if (ibnl_add_client(RDMA_NL_C4IW, RDMA_NL_IWPM_NUM_OPS,
  1163. c4iw_nl_cb_table))
  1164. pr_err("%s[%u]: Failed to add netlink callback\n"
  1165. , __func__, __LINE__);
  1166. err = iwpm_init(RDMA_NL_C4IW);
  1167. if (err) {
  1168. pr_err("port mapper initialization failed with %d\n", err);
  1169. ibnl_remove_client(RDMA_NL_C4IW);
  1170. c4iw_cm_term();
  1171. debugfs_remove_recursive(c4iw_debugfs_root);
  1172. return err;
  1173. }
  1174. cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
  1175. return 0;
  1176. }
  1177. static void __exit c4iw_exit_module(void)
  1178. {
  1179. struct uld_ctx *ctx, *tmp;
  1180. mutex_lock(&dev_mutex);
  1181. list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
  1182. if (ctx->dev)
  1183. c4iw_remove(ctx);
  1184. kfree(ctx);
  1185. }
  1186. mutex_unlock(&dev_mutex);
  1187. cxgb4_unregister_uld(CXGB4_ULD_RDMA);
  1188. iwpm_exit(RDMA_NL_C4IW);
  1189. ibnl_remove_client(RDMA_NL_C4IW);
  1190. c4iw_cm_term();
  1191. debugfs_remove_recursive(c4iw_debugfs_root);
  1192. }
  1193. module_init(c4iw_init_module);
  1194. module_exit(c4iw_exit_module);