i2c-sis96x.c 8.5 KB

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  1. /*
  2. Copyright (c) 2003 Mark M. Hoffman <mhoffman@lightlink.com>
  3. This program is free software; you can redistribute it and/or modify
  4. it under the terms of the GNU General Public License as published by
  5. the Free Software Foundation; either version 2 of the License, or
  6. (at your option) any later version.
  7. This program is distributed in the hope that it will be useful,
  8. but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. GNU General Public License for more details.
  11. You should have received a copy of the GNU General Public License
  12. along with this program; if not, write to the Free Software
  13. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  14. */
  15. /*
  16. This module must be considered BETA unless and until
  17. the chipset manufacturer releases a datasheet.
  18. The register definitions are based on the SiS630.
  19. This module relies on quirk_sis_96x_smbus (drivers/pci/quirks.c)
  20. for just about every machine for which users have reported.
  21. If this module isn't detecting your 96x south bridge, have a
  22. look there.
  23. We assume there can only be one SiS96x with one SMBus interface.
  24. */
  25. #include <linux/module.h>
  26. #include <linux/pci.h>
  27. #include <linux/kernel.h>
  28. #include <linux/delay.h>
  29. #include <linux/stddef.h>
  30. #include <linux/ioport.h>
  31. #include <linux/i2c.h>
  32. #include <linux/acpi.h>
  33. #include <linux/io.h>
  34. /* base address register in PCI config space */
  35. #define SIS96x_BAR 0x04
  36. /* SiS96x SMBus registers */
  37. #define SMB_STS 0x00
  38. #define SMB_EN 0x01
  39. #define SMB_CNT 0x02
  40. #define SMB_HOST_CNT 0x03
  41. #define SMB_ADDR 0x04
  42. #define SMB_CMD 0x05
  43. #define SMB_PCOUNT 0x06
  44. #define SMB_COUNT 0x07
  45. #define SMB_BYTE 0x08
  46. #define SMB_DEV_ADDR 0x10
  47. #define SMB_DB0 0x11
  48. #define SMB_DB1 0x12
  49. #define SMB_SAA 0x13
  50. /* register count for request_region */
  51. #define SMB_IOSIZE 0x20
  52. /* Other settings */
  53. #define MAX_TIMEOUT 500
  54. /* SiS96x SMBus constants */
  55. #define SIS96x_QUICK 0x00
  56. #define SIS96x_BYTE 0x01
  57. #define SIS96x_BYTE_DATA 0x02
  58. #define SIS96x_WORD_DATA 0x03
  59. #define SIS96x_PROC_CALL 0x04
  60. #define SIS96x_BLOCK_DATA 0x05
  61. static struct pci_driver sis96x_driver;
  62. static struct i2c_adapter sis96x_adapter;
  63. static u16 sis96x_smbus_base;
  64. static inline u8 sis96x_read(u8 reg)
  65. {
  66. return inb(sis96x_smbus_base + reg) ;
  67. }
  68. static inline void sis96x_write(u8 reg, u8 data)
  69. {
  70. outb(data, sis96x_smbus_base + reg) ;
  71. }
  72. /* Execute a SMBus transaction.
  73. int size is from SIS96x_QUICK to SIS96x_BLOCK_DATA
  74. */
  75. static int sis96x_transaction(int size)
  76. {
  77. int temp;
  78. int result = 0;
  79. int timeout = 0;
  80. dev_dbg(&sis96x_adapter.dev, "SMBus transaction %d\n", size);
  81. /* Make sure the SMBus host is ready to start transmitting */
  82. if (((temp = sis96x_read(SMB_CNT)) & 0x03) != 0x00) {
  83. dev_dbg(&sis96x_adapter.dev, "SMBus busy (0x%02x). "
  84. "Resetting...\n", temp);
  85. /* kill the transaction */
  86. sis96x_write(SMB_HOST_CNT, 0x20);
  87. /* check it again */
  88. if (((temp = sis96x_read(SMB_CNT)) & 0x03) != 0x00) {
  89. dev_dbg(&sis96x_adapter.dev, "Failed (0x%02x)\n", temp);
  90. return -EBUSY;
  91. } else {
  92. dev_dbg(&sis96x_adapter.dev, "Successful\n");
  93. }
  94. }
  95. /* Turn off timeout interrupts, set fast host clock */
  96. sis96x_write(SMB_CNT, 0x20);
  97. /* clear all (sticky) status flags */
  98. temp = sis96x_read(SMB_STS);
  99. sis96x_write(SMB_STS, temp & 0x1e);
  100. /* start the transaction by setting bit 4 and size bits */
  101. sis96x_write(SMB_HOST_CNT, 0x10 | (size & 0x07));
  102. /* We will always wait for a fraction of a second! */
  103. do {
  104. msleep(1);
  105. temp = sis96x_read(SMB_STS);
  106. } while (!(temp & 0x0e) && (timeout++ < MAX_TIMEOUT));
  107. /* If the SMBus is still busy, we give up */
  108. if (timeout > MAX_TIMEOUT) {
  109. dev_dbg(&sis96x_adapter.dev, "SMBus Timeout! (0x%02x)\n", temp);
  110. result = -ETIMEDOUT;
  111. }
  112. /* device error - probably missing ACK */
  113. if (temp & 0x02) {
  114. dev_dbg(&sis96x_adapter.dev, "Failed bus transaction!\n");
  115. result = -ENXIO;
  116. }
  117. /* bus collision */
  118. if (temp & 0x04) {
  119. dev_dbg(&sis96x_adapter.dev, "Bus collision!\n");
  120. result = -EIO;
  121. }
  122. /* Finish up by resetting the bus */
  123. sis96x_write(SMB_STS, temp);
  124. if ((temp = sis96x_read(SMB_STS))) {
  125. dev_dbg(&sis96x_adapter.dev, "Failed reset at "
  126. "end of transaction! (0x%02x)\n", temp);
  127. }
  128. return result;
  129. }
  130. /* Return negative errno on error. */
  131. static s32 sis96x_access(struct i2c_adapter * adap, u16 addr,
  132. unsigned short flags, char read_write,
  133. u8 command, int size, union i2c_smbus_data * data)
  134. {
  135. int status;
  136. switch (size) {
  137. case I2C_SMBUS_QUICK:
  138. sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
  139. size = SIS96x_QUICK;
  140. break;
  141. case I2C_SMBUS_BYTE:
  142. sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
  143. if (read_write == I2C_SMBUS_WRITE)
  144. sis96x_write(SMB_CMD, command);
  145. size = SIS96x_BYTE;
  146. break;
  147. case I2C_SMBUS_BYTE_DATA:
  148. sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
  149. sis96x_write(SMB_CMD, command);
  150. if (read_write == I2C_SMBUS_WRITE)
  151. sis96x_write(SMB_BYTE, data->byte);
  152. size = SIS96x_BYTE_DATA;
  153. break;
  154. case I2C_SMBUS_PROC_CALL:
  155. case I2C_SMBUS_WORD_DATA:
  156. sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
  157. sis96x_write(SMB_CMD, command);
  158. if (read_write == I2C_SMBUS_WRITE) {
  159. sis96x_write(SMB_BYTE, data->word & 0xff);
  160. sis96x_write(SMB_BYTE + 1, (data->word & 0xff00) >> 8);
  161. }
  162. size = (size == I2C_SMBUS_PROC_CALL ?
  163. SIS96x_PROC_CALL : SIS96x_WORD_DATA);
  164. break;
  165. default:
  166. dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
  167. return -EOPNOTSUPP;
  168. }
  169. status = sis96x_transaction(size);
  170. if (status)
  171. return status;
  172. if ((size != SIS96x_PROC_CALL) &&
  173. ((read_write == I2C_SMBUS_WRITE) || (size == SIS96x_QUICK)))
  174. return 0;
  175. switch (size) {
  176. case SIS96x_BYTE:
  177. case SIS96x_BYTE_DATA:
  178. data->byte = sis96x_read(SMB_BYTE);
  179. break;
  180. case SIS96x_WORD_DATA:
  181. case SIS96x_PROC_CALL:
  182. data->word = sis96x_read(SMB_BYTE) +
  183. (sis96x_read(SMB_BYTE + 1) << 8);
  184. break;
  185. }
  186. return 0;
  187. }
  188. static u32 sis96x_func(struct i2c_adapter *adapter)
  189. {
  190. return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
  191. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
  192. I2C_FUNC_SMBUS_PROC_CALL;
  193. }
  194. static const struct i2c_algorithm smbus_algorithm = {
  195. .smbus_xfer = sis96x_access,
  196. .functionality = sis96x_func,
  197. };
  198. static struct i2c_adapter sis96x_adapter = {
  199. .owner = THIS_MODULE,
  200. .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
  201. .algo = &smbus_algorithm,
  202. };
  203. static const struct pci_device_id sis96x_ids[] = {
  204. { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_SMBUS) },
  205. { 0, }
  206. };
  207. MODULE_DEVICE_TABLE (pci, sis96x_ids);
  208. static int sis96x_probe(struct pci_dev *dev,
  209. const struct pci_device_id *id)
  210. {
  211. u16 ww = 0;
  212. int retval;
  213. if (sis96x_smbus_base) {
  214. dev_err(&dev->dev, "Only one device supported.\n");
  215. return -EBUSY;
  216. }
  217. pci_read_config_word(dev, PCI_CLASS_DEVICE, &ww);
  218. if (PCI_CLASS_SERIAL_SMBUS != ww) {
  219. dev_err(&dev->dev, "Unsupported device class 0x%04x!\n", ww);
  220. return -ENODEV;
  221. }
  222. sis96x_smbus_base = pci_resource_start(dev, SIS96x_BAR);
  223. if (!sis96x_smbus_base) {
  224. dev_err(&dev->dev, "SiS96x SMBus base address "
  225. "not initialized!\n");
  226. return -EINVAL;
  227. }
  228. dev_info(&dev->dev, "SiS96x SMBus base address: 0x%04x\n",
  229. sis96x_smbus_base);
  230. retval = acpi_check_resource_conflict(&dev->resource[SIS96x_BAR]);
  231. if (retval)
  232. return -ENODEV;
  233. /* Everything is happy, let's grab the memory and set things up. */
  234. if (!request_region(sis96x_smbus_base, SMB_IOSIZE,
  235. sis96x_driver.name)) {
  236. dev_err(&dev->dev, "SMBus registers 0x%04x-0x%04x "
  237. "already in use!\n", sis96x_smbus_base,
  238. sis96x_smbus_base + SMB_IOSIZE - 1);
  239. sis96x_smbus_base = 0;
  240. return -EINVAL;
  241. }
  242. /* set up the sysfs linkage to our parent device */
  243. sis96x_adapter.dev.parent = &dev->dev;
  244. snprintf(sis96x_adapter.name, sizeof(sis96x_adapter.name),
  245. "SiS96x SMBus adapter at 0x%04x", sis96x_smbus_base);
  246. if ((retval = i2c_add_adapter(&sis96x_adapter))) {
  247. dev_err(&dev->dev, "Couldn't register adapter!\n");
  248. release_region(sis96x_smbus_base, SMB_IOSIZE);
  249. sis96x_smbus_base = 0;
  250. }
  251. return retval;
  252. }
  253. static void sis96x_remove(struct pci_dev *dev)
  254. {
  255. if (sis96x_smbus_base) {
  256. i2c_del_adapter(&sis96x_adapter);
  257. release_region(sis96x_smbus_base, SMB_IOSIZE);
  258. sis96x_smbus_base = 0;
  259. }
  260. }
  261. static struct pci_driver sis96x_driver = {
  262. .name = "sis96x_smbus",
  263. .id_table = sis96x_ids,
  264. .probe = sis96x_probe,
  265. .remove = sis96x_remove,
  266. };
  267. module_pci_driver(sis96x_driver);
  268. MODULE_AUTHOR("Mark M. Hoffman <mhoffman@lightlink.com>");
  269. MODULE_DESCRIPTION("SiS96x SMBus driver");
  270. MODULE_LICENSE("GPL");