vmwgfx_kms.c 55 KB

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  1. /**************************************************************************
  2. *
  3. * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include "vmwgfx_kms.h"
  28. /* Might need a hrtimer here? */
  29. #define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
  30. struct vmw_clip_rect {
  31. int x1, x2, y1, y2;
  32. };
  33. /**
  34. * Clip @num_rects number of @rects against @clip storing the
  35. * results in @out_rects and the number of passed rects in @out_num.
  36. */
  37. static void vmw_clip_cliprects(struct drm_clip_rect *rects,
  38. int num_rects,
  39. struct vmw_clip_rect clip,
  40. SVGASignedRect *out_rects,
  41. int *out_num)
  42. {
  43. int i, k;
  44. for (i = 0, k = 0; i < num_rects; i++) {
  45. int x1 = max_t(int, clip.x1, rects[i].x1);
  46. int y1 = max_t(int, clip.y1, rects[i].y1);
  47. int x2 = min_t(int, clip.x2, rects[i].x2);
  48. int y2 = min_t(int, clip.y2, rects[i].y2);
  49. if (x1 >= x2)
  50. continue;
  51. if (y1 >= y2)
  52. continue;
  53. out_rects[k].left = x1;
  54. out_rects[k].top = y1;
  55. out_rects[k].right = x2;
  56. out_rects[k].bottom = y2;
  57. k++;
  58. }
  59. *out_num = k;
  60. }
  61. void vmw_display_unit_cleanup(struct vmw_display_unit *du)
  62. {
  63. if (du->cursor_surface)
  64. vmw_surface_unreference(&du->cursor_surface);
  65. if (du->cursor_dmabuf)
  66. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  67. drm_sysfs_connector_remove(&du->connector);
  68. drm_crtc_cleanup(&du->crtc);
  69. drm_encoder_cleanup(&du->encoder);
  70. drm_connector_cleanup(&du->connector);
  71. }
  72. /*
  73. * Display Unit Cursor functions
  74. */
  75. int vmw_cursor_update_image(struct vmw_private *dev_priv,
  76. u32 *image, u32 width, u32 height,
  77. u32 hotspotX, u32 hotspotY)
  78. {
  79. struct {
  80. u32 cmd;
  81. SVGAFifoCmdDefineAlphaCursor cursor;
  82. } *cmd;
  83. u32 image_size = width * height * 4;
  84. u32 cmd_size = sizeof(*cmd) + image_size;
  85. if (!image)
  86. return -EINVAL;
  87. cmd = vmw_fifo_reserve(dev_priv, cmd_size);
  88. if (unlikely(cmd == NULL)) {
  89. DRM_ERROR("Fifo reserve failed.\n");
  90. return -ENOMEM;
  91. }
  92. memset(cmd, 0, sizeof(*cmd));
  93. memcpy(&cmd[1], image, image_size);
  94. cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
  95. cmd->cursor.id = cpu_to_le32(0);
  96. cmd->cursor.width = cpu_to_le32(width);
  97. cmd->cursor.height = cpu_to_le32(height);
  98. cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
  99. cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
  100. vmw_fifo_commit(dev_priv, cmd_size);
  101. return 0;
  102. }
  103. int vmw_cursor_update_dmabuf(struct vmw_private *dev_priv,
  104. struct vmw_dma_buffer *dmabuf,
  105. u32 width, u32 height,
  106. u32 hotspotX, u32 hotspotY)
  107. {
  108. struct ttm_bo_kmap_obj map;
  109. unsigned long kmap_offset;
  110. unsigned long kmap_num;
  111. void *virtual;
  112. bool dummy;
  113. int ret;
  114. kmap_offset = 0;
  115. kmap_num = (width*height*4 + PAGE_SIZE - 1) >> PAGE_SHIFT;
  116. ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
  117. if (unlikely(ret != 0)) {
  118. DRM_ERROR("reserve failed\n");
  119. return -EINVAL;
  120. }
  121. ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
  122. if (unlikely(ret != 0))
  123. goto err_unreserve;
  124. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  125. ret = vmw_cursor_update_image(dev_priv, virtual, width, height,
  126. hotspotX, hotspotY);
  127. ttm_bo_kunmap(&map);
  128. err_unreserve:
  129. ttm_bo_unreserve(&dmabuf->base);
  130. return ret;
  131. }
  132. void vmw_cursor_update_position(struct vmw_private *dev_priv,
  133. bool show, int x, int y)
  134. {
  135. __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  136. uint32_t count;
  137. iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
  138. iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
  139. iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
  140. count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  141. iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  142. }
  143. int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
  144. uint32_t handle, uint32_t width, uint32_t height)
  145. {
  146. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  147. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  148. struct vmw_surface *surface = NULL;
  149. struct vmw_dma_buffer *dmabuf = NULL;
  150. int ret;
  151. /*
  152. * FIXME: Unclear whether there's any global state touched by the
  153. * cursor_set function, especially vmw_cursor_update_position looks
  154. * suspicious. For now take the easy route and reacquire all locks. We
  155. * can do this since the caller in the drm core doesn't check anything
  156. * which is protected by any looks.
  157. */
  158. drm_modeset_unlock(&crtc->mutex);
  159. drm_modeset_lock_all(dev_priv->dev);
  160. /* A lot of the code assumes this */
  161. if (handle && (width != 64 || height != 64)) {
  162. ret = -EINVAL;
  163. goto out;
  164. }
  165. if (handle) {
  166. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  167. ret = vmw_user_lookup_handle(dev_priv, tfile,
  168. handle, &surface, &dmabuf);
  169. if (ret) {
  170. DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
  171. ret = -EINVAL;
  172. goto out;
  173. }
  174. }
  175. /* need to do this before taking down old image */
  176. if (surface && !surface->snooper.image) {
  177. DRM_ERROR("surface not suitable for cursor\n");
  178. vmw_surface_unreference(&surface);
  179. ret = -EINVAL;
  180. goto out;
  181. }
  182. /* takedown old cursor */
  183. if (du->cursor_surface) {
  184. du->cursor_surface->snooper.crtc = NULL;
  185. vmw_surface_unreference(&du->cursor_surface);
  186. }
  187. if (du->cursor_dmabuf)
  188. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  189. /* setup new image */
  190. if (surface) {
  191. /* vmw_user_surface_lookup takes one reference */
  192. du->cursor_surface = surface;
  193. du->cursor_surface->snooper.crtc = crtc;
  194. du->cursor_age = du->cursor_surface->snooper.age;
  195. vmw_cursor_update_image(dev_priv, surface->snooper.image,
  196. 64, 64, du->hotspot_x, du->hotspot_y);
  197. } else if (dmabuf) {
  198. /* vmw_user_surface_lookup takes one reference */
  199. du->cursor_dmabuf = dmabuf;
  200. ret = vmw_cursor_update_dmabuf(dev_priv, dmabuf, width, height,
  201. du->hotspot_x, du->hotspot_y);
  202. } else {
  203. vmw_cursor_update_position(dev_priv, false, 0, 0);
  204. ret = 0;
  205. goto out;
  206. }
  207. vmw_cursor_update_position(dev_priv, true,
  208. du->cursor_x + du->hotspot_x,
  209. du->cursor_y + du->hotspot_y);
  210. ret = 0;
  211. out:
  212. drm_modeset_unlock_all(dev_priv->dev);
  213. drm_modeset_lock(&crtc->mutex, NULL);
  214. return ret;
  215. }
  216. int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  217. {
  218. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  219. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  220. bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
  221. du->cursor_x = x + crtc->x;
  222. du->cursor_y = y + crtc->y;
  223. /*
  224. * FIXME: Unclear whether there's any global state touched by the
  225. * cursor_set function, especially vmw_cursor_update_position looks
  226. * suspicious. For now take the easy route and reacquire all locks. We
  227. * can do this since the caller in the drm core doesn't check anything
  228. * which is protected by any looks.
  229. */
  230. drm_modeset_unlock(&crtc->mutex);
  231. drm_modeset_lock_all(dev_priv->dev);
  232. vmw_cursor_update_position(dev_priv, shown,
  233. du->cursor_x + du->hotspot_x,
  234. du->cursor_y + du->hotspot_y);
  235. drm_modeset_unlock_all(dev_priv->dev);
  236. drm_modeset_lock(&crtc->mutex, NULL);
  237. return 0;
  238. }
  239. void vmw_kms_cursor_snoop(struct vmw_surface *srf,
  240. struct ttm_object_file *tfile,
  241. struct ttm_buffer_object *bo,
  242. SVGA3dCmdHeader *header)
  243. {
  244. struct ttm_bo_kmap_obj map;
  245. unsigned long kmap_offset;
  246. unsigned long kmap_num;
  247. SVGA3dCopyBox *box;
  248. unsigned box_count;
  249. void *virtual;
  250. bool dummy;
  251. struct vmw_dma_cmd {
  252. SVGA3dCmdHeader header;
  253. SVGA3dCmdSurfaceDMA dma;
  254. } *cmd;
  255. int i, ret;
  256. cmd = container_of(header, struct vmw_dma_cmd, header);
  257. /* No snooper installed */
  258. if (!srf->snooper.image)
  259. return;
  260. if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
  261. DRM_ERROR("face and mipmap for cursors should never != 0\n");
  262. return;
  263. }
  264. if (cmd->header.size < 64) {
  265. DRM_ERROR("at least one full copy box must be given\n");
  266. return;
  267. }
  268. box = (SVGA3dCopyBox *)&cmd[1];
  269. box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
  270. sizeof(SVGA3dCopyBox);
  271. if (cmd->dma.guest.ptr.offset % PAGE_SIZE ||
  272. box->x != 0 || box->y != 0 || box->z != 0 ||
  273. box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
  274. box->d != 1 || box_count != 1) {
  275. /* TODO handle none page aligned offsets */
  276. /* TODO handle more dst & src != 0 */
  277. /* TODO handle more then one copy */
  278. DRM_ERROR("Cant snoop dma request for cursor!\n");
  279. DRM_ERROR("(%u, %u, %u) (%u, %u, %u) (%ux%ux%u) %u %u\n",
  280. box->srcx, box->srcy, box->srcz,
  281. box->x, box->y, box->z,
  282. box->w, box->h, box->d, box_count,
  283. cmd->dma.guest.ptr.offset);
  284. return;
  285. }
  286. kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
  287. kmap_num = (64*64*4) >> PAGE_SHIFT;
  288. ret = ttm_bo_reserve(bo, true, false, false, 0);
  289. if (unlikely(ret != 0)) {
  290. DRM_ERROR("reserve failed\n");
  291. return;
  292. }
  293. ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
  294. if (unlikely(ret != 0))
  295. goto err_unreserve;
  296. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  297. if (box->w == 64 && cmd->dma.guest.pitch == 64*4) {
  298. memcpy(srf->snooper.image, virtual, 64*64*4);
  299. } else {
  300. /* Image is unsigned pointer. */
  301. for (i = 0; i < box->h; i++)
  302. memcpy(srf->snooper.image + i * 64,
  303. virtual + i * cmd->dma.guest.pitch,
  304. box->w * 4);
  305. }
  306. srf->snooper.age++;
  307. /* we can't call this function from this function since execbuf has
  308. * reserved fifo space.
  309. *
  310. * if (srf->snooper.crtc)
  311. * vmw_ldu_crtc_cursor_update_image(dev_priv,
  312. * srf->snooper.image, 64, 64,
  313. * du->hotspot_x, du->hotspot_y);
  314. */
  315. ttm_bo_kunmap(&map);
  316. err_unreserve:
  317. ttm_bo_unreserve(bo);
  318. }
  319. void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
  320. {
  321. struct drm_device *dev = dev_priv->dev;
  322. struct vmw_display_unit *du;
  323. struct drm_crtc *crtc;
  324. mutex_lock(&dev->mode_config.mutex);
  325. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  326. du = vmw_crtc_to_du(crtc);
  327. if (!du->cursor_surface ||
  328. du->cursor_age == du->cursor_surface->snooper.age)
  329. continue;
  330. du->cursor_age = du->cursor_surface->snooper.age;
  331. vmw_cursor_update_image(dev_priv,
  332. du->cursor_surface->snooper.image,
  333. 64, 64, du->hotspot_x, du->hotspot_y);
  334. }
  335. mutex_unlock(&dev->mode_config.mutex);
  336. }
  337. /*
  338. * Generic framebuffer code
  339. */
  340. /*
  341. * Surface framebuffer code
  342. */
  343. #define vmw_framebuffer_to_vfbs(x) \
  344. container_of(x, struct vmw_framebuffer_surface, base.base)
  345. struct vmw_framebuffer_surface {
  346. struct vmw_framebuffer base;
  347. struct vmw_surface *surface;
  348. struct vmw_dma_buffer *buffer;
  349. struct list_head head;
  350. struct drm_master *master;
  351. };
  352. static void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
  353. {
  354. struct vmw_framebuffer_surface *vfbs =
  355. vmw_framebuffer_to_vfbs(framebuffer);
  356. struct vmw_master *vmaster = vmw_master(vfbs->master);
  357. mutex_lock(&vmaster->fb_surf_mutex);
  358. list_del(&vfbs->head);
  359. mutex_unlock(&vmaster->fb_surf_mutex);
  360. drm_master_put(&vfbs->master);
  361. drm_framebuffer_cleanup(framebuffer);
  362. vmw_surface_unreference(&vfbs->surface);
  363. ttm_base_object_unref(&vfbs->base.user_obj);
  364. kfree(vfbs);
  365. }
  366. static int do_surface_dirty_sou(struct vmw_private *dev_priv,
  367. struct drm_file *file_priv,
  368. struct vmw_framebuffer *framebuffer,
  369. unsigned flags, unsigned color,
  370. struct drm_clip_rect *clips,
  371. unsigned num_clips, int inc,
  372. struct vmw_fence_obj **out_fence)
  373. {
  374. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  375. struct drm_clip_rect *clips_ptr;
  376. struct drm_clip_rect *tmp;
  377. struct drm_crtc *crtc;
  378. size_t fifo_size;
  379. int i, num_units;
  380. int ret = 0; /* silence warning */
  381. int left, right, top, bottom;
  382. struct {
  383. SVGA3dCmdHeader header;
  384. SVGA3dCmdBlitSurfaceToScreen body;
  385. } *cmd;
  386. SVGASignedRect *blits;
  387. num_units = 0;
  388. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
  389. head) {
  390. if (crtc->primary->fb != &framebuffer->base)
  391. continue;
  392. units[num_units++] = vmw_crtc_to_du(crtc);
  393. }
  394. BUG_ON(!clips || !num_clips);
  395. tmp = kzalloc(sizeof(*tmp) * num_clips, GFP_KERNEL);
  396. if (unlikely(tmp == NULL)) {
  397. DRM_ERROR("Temporary cliprect memory alloc failed.\n");
  398. return -ENOMEM;
  399. }
  400. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  401. cmd = kzalloc(fifo_size, GFP_KERNEL);
  402. if (unlikely(cmd == NULL)) {
  403. DRM_ERROR("Temporary fifo memory alloc failed.\n");
  404. ret = -ENOMEM;
  405. goto out_free_tmp;
  406. }
  407. /* setup blits pointer */
  408. blits = (SVGASignedRect *)&cmd[1];
  409. /* initial clip region */
  410. left = clips->x1;
  411. right = clips->x2;
  412. top = clips->y1;
  413. bottom = clips->y2;
  414. /* skip the first clip rect */
  415. for (i = 1, clips_ptr = clips + inc;
  416. i < num_clips; i++, clips_ptr += inc) {
  417. left = min_t(int, left, (int)clips_ptr->x1);
  418. right = max_t(int, right, (int)clips_ptr->x2);
  419. top = min_t(int, top, (int)clips_ptr->y1);
  420. bottom = max_t(int, bottom, (int)clips_ptr->y2);
  421. }
  422. /* only need to do this once */
  423. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  424. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  425. cmd->body.srcRect.left = left;
  426. cmd->body.srcRect.right = right;
  427. cmd->body.srcRect.top = top;
  428. cmd->body.srcRect.bottom = bottom;
  429. clips_ptr = clips;
  430. for (i = 0; i < num_clips; i++, clips_ptr += inc) {
  431. tmp[i].x1 = clips_ptr->x1 - left;
  432. tmp[i].x2 = clips_ptr->x2 - left;
  433. tmp[i].y1 = clips_ptr->y1 - top;
  434. tmp[i].y2 = clips_ptr->y2 - top;
  435. }
  436. /* do per unit writing, reuse fifo for each */
  437. for (i = 0; i < num_units; i++) {
  438. struct vmw_display_unit *unit = units[i];
  439. struct vmw_clip_rect clip;
  440. int num;
  441. clip.x1 = left - unit->crtc.x;
  442. clip.y1 = top - unit->crtc.y;
  443. clip.x2 = right - unit->crtc.x;
  444. clip.y2 = bottom - unit->crtc.y;
  445. /* skip any crtcs that misses the clip region */
  446. if (clip.x1 >= unit->crtc.mode.hdisplay ||
  447. clip.y1 >= unit->crtc.mode.vdisplay ||
  448. clip.x2 <= 0 || clip.y2 <= 0)
  449. continue;
  450. /*
  451. * In order for the clip rects to be correctly scaled
  452. * the src and dest rects needs to be the same size.
  453. */
  454. cmd->body.destRect.left = clip.x1;
  455. cmd->body.destRect.right = clip.x2;
  456. cmd->body.destRect.top = clip.y1;
  457. cmd->body.destRect.bottom = clip.y2;
  458. /* create a clip rect of the crtc in dest coords */
  459. clip.x2 = unit->crtc.mode.hdisplay - clip.x1;
  460. clip.y2 = unit->crtc.mode.vdisplay - clip.y1;
  461. clip.x1 = 0 - clip.x1;
  462. clip.y1 = 0 - clip.y1;
  463. /* need to reset sid as it is changed by execbuf */
  464. cmd->body.srcImage.sid = cpu_to_le32(framebuffer->user_handle);
  465. cmd->body.destScreenId = unit->unit;
  466. /* clip and write blits to cmd stream */
  467. vmw_clip_cliprects(tmp, num_clips, clip, blits, &num);
  468. /* if no cliprects hit skip this */
  469. if (num == 0)
  470. continue;
  471. /* only return the last fence */
  472. if (out_fence && *out_fence)
  473. vmw_fence_obj_unreference(out_fence);
  474. /* recalculate package length */
  475. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num;
  476. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  477. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  478. fifo_size, 0, NULL, out_fence);
  479. if (unlikely(ret != 0))
  480. break;
  481. }
  482. kfree(cmd);
  483. out_free_tmp:
  484. kfree(tmp);
  485. return ret;
  486. }
  487. static int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
  488. struct drm_file *file_priv,
  489. unsigned flags, unsigned color,
  490. struct drm_clip_rect *clips,
  491. unsigned num_clips)
  492. {
  493. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  494. struct vmw_framebuffer_surface *vfbs =
  495. vmw_framebuffer_to_vfbs(framebuffer);
  496. struct drm_clip_rect norect;
  497. int ret, inc = 1;
  498. if (unlikely(vfbs->master != file_priv->master))
  499. return -EINVAL;
  500. /* Require ScreenObject support for 3D */
  501. if (!dev_priv->sou_priv)
  502. return -EINVAL;
  503. drm_modeset_lock_all(dev_priv->dev);
  504. ret = ttm_read_lock(&dev_priv->reservation_sem, true);
  505. if (unlikely(ret != 0)) {
  506. drm_modeset_unlock_all(dev_priv->dev);
  507. return ret;
  508. }
  509. if (!num_clips) {
  510. num_clips = 1;
  511. clips = &norect;
  512. norect.x1 = norect.y1 = 0;
  513. norect.x2 = framebuffer->width;
  514. norect.y2 = framebuffer->height;
  515. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  516. num_clips /= 2;
  517. inc = 2; /* skip source rects */
  518. }
  519. ret = do_surface_dirty_sou(dev_priv, file_priv, &vfbs->base,
  520. flags, color,
  521. clips, num_clips, inc, NULL);
  522. ttm_read_unlock(&dev_priv->reservation_sem);
  523. drm_modeset_unlock_all(dev_priv->dev);
  524. return 0;
  525. }
  526. static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
  527. .destroy = vmw_framebuffer_surface_destroy,
  528. .dirty = vmw_framebuffer_surface_dirty,
  529. };
  530. static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
  531. struct drm_file *file_priv,
  532. struct vmw_surface *surface,
  533. struct vmw_framebuffer **out,
  534. const struct drm_mode_fb_cmd
  535. *mode_cmd)
  536. {
  537. struct drm_device *dev = dev_priv->dev;
  538. struct vmw_framebuffer_surface *vfbs;
  539. enum SVGA3dSurfaceFormat format;
  540. struct vmw_master *vmaster = vmw_master(file_priv->master);
  541. int ret;
  542. /* 3D is only supported on HWv8 hosts which supports screen objects */
  543. if (!dev_priv->sou_priv)
  544. return -ENOSYS;
  545. /*
  546. * Sanity checks.
  547. */
  548. /* Surface must be marked as a scanout. */
  549. if (unlikely(!surface->scanout))
  550. return -EINVAL;
  551. if (unlikely(surface->mip_levels[0] != 1 ||
  552. surface->num_sizes != 1 ||
  553. surface->base_size.width < mode_cmd->width ||
  554. surface->base_size.height < mode_cmd->height ||
  555. surface->base_size.depth != 1)) {
  556. DRM_ERROR("Incompatible surface dimensions "
  557. "for requested mode.\n");
  558. return -EINVAL;
  559. }
  560. switch (mode_cmd->depth) {
  561. case 32:
  562. format = SVGA3D_A8R8G8B8;
  563. break;
  564. case 24:
  565. format = SVGA3D_X8R8G8B8;
  566. break;
  567. case 16:
  568. format = SVGA3D_R5G6B5;
  569. break;
  570. case 15:
  571. format = SVGA3D_A1R5G5B5;
  572. break;
  573. case 8:
  574. format = SVGA3D_LUMINANCE8;
  575. break;
  576. default:
  577. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  578. return -EINVAL;
  579. }
  580. if (unlikely(format != surface->format)) {
  581. DRM_ERROR("Invalid surface format for requested mode.\n");
  582. return -EINVAL;
  583. }
  584. vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
  585. if (!vfbs) {
  586. ret = -ENOMEM;
  587. goto out_err1;
  588. }
  589. if (!vmw_surface_reference(surface)) {
  590. DRM_ERROR("failed to reference surface %p\n", surface);
  591. ret = -EINVAL;
  592. goto out_err2;
  593. }
  594. /* XXX get the first 3 from the surface info */
  595. vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
  596. vfbs->base.base.pitches[0] = mode_cmd->pitch;
  597. vfbs->base.base.depth = mode_cmd->depth;
  598. vfbs->base.base.width = mode_cmd->width;
  599. vfbs->base.base.height = mode_cmd->height;
  600. vfbs->surface = surface;
  601. vfbs->base.user_handle = mode_cmd->handle;
  602. vfbs->master = drm_master_get(file_priv->master);
  603. mutex_lock(&vmaster->fb_surf_mutex);
  604. list_add_tail(&vfbs->head, &vmaster->fb_surf);
  605. mutex_unlock(&vmaster->fb_surf_mutex);
  606. *out = &vfbs->base;
  607. ret = drm_framebuffer_init(dev, &vfbs->base.base,
  608. &vmw_framebuffer_surface_funcs);
  609. if (ret)
  610. goto out_err3;
  611. return 0;
  612. out_err3:
  613. vmw_surface_unreference(&surface);
  614. out_err2:
  615. kfree(vfbs);
  616. out_err1:
  617. return ret;
  618. }
  619. /*
  620. * Dmabuf framebuffer code
  621. */
  622. #define vmw_framebuffer_to_vfbd(x) \
  623. container_of(x, struct vmw_framebuffer_dmabuf, base.base)
  624. struct vmw_framebuffer_dmabuf {
  625. struct vmw_framebuffer base;
  626. struct vmw_dma_buffer *buffer;
  627. };
  628. static void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
  629. {
  630. struct vmw_framebuffer_dmabuf *vfbd =
  631. vmw_framebuffer_to_vfbd(framebuffer);
  632. drm_framebuffer_cleanup(framebuffer);
  633. vmw_dmabuf_unreference(&vfbd->buffer);
  634. ttm_base_object_unref(&vfbd->base.user_obj);
  635. kfree(vfbd);
  636. }
  637. static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
  638. struct vmw_framebuffer *framebuffer,
  639. unsigned flags, unsigned color,
  640. struct drm_clip_rect *clips,
  641. unsigned num_clips, int increment)
  642. {
  643. size_t fifo_size;
  644. int i;
  645. struct {
  646. uint32_t header;
  647. SVGAFifoCmdUpdate body;
  648. } *cmd;
  649. fifo_size = sizeof(*cmd) * num_clips;
  650. cmd = vmw_fifo_reserve(dev_priv, fifo_size);
  651. if (unlikely(cmd == NULL)) {
  652. DRM_ERROR("Fifo reserve failed.\n");
  653. return -ENOMEM;
  654. }
  655. memset(cmd, 0, fifo_size);
  656. for (i = 0; i < num_clips; i++, clips += increment) {
  657. cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
  658. cmd[i].body.x = cpu_to_le32(clips->x1);
  659. cmd[i].body.y = cpu_to_le32(clips->y1);
  660. cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
  661. cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
  662. }
  663. vmw_fifo_commit(dev_priv, fifo_size);
  664. return 0;
  665. }
  666. static int do_dmabuf_define_gmrfb(struct drm_file *file_priv,
  667. struct vmw_private *dev_priv,
  668. struct vmw_framebuffer *framebuffer)
  669. {
  670. int depth = framebuffer->base.depth;
  671. size_t fifo_size;
  672. int ret;
  673. struct {
  674. uint32_t header;
  675. SVGAFifoCmdDefineGMRFB body;
  676. } *cmd;
  677. /* Emulate RGBA support, contrary to svga_reg.h this is not
  678. * supported by hosts. This is only a problem if we are reading
  679. * this value later and expecting what we uploaded back.
  680. */
  681. if (depth == 32)
  682. depth = 24;
  683. fifo_size = sizeof(*cmd);
  684. cmd = kmalloc(fifo_size, GFP_KERNEL);
  685. if (unlikely(cmd == NULL)) {
  686. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  687. return -ENOMEM;
  688. }
  689. memset(cmd, 0, fifo_size);
  690. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  691. cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
  692. cmd->body.format.colorDepth = depth;
  693. cmd->body.format.reserved = 0;
  694. cmd->body.bytesPerLine = framebuffer->base.pitches[0];
  695. cmd->body.ptr.gmrId = framebuffer->user_handle;
  696. cmd->body.ptr.offset = 0;
  697. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  698. fifo_size, 0, NULL, NULL);
  699. kfree(cmd);
  700. return ret;
  701. }
  702. static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
  703. struct vmw_private *dev_priv,
  704. struct vmw_framebuffer *framebuffer,
  705. unsigned flags, unsigned color,
  706. struct drm_clip_rect *clips,
  707. unsigned num_clips, int increment,
  708. struct vmw_fence_obj **out_fence)
  709. {
  710. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  711. struct drm_clip_rect *clips_ptr;
  712. int i, k, num_units, ret;
  713. struct drm_crtc *crtc;
  714. size_t fifo_size;
  715. struct {
  716. uint32_t header;
  717. SVGAFifoCmdBlitGMRFBToScreen body;
  718. } *blits;
  719. ret = do_dmabuf_define_gmrfb(file_priv, dev_priv, framebuffer);
  720. if (unlikely(ret != 0))
  721. return ret; /* define_gmrfb prints warnings */
  722. fifo_size = sizeof(*blits) * num_clips;
  723. blits = kmalloc(fifo_size, GFP_KERNEL);
  724. if (unlikely(blits == NULL)) {
  725. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  726. return -ENOMEM;
  727. }
  728. num_units = 0;
  729. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  730. if (crtc->primary->fb != &framebuffer->base)
  731. continue;
  732. units[num_units++] = vmw_crtc_to_du(crtc);
  733. }
  734. for (k = 0; k < num_units; k++) {
  735. struct vmw_display_unit *unit = units[k];
  736. int hit_num = 0;
  737. clips_ptr = clips;
  738. for (i = 0; i < num_clips; i++, clips_ptr += increment) {
  739. int clip_x1 = clips_ptr->x1 - unit->crtc.x;
  740. int clip_y1 = clips_ptr->y1 - unit->crtc.y;
  741. int clip_x2 = clips_ptr->x2 - unit->crtc.x;
  742. int clip_y2 = clips_ptr->y2 - unit->crtc.y;
  743. int move_x, move_y;
  744. /* skip any crtcs that misses the clip region */
  745. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  746. clip_y1 >= unit->crtc.mode.vdisplay ||
  747. clip_x2 <= 0 || clip_y2 <= 0)
  748. continue;
  749. /* clip size to crtc size */
  750. clip_x2 = min_t(int, clip_x2, unit->crtc.mode.hdisplay);
  751. clip_y2 = min_t(int, clip_y2, unit->crtc.mode.vdisplay);
  752. /* translate both src and dest to bring clip into screen */
  753. move_x = min_t(int, clip_x1, 0);
  754. move_y = min_t(int, clip_y1, 0);
  755. /* actual translate done here */
  756. blits[hit_num].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
  757. blits[hit_num].body.destScreenId = unit->unit;
  758. blits[hit_num].body.srcOrigin.x = clips_ptr->x1 - move_x;
  759. blits[hit_num].body.srcOrigin.y = clips_ptr->y1 - move_y;
  760. blits[hit_num].body.destRect.left = clip_x1 - move_x;
  761. blits[hit_num].body.destRect.top = clip_y1 - move_y;
  762. blits[hit_num].body.destRect.right = clip_x2;
  763. blits[hit_num].body.destRect.bottom = clip_y2;
  764. hit_num++;
  765. }
  766. /* no clips hit the crtc */
  767. if (hit_num == 0)
  768. continue;
  769. /* only return the last fence */
  770. if (out_fence && *out_fence)
  771. vmw_fence_obj_unreference(out_fence);
  772. fifo_size = sizeof(*blits) * hit_num;
  773. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, blits,
  774. fifo_size, 0, NULL, out_fence);
  775. if (unlikely(ret != 0))
  776. break;
  777. }
  778. kfree(blits);
  779. return ret;
  780. }
  781. static int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
  782. struct drm_file *file_priv,
  783. unsigned flags, unsigned color,
  784. struct drm_clip_rect *clips,
  785. unsigned num_clips)
  786. {
  787. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  788. struct vmw_framebuffer_dmabuf *vfbd =
  789. vmw_framebuffer_to_vfbd(framebuffer);
  790. struct drm_clip_rect norect;
  791. int ret, increment = 1;
  792. drm_modeset_lock_all(dev_priv->dev);
  793. ret = ttm_read_lock(&dev_priv->reservation_sem, true);
  794. if (unlikely(ret != 0)) {
  795. drm_modeset_unlock_all(dev_priv->dev);
  796. return ret;
  797. }
  798. if (!num_clips) {
  799. num_clips = 1;
  800. clips = &norect;
  801. norect.x1 = norect.y1 = 0;
  802. norect.x2 = framebuffer->width;
  803. norect.y2 = framebuffer->height;
  804. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  805. num_clips /= 2;
  806. increment = 2;
  807. }
  808. if (dev_priv->ldu_priv) {
  809. ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base,
  810. flags, color,
  811. clips, num_clips, increment);
  812. } else {
  813. ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
  814. flags, color,
  815. clips, num_clips, increment, NULL);
  816. }
  817. ttm_read_unlock(&dev_priv->reservation_sem);
  818. drm_modeset_unlock_all(dev_priv->dev);
  819. return ret;
  820. }
  821. static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
  822. .destroy = vmw_framebuffer_dmabuf_destroy,
  823. .dirty = vmw_framebuffer_dmabuf_dirty,
  824. };
  825. /**
  826. * Pin the dmabuffer to the start of vram.
  827. */
  828. static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
  829. {
  830. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  831. struct vmw_framebuffer_dmabuf *vfbd =
  832. vmw_framebuffer_to_vfbd(&vfb->base);
  833. int ret;
  834. /* This code should not be used with screen objects */
  835. BUG_ON(dev_priv->sou_priv);
  836. vmw_overlay_pause_all(dev_priv);
  837. ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
  838. vmw_overlay_resume_all(dev_priv);
  839. WARN_ON(ret != 0);
  840. return 0;
  841. }
  842. static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
  843. {
  844. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  845. struct vmw_framebuffer_dmabuf *vfbd =
  846. vmw_framebuffer_to_vfbd(&vfb->base);
  847. if (!vfbd->buffer) {
  848. WARN_ON(!vfbd->buffer);
  849. return 0;
  850. }
  851. return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
  852. }
  853. static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
  854. struct vmw_dma_buffer *dmabuf,
  855. struct vmw_framebuffer **out,
  856. const struct drm_mode_fb_cmd
  857. *mode_cmd)
  858. {
  859. struct drm_device *dev = dev_priv->dev;
  860. struct vmw_framebuffer_dmabuf *vfbd;
  861. unsigned int requested_size;
  862. int ret;
  863. requested_size = mode_cmd->height * mode_cmd->pitch;
  864. if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
  865. DRM_ERROR("Screen buffer object size is too small "
  866. "for requested mode.\n");
  867. return -EINVAL;
  868. }
  869. /* Limited framebuffer color depth support for screen objects */
  870. if (dev_priv->sou_priv) {
  871. switch (mode_cmd->depth) {
  872. case 32:
  873. case 24:
  874. /* Only support 32 bpp for 32 and 24 depth fbs */
  875. if (mode_cmd->bpp == 32)
  876. break;
  877. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  878. mode_cmd->depth, mode_cmd->bpp);
  879. return -EINVAL;
  880. case 16:
  881. case 15:
  882. /* Only support 16 bpp for 16 and 15 depth fbs */
  883. if (mode_cmd->bpp == 16)
  884. break;
  885. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  886. mode_cmd->depth, mode_cmd->bpp);
  887. return -EINVAL;
  888. default:
  889. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  890. return -EINVAL;
  891. }
  892. }
  893. vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
  894. if (!vfbd) {
  895. ret = -ENOMEM;
  896. goto out_err1;
  897. }
  898. if (!vmw_dmabuf_reference(dmabuf)) {
  899. DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
  900. ret = -EINVAL;
  901. goto out_err2;
  902. }
  903. vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
  904. vfbd->base.base.pitches[0] = mode_cmd->pitch;
  905. vfbd->base.base.depth = mode_cmd->depth;
  906. vfbd->base.base.width = mode_cmd->width;
  907. vfbd->base.base.height = mode_cmd->height;
  908. if (!dev_priv->sou_priv) {
  909. vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
  910. vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
  911. }
  912. vfbd->base.dmabuf = true;
  913. vfbd->buffer = dmabuf;
  914. vfbd->base.user_handle = mode_cmd->handle;
  915. *out = &vfbd->base;
  916. ret = drm_framebuffer_init(dev, &vfbd->base.base,
  917. &vmw_framebuffer_dmabuf_funcs);
  918. if (ret)
  919. goto out_err3;
  920. return 0;
  921. out_err3:
  922. vmw_dmabuf_unreference(&dmabuf);
  923. out_err2:
  924. kfree(vfbd);
  925. out_err1:
  926. return ret;
  927. }
  928. /*
  929. * Generic Kernel modesetting functions
  930. */
  931. static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
  932. struct drm_file *file_priv,
  933. struct drm_mode_fb_cmd2 *mode_cmd2)
  934. {
  935. struct vmw_private *dev_priv = vmw_priv(dev);
  936. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  937. struct vmw_framebuffer *vfb = NULL;
  938. struct vmw_surface *surface = NULL;
  939. struct vmw_dma_buffer *bo = NULL;
  940. struct ttm_base_object *user_obj;
  941. struct drm_mode_fb_cmd mode_cmd;
  942. int ret;
  943. mode_cmd.width = mode_cmd2->width;
  944. mode_cmd.height = mode_cmd2->height;
  945. mode_cmd.pitch = mode_cmd2->pitches[0];
  946. mode_cmd.handle = mode_cmd2->handles[0];
  947. drm_fb_get_bpp_depth(mode_cmd2->pixel_format, &mode_cmd.depth,
  948. &mode_cmd.bpp);
  949. /**
  950. * This code should be conditioned on Screen Objects not being used.
  951. * If screen objects are used, we can allocate a GMR to hold the
  952. * requested framebuffer.
  953. */
  954. if (!vmw_kms_validate_mode_vram(dev_priv,
  955. mode_cmd.pitch,
  956. mode_cmd.height)) {
  957. DRM_ERROR("VRAM size is too small for requested mode.\n");
  958. return ERR_PTR(-ENOMEM);
  959. }
  960. /*
  961. * Take a reference on the user object of the resource
  962. * backing the kms fb. This ensures that user-space handle
  963. * lookups on that resource will always work as long as
  964. * it's registered with a kms framebuffer. This is important,
  965. * since vmw_execbuf_process identifies resources in the
  966. * command stream using user-space handles.
  967. */
  968. user_obj = ttm_base_object_lookup(tfile, mode_cmd.handle);
  969. if (unlikely(user_obj == NULL)) {
  970. DRM_ERROR("Could not locate requested kms frame buffer.\n");
  971. return ERR_PTR(-ENOENT);
  972. }
  973. /**
  974. * End conditioned code.
  975. */
  976. /* returns either a dmabuf or surface */
  977. ret = vmw_user_lookup_handle(dev_priv, tfile,
  978. mode_cmd.handle,
  979. &surface, &bo);
  980. if (ret)
  981. goto err_out;
  982. /* Create the new framebuffer depending one what we got back */
  983. if (bo)
  984. ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
  985. &mode_cmd);
  986. else if (surface)
  987. ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv,
  988. surface, &vfb, &mode_cmd);
  989. else
  990. BUG();
  991. err_out:
  992. /* vmw_user_lookup_handle takes one ref so does new_fb */
  993. if (bo)
  994. vmw_dmabuf_unreference(&bo);
  995. if (surface)
  996. vmw_surface_unreference(&surface);
  997. if (ret) {
  998. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  999. ttm_base_object_unref(&user_obj);
  1000. return ERR_PTR(ret);
  1001. } else
  1002. vfb->user_obj = user_obj;
  1003. return &vfb->base;
  1004. }
  1005. static const struct drm_mode_config_funcs vmw_kms_funcs = {
  1006. .fb_create = vmw_kms_fb_create,
  1007. };
  1008. int vmw_kms_present(struct vmw_private *dev_priv,
  1009. struct drm_file *file_priv,
  1010. struct vmw_framebuffer *vfb,
  1011. struct vmw_surface *surface,
  1012. uint32_t sid,
  1013. int32_t destX, int32_t destY,
  1014. struct drm_vmw_rect *clips,
  1015. uint32_t num_clips)
  1016. {
  1017. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  1018. struct drm_clip_rect *tmp;
  1019. struct drm_crtc *crtc;
  1020. size_t fifo_size;
  1021. int i, k, num_units;
  1022. int ret = 0; /* silence warning */
  1023. int left, right, top, bottom;
  1024. struct {
  1025. SVGA3dCmdHeader header;
  1026. SVGA3dCmdBlitSurfaceToScreen body;
  1027. } *cmd;
  1028. SVGASignedRect *blits;
  1029. num_units = 0;
  1030. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  1031. if (crtc->primary->fb != &vfb->base)
  1032. continue;
  1033. units[num_units++] = vmw_crtc_to_du(crtc);
  1034. }
  1035. BUG_ON(surface == NULL);
  1036. BUG_ON(!clips || !num_clips);
  1037. tmp = kzalloc(sizeof(*tmp) * num_clips, GFP_KERNEL);
  1038. if (unlikely(tmp == NULL)) {
  1039. DRM_ERROR("Temporary cliprect memory alloc failed.\n");
  1040. return -ENOMEM;
  1041. }
  1042. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  1043. cmd = kmalloc(fifo_size, GFP_KERNEL);
  1044. if (unlikely(cmd == NULL)) {
  1045. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  1046. ret = -ENOMEM;
  1047. goto out_free_tmp;
  1048. }
  1049. left = clips->x;
  1050. right = clips->x + clips->w;
  1051. top = clips->y;
  1052. bottom = clips->y + clips->h;
  1053. for (i = 1; i < num_clips; i++) {
  1054. left = min_t(int, left, (int)clips[i].x);
  1055. right = max_t(int, right, (int)clips[i].x + clips[i].w);
  1056. top = min_t(int, top, (int)clips[i].y);
  1057. bottom = max_t(int, bottom, (int)clips[i].y + clips[i].h);
  1058. }
  1059. /* only need to do this once */
  1060. memset(cmd, 0, fifo_size);
  1061. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  1062. blits = (SVGASignedRect *)&cmd[1];
  1063. cmd->body.srcRect.left = left;
  1064. cmd->body.srcRect.right = right;
  1065. cmd->body.srcRect.top = top;
  1066. cmd->body.srcRect.bottom = bottom;
  1067. for (i = 0; i < num_clips; i++) {
  1068. tmp[i].x1 = clips[i].x - left;
  1069. tmp[i].x2 = clips[i].x + clips[i].w - left;
  1070. tmp[i].y1 = clips[i].y - top;
  1071. tmp[i].y2 = clips[i].y + clips[i].h - top;
  1072. }
  1073. for (k = 0; k < num_units; k++) {
  1074. struct vmw_display_unit *unit = units[k];
  1075. struct vmw_clip_rect clip;
  1076. int num;
  1077. clip.x1 = left + destX - unit->crtc.x;
  1078. clip.y1 = top + destY - unit->crtc.y;
  1079. clip.x2 = right + destX - unit->crtc.x;
  1080. clip.y2 = bottom + destY - unit->crtc.y;
  1081. /* skip any crtcs that misses the clip region */
  1082. if (clip.x1 >= unit->crtc.mode.hdisplay ||
  1083. clip.y1 >= unit->crtc.mode.vdisplay ||
  1084. clip.x2 <= 0 || clip.y2 <= 0)
  1085. continue;
  1086. /*
  1087. * In order for the clip rects to be correctly scaled
  1088. * the src and dest rects needs to be the same size.
  1089. */
  1090. cmd->body.destRect.left = clip.x1;
  1091. cmd->body.destRect.right = clip.x2;
  1092. cmd->body.destRect.top = clip.y1;
  1093. cmd->body.destRect.bottom = clip.y2;
  1094. /* create a clip rect of the crtc in dest coords */
  1095. clip.x2 = unit->crtc.mode.hdisplay - clip.x1;
  1096. clip.y2 = unit->crtc.mode.vdisplay - clip.y1;
  1097. clip.x1 = 0 - clip.x1;
  1098. clip.y1 = 0 - clip.y1;
  1099. /* need to reset sid as it is changed by execbuf */
  1100. cmd->body.srcImage.sid = sid;
  1101. cmd->body.destScreenId = unit->unit;
  1102. /* clip and write blits to cmd stream */
  1103. vmw_clip_cliprects(tmp, num_clips, clip, blits, &num);
  1104. /* if no cliprects hit skip this */
  1105. if (num == 0)
  1106. continue;
  1107. /* recalculate package length */
  1108. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num;
  1109. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  1110. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  1111. fifo_size, 0, NULL, NULL);
  1112. if (unlikely(ret != 0))
  1113. break;
  1114. }
  1115. kfree(cmd);
  1116. out_free_tmp:
  1117. kfree(tmp);
  1118. return ret;
  1119. }
  1120. int vmw_kms_readback(struct vmw_private *dev_priv,
  1121. struct drm_file *file_priv,
  1122. struct vmw_framebuffer *vfb,
  1123. struct drm_vmw_fence_rep __user *user_fence_rep,
  1124. struct drm_vmw_rect *clips,
  1125. uint32_t num_clips)
  1126. {
  1127. struct vmw_framebuffer_dmabuf *vfbd =
  1128. vmw_framebuffer_to_vfbd(&vfb->base);
  1129. struct vmw_dma_buffer *dmabuf = vfbd->buffer;
  1130. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  1131. struct drm_crtc *crtc;
  1132. size_t fifo_size;
  1133. int i, k, ret, num_units, blits_pos;
  1134. struct {
  1135. uint32_t header;
  1136. SVGAFifoCmdDefineGMRFB body;
  1137. } *cmd;
  1138. struct {
  1139. uint32_t header;
  1140. SVGAFifoCmdBlitScreenToGMRFB body;
  1141. } *blits;
  1142. num_units = 0;
  1143. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  1144. if (crtc->primary->fb != &vfb->base)
  1145. continue;
  1146. units[num_units++] = vmw_crtc_to_du(crtc);
  1147. }
  1148. BUG_ON(dmabuf == NULL);
  1149. BUG_ON(!clips || !num_clips);
  1150. /* take a safe guess at fifo size */
  1151. fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips * num_units;
  1152. cmd = kmalloc(fifo_size, GFP_KERNEL);
  1153. if (unlikely(cmd == NULL)) {
  1154. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  1155. return -ENOMEM;
  1156. }
  1157. memset(cmd, 0, fifo_size);
  1158. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  1159. cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
  1160. cmd->body.format.colorDepth = vfb->base.depth;
  1161. cmd->body.format.reserved = 0;
  1162. cmd->body.bytesPerLine = vfb->base.pitches[0];
  1163. cmd->body.ptr.gmrId = vfb->user_handle;
  1164. cmd->body.ptr.offset = 0;
  1165. blits = (void *)&cmd[1];
  1166. blits_pos = 0;
  1167. for (i = 0; i < num_units; i++) {
  1168. struct drm_vmw_rect *c = clips;
  1169. for (k = 0; k < num_clips; k++, c++) {
  1170. /* transform clip coords to crtc origin based coords */
  1171. int clip_x1 = c->x - units[i]->crtc.x;
  1172. int clip_x2 = c->x - units[i]->crtc.x + c->w;
  1173. int clip_y1 = c->y - units[i]->crtc.y;
  1174. int clip_y2 = c->y - units[i]->crtc.y + c->h;
  1175. int dest_x = c->x;
  1176. int dest_y = c->y;
  1177. /* compensate for clipping, we negate
  1178. * a negative number and add that.
  1179. */
  1180. if (clip_x1 < 0)
  1181. dest_x += -clip_x1;
  1182. if (clip_y1 < 0)
  1183. dest_y += -clip_y1;
  1184. /* clip */
  1185. clip_x1 = max(clip_x1, 0);
  1186. clip_y1 = max(clip_y1, 0);
  1187. clip_x2 = min(clip_x2, units[i]->crtc.mode.hdisplay);
  1188. clip_y2 = min(clip_y2, units[i]->crtc.mode.vdisplay);
  1189. /* and cull any rects that misses the crtc */
  1190. if (clip_x1 >= units[i]->crtc.mode.hdisplay ||
  1191. clip_y1 >= units[i]->crtc.mode.vdisplay ||
  1192. clip_x2 <= 0 || clip_y2 <= 0)
  1193. continue;
  1194. blits[blits_pos].header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
  1195. blits[blits_pos].body.srcScreenId = units[i]->unit;
  1196. blits[blits_pos].body.destOrigin.x = dest_x;
  1197. blits[blits_pos].body.destOrigin.y = dest_y;
  1198. blits[blits_pos].body.srcRect.left = clip_x1;
  1199. blits[blits_pos].body.srcRect.top = clip_y1;
  1200. blits[blits_pos].body.srcRect.right = clip_x2;
  1201. blits[blits_pos].body.srcRect.bottom = clip_y2;
  1202. blits_pos++;
  1203. }
  1204. }
  1205. /* reset size here and use calculated exact size from loops */
  1206. fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos;
  1207. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
  1208. 0, user_fence_rep, NULL);
  1209. kfree(cmd);
  1210. return ret;
  1211. }
  1212. int vmw_kms_init(struct vmw_private *dev_priv)
  1213. {
  1214. struct drm_device *dev = dev_priv->dev;
  1215. int ret;
  1216. drm_mode_config_init(dev);
  1217. dev->mode_config.funcs = &vmw_kms_funcs;
  1218. dev->mode_config.min_width = 1;
  1219. dev->mode_config.min_height = 1;
  1220. /* assumed largest fb size */
  1221. dev->mode_config.max_width = 8192;
  1222. dev->mode_config.max_height = 8192;
  1223. ret = vmw_kms_init_screen_object_display(dev_priv);
  1224. if (ret) /* Fallback */
  1225. (void)vmw_kms_init_legacy_display_system(dev_priv);
  1226. return 0;
  1227. }
  1228. int vmw_kms_close(struct vmw_private *dev_priv)
  1229. {
  1230. /*
  1231. * Docs says we should take the lock before calling this function
  1232. * but since it destroys encoders and our destructor calls
  1233. * drm_encoder_cleanup which takes the lock we deadlock.
  1234. */
  1235. drm_mode_config_cleanup(dev_priv->dev);
  1236. if (dev_priv->sou_priv)
  1237. vmw_kms_close_screen_object_display(dev_priv);
  1238. else
  1239. vmw_kms_close_legacy_display_system(dev_priv);
  1240. return 0;
  1241. }
  1242. int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
  1243. struct drm_file *file_priv)
  1244. {
  1245. struct drm_vmw_cursor_bypass_arg *arg = data;
  1246. struct vmw_display_unit *du;
  1247. struct drm_mode_object *obj;
  1248. struct drm_crtc *crtc;
  1249. int ret = 0;
  1250. mutex_lock(&dev->mode_config.mutex);
  1251. if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
  1252. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1253. du = vmw_crtc_to_du(crtc);
  1254. du->hotspot_x = arg->xhot;
  1255. du->hotspot_y = arg->yhot;
  1256. }
  1257. mutex_unlock(&dev->mode_config.mutex);
  1258. return 0;
  1259. }
  1260. obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
  1261. if (!obj) {
  1262. ret = -ENOENT;
  1263. goto out;
  1264. }
  1265. crtc = obj_to_crtc(obj);
  1266. du = vmw_crtc_to_du(crtc);
  1267. du->hotspot_x = arg->xhot;
  1268. du->hotspot_y = arg->yhot;
  1269. out:
  1270. mutex_unlock(&dev->mode_config.mutex);
  1271. return ret;
  1272. }
  1273. int vmw_kms_write_svga(struct vmw_private *vmw_priv,
  1274. unsigned width, unsigned height, unsigned pitch,
  1275. unsigned bpp, unsigned depth)
  1276. {
  1277. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1278. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
  1279. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1280. iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1281. vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
  1282. vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
  1283. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
  1284. if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
  1285. DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
  1286. depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
  1287. return -EINVAL;
  1288. }
  1289. return 0;
  1290. }
  1291. int vmw_kms_save_vga(struct vmw_private *vmw_priv)
  1292. {
  1293. struct vmw_vga_topology_state *save;
  1294. uint32_t i;
  1295. vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
  1296. vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
  1297. vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
  1298. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1299. vmw_priv->vga_pitchlock =
  1300. vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
  1301. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1302. vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
  1303. SVGA_FIFO_PITCHLOCK);
  1304. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1305. return 0;
  1306. vmw_priv->num_displays = vmw_read(vmw_priv,
  1307. SVGA_REG_NUM_GUEST_DISPLAYS);
  1308. if (vmw_priv->num_displays == 0)
  1309. vmw_priv->num_displays = 1;
  1310. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1311. save = &vmw_priv->vga_save[i];
  1312. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1313. save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
  1314. save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
  1315. save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
  1316. save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
  1317. save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
  1318. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1319. if (i == 0 && vmw_priv->num_displays == 1 &&
  1320. save->width == 0 && save->height == 0) {
  1321. /*
  1322. * It should be fairly safe to assume that these
  1323. * values are uninitialized.
  1324. */
  1325. save->width = vmw_priv->vga_width - save->pos_x;
  1326. save->height = vmw_priv->vga_height - save->pos_y;
  1327. }
  1328. }
  1329. return 0;
  1330. }
  1331. int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
  1332. {
  1333. struct vmw_vga_topology_state *save;
  1334. uint32_t i;
  1335. vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
  1336. vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
  1337. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
  1338. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1339. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
  1340. vmw_priv->vga_pitchlock);
  1341. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1342. iowrite32(vmw_priv->vga_pitchlock,
  1343. vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1344. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1345. return 0;
  1346. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1347. save = &vmw_priv->vga_save[i];
  1348. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1349. vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
  1350. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
  1351. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
  1352. vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
  1353. vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
  1354. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1355. }
  1356. return 0;
  1357. }
  1358. bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
  1359. uint32_t pitch,
  1360. uint32_t height)
  1361. {
  1362. return ((u64) pitch * (u64) height) < (u64) dev_priv->prim_bb_mem;
  1363. }
  1364. /**
  1365. * Function called by DRM code called with vbl_lock held.
  1366. */
  1367. u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
  1368. {
  1369. return 0;
  1370. }
  1371. /**
  1372. * Function called by DRM code called with vbl_lock held.
  1373. */
  1374. int vmw_enable_vblank(struct drm_device *dev, int crtc)
  1375. {
  1376. return -ENOSYS;
  1377. }
  1378. /**
  1379. * Function called by DRM code called with vbl_lock held.
  1380. */
  1381. void vmw_disable_vblank(struct drm_device *dev, int crtc)
  1382. {
  1383. }
  1384. /*
  1385. * Small shared kms functions.
  1386. */
  1387. static int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
  1388. struct drm_vmw_rect *rects)
  1389. {
  1390. struct drm_device *dev = dev_priv->dev;
  1391. struct vmw_display_unit *du;
  1392. struct drm_connector *con;
  1393. mutex_lock(&dev->mode_config.mutex);
  1394. #if 0
  1395. {
  1396. unsigned int i;
  1397. DRM_INFO("%s: new layout ", __func__);
  1398. for (i = 0; i < num; i++)
  1399. DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
  1400. rects[i].w, rects[i].h);
  1401. DRM_INFO("\n");
  1402. }
  1403. #endif
  1404. list_for_each_entry(con, &dev->mode_config.connector_list, head) {
  1405. du = vmw_connector_to_du(con);
  1406. if (num > du->unit) {
  1407. du->pref_width = rects[du->unit].w;
  1408. du->pref_height = rects[du->unit].h;
  1409. du->pref_active = true;
  1410. du->gui_x = rects[du->unit].x;
  1411. du->gui_y = rects[du->unit].y;
  1412. } else {
  1413. du->pref_width = 800;
  1414. du->pref_height = 600;
  1415. du->pref_active = false;
  1416. }
  1417. con->status = vmw_du_connector_detect(con, true);
  1418. }
  1419. mutex_unlock(&dev->mode_config.mutex);
  1420. return 0;
  1421. }
  1422. int vmw_du_page_flip(struct drm_crtc *crtc,
  1423. struct drm_framebuffer *fb,
  1424. struct drm_pending_vblank_event *event,
  1425. uint32_t page_flip_flags)
  1426. {
  1427. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  1428. struct drm_framebuffer *old_fb = crtc->primary->fb;
  1429. struct vmw_framebuffer *vfb = vmw_framebuffer_to_vfb(fb);
  1430. struct drm_file *file_priv ;
  1431. struct vmw_fence_obj *fence = NULL;
  1432. struct drm_clip_rect clips;
  1433. int ret;
  1434. if (event == NULL)
  1435. return -EINVAL;
  1436. /* require ScreenObject support for page flipping */
  1437. if (!dev_priv->sou_priv)
  1438. return -ENOSYS;
  1439. file_priv = event->base.file_priv;
  1440. if (!vmw_kms_screen_object_flippable(dev_priv, crtc))
  1441. return -EINVAL;
  1442. crtc->primary->fb = fb;
  1443. /* do a full screen dirty update */
  1444. clips.x1 = clips.y1 = 0;
  1445. clips.x2 = fb->width;
  1446. clips.y2 = fb->height;
  1447. if (vfb->dmabuf)
  1448. ret = do_dmabuf_dirty_sou(file_priv, dev_priv, vfb,
  1449. 0, 0, &clips, 1, 1, &fence);
  1450. else
  1451. ret = do_surface_dirty_sou(dev_priv, file_priv, vfb,
  1452. 0, 0, &clips, 1, 1, &fence);
  1453. if (ret != 0)
  1454. goto out_no_fence;
  1455. if (!fence) {
  1456. ret = -EINVAL;
  1457. goto out_no_fence;
  1458. }
  1459. ret = vmw_event_fence_action_queue(file_priv, fence,
  1460. &event->base,
  1461. &event->event.tv_sec,
  1462. &event->event.tv_usec,
  1463. true);
  1464. /*
  1465. * No need to hold on to this now. The only cleanup
  1466. * we need to do if we fail is unref the fence.
  1467. */
  1468. vmw_fence_obj_unreference(&fence);
  1469. if (vmw_crtc_to_du(crtc)->is_implicit)
  1470. vmw_kms_screen_object_update_implicit_fb(dev_priv, crtc);
  1471. return ret;
  1472. out_no_fence:
  1473. crtc->primary->fb = old_fb;
  1474. return ret;
  1475. }
  1476. void vmw_du_crtc_save(struct drm_crtc *crtc)
  1477. {
  1478. }
  1479. void vmw_du_crtc_restore(struct drm_crtc *crtc)
  1480. {
  1481. }
  1482. void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
  1483. u16 *r, u16 *g, u16 *b,
  1484. uint32_t start, uint32_t size)
  1485. {
  1486. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  1487. int i;
  1488. for (i = 0; i < size; i++) {
  1489. DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
  1490. r[i], g[i], b[i]);
  1491. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
  1492. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
  1493. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
  1494. }
  1495. }
  1496. void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
  1497. {
  1498. }
  1499. void vmw_du_connector_save(struct drm_connector *connector)
  1500. {
  1501. }
  1502. void vmw_du_connector_restore(struct drm_connector *connector)
  1503. {
  1504. }
  1505. enum drm_connector_status
  1506. vmw_du_connector_detect(struct drm_connector *connector, bool force)
  1507. {
  1508. uint32_t num_displays;
  1509. struct drm_device *dev = connector->dev;
  1510. struct vmw_private *dev_priv = vmw_priv(dev);
  1511. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1512. mutex_lock(&dev_priv->hw_mutex);
  1513. num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
  1514. mutex_unlock(&dev_priv->hw_mutex);
  1515. return ((vmw_connector_to_du(connector)->unit < num_displays &&
  1516. du->pref_active) ?
  1517. connector_status_connected : connector_status_disconnected);
  1518. }
  1519. static struct drm_display_mode vmw_kms_connector_builtin[] = {
  1520. /* 640x480@60Hz */
  1521. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  1522. 752, 800, 0, 480, 489, 492, 525, 0,
  1523. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1524. /* 800x600@60Hz */
  1525. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
  1526. 968, 1056, 0, 600, 601, 605, 628, 0,
  1527. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1528. /* 1024x768@60Hz */
  1529. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
  1530. 1184, 1344, 0, 768, 771, 777, 806, 0,
  1531. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1532. /* 1152x864@75Hz */
  1533. { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
  1534. 1344, 1600, 0, 864, 865, 868, 900, 0,
  1535. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1536. /* 1280x768@60Hz */
  1537. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
  1538. 1472, 1664, 0, 768, 771, 778, 798, 0,
  1539. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1540. /* 1280x800@60Hz */
  1541. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
  1542. 1480, 1680, 0, 800, 803, 809, 831, 0,
  1543. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1544. /* 1280x960@60Hz */
  1545. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
  1546. 1488, 1800, 0, 960, 961, 964, 1000, 0,
  1547. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1548. /* 1280x1024@60Hz */
  1549. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
  1550. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  1551. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1552. /* 1360x768@60Hz */
  1553. { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
  1554. 1536, 1792, 0, 768, 771, 777, 795, 0,
  1555. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1556. /* 1440x1050@60Hz */
  1557. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
  1558. 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
  1559. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1560. /* 1440x900@60Hz */
  1561. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
  1562. 1672, 1904, 0, 900, 903, 909, 934, 0,
  1563. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1564. /* 1600x1200@60Hz */
  1565. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
  1566. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  1567. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1568. /* 1680x1050@60Hz */
  1569. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
  1570. 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
  1571. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1572. /* 1792x1344@60Hz */
  1573. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
  1574. 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
  1575. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1576. /* 1853x1392@60Hz */
  1577. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
  1578. 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
  1579. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1580. /* 1920x1200@60Hz */
  1581. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
  1582. 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
  1583. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1584. /* 1920x1440@60Hz */
  1585. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
  1586. 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
  1587. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1588. /* 2560x1600@60Hz */
  1589. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
  1590. 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
  1591. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1592. /* Terminate */
  1593. { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
  1594. };
  1595. /**
  1596. * vmw_guess_mode_timing - Provide fake timings for a
  1597. * 60Hz vrefresh mode.
  1598. *
  1599. * @mode - Pointer to a struct drm_display_mode with hdisplay and vdisplay
  1600. * members filled in.
  1601. */
  1602. static void vmw_guess_mode_timing(struct drm_display_mode *mode)
  1603. {
  1604. mode->hsync_start = mode->hdisplay + 50;
  1605. mode->hsync_end = mode->hsync_start + 50;
  1606. mode->htotal = mode->hsync_end + 50;
  1607. mode->vsync_start = mode->vdisplay + 50;
  1608. mode->vsync_end = mode->vsync_start + 50;
  1609. mode->vtotal = mode->vsync_end + 50;
  1610. mode->clock = (u32)mode->htotal * (u32)mode->vtotal / 100 * 6;
  1611. mode->vrefresh = drm_mode_vrefresh(mode);
  1612. }
  1613. int vmw_du_connector_fill_modes(struct drm_connector *connector,
  1614. uint32_t max_width, uint32_t max_height)
  1615. {
  1616. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1617. struct drm_device *dev = connector->dev;
  1618. struct vmw_private *dev_priv = vmw_priv(dev);
  1619. struct drm_display_mode *mode = NULL;
  1620. struct drm_display_mode *bmode;
  1621. struct drm_display_mode prefmode = { DRM_MODE("preferred",
  1622. DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
  1623. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  1624. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
  1625. };
  1626. int i;
  1627. /* Add preferred mode */
  1628. {
  1629. mode = drm_mode_duplicate(dev, &prefmode);
  1630. if (!mode)
  1631. return 0;
  1632. mode->hdisplay = du->pref_width;
  1633. mode->vdisplay = du->pref_height;
  1634. vmw_guess_mode_timing(mode);
  1635. if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
  1636. mode->vdisplay)) {
  1637. drm_mode_probed_add(connector, mode);
  1638. } else {
  1639. drm_mode_destroy(dev, mode);
  1640. mode = NULL;
  1641. }
  1642. if (du->pref_mode) {
  1643. list_del_init(&du->pref_mode->head);
  1644. drm_mode_destroy(dev, du->pref_mode);
  1645. }
  1646. /* mode might be null here, this is intended */
  1647. du->pref_mode = mode;
  1648. }
  1649. for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
  1650. bmode = &vmw_kms_connector_builtin[i];
  1651. if (bmode->hdisplay > max_width ||
  1652. bmode->vdisplay > max_height)
  1653. continue;
  1654. if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
  1655. bmode->vdisplay))
  1656. continue;
  1657. mode = drm_mode_duplicate(dev, bmode);
  1658. if (!mode)
  1659. return 0;
  1660. mode->vrefresh = drm_mode_vrefresh(mode);
  1661. drm_mode_probed_add(connector, mode);
  1662. }
  1663. /* Move the prefered mode first, help apps pick the right mode. */
  1664. if (du->pref_mode)
  1665. list_move(&du->pref_mode->head, &connector->probed_modes);
  1666. drm_mode_connector_list_update(connector, true);
  1667. return 1;
  1668. }
  1669. int vmw_du_connector_set_property(struct drm_connector *connector,
  1670. struct drm_property *property,
  1671. uint64_t val)
  1672. {
  1673. return 0;
  1674. }
  1675. int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
  1676. struct drm_file *file_priv)
  1677. {
  1678. struct vmw_private *dev_priv = vmw_priv(dev);
  1679. struct drm_vmw_update_layout_arg *arg =
  1680. (struct drm_vmw_update_layout_arg *)data;
  1681. void __user *user_rects;
  1682. struct drm_vmw_rect *rects;
  1683. unsigned rects_size;
  1684. int ret;
  1685. int i;
  1686. struct drm_mode_config *mode_config = &dev->mode_config;
  1687. ret = ttm_read_lock(&dev_priv->reservation_sem, true);
  1688. if (unlikely(ret != 0))
  1689. return ret;
  1690. if (!arg->num_outputs) {
  1691. struct drm_vmw_rect def_rect = {0, 0, 800, 600};
  1692. vmw_du_update_layout(dev_priv, 1, &def_rect);
  1693. goto out_unlock;
  1694. }
  1695. rects_size = arg->num_outputs * sizeof(struct drm_vmw_rect);
  1696. rects = kcalloc(arg->num_outputs, sizeof(struct drm_vmw_rect),
  1697. GFP_KERNEL);
  1698. if (unlikely(!rects)) {
  1699. ret = -ENOMEM;
  1700. goto out_unlock;
  1701. }
  1702. user_rects = (void __user *)(unsigned long)arg->rects;
  1703. ret = copy_from_user(rects, user_rects, rects_size);
  1704. if (unlikely(ret != 0)) {
  1705. DRM_ERROR("Failed to get rects.\n");
  1706. ret = -EFAULT;
  1707. goto out_free;
  1708. }
  1709. for (i = 0; i < arg->num_outputs; ++i) {
  1710. if (rects[i].x < 0 ||
  1711. rects[i].y < 0 ||
  1712. rects[i].x + rects[i].w > mode_config->max_width ||
  1713. rects[i].y + rects[i].h > mode_config->max_height) {
  1714. DRM_ERROR("Invalid GUI layout.\n");
  1715. ret = -EINVAL;
  1716. goto out_free;
  1717. }
  1718. }
  1719. vmw_du_update_layout(dev_priv, arg->num_outputs, rects);
  1720. out_free:
  1721. kfree(rects);
  1722. out_unlock:
  1723. ttm_read_unlock(&dev_priv->reservation_sem);
  1724. return ret;
  1725. }