vce_v1_0.c 4.5 KB

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  1. /*
  2. * Copyright 2013 Advanced Micro Devices, Inc.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. * Authors: Christian König <christian.koenig@amd.com>
  26. */
  27. #include <linux/firmware.h>
  28. #include <drm/drmP.h>
  29. #include "radeon.h"
  30. #include "radeon_asic.h"
  31. #include "sid.h"
  32. /**
  33. * vce_v1_0_get_rptr - get read pointer
  34. *
  35. * @rdev: radeon_device pointer
  36. * @ring: radeon_ring pointer
  37. *
  38. * Returns the current hardware read pointer
  39. */
  40. uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
  41. struct radeon_ring *ring)
  42. {
  43. if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
  44. return RREG32(VCE_RB_RPTR);
  45. else
  46. return RREG32(VCE_RB_RPTR2);
  47. }
  48. /**
  49. * vce_v1_0_get_wptr - get write pointer
  50. *
  51. * @rdev: radeon_device pointer
  52. * @ring: radeon_ring pointer
  53. *
  54. * Returns the current hardware write pointer
  55. */
  56. uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
  57. struct radeon_ring *ring)
  58. {
  59. if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
  60. return RREG32(VCE_RB_WPTR);
  61. else
  62. return RREG32(VCE_RB_WPTR2);
  63. }
  64. /**
  65. * vce_v1_0_set_wptr - set write pointer
  66. *
  67. * @rdev: radeon_device pointer
  68. * @ring: radeon_ring pointer
  69. *
  70. * Commits the write pointer to the hardware
  71. */
  72. void vce_v1_0_set_wptr(struct radeon_device *rdev,
  73. struct radeon_ring *ring)
  74. {
  75. if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
  76. WREG32(VCE_RB_WPTR, ring->wptr);
  77. else
  78. WREG32(VCE_RB_WPTR2, ring->wptr);
  79. }
  80. /**
  81. * vce_v1_0_start - start VCE block
  82. *
  83. * @rdev: radeon_device pointer
  84. *
  85. * Setup and start the VCE block
  86. */
  87. int vce_v1_0_start(struct radeon_device *rdev)
  88. {
  89. struct radeon_ring *ring;
  90. int i, j, r;
  91. /* set BUSY flag */
  92. WREG32_P(VCE_STATUS, 1, ~1);
  93. ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
  94. WREG32(VCE_RB_RPTR, ring->wptr);
  95. WREG32(VCE_RB_WPTR, ring->wptr);
  96. WREG32(VCE_RB_BASE_LO, ring->gpu_addr);
  97. WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
  98. WREG32(VCE_RB_SIZE, ring->ring_size / 4);
  99. ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
  100. WREG32(VCE_RB_RPTR2, ring->wptr);
  101. WREG32(VCE_RB_WPTR2, ring->wptr);
  102. WREG32(VCE_RB_BASE_LO2, ring->gpu_addr);
  103. WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
  104. WREG32(VCE_RB_SIZE2, ring->ring_size / 4);
  105. WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN);
  106. WREG32_P(VCE_SOFT_RESET,
  107. VCE_ECPU_SOFT_RESET |
  108. VCE_FME_SOFT_RESET, ~(
  109. VCE_ECPU_SOFT_RESET |
  110. VCE_FME_SOFT_RESET));
  111. mdelay(100);
  112. WREG32_P(VCE_SOFT_RESET, 0, ~(
  113. VCE_ECPU_SOFT_RESET |
  114. VCE_FME_SOFT_RESET));
  115. for (i = 0; i < 10; ++i) {
  116. uint32_t status;
  117. for (j = 0; j < 100; ++j) {
  118. status = RREG32(VCE_STATUS);
  119. if (status & 2)
  120. break;
  121. mdelay(10);
  122. }
  123. r = 0;
  124. if (status & 2)
  125. break;
  126. DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
  127. WREG32_P(VCE_SOFT_RESET, VCE_ECPU_SOFT_RESET, ~VCE_ECPU_SOFT_RESET);
  128. mdelay(10);
  129. WREG32_P(VCE_SOFT_RESET, 0, ~VCE_ECPU_SOFT_RESET);
  130. mdelay(10);
  131. r = -1;
  132. }
  133. /* clear BUSY flag */
  134. WREG32_P(VCE_STATUS, 0, ~1);
  135. if (r) {
  136. DRM_ERROR("VCE not responding, giving up!!!\n");
  137. return r;
  138. }
  139. return 0;
  140. }
  141. int vce_v1_0_init(struct radeon_device *rdev)
  142. {
  143. struct radeon_ring *ring;
  144. int r;
  145. r = vce_v1_0_start(rdev);
  146. if (r)
  147. return r;
  148. ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
  149. ring->ready = true;
  150. r = radeon_ring_test(rdev, TN_RING_TYPE_VCE1_INDEX, ring);
  151. if (r) {
  152. ring->ready = false;
  153. return r;
  154. }
  155. ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
  156. ring->ready = true;
  157. r = radeon_ring_test(rdev, TN_RING_TYPE_VCE2_INDEX, ring);
  158. if (r) {
  159. ring->ready = false;
  160. return r;
  161. }
  162. DRM_INFO("VCE initialized successfully.\n");
  163. return 0;
  164. }