radeon_vce.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771
  1. /*
  2. * Copyright 2013 Advanced Micro Devices, Inc.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. * Authors: Christian König <christian.koenig@amd.com>
  26. */
  27. #include <linux/firmware.h>
  28. #include <linux/module.h>
  29. #include <drm/drmP.h>
  30. #include <drm/drm.h>
  31. #include "radeon.h"
  32. #include "radeon_asic.h"
  33. #include "sid.h"
  34. /* 1 second timeout */
  35. #define VCE_IDLE_TIMEOUT_MS 1000
  36. /* Firmware Names */
  37. #define FIRMWARE_BONAIRE "radeon/BONAIRE_vce.bin"
  38. MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  39. static void radeon_vce_idle_work_handler(struct work_struct *work);
  40. /**
  41. * radeon_vce_init - allocate memory, load vce firmware
  42. *
  43. * @rdev: radeon_device pointer
  44. *
  45. * First step to get VCE online, allocate memory and load the firmware
  46. */
  47. int radeon_vce_init(struct radeon_device *rdev)
  48. {
  49. static const char *fw_version = "[ATI LIB=VCEFW,";
  50. static const char *fb_version = "[ATI LIB=VCEFWSTATS,";
  51. unsigned long size;
  52. const char *fw_name, *c;
  53. uint8_t start, mid, end;
  54. int i, r;
  55. INIT_DELAYED_WORK(&rdev->vce.idle_work, radeon_vce_idle_work_handler);
  56. switch (rdev->family) {
  57. case CHIP_BONAIRE:
  58. case CHIP_KAVERI:
  59. case CHIP_KABINI:
  60. case CHIP_HAWAII:
  61. case CHIP_MULLINS:
  62. fw_name = FIRMWARE_BONAIRE;
  63. break;
  64. default:
  65. return -EINVAL;
  66. }
  67. r = request_firmware(&rdev->vce_fw, fw_name, rdev->dev);
  68. if (r) {
  69. dev_err(rdev->dev, "radeon_vce: Can't load firmware \"%s\"\n",
  70. fw_name);
  71. return r;
  72. }
  73. /* search for firmware version */
  74. size = rdev->vce_fw->size - strlen(fw_version) - 9;
  75. c = rdev->vce_fw->data;
  76. for (;size > 0; --size, ++c)
  77. if (strncmp(c, fw_version, strlen(fw_version)) == 0)
  78. break;
  79. if (size == 0)
  80. return -EINVAL;
  81. c += strlen(fw_version);
  82. if (sscanf(c, "%2hhd.%2hhd.%2hhd]", &start, &mid, &end) != 3)
  83. return -EINVAL;
  84. /* search for feedback version */
  85. size = rdev->vce_fw->size - strlen(fb_version) - 3;
  86. c = rdev->vce_fw->data;
  87. for (;size > 0; --size, ++c)
  88. if (strncmp(c, fb_version, strlen(fb_version)) == 0)
  89. break;
  90. if (size == 0)
  91. return -EINVAL;
  92. c += strlen(fb_version);
  93. if (sscanf(c, "%2u]", &rdev->vce.fb_version) != 1)
  94. return -EINVAL;
  95. DRM_INFO("Found VCE firmware/feedback version %hhd.%hhd.%hhd / %d!\n",
  96. start, mid, end, rdev->vce.fb_version);
  97. rdev->vce.fw_version = (start << 24) | (mid << 16) | (end << 8);
  98. /* we can only work with this fw version for now */
  99. if (rdev->vce.fw_version != ((40 << 24) | (2 << 16) | (2 << 8)))
  100. return -EINVAL;
  101. /* allocate firmware, stack and heap BO */
  102. size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size) +
  103. RADEON_VCE_STACK_SIZE + RADEON_VCE_HEAP_SIZE;
  104. r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
  105. RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->vce.vcpu_bo);
  106. if (r) {
  107. dev_err(rdev->dev, "(%d) failed to allocate VCE bo\n", r);
  108. return r;
  109. }
  110. r = radeon_bo_reserve(rdev->vce.vcpu_bo, false);
  111. if (r) {
  112. radeon_bo_unref(&rdev->vce.vcpu_bo);
  113. dev_err(rdev->dev, "(%d) failed to reserve VCE bo\n", r);
  114. return r;
  115. }
  116. r = radeon_bo_pin(rdev->vce.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
  117. &rdev->vce.gpu_addr);
  118. radeon_bo_unreserve(rdev->vce.vcpu_bo);
  119. if (r) {
  120. radeon_bo_unref(&rdev->vce.vcpu_bo);
  121. dev_err(rdev->dev, "(%d) VCE bo pin failed\n", r);
  122. return r;
  123. }
  124. for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
  125. atomic_set(&rdev->vce.handles[i], 0);
  126. rdev->vce.filp[i] = NULL;
  127. }
  128. return 0;
  129. }
  130. /**
  131. * radeon_vce_fini - free memory
  132. *
  133. * @rdev: radeon_device pointer
  134. *
  135. * Last step on VCE teardown, free firmware memory
  136. */
  137. void radeon_vce_fini(struct radeon_device *rdev)
  138. {
  139. if (rdev->vce.vcpu_bo == NULL)
  140. return;
  141. radeon_bo_unref(&rdev->vce.vcpu_bo);
  142. release_firmware(rdev->vce_fw);
  143. }
  144. /**
  145. * radeon_vce_suspend - unpin VCE fw memory
  146. *
  147. * @rdev: radeon_device pointer
  148. *
  149. */
  150. int radeon_vce_suspend(struct radeon_device *rdev)
  151. {
  152. int i;
  153. if (rdev->vce.vcpu_bo == NULL)
  154. return 0;
  155. for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i)
  156. if (atomic_read(&rdev->vce.handles[i]))
  157. break;
  158. if (i == RADEON_MAX_VCE_HANDLES)
  159. return 0;
  160. /* TODO: suspending running encoding sessions isn't supported */
  161. return -EINVAL;
  162. }
  163. /**
  164. * radeon_vce_resume - pin VCE fw memory
  165. *
  166. * @rdev: radeon_device pointer
  167. *
  168. */
  169. int radeon_vce_resume(struct radeon_device *rdev)
  170. {
  171. void *cpu_addr;
  172. int r;
  173. if (rdev->vce.vcpu_bo == NULL)
  174. return -EINVAL;
  175. r = radeon_bo_reserve(rdev->vce.vcpu_bo, false);
  176. if (r) {
  177. dev_err(rdev->dev, "(%d) failed to reserve VCE bo\n", r);
  178. return r;
  179. }
  180. r = radeon_bo_kmap(rdev->vce.vcpu_bo, &cpu_addr);
  181. if (r) {
  182. radeon_bo_unreserve(rdev->vce.vcpu_bo);
  183. dev_err(rdev->dev, "(%d) VCE map failed\n", r);
  184. return r;
  185. }
  186. memcpy(cpu_addr, rdev->vce_fw->data, rdev->vce_fw->size);
  187. radeon_bo_kunmap(rdev->vce.vcpu_bo);
  188. radeon_bo_unreserve(rdev->vce.vcpu_bo);
  189. return 0;
  190. }
  191. /**
  192. * radeon_vce_idle_work_handler - power off VCE
  193. *
  194. * @work: pointer to work structure
  195. *
  196. * power of VCE when it's not used any more
  197. */
  198. static void radeon_vce_idle_work_handler(struct work_struct *work)
  199. {
  200. struct radeon_device *rdev =
  201. container_of(work, struct radeon_device, vce.idle_work.work);
  202. if ((radeon_fence_count_emitted(rdev, TN_RING_TYPE_VCE1_INDEX) == 0) &&
  203. (radeon_fence_count_emitted(rdev, TN_RING_TYPE_VCE2_INDEX) == 0)) {
  204. if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
  205. radeon_dpm_enable_vce(rdev, false);
  206. } else {
  207. radeon_set_vce_clocks(rdev, 0, 0);
  208. }
  209. } else {
  210. schedule_delayed_work(&rdev->vce.idle_work,
  211. msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
  212. }
  213. }
  214. /**
  215. * radeon_vce_note_usage - power up VCE
  216. *
  217. * @rdev: radeon_device pointer
  218. *
  219. * Make sure VCE is powerd up when we want to use it
  220. */
  221. void radeon_vce_note_usage(struct radeon_device *rdev)
  222. {
  223. bool streams_changed = false;
  224. bool set_clocks = !cancel_delayed_work_sync(&rdev->vce.idle_work);
  225. set_clocks &= schedule_delayed_work(&rdev->vce.idle_work,
  226. msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
  227. if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
  228. /* XXX figure out if the streams changed */
  229. streams_changed = false;
  230. }
  231. if (set_clocks || streams_changed) {
  232. if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
  233. radeon_dpm_enable_vce(rdev, true);
  234. } else {
  235. radeon_set_vce_clocks(rdev, 53300, 40000);
  236. }
  237. }
  238. }
  239. /**
  240. * radeon_vce_free_handles - free still open VCE handles
  241. *
  242. * @rdev: radeon_device pointer
  243. * @filp: drm file pointer
  244. *
  245. * Close all VCE handles still open by this file pointer
  246. */
  247. void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp)
  248. {
  249. int i, r;
  250. for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
  251. uint32_t handle = atomic_read(&rdev->vce.handles[i]);
  252. if (!handle || rdev->vce.filp[i] != filp)
  253. continue;
  254. radeon_vce_note_usage(rdev);
  255. r = radeon_vce_get_destroy_msg(rdev, TN_RING_TYPE_VCE1_INDEX,
  256. handle, NULL);
  257. if (r)
  258. DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
  259. rdev->vce.filp[i] = NULL;
  260. atomic_set(&rdev->vce.handles[i], 0);
  261. }
  262. }
  263. /**
  264. * radeon_vce_get_create_msg - generate a VCE create msg
  265. *
  266. * @rdev: radeon_device pointer
  267. * @ring: ring we should submit the msg to
  268. * @handle: VCE session handle to use
  269. * @fence: optional fence to return
  270. *
  271. * Open up a stream for HW test
  272. */
  273. int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
  274. uint32_t handle, struct radeon_fence **fence)
  275. {
  276. const unsigned ib_size_dw = 1024;
  277. struct radeon_ib ib;
  278. uint64_t dummy;
  279. int i, r;
  280. r = radeon_ib_get(rdev, ring, &ib, NULL, ib_size_dw * 4);
  281. if (r) {
  282. DRM_ERROR("radeon: failed to get ib (%d).\n", r);
  283. return r;
  284. }
  285. dummy = ib.gpu_addr + 1024;
  286. /* stitch together an VCE create msg */
  287. ib.length_dw = 0;
  288. ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
  289. ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
  290. ib.ptr[ib.length_dw++] = handle;
  291. ib.ptr[ib.length_dw++] = 0x00000030; /* len */
  292. ib.ptr[ib.length_dw++] = 0x01000001; /* create cmd */
  293. ib.ptr[ib.length_dw++] = 0x00000000;
  294. ib.ptr[ib.length_dw++] = 0x00000042;
  295. ib.ptr[ib.length_dw++] = 0x0000000a;
  296. ib.ptr[ib.length_dw++] = 0x00000001;
  297. ib.ptr[ib.length_dw++] = 0x00000080;
  298. ib.ptr[ib.length_dw++] = 0x00000060;
  299. ib.ptr[ib.length_dw++] = 0x00000100;
  300. ib.ptr[ib.length_dw++] = 0x00000100;
  301. ib.ptr[ib.length_dw++] = 0x0000000c;
  302. ib.ptr[ib.length_dw++] = 0x00000000;
  303. ib.ptr[ib.length_dw++] = 0x00000014; /* len */
  304. ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
  305. ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
  306. ib.ptr[ib.length_dw++] = dummy;
  307. ib.ptr[ib.length_dw++] = 0x00000001;
  308. for (i = ib.length_dw; i < ib_size_dw; ++i)
  309. ib.ptr[i] = 0x0;
  310. r = radeon_ib_schedule(rdev, &ib, NULL);
  311. if (r) {
  312. DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
  313. }
  314. if (fence)
  315. *fence = radeon_fence_ref(ib.fence);
  316. radeon_ib_free(rdev, &ib);
  317. return r;
  318. }
  319. /**
  320. * radeon_vce_get_destroy_msg - generate a VCE destroy msg
  321. *
  322. * @rdev: radeon_device pointer
  323. * @ring: ring we should submit the msg to
  324. * @handle: VCE session handle to use
  325. * @fence: optional fence to return
  326. *
  327. * Close up a stream for HW test or if userspace failed to do so
  328. */
  329. int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
  330. uint32_t handle, struct radeon_fence **fence)
  331. {
  332. const unsigned ib_size_dw = 1024;
  333. struct radeon_ib ib;
  334. uint64_t dummy;
  335. int i, r;
  336. r = radeon_ib_get(rdev, ring, &ib, NULL, ib_size_dw * 4);
  337. if (r) {
  338. DRM_ERROR("radeon: failed to get ib (%d).\n", r);
  339. return r;
  340. }
  341. dummy = ib.gpu_addr + 1024;
  342. /* stitch together an VCE destroy msg */
  343. ib.length_dw = 0;
  344. ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
  345. ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
  346. ib.ptr[ib.length_dw++] = handle;
  347. ib.ptr[ib.length_dw++] = 0x00000014; /* len */
  348. ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
  349. ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
  350. ib.ptr[ib.length_dw++] = dummy;
  351. ib.ptr[ib.length_dw++] = 0x00000001;
  352. ib.ptr[ib.length_dw++] = 0x00000008; /* len */
  353. ib.ptr[ib.length_dw++] = 0x02000001; /* destroy cmd */
  354. for (i = ib.length_dw; i < ib_size_dw; ++i)
  355. ib.ptr[i] = 0x0;
  356. r = radeon_ib_schedule(rdev, &ib, NULL);
  357. if (r) {
  358. DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
  359. }
  360. if (fence)
  361. *fence = radeon_fence_ref(ib.fence);
  362. radeon_ib_free(rdev, &ib);
  363. return r;
  364. }
  365. /**
  366. * radeon_vce_cs_reloc - command submission relocation
  367. *
  368. * @p: parser context
  369. * @lo: address of lower dword
  370. * @hi: address of higher dword
  371. * @size: size of checker for relocation buffer
  372. *
  373. * Patch relocation inside command stream with real buffer address
  374. */
  375. int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi,
  376. unsigned size)
  377. {
  378. struct radeon_cs_chunk *relocs_chunk;
  379. struct radeon_cs_reloc *reloc;
  380. uint64_t start, end, offset;
  381. unsigned idx;
  382. relocs_chunk = &p->chunks[p->chunk_relocs_idx];
  383. offset = radeon_get_ib_value(p, lo);
  384. idx = radeon_get_ib_value(p, hi);
  385. if (idx >= relocs_chunk->length_dw) {
  386. DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
  387. idx, relocs_chunk->length_dw);
  388. return -EINVAL;
  389. }
  390. reloc = p->relocs_ptr[(idx / 4)];
  391. start = reloc->gpu_offset;
  392. end = start + radeon_bo_size(reloc->robj);
  393. start += offset;
  394. p->ib.ptr[lo] = start & 0xFFFFFFFF;
  395. p->ib.ptr[hi] = start >> 32;
  396. if (end <= start) {
  397. DRM_ERROR("invalid reloc offset %llX!\n", offset);
  398. return -EINVAL;
  399. }
  400. if ((end - start) < size) {
  401. DRM_ERROR("buffer to small (%d / %d)!\n",
  402. (unsigned)(end - start), size);
  403. return -EINVAL;
  404. }
  405. return 0;
  406. }
  407. /**
  408. * radeon_vce_validate_handle - validate stream handle
  409. *
  410. * @p: parser context
  411. * @handle: handle to validate
  412. *
  413. * Validates the handle and return the found session index or -EINVAL
  414. * we we don't have another free session index.
  415. */
  416. int radeon_vce_validate_handle(struct radeon_cs_parser *p, uint32_t handle)
  417. {
  418. unsigned i;
  419. /* validate the handle */
  420. for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
  421. if (atomic_read(&p->rdev->vce.handles[i]) == handle)
  422. return i;
  423. }
  424. /* handle not found try to alloc a new one */
  425. for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
  426. if (!atomic_cmpxchg(&p->rdev->vce.handles[i], 0, handle)) {
  427. p->rdev->vce.filp[i] = p->filp;
  428. p->rdev->vce.img_size[i] = 0;
  429. return i;
  430. }
  431. }
  432. DRM_ERROR("No more free VCE handles!\n");
  433. return -EINVAL;
  434. }
  435. /**
  436. * radeon_vce_cs_parse - parse and validate the command stream
  437. *
  438. * @p: parser context
  439. *
  440. */
  441. int radeon_vce_cs_parse(struct radeon_cs_parser *p)
  442. {
  443. int session_idx = -1;
  444. bool destroyed = false;
  445. uint32_t tmp, handle = 0;
  446. uint32_t *size = &tmp;
  447. int i, r;
  448. while (p->idx < p->chunks[p->chunk_ib_idx].length_dw) {
  449. uint32_t len = radeon_get_ib_value(p, p->idx);
  450. uint32_t cmd = radeon_get_ib_value(p, p->idx + 1);
  451. if ((len < 8) || (len & 3)) {
  452. DRM_ERROR("invalid VCE command length (%d)!\n", len);
  453. return -EINVAL;
  454. }
  455. if (destroyed) {
  456. DRM_ERROR("No other command allowed after destroy!\n");
  457. return -EINVAL;
  458. }
  459. switch (cmd) {
  460. case 0x00000001: // session
  461. handle = radeon_get_ib_value(p, p->idx + 2);
  462. session_idx = radeon_vce_validate_handle(p, handle);
  463. if (session_idx < 0)
  464. return session_idx;
  465. size = &p->rdev->vce.img_size[session_idx];
  466. break;
  467. case 0x00000002: // task info
  468. break;
  469. case 0x01000001: // create
  470. *size = radeon_get_ib_value(p, p->idx + 8) *
  471. radeon_get_ib_value(p, p->idx + 10) *
  472. 8 * 3 / 2;
  473. break;
  474. case 0x04000001: // config extension
  475. case 0x04000002: // pic control
  476. case 0x04000005: // rate control
  477. case 0x04000007: // motion estimation
  478. case 0x04000008: // rdo
  479. break;
  480. case 0x03000001: // encode
  481. r = radeon_vce_cs_reloc(p, p->idx + 10, p->idx + 9,
  482. *size);
  483. if (r)
  484. return r;
  485. r = radeon_vce_cs_reloc(p, p->idx + 12, p->idx + 11,
  486. *size / 3);
  487. if (r)
  488. return r;
  489. break;
  490. case 0x02000001: // destroy
  491. destroyed = true;
  492. break;
  493. case 0x05000001: // context buffer
  494. r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
  495. *size * 2);
  496. if (r)
  497. return r;
  498. break;
  499. case 0x05000004: // video bitstream buffer
  500. tmp = radeon_get_ib_value(p, p->idx + 4);
  501. r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
  502. tmp);
  503. if (r)
  504. return r;
  505. break;
  506. case 0x05000005: // feedback buffer
  507. r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
  508. 4096);
  509. if (r)
  510. return r;
  511. break;
  512. default:
  513. DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
  514. return -EINVAL;
  515. }
  516. if (session_idx == -1) {
  517. DRM_ERROR("no session command at start of IB\n");
  518. return -EINVAL;
  519. }
  520. p->idx += len / 4;
  521. }
  522. if (destroyed) {
  523. /* IB contains a destroy msg, free the handle */
  524. for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i)
  525. atomic_cmpxchg(&p->rdev->vce.handles[i], handle, 0);
  526. }
  527. return 0;
  528. }
  529. /**
  530. * radeon_vce_semaphore_emit - emit a semaphore command
  531. *
  532. * @rdev: radeon_device pointer
  533. * @ring: engine to use
  534. * @semaphore: address of semaphore
  535. * @emit_wait: true=emit wait, false=emit signal
  536. *
  537. */
  538. bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
  539. struct radeon_ring *ring,
  540. struct radeon_semaphore *semaphore,
  541. bool emit_wait)
  542. {
  543. uint64_t addr = semaphore->gpu_addr;
  544. radeon_ring_write(ring, VCE_CMD_SEMAPHORE);
  545. radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
  546. radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
  547. radeon_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0));
  548. if (!emit_wait)
  549. radeon_ring_write(ring, VCE_CMD_END);
  550. return true;
  551. }
  552. /**
  553. * radeon_vce_ib_execute - execute indirect buffer
  554. *
  555. * @rdev: radeon_device pointer
  556. * @ib: the IB to execute
  557. *
  558. */
  559. void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
  560. {
  561. struct radeon_ring *ring = &rdev->ring[ib->ring];
  562. radeon_ring_write(ring, VCE_CMD_IB);
  563. radeon_ring_write(ring, ib->gpu_addr);
  564. radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
  565. radeon_ring_write(ring, ib->length_dw);
  566. }
  567. /**
  568. * radeon_vce_fence_emit - add a fence command to the ring
  569. *
  570. * @rdev: radeon_device pointer
  571. * @fence: the fence
  572. *
  573. */
  574. void radeon_vce_fence_emit(struct radeon_device *rdev,
  575. struct radeon_fence *fence)
  576. {
  577. struct radeon_ring *ring = &rdev->ring[fence->ring];
  578. uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
  579. radeon_ring_write(ring, VCE_CMD_FENCE);
  580. radeon_ring_write(ring, addr);
  581. radeon_ring_write(ring, upper_32_bits(addr));
  582. radeon_ring_write(ring, fence->seq);
  583. radeon_ring_write(ring, VCE_CMD_TRAP);
  584. radeon_ring_write(ring, VCE_CMD_END);
  585. }
  586. /**
  587. * radeon_vce_ring_test - test if VCE ring is working
  588. *
  589. * @rdev: radeon_device pointer
  590. * @ring: the engine to test on
  591. *
  592. */
  593. int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
  594. {
  595. uint32_t rptr = vce_v1_0_get_rptr(rdev, ring);
  596. unsigned i;
  597. int r;
  598. r = radeon_ring_lock(rdev, ring, 16);
  599. if (r) {
  600. DRM_ERROR("radeon: vce failed to lock ring %d (%d).\n",
  601. ring->idx, r);
  602. return r;
  603. }
  604. radeon_ring_write(ring, VCE_CMD_END);
  605. radeon_ring_unlock_commit(rdev, ring);
  606. for (i = 0; i < rdev->usec_timeout; i++) {
  607. if (vce_v1_0_get_rptr(rdev, ring) != rptr)
  608. break;
  609. DRM_UDELAY(1);
  610. }
  611. if (i < rdev->usec_timeout) {
  612. DRM_INFO("ring test on %d succeeded in %d usecs\n",
  613. ring->idx, i);
  614. } else {
  615. DRM_ERROR("radeon: ring %d test failed\n",
  616. ring->idx);
  617. r = -ETIMEDOUT;
  618. }
  619. return r;
  620. }
  621. /**
  622. * radeon_vce_ib_test - test if VCE IBs are working
  623. *
  624. * @rdev: radeon_device pointer
  625. * @ring: the engine to test on
  626. *
  627. */
  628. int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
  629. {
  630. struct radeon_fence *fence = NULL;
  631. int r;
  632. r = radeon_vce_get_create_msg(rdev, ring->idx, 1, NULL);
  633. if (r) {
  634. DRM_ERROR("radeon: failed to get create msg (%d).\n", r);
  635. goto error;
  636. }
  637. r = radeon_vce_get_destroy_msg(rdev, ring->idx, 1, &fence);
  638. if (r) {
  639. DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r);
  640. goto error;
  641. }
  642. r = radeon_fence_wait(fence, false);
  643. if (r) {
  644. DRM_ERROR("radeon: fence wait failed (%d).\n", r);
  645. } else {
  646. DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
  647. }
  648. error:
  649. radeon_fence_unref(&fence);
  650. return r;
  651. }