radeon_ttm.c 26 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30. * Dave Airlie
  31. */
  32. #include <ttm/ttm_bo_api.h>
  33. #include <ttm/ttm_bo_driver.h>
  34. #include <ttm/ttm_placement.h>
  35. #include <ttm/ttm_module.h>
  36. #include <ttm/ttm_page_alloc.h>
  37. #include <drm/drmP.h>
  38. #include <drm/radeon_drm.h>
  39. #include <linux/seq_file.h>
  40. #include <linux/slab.h>
  41. #include <linux/swiotlb.h>
  42. #include <linux/debugfs.h>
  43. #include "radeon_reg.h"
  44. #include "radeon.h"
  45. #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  46. static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
  47. static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
  48. static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
  49. {
  50. struct radeon_mman *mman;
  51. struct radeon_device *rdev;
  52. mman = container_of(bdev, struct radeon_mman, bdev);
  53. rdev = container_of(mman, struct radeon_device, mman);
  54. return rdev;
  55. }
  56. /*
  57. * Global memory.
  58. */
  59. static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
  60. {
  61. return ttm_mem_global_init(ref->object);
  62. }
  63. static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
  64. {
  65. ttm_mem_global_release(ref->object);
  66. }
  67. static int radeon_ttm_global_init(struct radeon_device *rdev)
  68. {
  69. struct drm_global_reference *global_ref;
  70. int r;
  71. rdev->mman.mem_global_referenced = false;
  72. global_ref = &rdev->mman.mem_global_ref;
  73. global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  74. global_ref->size = sizeof(struct ttm_mem_global);
  75. global_ref->init = &radeon_ttm_mem_global_init;
  76. global_ref->release = &radeon_ttm_mem_global_release;
  77. r = drm_global_item_ref(global_ref);
  78. if (r != 0) {
  79. DRM_ERROR("Failed setting up TTM memory accounting "
  80. "subsystem.\n");
  81. return r;
  82. }
  83. rdev->mman.bo_global_ref.mem_glob =
  84. rdev->mman.mem_global_ref.object;
  85. global_ref = &rdev->mman.bo_global_ref.ref;
  86. global_ref->global_type = DRM_GLOBAL_TTM_BO;
  87. global_ref->size = sizeof(struct ttm_bo_global);
  88. global_ref->init = &ttm_bo_global_init;
  89. global_ref->release = &ttm_bo_global_release;
  90. r = drm_global_item_ref(global_ref);
  91. if (r != 0) {
  92. DRM_ERROR("Failed setting up TTM BO subsystem.\n");
  93. drm_global_item_unref(&rdev->mman.mem_global_ref);
  94. return r;
  95. }
  96. rdev->mman.mem_global_referenced = true;
  97. return 0;
  98. }
  99. static void radeon_ttm_global_fini(struct radeon_device *rdev)
  100. {
  101. if (rdev->mman.mem_global_referenced) {
  102. drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
  103. drm_global_item_unref(&rdev->mman.mem_global_ref);
  104. rdev->mman.mem_global_referenced = false;
  105. }
  106. }
  107. static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  108. {
  109. return 0;
  110. }
  111. static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  112. struct ttm_mem_type_manager *man)
  113. {
  114. struct radeon_device *rdev;
  115. rdev = radeon_get_rdev(bdev);
  116. switch (type) {
  117. case TTM_PL_SYSTEM:
  118. /* System memory */
  119. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  120. man->available_caching = TTM_PL_MASK_CACHING;
  121. man->default_caching = TTM_PL_FLAG_CACHED;
  122. break;
  123. case TTM_PL_TT:
  124. man->func = &ttm_bo_manager_func;
  125. man->gpu_offset = rdev->mc.gtt_start;
  126. man->available_caching = TTM_PL_MASK_CACHING;
  127. man->default_caching = TTM_PL_FLAG_CACHED;
  128. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
  129. #if __OS_HAS_AGP
  130. if (rdev->flags & RADEON_IS_AGP) {
  131. if (!rdev->ddev->agp) {
  132. DRM_ERROR("AGP is not enabled for memory type %u\n",
  133. (unsigned)type);
  134. return -EINVAL;
  135. }
  136. if (!rdev->ddev->agp->cant_use_aperture)
  137. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  138. man->available_caching = TTM_PL_FLAG_UNCACHED |
  139. TTM_PL_FLAG_WC;
  140. man->default_caching = TTM_PL_FLAG_WC;
  141. }
  142. #endif
  143. break;
  144. case TTM_PL_VRAM:
  145. /* "On-card" video ram */
  146. man->func = &ttm_bo_manager_func;
  147. man->gpu_offset = rdev->mc.vram_start;
  148. man->flags = TTM_MEMTYPE_FLAG_FIXED |
  149. TTM_MEMTYPE_FLAG_MAPPABLE;
  150. man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
  151. man->default_caching = TTM_PL_FLAG_WC;
  152. break;
  153. default:
  154. DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
  155. return -EINVAL;
  156. }
  157. return 0;
  158. }
  159. static void radeon_evict_flags(struct ttm_buffer_object *bo,
  160. struct ttm_placement *placement)
  161. {
  162. struct radeon_bo *rbo;
  163. static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  164. if (!radeon_ttm_bo_is_radeon_bo(bo)) {
  165. placement->fpfn = 0;
  166. placement->lpfn = 0;
  167. placement->placement = &placements;
  168. placement->busy_placement = &placements;
  169. placement->num_placement = 1;
  170. placement->num_busy_placement = 1;
  171. return;
  172. }
  173. rbo = container_of(bo, struct radeon_bo, tbo);
  174. switch (bo->mem.mem_type) {
  175. case TTM_PL_VRAM:
  176. if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false)
  177. radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
  178. else
  179. radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
  180. break;
  181. case TTM_PL_TT:
  182. default:
  183. radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
  184. }
  185. *placement = rbo->placement;
  186. }
  187. static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
  188. {
  189. struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
  190. return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
  191. }
  192. static void radeon_move_null(struct ttm_buffer_object *bo,
  193. struct ttm_mem_reg *new_mem)
  194. {
  195. struct ttm_mem_reg *old_mem = &bo->mem;
  196. BUG_ON(old_mem->mm_node != NULL);
  197. *old_mem = *new_mem;
  198. new_mem->mm_node = NULL;
  199. }
  200. static int radeon_move_blit(struct ttm_buffer_object *bo,
  201. bool evict, bool no_wait_gpu,
  202. struct ttm_mem_reg *new_mem,
  203. struct ttm_mem_reg *old_mem)
  204. {
  205. struct radeon_device *rdev;
  206. uint64_t old_start, new_start;
  207. struct radeon_fence *fence;
  208. int r, ridx;
  209. rdev = radeon_get_rdev(bo->bdev);
  210. ridx = radeon_copy_ring_index(rdev);
  211. old_start = old_mem->start << PAGE_SHIFT;
  212. new_start = new_mem->start << PAGE_SHIFT;
  213. switch (old_mem->mem_type) {
  214. case TTM_PL_VRAM:
  215. old_start += rdev->mc.vram_start;
  216. break;
  217. case TTM_PL_TT:
  218. old_start += rdev->mc.gtt_start;
  219. break;
  220. default:
  221. DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
  222. return -EINVAL;
  223. }
  224. switch (new_mem->mem_type) {
  225. case TTM_PL_VRAM:
  226. new_start += rdev->mc.vram_start;
  227. break;
  228. case TTM_PL_TT:
  229. new_start += rdev->mc.gtt_start;
  230. break;
  231. default:
  232. DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
  233. return -EINVAL;
  234. }
  235. if (!rdev->ring[ridx].ready) {
  236. DRM_ERROR("Trying to move memory with ring turned off.\n");
  237. return -EINVAL;
  238. }
  239. BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
  240. /* sync other rings */
  241. fence = bo->sync_obj;
  242. r = radeon_copy(rdev, old_start, new_start,
  243. new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */
  244. &fence);
  245. /* FIXME: handle copy error */
  246. r = ttm_bo_move_accel_cleanup(bo, (void *)fence,
  247. evict, no_wait_gpu, new_mem);
  248. radeon_fence_unref(&fence);
  249. return r;
  250. }
  251. static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
  252. bool evict, bool interruptible,
  253. bool no_wait_gpu,
  254. struct ttm_mem_reg *new_mem)
  255. {
  256. struct radeon_device *rdev;
  257. struct ttm_mem_reg *old_mem = &bo->mem;
  258. struct ttm_mem_reg tmp_mem;
  259. u32 placements;
  260. struct ttm_placement placement;
  261. int r;
  262. rdev = radeon_get_rdev(bo->bdev);
  263. tmp_mem = *new_mem;
  264. tmp_mem.mm_node = NULL;
  265. placement.fpfn = 0;
  266. placement.lpfn = 0;
  267. placement.num_placement = 1;
  268. placement.placement = &placements;
  269. placement.num_busy_placement = 1;
  270. placement.busy_placement = &placements;
  271. placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  272. r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
  273. interruptible, no_wait_gpu);
  274. if (unlikely(r)) {
  275. return r;
  276. }
  277. r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
  278. if (unlikely(r)) {
  279. goto out_cleanup;
  280. }
  281. r = ttm_tt_bind(bo->ttm, &tmp_mem);
  282. if (unlikely(r)) {
  283. goto out_cleanup;
  284. }
  285. r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
  286. if (unlikely(r)) {
  287. goto out_cleanup;
  288. }
  289. r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
  290. out_cleanup:
  291. ttm_bo_mem_put(bo, &tmp_mem);
  292. return r;
  293. }
  294. static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
  295. bool evict, bool interruptible,
  296. bool no_wait_gpu,
  297. struct ttm_mem_reg *new_mem)
  298. {
  299. struct radeon_device *rdev;
  300. struct ttm_mem_reg *old_mem = &bo->mem;
  301. struct ttm_mem_reg tmp_mem;
  302. struct ttm_placement placement;
  303. u32 placements;
  304. int r;
  305. rdev = radeon_get_rdev(bo->bdev);
  306. tmp_mem = *new_mem;
  307. tmp_mem.mm_node = NULL;
  308. placement.fpfn = 0;
  309. placement.lpfn = 0;
  310. placement.num_placement = 1;
  311. placement.placement = &placements;
  312. placement.num_busy_placement = 1;
  313. placement.busy_placement = &placements;
  314. placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  315. r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
  316. interruptible, no_wait_gpu);
  317. if (unlikely(r)) {
  318. return r;
  319. }
  320. r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
  321. if (unlikely(r)) {
  322. goto out_cleanup;
  323. }
  324. r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
  325. if (unlikely(r)) {
  326. goto out_cleanup;
  327. }
  328. out_cleanup:
  329. ttm_bo_mem_put(bo, &tmp_mem);
  330. return r;
  331. }
  332. static int radeon_bo_move(struct ttm_buffer_object *bo,
  333. bool evict, bool interruptible,
  334. bool no_wait_gpu,
  335. struct ttm_mem_reg *new_mem)
  336. {
  337. struct radeon_device *rdev;
  338. struct ttm_mem_reg *old_mem = &bo->mem;
  339. int r;
  340. rdev = radeon_get_rdev(bo->bdev);
  341. if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
  342. radeon_move_null(bo, new_mem);
  343. return 0;
  344. }
  345. if ((old_mem->mem_type == TTM_PL_TT &&
  346. new_mem->mem_type == TTM_PL_SYSTEM) ||
  347. (old_mem->mem_type == TTM_PL_SYSTEM &&
  348. new_mem->mem_type == TTM_PL_TT)) {
  349. /* bind is enough */
  350. radeon_move_null(bo, new_mem);
  351. return 0;
  352. }
  353. if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
  354. rdev->asic->copy.copy == NULL) {
  355. /* use memcpy */
  356. goto memcpy;
  357. }
  358. if (old_mem->mem_type == TTM_PL_VRAM &&
  359. new_mem->mem_type == TTM_PL_SYSTEM) {
  360. r = radeon_move_vram_ram(bo, evict, interruptible,
  361. no_wait_gpu, new_mem);
  362. } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
  363. new_mem->mem_type == TTM_PL_VRAM) {
  364. r = radeon_move_ram_vram(bo, evict, interruptible,
  365. no_wait_gpu, new_mem);
  366. } else {
  367. r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
  368. }
  369. if (r) {
  370. memcpy:
  371. r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
  372. if (r) {
  373. return r;
  374. }
  375. }
  376. /* update statistics */
  377. atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
  378. return 0;
  379. }
  380. static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
  381. {
  382. struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
  383. struct radeon_device *rdev = radeon_get_rdev(bdev);
  384. mem->bus.addr = NULL;
  385. mem->bus.offset = 0;
  386. mem->bus.size = mem->num_pages << PAGE_SHIFT;
  387. mem->bus.base = 0;
  388. mem->bus.is_iomem = false;
  389. if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
  390. return -EINVAL;
  391. switch (mem->mem_type) {
  392. case TTM_PL_SYSTEM:
  393. /* system memory */
  394. return 0;
  395. case TTM_PL_TT:
  396. #if __OS_HAS_AGP
  397. if (rdev->flags & RADEON_IS_AGP) {
  398. /* RADEON_IS_AGP is set only if AGP is active */
  399. mem->bus.offset = mem->start << PAGE_SHIFT;
  400. mem->bus.base = rdev->mc.agp_base;
  401. mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
  402. }
  403. #endif
  404. break;
  405. case TTM_PL_VRAM:
  406. mem->bus.offset = mem->start << PAGE_SHIFT;
  407. /* check if it's visible */
  408. if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
  409. return -EINVAL;
  410. mem->bus.base = rdev->mc.aper_base;
  411. mem->bus.is_iomem = true;
  412. #ifdef __alpha__
  413. /*
  414. * Alpha: use bus.addr to hold the ioremap() return,
  415. * so we can modify bus.base below.
  416. */
  417. if (mem->placement & TTM_PL_FLAG_WC)
  418. mem->bus.addr =
  419. ioremap_wc(mem->bus.base + mem->bus.offset,
  420. mem->bus.size);
  421. else
  422. mem->bus.addr =
  423. ioremap_nocache(mem->bus.base + mem->bus.offset,
  424. mem->bus.size);
  425. /*
  426. * Alpha: Use just the bus offset plus
  427. * the hose/domain memory base for bus.base.
  428. * It then can be used to build PTEs for VRAM
  429. * access, as done in ttm_bo_vm_fault().
  430. */
  431. mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
  432. rdev->ddev->hose->dense_mem_base;
  433. #endif
  434. break;
  435. default:
  436. return -EINVAL;
  437. }
  438. return 0;
  439. }
  440. static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
  441. {
  442. }
  443. static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible)
  444. {
  445. return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
  446. }
  447. static int radeon_sync_obj_flush(void *sync_obj)
  448. {
  449. return 0;
  450. }
  451. static void radeon_sync_obj_unref(void **sync_obj)
  452. {
  453. radeon_fence_unref((struct radeon_fence **)sync_obj);
  454. }
  455. static void *radeon_sync_obj_ref(void *sync_obj)
  456. {
  457. return radeon_fence_ref((struct radeon_fence *)sync_obj);
  458. }
  459. static bool radeon_sync_obj_signaled(void *sync_obj)
  460. {
  461. return radeon_fence_signaled((struct radeon_fence *)sync_obj);
  462. }
  463. /*
  464. * TTM backend functions.
  465. */
  466. struct radeon_ttm_tt {
  467. struct ttm_dma_tt ttm;
  468. struct radeon_device *rdev;
  469. u64 offset;
  470. };
  471. static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
  472. struct ttm_mem_reg *bo_mem)
  473. {
  474. struct radeon_ttm_tt *gtt = (void*)ttm;
  475. int r;
  476. gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
  477. if (!ttm->num_pages) {
  478. WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
  479. ttm->num_pages, bo_mem, ttm);
  480. }
  481. r = radeon_gart_bind(gtt->rdev, gtt->offset,
  482. ttm->num_pages, ttm->pages, gtt->ttm.dma_address);
  483. if (r) {
  484. DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
  485. ttm->num_pages, (unsigned)gtt->offset);
  486. return r;
  487. }
  488. return 0;
  489. }
  490. static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
  491. {
  492. struct radeon_ttm_tt *gtt = (void *)ttm;
  493. radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
  494. return 0;
  495. }
  496. static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
  497. {
  498. struct radeon_ttm_tt *gtt = (void *)ttm;
  499. ttm_dma_tt_fini(&gtt->ttm);
  500. kfree(gtt);
  501. }
  502. static struct ttm_backend_func radeon_backend_func = {
  503. .bind = &radeon_ttm_backend_bind,
  504. .unbind = &radeon_ttm_backend_unbind,
  505. .destroy = &radeon_ttm_backend_destroy,
  506. };
  507. static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
  508. unsigned long size, uint32_t page_flags,
  509. struct page *dummy_read_page)
  510. {
  511. struct radeon_device *rdev;
  512. struct radeon_ttm_tt *gtt;
  513. rdev = radeon_get_rdev(bdev);
  514. #if __OS_HAS_AGP
  515. if (rdev->flags & RADEON_IS_AGP) {
  516. return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
  517. size, page_flags, dummy_read_page);
  518. }
  519. #endif
  520. gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
  521. if (gtt == NULL) {
  522. return NULL;
  523. }
  524. gtt->ttm.ttm.func = &radeon_backend_func;
  525. gtt->rdev = rdev;
  526. if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
  527. kfree(gtt);
  528. return NULL;
  529. }
  530. return &gtt->ttm.ttm;
  531. }
  532. static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
  533. {
  534. struct radeon_device *rdev;
  535. struct radeon_ttm_tt *gtt = (void *)ttm;
  536. unsigned i;
  537. int r;
  538. bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
  539. if (ttm->state != tt_unpopulated)
  540. return 0;
  541. if (slave && ttm->sg) {
  542. drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
  543. gtt->ttm.dma_address, ttm->num_pages);
  544. ttm->state = tt_unbound;
  545. return 0;
  546. }
  547. rdev = radeon_get_rdev(ttm->bdev);
  548. #if __OS_HAS_AGP
  549. if (rdev->flags & RADEON_IS_AGP) {
  550. return ttm_agp_tt_populate(ttm);
  551. }
  552. #endif
  553. #ifdef CONFIG_SWIOTLB
  554. if (swiotlb_nr_tbl()) {
  555. return ttm_dma_populate(&gtt->ttm, rdev->dev);
  556. }
  557. #endif
  558. r = ttm_pool_populate(ttm);
  559. if (r) {
  560. return r;
  561. }
  562. for (i = 0; i < ttm->num_pages; i++) {
  563. gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
  564. 0, PAGE_SIZE,
  565. PCI_DMA_BIDIRECTIONAL);
  566. if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
  567. while (--i) {
  568. pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
  569. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  570. gtt->ttm.dma_address[i] = 0;
  571. }
  572. ttm_pool_unpopulate(ttm);
  573. return -EFAULT;
  574. }
  575. }
  576. return 0;
  577. }
  578. static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
  579. {
  580. struct radeon_device *rdev;
  581. struct radeon_ttm_tt *gtt = (void *)ttm;
  582. unsigned i;
  583. bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
  584. if (slave)
  585. return;
  586. rdev = radeon_get_rdev(ttm->bdev);
  587. #if __OS_HAS_AGP
  588. if (rdev->flags & RADEON_IS_AGP) {
  589. ttm_agp_tt_unpopulate(ttm);
  590. return;
  591. }
  592. #endif
  593. #ifdef CONFIG_SWIOTLB
  594. if (swiotlb_nr_tbl()) {
  595. ttm_dma_unpopulate(&gtt->ttm, rdev->dev);
  596. return;
  597. }
  598. #endif
  599. for (i = 0; i < ttm->num_pages; i++) {
  600. if (gtt->ttm.dma_address[i]) {
  601. pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
  602. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  603. }
  604. }
  605. ttm_pool_unpopulate(ttm);
  606. }
  607. static struct ttm_bo_driver radeon_bo_driver = {
  608. .ttm_tt_create = &radeon_ttm_tt_create,
  609. .ttm_tt_populate = &radeon_ttm_tt_populate,
  610. .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
  611. .invalidate_caches = &radeon_invalidate_caches,
  612. .init_mem_type = &radeon_init_mem_type,
  613. .evict_flags = &radeon_evict_flags,
  614. .move = &radeon_bo_move,
  615. .verify_access = &radeon_verify_access,
  616. .sync_obj_signaled = &radeon_sync_obj_signaled,
  617. .sync_obj_wait = &radeon_sync_obj_wait,
  618. .sync_obj_flush = &radeon_sync_obj_flush,
  619. .sync_obj_unref = &radeon_sync_obj_unref,
  620. .sync_obj_ref = &radeon_sync_obj_ref,
  621. .move_notify = &radeon_bo_move_notify,
  622. .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
  623. .io_mem_reserve = &radeon_ttm_io_mem_reserve,
  624. .io_mem_free = &radeon_ttm_io_mem_free,
  625. };
  626. int radeon_ttm_init(struct radeon_device *rdev)
  627. {
  628. int r;
  629. r = radeon_ttm_global_init(rdev);
  630. if (r) {
  631. return r;
  632. }
  633. /* No others user of address space so set it to 0 */
  634. r = ttm_bo_device_init(&rdev->mman.bdev,
  635. rdev->mman.bo_global_ref.ref.object,
  636. &radeon_bo_driver,
  637. rdev->ddev->anon_inode->i_mapping,
  638. DRM_FILE_PAGE_OFFSET,
  639. rdev->need_dma32);
  640. if (r) {
  641. DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
  642. return r;
  643. }
  644. rdev->mman.initialized = true;
  645. r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
  646. rdev->mc.real_vram_size >> PAGE_SHIFT);
  647. if (r) {
  648. DRM_ERROR("Failed initializing VRAM heap.\n");
  649. return r;
  650. }
  651. /* Change the size here instead of the init above so only lpfn is affected */
  652. radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
  653. r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
  654. RADEON_GEM_DOMAIN_VRAM,
  655. NULL, &rdev->stollen_vga_memory);
  656. if (r) {
  657. return r;
  658. }
  659. r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
  660. if (r)
  661. return r;
  662. r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
  663. radeon_bo_unreserve(rdev->stollen_vga_memory);
  664. if (r) {
  665. radeon_bo_unref(&rdev->stollen_vga_memory);
  666. return r;
  667. }
  668. DRM_INFO("radeon: %uM of VRAM memory ready\n",
  669. (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
  670. r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
  671. rdev->mc.gtt_size >> PAGE_SHIFT);
  672. if (r) {
  673. DRM_ERROR("Failed initializing GTT heap.\n");
  674. return r;
  675. }
  676. DRM_INFO("radeon: %uM of GTT memory ready.\n",
  677. (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
  678. r = radeon_ttm_debugfs_init(rdev);
  679. if (r) {
  680. DRM_ERROR("Failed to init debugfs\n");
  681. return r;
  682. }
  683. return 0;
  684. }
  685. void radeon_ttm_fini(struct radeon_device *rdev)
  686. {
  687. int r;
  688. if (!rdev->mman.initialized)
  689. return;
  690. radeon_ttm_debugfs_fini(rdev);
  691. if (rdev->stollen_vga_memory) {
  692. r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
  693. if (r == 0) {
  694. radeon_bo_unpin(rdev->stollen_vga_memory);
  695. radeon_bo_unreserve(rdev->stollen_vga_memory);
  696. }
  697. radeon_bo_unref(&rdev->stollen_vga_memory);
  698. }
  699. ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
  700. ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
  701. ttm_bo_device_release(&rdev->mman.bdev);
  702. radeon_gart_fini(rdev);
  703. radeon_ttm_global_fini(rdev);
  704. rdev->mman.initialized = false;
  705. DRM_INFO("radeon: ttm finalized\n");
  706. }
  707. /* this should only be called at bootup or when userspace
  708. * isn't running */
  709. void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
  710. {
  711. struct ttm_mem_type_manager *man;
  712. if (!rdev->mman.initialized)
  713. return;
  714. man = &rdev->mman.bdev.man[TTM_PL_VRAM];
  715. /* this just adjusts TTM size idea, which sets lpfn to the correct value */
  716. man->size = size >> PAGE_SHIFT;
  717. }
  718. static struct vm_operations_struct radeon_ttm_vm_ops;
  719. static const struct vm_operations_struct *ttm_vm_ops = NULL;
  720. static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
  721. {
  722. struct ttm_buffer_object *bo;
  723. struct radeon_device *rdev;
  724. int r;
  725. bo = (struct ttm_buffer_object *)vma->vm_private_data;
  726. if (bo == NULL) {
  727. return VM_FAULT_NOPAGE;
  728. }
  729. rdev = radeon_get_rdev(bo->bdev);
  730. down_read(&rdev->pm.mclk_lock);
  731. r = ttm_vm_ops->fault(vma, vmf);
  732. up_read(&rdev->pm.mclk_lock);
  733. return r;
  734. }
  735. int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
  736. {
  737. struct drm_file *file_priv;
  738. struct radeon_device *rdev;
  739. int r;
  740. if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
  741. return drm_mmap(filp, vma);
  742. }
  743. file_priv = filp->private_data;
  744. rdev = file_priv->minor->dev->dev_private;
  745. if (rdev == NULL) {
  746. return -EINVAL;
  747. }
  748. r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
  749. if (unlikely(r != 0)) {
  750. return r;
  751. }
  752. if (unlikely(ttm_vm_ops == NULL)) {
  753. ttm_vm_ops = vma->vm_ops;
  754. radeon_ttm_vm_ops = *ttm_vm_ops;
  755. radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
  756. }
  757. vma->vm_ops = &radeon_ttm_vm_ops;
  758. return 0;
  759. }
  760. #if defined(CONFIG_DEBUG_FS)
  761. static int radeon_mm_dump_table(struct seq_file *m, void *data)
  762. {
  763. struct drm_info_node *node = (struct drm_info_node *)m->private;
  764. unsigned ttm_pl = *(int *)node->info_ent->data;
  765. struct drm_device *dev = node->minor->dev;
  766. struct radeon_device *rdev = dev->dev_private;
  767. struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
  768. int ret;
  769. struct ttm_bo_global *glob = rdev->mman.bdev.glob;
  770. spin_lock(&glob->lru_lock);
  771. ret = drm_mm_dump_table(m, mm);
  772. spin_unlock(&glob->lru_lock);
  773. return ret;
  774. }
  775. static int ttm_pl_vram = TTM_PL_VRAM;
  776. static int ttm_pl_tt = TTM_PL_TT;
  777. static struct drm_info_list radeon_ttm_debugfs_list[] = {
  778. {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
  779. {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
  780. {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
  781. #ifdef CONFIG_SWIOTLB
  782. {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
  783. #endif
  784. };
  785. static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
  786. {
  787. struct radeon_device *rdev = inode->i_private;
  788. i_size_write(inode, rdev->mc.mc_vram_size);
  789. filep->private_data = inode->i_private;
  790. return 0;
  791. }
  792. static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
  793. size_t size, loff_t *pos)
  794. {
  795. struct radeon_device *rdev = f->private_data;
  796. ssize_t result = 0;
  797. int r;
  798. if (size & 0x3 || *pos & 0x3)
  799. return -EINVAL;
  800. while (size) {
  801. unsigned long flags;
  802. uint32_t value;
  803. if (*pos >= rdev->mc.mc_vram_size)
  804. return result;
  805. spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
  806. WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
  807. if (rdev->family >= CHIP_CEDAR)
  808. WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
  809. value = RREG32(RADEON_MM_DATA);
  810. spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
  811. r = put_user(value, (uint32_t *)buf);
  812. if (r)
  813. return r;
  814. result += 4;
  815. buf += 4;
  816. *pos += 4;
  817. size -= 4;
  818. }
  819. return result;
  820. }
  821. static const struct file_operations radeon_ttm_vram_fops = {
  822. .owner = THIS_MODULE,
  823. .open = radeon_ttm_vram_open,
  824. .read = radeon_ttm_vram_read,
  825. .llseek = default_llseek
  826. };
  827. static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
  828. {
  829. struct radeon_device *rdev = inode->i_private;
  830. i_size_write(inode, rdev->mc.gtt_size);
  831. filep->private_data = inode->i_private;
  832. return 0;
  833. }
  834. static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
  835. size_t size, loff_t *pos)
  836. {
  837. struct radeon_device *rdev = f->private_data;
  838. ssize_t result = 0;
  839. int r;
  840. while (size) {
  841. loff_t p = *pos / PAGE_SIZE;
  842. unsigned off = *pos & ~PAGE_MASK;
  843. size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
  844. struct page *page;
  845. void *ptr;
  846. if (p >= rdev->gart.num_cpu_pages)
  847. return result;
  848. page = rdev->gart.pages[p];
  849. if (page) {
  850. ptr = kmap(page);
  851. ptr += off;
  852. r = copy_to_user(buf, ptr, cur_size);
  853. kunmap(rdev->gart.pages[p]);
  854. } else
  855. r = clear_user(buf, cur_size);
  856. if (r)
  857. return -EFAULT;
  858. result += cur_size;
  859. buf += cur_size;
  860. *pos += cur_size;
  861. size -= cur_size;
  862. }
  863. return result;
  864. }
  865. static const struct file_operations radeon_ttm_gtt_fops = {
  866. .owner = THIS_MODULE,
  867. .open = radeon_ttm_gtt_open,
  868. .read = radeon_ttm_gtt_read,
  869. .llseek = default_llseek
  870. };
  871. #endif
  872. static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
  873. {
  874. #if defined(CONFIG_DEBUG_FS)
  875. unsigned count;
  876. struct drm_minor *minor = rdev->ddev->primary;
  877. struct dentry *ent, *root = minor->debugfs_root;
  878. ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
  879. rdev, &radeon_ttm_vram_fops);
  880. if (IS_ERR(ent))
  881. return PTR_ERR(ent);
  882. rdev->mman.vram = ent;
  883. ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
  884. rdev, &radeon_ttm_gtt_fops);
  885. if (IS_ERR(ent))
  886. return PTR_ERR(ent);
  887. rdev->mman.gtt = ent;
  888. count = ARRAY_SIZE(radeon_ttm_debugfs_list);
  889. #ifdef CONFIG_SWIOTLB
  890. if (!swiotlb_nr_tbl())
  891. --count;
  892. #endif
  893. return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
  894. #else
  895. return 0;
  896. #endif
  897. }
  898. static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
  899. {
  900. #if defined(CONFIG_DEBUG_FS)
  901. debugfs_remove(rdev->mman.vram);
  902. rdev->mman.vram = NULL;
  903. debugfs_remove(rdev->mman.gtt);
  904. rdev->mman.gtt = NULL;
  905. #endif
  906. }