radeon_gart.c 11 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <drm/drmP.h>
  29. #include <drm/radeon_drm.h>
  30. #include "radeon.h"
  31. /*
  32. * GART
  33. * The GART (Graphics Aperture Remapping Table) is an aperture
  34. * in the GPU's address space. System pages can be mapped into
  35. * the aperture and look like contiguous pages from the GPU's
  36. * perspective. A page table maps the pages in the aperture
  37. * to the actual backing pages in system memory.
  38. *
  39. * Radeon GPUs support both an internal GART, as described above,
  40. * and AGP. AGP works similarly, but the GART table is configured
  41. * and maintained by the northbridge rather than the driver.
  42. * Radeon hw has a separate AGP aperture that is programmed to
  43. * point to the AGP aperture provided by the northbridge and the
  44. * requests are passed through to the northbridge aperture.
  45. * Both AGP and internal GART can be used at the same time, however
  46. * that is not currently supported by the driver.
  47. *
  48. * This file handles the common internal GART management.
  49. */
  50. /*
  51. * Common GART table functions.
  52. */
  53. /**
  54. * radeon_gart_table_ram_alloc - allocate system ram for gart page table
  55. *
  56. * @rdev: radeon_device pointer
  57. *
  58. * Allocate system memory for GART page table
  59. * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
  60. * gart table to be in system memory.
  61. * Returns 0 for success, -ENOMEM for failure.
  62. */
  63. int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
  64. {
  65. void *ptr;
  66. ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
  67. &rdev->gart.table_addr);
  68. if (ptr == NULL) {
  69. return -ENOMEM;
  70. }
  71. #ifdef CONFIG_X86
  72. if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
  73. rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  74. set_memory_uc((unsigned long)ptr,
  75. rdev->gart.table_size >> PAGE_SHIFT);
  76. }
  77. #endif
  78. rdev->gart.ptr = ptr;
  79. memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size);
  80. return 0;
  81. }
  82. /**
  83. * radeon_gart_table_ram_free - free system ram for gart page table
  84. *
  85. * @rdev: radeon_device pointer
  86. *
  87. * Free system memory for GART page table
  88. * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
  89. * gart table to be in system memory.
  90. */
  91. void radeon_gart_table_ram_free(struct radeon_device *rdev)
  92. {
  93. if (rdev->gart.ptr == NULL) {
  94. return;
  95. }
  96. #ifdef CONFIG_X86
  97. if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
  98. rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  99. set_memory_wb((unsigned long)rdev->gart.ptr,
  100. rdev->gart.table_size >> PAGE_SHIFT);
  101. }
  102. #endif
  103. pci_free_consistent(rdev->pdev, rdev->gart.table_size,
  104. (void *)rdev->gart.ptr,
  105. rdev->gart.table_addr);
  106. rdev->gart.ptr = NULL;
  107. rdev->gart.table_addr = 0;
  108. }
  109. /**
  110. * radeon_gart_table_vram_alloc - allocate vram for gart page table
  111. *
  112. * @rdev: radeon_device pointer
  113. *
  114. * Allocate video memory for GART page table
  115. * (pcie r4xx, r5xx+). These asics require the
  116. * gart table to be in video memory.
  117. * Returns 0 for success, error for failure.
  118. */
  119. int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
  120. {
  121. int r;
  122. if (rdev->gart.robj == NULL) {
  123. r = radeon_bo_create(rdev, rdev->gart.table_size,
  124. PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
  125. NULL, &rdev->gart.robj);
  126. if (r) {
  127. return r;
  128. }
  129. }
  130. return 0;
  131. }
  132. /**
  133. * radeon_gart_table_vram_pin - pin gart page table in vram
  134. *
  135. * @rdev: radeon_device pointer
  136. *
  137. * Pin the GART page table in vram so it will not be moved
  138. * by the memory manager (pcie r4xx, r5xx+). These asics require the
  139. * gart table to be in video memory.
  140. * Returns 0 for success, error for failure.
  141. */
  142. int radeon_gart_table_vram_pin(struct radeon_device *rdev)
  143. {
  144. uint64_t gpu_addr;
  145. int r;
  146. r = radeon_bo_reserve(rdev->gart.robj, false);
  147. if (unlikely(r != 0))
  148. return r;
  149. r = radeon_bo_pin(rdev->gart.robj,
  150. RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
  151. if (r) {
  152. radeon_bo_unreserve(rdev->gart.robj);
  153. return r;
  154. }
  155. r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr);
  156. if (r)
  157. radeon_bo_unpin(rdev->gart.robj);
  158. radeon_bo_unreserve(rdev->gart.robj);
  159. rdev->gart.table_addr = gpu_addr;
  160. return r;
  161. }
  162. /**
  163. * radeon_gart_table_vram_unpin - unpin gart page table in vram
  164. *
  165. * @rdev: radeon_device pointer
  166. *
  167. * Unpin the GART page table in vram (pcie r4xx, r5xx+).
  168. * These asics require the gart table to be in video memory.
  169. */
  170. void radeon_gart_table_vram_unpin(struct radeon_device *rdev)
  171. {
  172. int r;
  173. if (rdev->gart.robj == NULL) {
  174. return;
  175. }
  176. r = radeon_bo_reserve(rdev->gart.robj, false);
  177. if (likely(r == 0)) {
  178. radeon_bo_kunmap(rdev->gart.robj);
  179. radeon_bo_unpin(rdev->gart.robj);
  180. radeon_bo_unreserve(rdev->gart.robj);
  181. rdev->gart.ptr = NULL;
  182. }
  183. }
  184. /**
  185. * radeon_gart_table_vram_free - free gart page table vram
  186. *
  187. * @rdev: radeon_device pointer
  188. *
  189. * Free the video memory used for the GART page table
  190. * (pcie r4xx, r5xx+). These asics require the gart table to
  191. * be in video memory.
  192. */
  193. void radeon_gart_table_vram_free(struct radeon_device *rdev)
  194. {
  195. if (rdev->gart.robj == NULL) {
  196. return;
  197. }
  198. radeon_bo_unref(&rdev->gart.robj);
  199. }
  200. /*
  201. * Common gart functions.
  202. */
  203. /**
  204. * radeon_gart_unbind - unbind pages from the gart page table
  205. *
  206. * @rdev: radeon_device pointer
  207. * @offset: offset into the GPU's gart aperture
  208. * @pages: number of pages to unbind
  209. *
  210. * Unbinds the requested pages from the gart page table and
  211. * replaces them with the dummy page (all asics).
  212. */
  213. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  214. int pages)
  215. {
  216. unsigned t;
  217. unsigned p;
  218. int i, j;
  219. u64 page_base;
  220. if (!rdev->gart.ready) {
  221. WARN(1, "trying to unbind memory from uninitialized GART !\n");
  222. return;
  223. }
  224. t = offset / RADEON_GPU_PAGE_SIZE;
  225. p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
  226. for (i = 0; i < pages; i++, p++) {
  227. if (rdev->gart.pages[p]) {
  228. rdev->gart.pages[p] = NULL;
  229. rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
  230. page_base = rdev->gart.pages_addr[p];
  231. for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
  232. if (rdev->gart.ptr) {
  233. radeon_gart_set_page(rdev, t, page_base);
  234. }
  235. page_base += RADEON_GPU_PAGE_SIZE;
  236. }
  237. }
  238. }
  239. mb();
  240. radeon_gart_tlb_flush(rdev);
  241. }
  242. /**
  243. * radeon_gart_bind - bind pages into the gart page table
  244. *
  245. * @rdev: radeon_device pointer
  246. * @offset: offset into the GPU's gart aperture
  247. * @pages: number of pages to bind
  248. * @pagelist: pages to bind
  249. * @dma_addr: DMA addresses of pages
  250. *
  251. * Binds the requested pages to the gart page table
  252. * (all asics).
  253. * Returns 0 for success, -EINVAL for failure.
  254. */
  255. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  256. int pages, struct page **pagelist, dma_addr_t *dma_addr)
  257. {
  258. unsigned t;
  259. unsigned p;
  260. uint64_t page_base;
  261. int i, j;
  262. if (!rdev->gart.ready) {
  263. WARN(1, "trying to bind memory to uninitialized GART !\n");
  264. return -EINVAL;
  265. }
  266. t = offset / RADEON_GPU_PAGE_SIZE;
  267. p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
  268. for (i = 0; i < pages; i++, p++) {
  269. rdev->gart.pages_addr[p] = dma_addr[i];
  270. rdev->gart.pages[p] = pagelist[i];
  271. if (rdev->gart.ptr) {
  272. page_base = rdev->gart.pages_addr[p];
  273. for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
  274. radeon_gart_set_page(rdev, t, page_base);
  275. page_base += RADEON_GPU_PAGE_SIZE;
  276. }
  277. }
  278. }
  279. mb();
  280. radeon_gart_tlb_flush(rdev);
  281. return 0;
  282. }
  283. /**
  284. * radeon_gart_restore - bind all pages in the gart page table
  285. *
  286. * @rdev: radeon_device pointer
  287. *
  288. * Binds all pages in the gart page table (all asics).
  289. * Used to rebuild the gart table on device startup or resume.
  290. */
  291. void radeon_gart_restore(struct radeon_device *rdev)
  292. {
  293. int i, j, t;
  294. u64 page_base;
  295. if (!rdev->gart.ptr) {
  296. return;
  297. }
  298. for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) {
  299. page_base = rdev->gart.pages_addr[i];
  300. for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
  301. radeon_gart_set_page(rdev, t, page_base);
  302. page_base += RADEON_GPU_PAGE_SIZE;
  303. }
  304. }
  305. mb();
  306. radeon_gart_tlb_flush(rdev);
  307. }
  308. /**
  309. * radeon_gart_init - init the driver info for managing the gart
  310. *
  311. * @rdev: radeon_device pointer
  312. *
  313. * Allocate the dummy page and init the gart driver info (all asics).
  314. * Returns 0 for success, error for failure.
  315. */
  316. int radeon_gart_init(struct radeon_device *rdev)
  317. {
  318. int r, i;
  319. if (rdev->gart.pages) {
  320. return 0;
  321. }
  322. /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
  323. if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
  324. DRM_ERROR("Page size is smaller than GPU page size!\n");
  325. return -EINVAL;
  326. }
  327. r = radeon_dummy_page_init(rdev);
  328. if (r)
  329. return r;
  330. /* Compute table size */
  331. rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
  332. rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
  333. DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
  334. rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
  335. /* Allocate pages table */
  336. rdev->gart.pages = vzalloc(sizeof(void *) * rdev->gart.num_cpu_pages);
  337. if (rdev->gart.pages == NULL) {
  338. radeon_gart_fini(rdev);
  339. return -ENOMEM;
  340. }
  341. rdev->gart.pages_addr = vzalloc(sizeof(dma_addr_t) *
  342. rdev->gart.num_cpu_pages);
  343. if (rdev->gart.pages_addr == NULL) {
  344. radeon_gart_fini(rdev);
  345. return -ENOMEM;
  346. }
  347. /* set GART entry to point to the dummy page by default */
  348. for (i = 0; i < rdev->gart.num_cpu_pages; i++) {
  349. rdev->gart.pages_addr[i] = rdev->dummy_page.addr;
  350. }
  351. return 0;
  352. }
  353. /**
  354. * radeon_gart_fini - tear down the driver info for managing the gart
  355. *
  356. * @rdev: radeon_device pointer
  357. *
  358. * Tear down the gart driver info and free the dummy page (all asics).
  359. */
  360. void radeon_gart_fini(struct radeon_device *rdev)
  361. {
  362. if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) {
  363. /* unbind pages */
  364. radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
  365. }
  366. rdev->gart.ready = false;
  367. vfree(rdev->gart.pages);
  368. vfree(rdev->gart.pages_addr);
  369. rdev->gart.pages = NULL;
  370. rdev->gart.pages_addr = NULL;
  371. radeon_dummy_page_fini(rdev);
  372. }