radeon_asic.h 41 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #ifndef __RADEON_ASIC_H__
  29. #define __RADEON_ASIC_H__
  30. /*
  31. * common functions
  32. */
  33. uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
  34. void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  35. uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
  36. void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  37. uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
  38. void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  39. uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
  40. void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
  41. void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  42. void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
  43. u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
  44. void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
  45. u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
  46. /*
  47. * r100,rv100,rs100,rv200,rs200
  48. */
  49. struct r100_mc_save {
  50. u32 GENMO_WT;
  51. u32 CRTC_EXT_CNTL;
  52. u32 CRTC_GEN_CNTL;
  53. u32 CRTC2_GEN_CNTL;
  54. u32 CUR_OFFSET;
  55. u32 CUR2_OFFSET;
  56. };
  57. int r100_init(struct radeon_device *rdev);
  58. void r100_fini(struct radeon_device *rdev);
  59. int r100_suspend(struct radeon_device *rdev);
  60. int r100_resume(struct radeon_device *rdev);
  61. void r100_vga_set_state(struct radeon_device *rdev, bool state);
  62. bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  63. int r100_asic_reset(struct radeon_device *rdev);
  64. u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
  65. void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  66. void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
  67. uint64_t addr);
  68. void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
  69. int r100_irq_set(struct radeon_device *rdev);
  70. int r100_irq_process(struct radeon_device *rdev);
  71. void r100_fence_ring_emit(struct radeon_device *rdev,
  72. struct radeon_fence *fence);
  73. bool r100_semaphore_ring_emit(struct radeon_device *rdev,
  74. struct radeon_ring *cp,
  75. struct radeon_semaphore *semaphore,
  76. bool emit_wait);
  77. int r100_cs_parse(struct radeon_cs_parser *p);
  78. void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  79. uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
  80. int r100_copy_blit(struct radeon_device *rdev,
  81. uint64_t src_offset,
  82. uint64_t dst_offset,
  83. unsigned num_gpu_pages,
  84. struct radeon_fence **fence);
  85. int r100_set_surface_reg(struct radeon_device *rdev, int reg,
  86. uint32_t tiling_flags, uint32_t pitch,
  87. uint32_t offset, uint32_t obj_size);
  88. void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
  89. void r100_bandwidth_update(struct radeon_device *rdev);
  90. void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  91. int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
  92. void r100_hpd_init(struct radeon_device *rdev);
  93. void r100_hpd_fini(struct radeon_device *rdev);
  94. bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  95. void r100_hpd_set_polarity(struct radeon_device *rdev,
  96. enum radeon_hpd_id hpd);
  97. int r100_debugfs_rbbm_init(struct radeon_device *rdev);
  98. int r100_debugfs_cp_init(struct radeon_device *rdev);
  99. void r100_cp_disable(struct radeon_device *rdev);
  100. int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  101. void r100_cp_fini(struct radeon_device *rdev);
  102. int r100_pci_gart_init(struct radeon_device *rdev);
  103. void r100_pci_gart_fini(struct radeon_device *rdev);
  104. int r100_pci_gart_enable(struct radeon_device *rdev);
  105. void r100_pci_gart_disable(struct radeon_device *rdev);
  106. int r100_debugfs_mc_info_init(struct radeon_device *rdev);
  107. int r100_gui_wait_for_idle(struct radeon_device *rdev);
  108. int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
  109. void r100_irq_disable(struct radeon_device *rdev);
  110. void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
  111. void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
  112. void r100_vram_init_sizes(struct radeon_device *rdev);
  113. int r100_cp_reset(struct radeon_device *rdev);
  114. void r100_vga_render_disable(struct radeon_device *rdev);
  115. void r100_restore_sanity(struct radeon_device *rdev);
  116. int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  117. struct radeon_cs_packet *pkt,
  118. struct radeon_bo *robj);
  119. int r100_cs_parse_packet0(struct radeon_cs_parser *p,
  120. struct radeon_cs_packet *pkt,
  121. const unsigned *auth, unsigned n,
  122. radeon_packet0_check_t check);
  123. int r100_cs_packet_parse(struct radeon_cs_parser *p,
  124. struct radeon_cs_packet *pkt,
  125. unsigned idx);
  126. void r100_enable_bm(struct radeon_device *rdev);
  127. void r100_set_common_regs(struct radeon_device *rdev);
  128. void r100_bm_disable(struct radeon_device *rdev);
  129. extern bool r100_gui_idle(struct radeon_device *rdev);
  130. extern void r100_pm_misc(struct radeon_device *rdev);
  131. extern void r100_pm_prepare(struct radeon_device *rdev);
  132. extern void r100_pm_finish(struct radeon_device *rdev);
  133. extern void r100_pm_init_profile(struct radeon_device *rdev);
  134. extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
  135. extern void r100_page_flip(struct radeon_device *rdev, int crtc,
  136. u64 crtc_base);
  137. extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc);
  138. extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
  139. extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
  140. u32 r100_gfx_get_rptr(struct radeon_device *rdev,
  141. struct radeon_ring *ring);
  142. u32 r100_gfx_get_wptr(struct radeon_device *rdev,
  143. struct radeon_ring *ring);
  144. void r100_gfx_set_wptr(struct radeon_device *rdev,
  145. struct radeon_ring *ring);
  146. /*
  147. * r200,rv250,rs300,rv280
  148. */
  149. extern int r200_copy_dma(struct radeon_device *rdev,
  150. uint64_t src_offset,
  151. uint64_t dst_offset,
  152. unsigned num_gpu_pages,
  153. struct radeon_fence **fence);
  154. void r200_set_safe_registers(struct radeon_device *rdev);
  155. /*
  156. * r300,r350,rv350,rv380
  157. */
  158. extern int r300_init(struct radeon_device *rdev);
  159. extern void r300_fini(struct radeon_device *rdev);
  160. extern int r300_suspend(struct radeon_device *rdev);
  161. extern int r300_resume(struct radeon_device *rdev);
  162. extern int r300_asic_reset(struct radeon_device *rdev);
  163. extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
  164. extern void r300_fence_ring_emit(struct radeon_device *rdev,
  165. struct radeon_fence *fence);
  166. extern int r300_cs_parse(struct radeon_cs_parser *p);
  167. extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
  168. extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
  169. uint64_t addr);
  170. extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
  171. extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
  172. extern void r300_set_reg_safe(struct radeon_device *rdev);
  173. extern void r300_mc_program(struct radeon_device *rdev);
  174. extern void r300_mc_init(struct radeon_device *rdev);
  175. extern void r300_clock_startup(struct radeon_device *rdev);
  176. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
  177. extern int rv370_pcie_gart_init(struct radeon_device *rdev);
  178. extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
  179. extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
  180. extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
  181. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
  182. /*
  183. * r420,r423,rv410
  184. */
  185. extern int r420_init(struct radeon_device *rdev);
  186. extern void r420_fini(struct radeon_device *rdev);
  187. extern int r420_suspend(struct radeon_device *rdev);
  188. extern int r420_resume(struct radeon_device *rdev);
  189. extern void r420_pm_init_profile(struct radeon_device *rdev);
  190. extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
  191. extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
  192. extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
  193. extern void r420_pipes_init(struct radeon_device *rdev);
  194. /*
  195. * rs400,rs480
  196. */
  197. extern int rs400_init(struct radeon_device *rdev);
  198. extern void rs400_fini(struct radeon_device *rdev);
  199. extern int rs400_suspend(struct radeon_device *rdev);
  200. extern int rs400_resume(struct radeon_device *rdev);
  201. void rs400_gart_tlb_flush(struct radeon_device *rdev);
  202. void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
  203. uint64_t addr);
  204. uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
  205. void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  206. int rs400_gart_init(struct radeon_device *rdev);
  207. int rs400_gart_enable(struct radeon_device *rdev);
  208. void rs400_gart_adjust_size(struct radeon_device *rdev);
  209. void rs400_gart_disable(struct radeon_device *rdev);
  210. void rs400_gart_fini(struct radeon_device *rdev);
  211. extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
  212. /*
  213. * rs600.
  214. */
  215. extern int rs600_asic_reset(struct radeon_device *rdev);
  216. extern int rs600_init(struct radeon_device *rdev);
  217. extern void rs600_fini(struct radeon_device *rdev);
  218. extern int rs600_suspend(struct radeon_device *rdev);
  219. extern int rs600_resume(struct radeon_device *rdev);
  220. int rs600_irq_set(struct radeon_device *rdev);
  221. int rs600_irq_process(struct radeon_device *rdev);
  222. void rs600_irq_disable(struct radeon_device *rdev);
  223. u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
  224. void rs600_gart_tlb_flush(struct radeon_device *rdev);
  225. void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
  226. uint64_t addr);
  227. uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
  228. void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  229. void rs600_bandwidth_update(struct radeon_device *rdev);
  230. void rs600_hpd_init(struct radeon_device *rdev);
  231. void rs600_hpd_fini(struct radeon_device *rdev);
  232. bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  233. void rs600_hpd_set_polarity(struct radeon_device *rdev,
  234. enum radeon_hpd_id hpd);
  235. extern void rs600_pm_misc(struct radeon_device *rdev);
  236. extern void rs600_pm_prepare(struct radeon_device *rdev);
  237. extern void rs600_pm_finish(struct radeon_device *rdev);
  238. extern void rs600_page_flip(struct radeon_device *rdev, int crtc,
  239. u64 crtc_base);
  240. extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc);
  241. void rs600_set_safe_registers(struct radeon_device *rdev);
  242. extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
  243. extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  244. /*
  245. * rs690,rs740
  246. */
  247. int rs690_init(struct radeon_device *rdev);
  248. void rs690_fini(struct radeon_device *rdev);
  249. int rs690_resume(struct radeon_device *rdev);
  250. int rs690_suspend(struct radeon_device *rdev);
  251. uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
  252. void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  253. void rs690_bandwidth_update(struct radeon_device *rdev);
  254. void rs690_line_buffer_adjust(struct radeon_device *rdev,
  255. struct drm_display_mode *mode1,
  256. struct drm_display_mode *mode2);
  257. extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
  258. /*
  259. * rv515
  260. */
  261. struct rv515_mc_save {
  262. u32 vga_render_control;
  263. u32 vga_hdp_control;
  264. bool crtc_enabled[2];
  265. };
  266. int rv515_init(struct radeon_device *rdev);
  267. void rv515_fini(struct radeon_device *rdev);
  268. uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
  269. void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  270. void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
  271. void rv515_bandwidth_update(struct radeon_device *rdev);
  272. int rv515_resume(struct radeon_device *rdev);
  273. int rv515_suspend(struct radeon_device *rdev);
  274. void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
  275. void rv515_vga_render_disable(struct radeon_device *rdev);
  276. void rv515_set_safe_registers(struct radeon_device *rdev);
  277. void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
  278. void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
  279. void rv515_clock_startup(struct radeon_device *rdev);
  280. void rv515_debugfs(struct radeon_device *rdev);
  281. int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  282. /*
  283. * r520,rv530,rv560,rv570,r580
  284. */
  285. int r520_init(struct radeon_device *rdev);
  286. int r520_resume(struct radeon_device *rdev);
  287. int r520_mc_wait_for_idle(struct radeon_device *rdev);
  288. /*
  289. * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
  290. */
  291. int r600_init(struct radeon_device *rdev);
  292. void r600_fini(struct radeon_device *rdev);
  293. int r600_suspend(struct radeon_device *rdev);
  294. int r600_resume(struct radeon_device *rdev);
  295. void r600_vga_set_state(struct radeon_device *rdev, bool state);
  296. int r600_wb_init(struct radeon_device *rdev);
  297. void r600_wb_fini(struct radeon_device *rdev);
  298. void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
  299. uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
  300. void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  301. int r600_cs_parse(struct radeon_cs_parser *p);
  302. int r600_dma_cs_parse(struct radeon_cs_parser *p);
  303. void r600_fence_ring_emit(struct radeon_device *rdev,
  304. struct radeon_fence *fence);
  305. bool r600_semaphore_ring_emit(struct radeon_device *rdev,
  306. struct radeon_ring *cp,
  307. struct radeon_semaphore *semaphore,
  308. bool emit_wait);
  309. void r600_dma_fence_ring_emit(struct radeon_device *rdev,
  310. struct radeon_fence *fence);
  311. bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
  312. struct radeon_ring *ring,
  313. struct radeon_semaphore *semaphore,
  314. bool emit_wait);
  315. void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  316. bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
  317. bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  318. int r600_asic_reset(struct radeon_device *rdev);
  319. int r600_set_surface_reg(struct radeon_device *rdev, int reg,
  320. uint32_t tiling_flags, uint32_t pitch,
  321. uint32_t offset, uint32_t obj_size);
  322. void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
  323. int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
  324. int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
  325. void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  326. int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
  327. int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
  328. int r600_copy_cpdma(struct radeon_device *rdev,
  329. uint64_t src_offset, uint64_t dst_offset,
  330. unsigned num_gpu_pages, struct radeon_fence **fence);
  331. int r600_copy_dma(struct radeon_device *rdev,
  332. uint64_t src_offset, uint64_t dst_offset,
  333. unsigned num_gpu_pages, struct radeon_fence **fence);
  334. void r600_hpd_init(struct radeon_device *rdev);
  335. void r600_hpd_fini(struct radeon_device *rdev);
  336. bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  337. void r600_hpd_set_polarity(struct radeon_device *rdev,
  338. enum radeon_hpd_id hpd);
  339. extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
  340. extern bool r600_gui_idle(struct radeon_device *rdev);
  341. extern void r600_pm_misc(struct radeon_device *rdev);
  342. extern void r600_pm_init_profile(struct radeon_device *rdev);
  343. extern void rs780_pm_init_profile(struct radeon_device *rdev);
  344. extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
  345. extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  346. extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
  347. extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
  348. extern int r600_get_pcie_lanes(struct radeon_device *rdev);
  349. bool r600_card_posted(struct radeon_device *rdev);
  350. void r600_cp_stop(struct radeon_device *rdev);
  351. int r600_cp_start(struct radeon_device *rdev);
  352. void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
  353. int r600_cp_resume(struct radeon_device *rdev);
  354. void r600_cp_fini(struct radeon_device *rdev);
  355. int r600_count_pipe_bits(uint32_t val);
  356. int r600_mc_wait_for_idle(struct radeon_device *rdev);
  357. int r600_pcie_gart_init(struct radeon_device *rdev);
  358. void r600_scratch_init(struct radeon_device *rdev);
  359. int r600_init_microcode(struct radeon_device *rdev);
  360. u32 r600_gfx_get_rptr(struct radeon_device *rdev,
  361. struct radeon_ring *ring);
  362. u32 r600_gfx_get_wptr(struct radeon_device *rdev,
  363. struct radeon_ring *ring);
  364. void r600_gfx_set_wptr(struct radeon_device *rdev,
  365. struct radeon_ring *ring);
  366. /* r600 irq */
  367. int r600_irq_process(struct radeon_device *rdev);
  368. int r600_irq_init(struct radeon_device *rdev);
  369. void r600_irq_fini(struct radeon_device *rdev);
  370. void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
  371. int r600_irq_set(struct radeon_device *rdev);
  372. void r600_irq_suspend(struct radeon_device *rdev);
  373. void r600_disable_interrupts(struct radeon_device *rdev);
  374. void r600_rlc_stop(struct radeon_device *rdev);
  375. /* r600 audio */
  376. int r600_audio_init(struct radeon_device *rdev);
  377. struct r600_audio_pin r600_audio_status(struct radeon_device *rdev);
  378. void r600_audio_fini(struct radeon_device *rdev);
  379. void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);
  380. void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
  381. size_t size);
  382. void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock);
  383. void r600_hdmi_audio_workaround(struct drm_encoder *encoder);
  384. int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
  385. void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
  386. void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
  387. void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  388. int r600_mc_wait_for_idle(struct radeon_device *rdev);
  389. u32 r600_get_xclk(struct radeon_device *rdev);
  390. uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
  391. int rv6xx_get_temp(struct radeon_device *rdev);
  392. int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  393. int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
  394. void r600_dpm_post_set_power_state(struct radeon_device *rdev);
  395. int r600_dpm_late_enable(struct radeon_device *rdev);
  396. /* r600 dma */
  397. uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
  398. struct radeon_ring *ring);
  399. uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
  400. struct radeon_ring *ring);
  401. void r600_dma_set_wptr(struct radeon_device *rdev,
  402. struct radeon_ring *ring);
  403. /* rv6xx dpm */
  404. int rv6xx_dpm_init(struct radeon_device *rdev);
  405. int rv6xx_dpm_enable(struct radeon_device *rdev);
  406. void rv6xx_dpm_disable(struct radeon_device *rdev);
  407. int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
  408. void rv6xx_setup_asic(struct radeon_device *rdev);
  409. void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
  410. void rv6xx_dpm_fini(struct radeon_device *rdev);
  411. u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
  412. u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
  413. void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
  414. struct radeon_ps *ps);
  415. void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  416. struct seq_file *m);
  417. int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
  418. enum radeon_dpm_forced_level level);
  419. /* rs780 dpm */
  420. int rs780_dpm_init(struct radeon_device *rdev);
  421. int rs780_dpm_enable(struct radeon_device *rdev);
  422. void rs780_dpm_disable(struct radeon_device *rdev);
  423. int rs780_dpm_set_power_state(struct radeon_device *rdev);
  424. void rs780_dpm_setup_asic(struct radeon_device *rdev);
  425. void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
  426. void rs780_dpm_fini(struct radeon_device *rdev);
  427. u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
  428. u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
  429. void rs780_dpm_print_power_state(struct radeon_device *rdev,
  430. struct radeon_ps *ps);
  431. void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  432. struct seq_file *m);
  433. int rs780_dpm_force_performance_level(struct radeon_device *rdev,
  434. enum radeon_dpm_forced_level level);
  435. /*
  436. * rv770,rv730,rv710,rv740
  437. */
  438. int rv770_init(struct radeon_device *rdev);
  439. void rv770_fini(struct radeon_device *rdev);
  440. int rv770_suspend(struct radeon_device *rdev);
  441. int rv770_resume(struct radeon_device *rdev);
  442. void rv770_pm_misc(struct radeon_device *rdev);
  443. void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
  444. bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc);
  445. void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
  446. void r700_cp_stop(struct radeon_device *rdev);
  447. void r700_cp_fini(struct radeon_device *rdev);
  448. int rv770_copy_dma(struct radeon_device *rdev,
  449. uint64_t src_offset, uint64_t dst_offset,
  450. unsigned num_gpu_pages,
  451. struct radeon_fence **fence);
  452. u32 rv770_get_xclk(struct radeon_device *rdev);
  453. int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  454. int rv770_get_temp(struct radeon_device *rdev);
  455. /* hdmi */
  456. void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  457. /* rv7xx pm */
  458. int rv770_dpm_init(struct radeon_device *rdev);
  459. int rv770_dpm_enable(struct radeon_device *rdev);
  460. int rv770_dpm_late_enable(struct radeon_device *rdev);
  461. void rv770_dpm_disable(struct radeon_device *rdev);
  462. int rv770_dpm_set_power_state(struct radeon_device *rdev);
  463. void rv770_dpm_setup_asic(struct radeon_device *rdev);
  464. void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
  465. void rv770_dpm_fini(struct radeon_device *rdev);
  466. u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
  467. u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
  468. void rv770_dpm_print_power_state(struct radeon_device *rdev,
  469. struct radeon_ps *ps);
  470. void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  471. struct seq_file *m);
  472. int rv770_dpm_force_performance_level(struct radeon_device *rdev,
  473. enum radeon_dpm_forced_level level);
  474. bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
  475. /*
  476. * evergreen
  477. */
  478. struct evergreen_mc_save {
  479. u32 vga_render_control;
  480. u32 vga_hdp_control;
  481. bool crtc_enabled[RADEON_MAX_CRTCS];
  482. };
  483. void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
  484. int evergreen_init(struct radeon_device *rdev);
  485. void evergreen_fini(struct radeon_device *rdev);
  486. int evergreen_suspend(struct radeon_device *rdev);
  487. int evergreen_resume(struct radeon_device *rdev);
  488. bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  489. bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  490. int evergreen_asic_reset(struct radeon_device *rdev);
  491. void evergreen_bandwidth_update(struct radeon_device *rdev);
  492. void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  493. void evergreen_hpd_init(struct radeon_device *rdev);
  494. void evergreen_hpd_fini(struct radeon_device *rdev);
  495. bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  496. void evergreen_hpd_set_polarity(struct radeon_device *rdev,
  497. enum radeon_hpd_id hpd);
  498. u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
  499. int evergreen_irq_set(struct radeon_device *rdev);
  500. int evergreen_irq_process(struct radeon_device *rdev);
  501. extern int evergreen_cs_parse(struct radeon_cs_parser *p);
  502. extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
  503. extern void evergreen_pm_misc(struct radeon_device *rdev);
  504. extern void evergreen_pm_prepare(struct radeon_device *rdev);
  505. extern void evergreen_pm_finish(struct radeon_device *rdev);
  506. extern void sumo_pm_init_profile(struct radeon_device *rdev);
  507. extern void btc_pm_init_profile(struct radeon_device *rdev);
  508. int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  509. int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  510. extern void evergreen_page_flip(struct radeon_device *rdev, int crtc,
  511. u64 crtc_base);
  512. extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc);
  513. extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
  514. void evergreen_disable_interrupt_state(struct radeon_device *rdev);
  515. int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
  516. void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
  517. struct radeon_fence *fence);
  518. void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
  519. struct radeon_ib *ib);
  520. int evergreen_copy_dma(struct radeon_device *rdev,
  521. uint64_t src_offset, uint64_t dst_offset,
  522. unsigned num_gpu_pages,
  523. struct radeon_fence **fence);
  524. void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
  525. void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  526. int evergreen_get_temp(struct radeon_device *rdev);
  527. int sumo_get_temp(struct radeon_device *rdev);
  528. int tn_get_temp(struct radeon_device *rdev);
  529. int cypress_dpm_init(struct radeon_device *rdev);
  530. void cypress_dpm_setup_asic(struct radeon_device *rdev);
  531. int cypress_dpm_enable(struct radeon_device *rdev);
  532. void cypress_dpm_disable(struct radeon_device *rdev);
  533. int cypress_dpm_set_power_state(struct radeon_device *rdev);
  534. void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
  535. void cypress_dpm_fini(struct radeon_device *rdev);
  536. bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
  537. int btc_dpm_init(struct radeon_device *rdev);
  538. void btc_dpm_setup_asic(struct radeon_device *rdev);
  539. int btc_dpm_enable(struct radeon_device *rdev);
  540. void btc_dpm_disable(struct radeon_device *rdev);
  541. int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
  542. int btc_dpm_set_power_state(struct radeon_device *rdev);
  543. void btc_dpm_post_set_power_state(struct radeon_device *rdev);
  544. void btc_dpm_fini(struct radeon_device *rdev);
  545. u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
  546. u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
  547. bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
  548. void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  549. struct seq_file *m);
  550. int sumo_dpm_init(struct radeon_device *rdev);
  551. int sumo_dpm_enable(struct radeon_device *rdev);
  552. int sumo_dpm_late_enable(struct radeon_device *rdev);
  553. void sumo_dpm_disable(struct radeon_device *rdev);
  554. int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
  555. int sumo_dpm_set_power_state(struct radeon_device *rdev);
  556. void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
  557. void sumo_dpm_setup_asic(struct radeon_device *rdev);
  558. void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
  559. void sumo_dpm_fini(struct radeon_device *rdev);
  560. u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
  561. u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
  562. void sumo_dpm_print_power_state(struct radeon_device *rdev,
  563. struct radeon_ps *ps);
  564. void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  565. struct seq_file *m);
  566. int sumo_dpm_force_performance_level(struct radeon_device *rdev,
  567. enum radeon_dpm_forced_level level);
  568. /*
  569. * cayman
  570. */
  571. void cayman_fence_ring_emit(struct radeon_device *rdev,
  572. struct radeon_fence *fence);
  573. void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
  574. int cayman_init(struct radeon_device *rdev);
  575. void cayman_fini(struct radeon_device *rdev);
  576. int cayman_suspend(struct radeon_device *rdev);
  577. int cayman_resume(struct radeon_device *rdev);
  578. int cayman_asic_reset(struct radeon_device *rdev);
  579. void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  580. int cayman_vm_init(struct radeon_device *rdev);
  581. void cayman_vm_fini(struct radeon_device *rdev);
  582. void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
  583. uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
  584. int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
  585. int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
  586. void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
  587. struct radeon_ib *ib);
  588. bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
  589. bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
  590. void cayman_dma_vm_set_page(struct radeon_device *rdev,
  591. struct radeon_ib *ib,
  592. uint64_t pe,
  593. uint64_t addr, unsigned count,
  594. uint32_t incr, uint32_t flags);
  595. void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
  596. u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
  597. struct radeon_ring *ring);
  598. u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
  599. struct radeon_ring *ring);
  600. void cayman_gfx_set_wptr(struct radeon_device *rdev,
  601. struct radeon_ring *ring);
  602. uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
  603. struct radeon_ring *ring);
  604. uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
  605. struct radeon_ring *ring);
  606. void cayman_dma_set_wptr(struct radeon_device *rdev,
  607. struct radeon_ring *ring);
  608. int ni_dpm_init(struct radeon_device *rdev);
  609. void ni_dpm_setup_asic(struct radeon_device *rdev);
  610. int ni_dpm_enable(struct radeon_device *rdev);
  611. void ni_dpm_disable(struct radeon_device *rdev);
  612. int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
  613. int ni_dpm_set_power_state(struct radeon_device *rdev);
  614. void ni_dpm_post_set_power_state(struct radeon_device *rdev);
  615. void ni_dpm_fini(struct radeon_device *rdev);
  616. u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
  617. u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
  618. void ni_dpm_print_power_state(struct radeon_device *rdev,
  619. struct radeon_ps *ps);
  620. void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  621. struct seq_file *m);
  622. int ni_dpm_force_performance_level(struct radeon_device *rdev,
  623. enum radeon_dpm_forced_level level);
  624. bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
  625. int trinity_dpm_init(struct radeon_device *rdev);
  626. int trinity_dpm_enable(struct radeon_device *rdev);
  627. int trinity_dpm_late_enable(struct radeon_device *rdev);
  628. void trinity_dpm_disable(struct radeon_device *rdev);
  629. int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
  630. int trinity_dpm_set_power_state(struct radeon_device *rdev);
  631. void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
  632. void trinity_dpm_setup_asic(struct radeon_device *rdev);
  633. void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
  634. void trinity_dpm_fini(struct radeon_device *rdev);
  635. u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
  636. u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
  637. void trinity_dpm_print_power_state(struct radeon_device *rdev,
  638. struct radeon_ps *ps);
  639. void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  640. struct seq_file *m);
  641. int trinity_dpm_force_performance_level(struct radeon_device *rdev,
  642. enum radeon_dpm_forced_level level);
  643. void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
  644. /* DCE6 - SI */
  645. void dce6_bandwidth_update(struct radeon_device *rdev);
  646. int dce6_audio_init(struct radeon_device *rdev);
  647. void dce6_audio_fini(struct radeon_device *rdev);
  648. /*
  649. * si
  650. */
  651. void si_fence_ring_emit(struct radeon_device *rdev,
  652. struct radeon_fence *fence);
  653. void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
  654. int si_init(struct radeon_device *rdev);
  655. void si_fini(struct radeon_device *rdev);
  656. int si_suspend(struct radeon_device *rdev);
  657. int si_resume(struct radeon_device *rdev);
  658. bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  659. bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  660. int si_asic_reset(struct radeon_device *rdev);
  661. void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  662. int si_irq_set(struct radeon_device *rdev);
  663. int si_irq_process(struct radeon_device *rdev);
  664. int si_vm_init(struct radeon_device *rdev);
  665. void si_vm_fini(struct radeon_device *rdev);
  666. void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
  667. int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
  668. int si_copy_dma(struct radeon_device *rdev,
  669. uint64_t src_offset, uint64_t dst_offset,
  670. unsigned num_gpu_pages,
  671. struct radeon_fence **fence);
  672. void si_dma_vm_set_page(struct radeon_device *rdev,
  673. struct radeon_ib *ib,
  674. uint64_t pe,
  675. uint64_t addr, unsigned count,
  676. uint32_t incr, uint32_t flags);
  677. void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
  678. u32 si_get_xclk(struct radeon_device *rdev);
  679. uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
  680. int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  681. int si_get_temp(struct radeon_device *rdev);
  682. int si_dpm_init(struct radeon_device *rdev);
  683. void si_dpm_setup_asic(struct radeon_device *rdev);
  684. int si_dpm_enable(struct radeon_device *rdev);
  685. int si_dpm_late_enable(struct radeon_device *rdev);
  686. void si_dpm_disable(struct radeon_device *rdev);
  687. int si_dpm_pre_set_power_state(struct radeon_device *rdev);
  688. int si_dpm_set_power_state(struct radeon_device *rdev);
  689. void si_dpm_post_set_power_state(struct radeon_device *rdev);
  690. void si_dpm_fini(struct radeon_device *rdev);
  691. void si_dpm_display_configuration_changed(struct radeon_device *rdev);
  692. void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  693. struct seq_file *m);
  694. int si_dpm_force_performance_level(struct radeon_device *rdev,
  695. enum radeon_dpm_forced_level level);
  696. /* DCE8 - CIK */
  697. void dce8_bandwidth_update(struct radeon_device *rdev);
  698. /*
  699. * cik
  700. */
  701. uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
  702. u32 cik_get_xclk(struct radeon_device *rdev);
  703. uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
  704. void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  705. int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  706. int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
  707. void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
  708. struct radeon_fence *fence);
  709. bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
  710. struct radeon_ring *ring,
  711. struct radeon_semaphore *semaphore,
  712. bool emit_wait);
  713. void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  714. int cik_copy_dma(struct radeon_device *rdev,
  715. uint64_t src_offset, uint64_t dst_offset,
  716. unsigned num_gpu_pages,
  717. struct radeon_fence **fence);
  718. int cik_copy_cpdma(struct radeon_device *rdev,
  719. uint64_t src_offset, uint64_t dst_offset,
  720. unsigned num_gpu_pages,
  721. struct radeon_fence **fence);
  722. int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
  723. int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
  724. bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
  725. void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
  726. struct radeon_fence *fence);
  727. void cik_fence_compute_ring_emit(struct radeon_device *rdev,
  728. struct radeon_fence *fence);
  729. bool cik_semaphore_ring_emit(struct radeon_device *rdev,
  730. struct radeon_ring *cp,
  731. struct radeon_semaphore *semaphore,
  732. bool emit_wait);
  733. void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
  734. int cik_init(struct radeon_device *rdev);
  735. void cik_fini(struct radeon_device *rdev);
  736. int cik_suspend(struct radeon_device *rdev);
  737. int cik_resume(struct radeon_device *rdev);
  738. bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  739. int cik_asic_reset(struct radeon_device *rdev);
  740. void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  741. int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
  742. int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
  743. int cik_irq_set(struct radeon_device *rdev);
  744. int cik_irq_process(struct radeon_device *rdev);
  745. int cik_vm_init(struct radeon_device *rdev);
  746. void cik_vm_fini(struct radeon_device *rdev);
  747. void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
  748. void cik_sdma_vm_set_page(struct radeon_device *rdev,
  749. struct radeon_ib *ib,
  750. uint64_t pe,
  751. uint64_t addr, unsigned count,
  752. uint32_t incr, uint32_t flags);
  753. void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
  754. int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
  755. u32 cik_gfx_get_rptr(struct radeon_device *rdev,
  756. struct radeon_ring *ring);
  757. u32 cik_gfx_get_wptr(struct radeon_device *rdev,
  758. struct radeon_ring *ring);
  759. void cik_gfx_set_wptr(struct radeon_device *rdev,
  760. struct radeon_ring *ring);
  761. u32 cik_compute_get_rptr(struct radeon_device *rdev,
  762. struct radeon_ring *ring);
  763. u32 cik_compute_get_wptr(struct radeon_device *rdev,
  764. struct radeon_ring *ring);
  765. void cik_compute_set_wptr(struct radeon_device *rdev,
  766. struct radeon_ring *ring);
  767. u32 cik_sdma_get_rptr(struct radeon_device *rdev,
  768. struct radeon_ring *ring);
  769. u32 cik_sdma_get_wptr(struct radeon_device *rdev,
  770. struct radeon_ring *ring);
  771. void cik_sdma_set_wptr(struct radeon_device *rdev,
  772. struct radeon_ring *ring);
  773. int ci_get_temp(struct radeon_device *rdev);
  774. int kv_get_temp(struct radeon_device *rdev);
  775. int ci_dpm_init(struct radeon_device *rdev);
  776. int ci_dpm_enable(struct radeon_device *rdev);
  777. int ci_dpm_late_enable(struct radeon_device *rdev);
  778. void ci_dpm_disable(struct radeon_device *rdev);
  779. int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
  780. int ci_dpm_set_power_state(struct radeon_device *rdev);
  781. void ci_dpm_post_set_power_state(struct radeon_device *rdev);
  782. void ci_dpm_setup_asic(struct radeon_device *rdev);
  783. void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
  784. void ci_dpm_fini(struct radeon_device *rdev);
  785. u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
  786. u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
  787. void ci_dpm_print_power_state(struct radeon_device *rdev,
  788. struct radeon_ps *ps);
  789. void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  790. struct seq_file *m);
  791. int ci_dpm_force_performance_level(struct radeon_device *rdev,
  792. enum radeon_dpm_forced_level level);
  793. bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
  794. void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
  795. int kv_dpm_init(struct radeon_device *rdev);
  796. int kv_dpm_enable(struct radeon_device *rdev);
  797. int kv_dpm_late_enable(struct radeon_device *rdev);
  798. void kv_dpm_disable(struct radeon_device *rdev);
  799. int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
  800. int kv_dpm_set_power_state(struct radeon_device *rdev);
  801. void kv_dpm_post_set_power_state(struct radeon_device *rdev);
  802. void kv_dpm_setup_asic(struct radeon_device *rdev);
  803. void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
  804. void kv_dpm_fini(struct radeon_device *rdev);
  805. u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
  806. u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
  807. void kv_dpm_print_power_state(struct radeon_device *rdev,
  808. struct radeon_ps *ps);
  809. void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  810. struct seq_file *m);
  811. int kv_dpm_force_performance_level(struct radeon_device *rdev,
  812. enum radeon_dpm_forced_level level);
  813. void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
  814. void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
  815. /* uvd v1.0 */
  816. uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
  817. struct radeon_ring *ring);
  818. uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
  819. struct radeon_ring *ring);
  820. void uvd_v1_0_set_wptr(struct radeon_device *rdev,
  821. struct radeon_ring *ring);
  822. int uvd_v1_0_init(struct radeon_device *rdev);
  823. void uvd_v1_0_fini(struct radeon_device *rdev);
  824. int uvd_v1_0_start(struct radeon_device *rdev);
  825. void uvd_v1_0_stop(struct radeon_device *rdev);
  826. int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
  827. int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
  828. bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
  829. struct radeon_ring *ring,
  830. struct radeon_semaphore *semaphore,
  831. bool emit_wait);
  832. void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  833. /* uvd v2.2 */
  834. int uvd_v2_2_resume(struct radeon_device *rdev);
  835. void uvd_v2_2_fence_emit(struct radeon_device *rdev,
  836. struct radeon_fence *fence);
  837. /* uvd v3.1 */
  838. bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
  839. struct radeon_ring *ring,
  840. struct radeon_semaphore *semaphore,
  841. bool emit_wait);
  842. /* uvd v4.2 */
  843. int uvd_v4_2_resume(struct radeon_device *rdev);
  844. /* vce v1.0 */
  845. uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
  846. struct radeon_ring *ring);
  847. uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
  848. struct radeon_ring *ring);
  849. void vce_v1_0_set_wptr(struct radeon_device *rdev,
  850. struct radeon_ring *ring);
  851. int vce_v1_0_init(struct radeon_device *rdev);
  852. int vce_v1_0_start(struct radeon_device *rdev);
  853. /* vce v2.0 */
  854. int vce_v2_0_resume(struct radeon_device *rdev);
  855. #endif