panel-s6e8aa0.c 29 KB

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  1. /*
  2. * MIPI-DSI based s6e8aa0 AMOLED LCD 5.3 inch panel driver.
  3. *
  4. * Copyright (c) 2013 Samsung Electronics Co., Ltd
  5. *
  6. * Inki Dae, <inki.dae@samsung.com>
  7. * Donghwa Lee, <dh09.lee@samsung.com>
  8. * Joongmock Shin <jmock.shin@samsung.com>
  9. * Eunchul Kim <chulspro.kim@samsung.com>
  10. * Tomasz Figa <t.figa@samsung.com>
  11. * Andrzej Hajda <a.hajda@samsung.com>
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License version 2 as
  15. * published by the Free Software Foundation.
  16. */
  17. #include <drm/drmP.h>
  18. #include <drm/drm_mipi_dsi.h>
  19. #include <drm/drm_panel.h>
  20. #include <linux/gpio/consumer.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <video/mipi_display.h>
  23. #include <video/of_videomode.h>
  24. #include <video/videomode.h>
  25. #define LDI_MTP_LENGTH 24
  26. #define GAMMA_LEVEL_NUM 25
  27. #define GAMMA_TABLE_LEN 26
  28. #define PANELCTL_SS_MASK (1 << 5)
  29. #define PANELCTL_SS_1_800 (0 << 5)
  30. #define PANELCTL_SS_800_1 (1 << 5)
  31. #define PANELCTL_GTCON_MASK (7 << 2)
  32. #define PANELCTL_GTCON_110 (6 << 2)
  33. #define PANELCTL_GTCON_111 (7 << 2)
  34. #define PANELCTL_CLK1_CON_MASK (7 << 3)
  35. #define PANELCTL_CLK1_000 (0 << 3)
  36. #define PANELCTL_CLK1_001 (1 << 3)
  37. #define PANELCTL_CLK2_CON_MASK (7 << 0)
  38. #define PANELCTL_CLK2_000 (0 << 0)
  39. #define PANELCTL_CLK2_001 (1 << 0)
  40. #define PANELCTL_INT1_CON_MASK (7 << 3)
  41. #define PANELCTL_INT1_000 (0 << 3)
  42. #define PANELCTL_INT1_001 (1 << 3)
  43. #define PANELCTL_INT2_CON_MASK (7 << 0)
  44. #define PANELCTL_INT2_000 (0 << 0)
  45. #define PANELCTL_INT2_001 (1 << 0)
  46. #define PANELCTL_BICTL_CON_MASK (7 << 3)
  47. #define PANELCTL_BICTL_000 (0 << 3)
  48. #define PANELCTL_BICTL_001 (1 << 3)
  49. #define PANELCTL_BICTLB_CON_MASK (7 << 0)
  50. #define PANELCTL_BICTLB_000 (0 << 0)
  51. #define PANELCTL_BICTLB_001 (1 << 0)
  52. #define PANELCTL_EM_CLK1_CON_MASK (7 << 3)
  53. #define PANELCTL_EM_CLK1_110 (6 << 3)
  54. #define PANELCTL_EM_CLK1_111 (7 << 3)
  55. #define PANELCTL_EM_CLK1B_CON_MASK (7 << 0)
  56. #define PANELCTL_EM_CLK1B_110 (6 << 0)
  57. #define PANELCTL_EM_CLK1B_111 (7 << 0)
  58. #define PANELCTL_EM_CLK2_CON_MASK (7 << 3)
  59. #define PANELCTL_EM_CLK2_110 (6 << 3)
  60. #define PANELCTL_EM_CLK2_111 (7 << 3)
  61. #define PANELCTL_EM_CLK2B_CON_MASK (7 << 0)
  62. #define PANELCTL_EM_CLK2B_110 (6 << 0)
  63. #define PANELCTL_EM_CLK2B_111 (7 << 0)
  64. #define PANELCTL_EM_INT1_CON_MASK (7 << 3)
  65. #define PANELCTL_EM_INT1_000 (0 << 3)
  66. #define PANELCTL_EM_INT1_001 (1 << 3)
  67. #define PANELCTL_EM_INT2_CON_MASK (7 << 0)
  68. #define PANELCTL_EM_INT2_000 (0 << 0)
  69. #define PANELCTL_EM_INT2_001 (1 << 0)
  70. #define AID_DISABLE (0x4)
  71. #define AID_1 (0x5)
  72. #define AID_2 (0x6)
  73. #define AID_3 (0x7)
  74. typedef u8 s6e8aa0_gamma_table[GAMMA_TABLE_LEN];
  75. struct s6e8aa0_variant {
  76. u8 version;
  77. const s6e8aa0_gamma_table *gamma_tables;
  78. };
  79. struct s6e8aa0 {
  80. struct device *dev;
  81. struct drm_panel panel;
  82. struct regulator_bulk_data supplies[2];
  83. struct gpio_desc *reset_gpio;
  84. u32 power_on_delay;
  85. u32 reset_delay;
  86. u32 init_delay;
  87. bool flip_horizontal;
  88. bool flip_vertical;
  89. struct videomode vm;
  90. u32 width_mm;
  91. u32 height_mm;
  92. u8 version;
  93. u8 id;
  94. const struct s6e8aa0_variant *variant;
  95. int brightness;
  96. /* This field is tested by functions directly accessing DSI bus before
  97. * transfer, transfer is skipped if it is set. In case of transfer
  98. * failure or unexpected response the field is set to error value.
  99. * Such construct allows to eliminate many checks in higher level
  100. * functions.
  101. */
  102. int error;
  103. };
  104. #define panel_to_s6e8aa0(p) container_of(p, struct s6e8aa0, panel)
  105. static int s6e8aa0_clear_error(struct s6e8aa0 *ctx)
  106. {
  107. int ret = ctx->error;
  108. ctx->error = 0;
  109. return ret;
  110. }
  111. static void s6e8aa0_dcs_write(struct s6e8aa0 *ctx, const void *data, size_t len)
  112. {
  113. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  114. int ret;
  115. if (ctx->error < 0)
  116. return;
  117. ret = mipi_dsi_dcs_write(dsi, dsi->channel, data, len);
  118. if (ret < 0) {
  119. dev_err(ctx->dev, "error %d writing dcs seq: %*ph\n", ret, len,
  120. data);
  121. ctx->error = ret;
  122. }
  123. }
  124. static int s6e8aa0_dcs_read(struct s6e8aa0 *ctx, u8 cmd, void *data, size_t len)
  125. {
  126. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  127. int ret;
  128. if (ctx->error < 0)
  129. return ctx->error;
  130. ret = mipi_dsi_dcs_read(dsi, dsi->channel, cmd, data, len);
  131. if (ret < 0) {
  132. dev_err(ctx->dev, "error %d reading dcs seq(%#x)\n", ret, cmd);
  133. ctx->error = ret;
  134. }
  135. return ret;
  136. }
  137. #define s6e8aa0_dcs_write_seq(ctx, seq...) \
  138. ({\
  139. const u8 d[] = { seq };\
  140. BUILD_BUG_ON_MSG(ARRAY_SIZE(d) > 64, "DCS sequence too big for stack");\
  141. s6e8aa0_dcs_write(ctx, d, ARRAY_SIZE(d));\
  142. })
  143. #define s6e8aa0_dcs_write_seq_static(ctx, seq...) \
  144. ({\
  145. static const u8 d[] = { seq };\
  146. s6e8aa0_dcs_write(ctx, d, ARRAY_SIZE(d));\
  147. })
  148. static void s6e8aa0_apply_level_1_key(struct s6e8aa0 *ctx)
  149. {
  150. s6e8aa0_dcs_write_seq_static(ctx, 0xf0, 0x5a, 0x5a);
  151. }
  152. static void s6e8aa0_panel_cond_set_v142(struct s6e8aa0 *ctx)
  153. {
  154. static const u8 aids[] = {
  155. 0x04, 0x04, 0x04, 0x04, 0x04, 0x60, 0x80, 0xA0
  156. };
  157. u8 aid = aids[ctx->id >> 5];
  158. u8 cfg = 0x3d;
  159. u8 clk_con = 0xc8;
  160. u8 int_con = 0x08;
  161. u8 bictl_con = 0x48;
  162. u8 em_clk1_con = 0xff;
  163. u8 em_clk2_con = 0xff;
  164. u8 em_int_con = 0xc8;
  165. if (ctx->flip_vertical) {
  166. /* GTCON */
  167. cfg &= ~(PANELCTL_GTCON_MASK);
  168. cfg |= (PANELCTL_GTCON_110);
  169. }
  170. if (ctx->flip_horizontal) {
  171. /* SS */
  172. cfg &= ~(PANELCTL_SS_MASK);
  173. cfg |= (PANELCTL_SS_1_800);
  174. }
  175. if (ctx->flip_horizontal || ctx->flip_vertical) {
  176. /* CLK1,2_CON */
  177. clk_con &= ~(PANELCTL_CLK1_CON_MASK |
  178. PANELCTL_CLK2_CON_MASK);
  179. clk_con |= (PANELCTL_CLK1_000 | PANELCTL_CLK2_001);
  180. /* INT1,2_CON */
  181. int_con &= ~(PANELCTL_INT1_CON_MASK |
  182. PANELCTL_INT2_CON_MASK);
  183. int_con |= (PANELCTL_INT1_000 | PANELCTL_INT2_001);
  184. /* BICTL,B_CON */
  185. bictl_con &= ~(PANELCTL_BICTL_CON_MASK |
  186. PANELCTL_BICTLB_CON_MASK);
  187. bictl_con |= (PANELCTL_BICTL_000 |
  188. PANELCTL_BICTLB_001);
  189. /* EM_CLK1,1B_CON */
  190. em_clk1_con &= ~(PANELCTL_EM_CLK1_CON_MASK |
  191. PANELCTL_EM_CLK1B_CON_MASK);
  192. em_clk1_con |= (PANELCTL_EM_CLK1_110 |
  193. PANELCTL_EM_CLK1B_110);
  194. /* EM_CLK2,2B_CON */
  195. em_clk2_con &= ~(PANELCTL_EM_CLK2_CON_MASK |
  196. PANELCTL_EM_CLK2B_CON_MASK);
  197. em_clk2_con |= (PANELCTL_EM_CLK2_110 |
  198. PANELCTL_EM_CLK2B_110);
  199. /* EM_INT1,2_CON */
  200. em_int_con &= ~(PANELCTL_EM_INT1_CON_MASK |
  201. PANELCTL_EM_INT2_CON_MASK);
  202. em_int_con |= (PANELCTL_EM_INT1_000 |
  203. PANELCTL_EM_INT2_001);
  204. }
  205. s6e8aa0_dcs_write_seq(ctx,
  206. 0xf8, cfg, 0x35, 0x00, 0x00, 0x00, 0x93, 0x00,
  207. 0x3c, 0x78, 0x08, 0x27, 0x7d, 0x3f, 0x00, 0x00,
  208. 0x00, 0x20, aid, 0x08, 0x6e, 0x00, 0x00, 0x00,
  209. 0x02, 0x07, 0x07, 0x23, 0x23, 0xc0, clk_con, int_con,
  210. bictl_con, 0xc1, 0x00, 0xc1, em_clk1_con, em_clk2_con,
  211. em_int_con);
  212. }
  213. static void s6e8aa0_panel_cond_set(struct s6e8aa0 *ctx)
  214. {
  215. if (ctx->version < 142)
  216. s6e8aa0_dcs_write_seq_static(ctx,
  217. 0xf8, 0x19, 0x35, 0x00, 0x00, 0x00, 0x94, 0x00,
  218. 0x3c, 0x78, 0x10, 0x27, 0x08, 0x6e, 0x00, 0x00,
  219. 0x00, 0x00, 0x04, 0x08, 0x6e, 0x00, 0x00, 0x00,
  220. 0x00, 0x07, 0x07, 0x23, 0x6e, 0xc0, 0xc1, 0x01,
  221. 0x81, 0xc1, 0x00, 0xc3, 0xf6, 0xf6, 0xc1
  222. );
  223. else
  224. s6e8aa0_panel_cond_set_v142(ctx);
  225. }
  226. static void s6e8aa0_display_condition_set(struct s6e8aa0 *ctx)
  227. {
  228. s6e8aa0_dcs_write_seq_static(ctx, 0xf2, 0x80, 0x03, 0x0d);
  229. }
  230. static void s6e8aa0_etc_source_control(struct s6e8aa0 *ctx)
  231. {
  232. s6e8aa0_dcs_write_seq_static(ctx, 0xf6, 0x00, 0x02, 0x00);
  233. }
  234. static void s6e8aa0_etc_pentile_control(struct s6e8aa0 *ctx)
  235. {
  236. static const u8 pent32[] = {
  237. 0xb6, 0x0c, 0x02, 0x03, 0x32, 0xc0, 0x44, 0x44, 0xc0, 0x00
  238. };
  239. static const u8 pent142[] = {
  240. 0xb6, 0x0c, 0x02, 0x03, 0x32, 0xff, 0x44, 0x44, 0xc0, 0x00
  241. };
  242. if (ctx->version < 142)
  243. s6e8aa0_dcs_write(ctx, pent32, ARRAY_SIZE(pent32));
  244. else
  245. s6e8aa0_dcs_write(ctx, pent142, ARRAY_SIZE(pent142));
  246. }
  247. static void s6e8aa0_etc_power_control(struct s6e8aa0 *ctx)
  248. {
  249. static const u8 pwr142[] = {
  250. 0xf4, 0xcf, 0x0a, 0x12, 0x10, 0x1e, 0x33, 0x02
  251. };
  252. static const u8 pwr32[] = {
  253. 0xf4, 0xcf, 0x0a, 0x15, 0x10, 0x19, 0x33, 0x02
  254. };
  255. if (ctx->version < 142)
  256. s6e8aa0_dcs_write(ctx, pwr32, ARRAY_SIZE(pwr32));
  257. else
  258. s6e8aa0_dcs_write(ctx, pwr142, ARRAY_SIZE(pwr142));
  259. }
  260. static void s6e8aa0_etc_elvss_control(struct s6e8aa0 *ctx)
  261. {
  262. u8 id = ctx->id ? 0 : 0x95;
  263. s6e8aa0_dcs_write_seq(ctx, 0xb1, 0x04, id);
  264. }
  265. static void s6e8aa0_elvss_nvm_set_v142(struct s6e8aa0 *ctx)
  266. {
  267. u8 br;
  268. switch (ctx->brightness) {
  269. case 0 ... 6: /* 30cd ~ 100cd */
  270. br = 0xdf;
  271. break;
  272. case 7 ... 11: /* 120cd ~ 150cd */
  273. br = 0xdd;
  274. break;
  275. case 12 ... 15: /* 180cd ~ 210cd */
  276. default:
  277. br = 0xd9;
  278. break;
  279. case 16 ... 24: /* 240cd ~ 300cd */
  280. br = 0xd0;
  281. break;
  282. }
  283. s6e8aa0_dcs_write_seq(ctx, 0xd9, 0x14, 0x40, 0x0c, 0xcb, 0xce, 0x6e,
  284. 0xc4, 0x0f, 0x40, 0x41, br, 0x00, 0x60, 0x19);
  285. }
  286. static void s6e8aa0_elvss_nvm_set(struct s6e8aa0 *ctx)
  287. {
  288. if (ctx->version < 142)
  289. s6e8aa0_dcs_write_seq_static(ctx,
  290. 0xd9, 0x14, 0x40, 0x0c, 0xcb, 0xce, 0x6e, 0xc4, 0x07,
  291. 0x40, 0x41, 0xc1, 0x00, 0x60, 0x19);
  292. else
  293. s6e8aa0_elvss_nvm_set_v142(ctx);
  294. };
  295. static void s6e8aa0_apply_level_2_key(struct s6e8aa0 *ctx)
  296. {
  297. s6e8aa0_dcs_write_seq_static(ctx, 0xfc, 0x5a, 0x5a);
  298. }
  299. static const s6e8aa0_gamma_table s6e8aa0_gamma_tables_v142[GAMMA_LEVEL_NUM] = {
  300. {
  301. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0x62, 0x55, 0x55,
  302. 0xaf, 0xb1, 0xb1, 0xbd, 0xce, 0xb7, 0x9a, 0xb1,
  303. 0x90, 0xb2, 0xc4, 0xae, 0x00, 0x60, 0x00, 0x40,
  304. 0x00, 0x70,
  305. }, {
  306. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0x74, 0x68, 0x69,
  307. 0xb8, 0xc1, 0xb7, 0xbd, 0xcd, 0xb8, 0x93, 0xab,
  308. 0x88, 0xb4, 0xc4, 0xb1, 0x00, 0x6b, 0x00, 0x4d,
  309. 0x00, 0x7d,
  310. }, {
  311. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0x95, 0x8a, 0x89,
  312. 0xb4, 0xc6, 0xb2, 0xc5, 0xd2, 0xbf, 0x90, 0xa8,
  313. 0x85, 0xb5, 0xc4, 0xb3, 0x00, 0x7b, 0x00, 0x5d,
  314. 0x00, 0x8f,
  315. }, {
  316. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0x9f, 0x98, 0x92,
  317. 0xb3, 0xc4, 0xb0, 0xbc, 0xcc, 0xb4, 0x91, 0xa6,
  318. 0x87, 0xb5, 0xc5, 0xb4, 0x00, 0x87, 0x00, 0x6a,
  319. 0x00, 0x9e,
  320. }, {
  321. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0x99, 0x93, 0x8b,
  322. 0xb2, 0xc2, 0xb0, 0xbd, 0xce, 0xb4, 0x90, 0xa6,
  323. 0x87, 0xb3, 0xc3, 0xb2, 0x00, 0x8d, 0x00, 0x70,
  324. 0x00, 0xa4,
  325. }, {
  326. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa7, 0xa5, 0x99,
  327. 0xb2, 0xc2, 0xb0, 0xbb, 0xcd, 0xb1, 0x93, 0xa7,
  328. 0x8a, 0xb2, 0xc1, 0xb0, 0x00, 0x92, 0x00, 0x75,
  329. 0x00, 0xaa,
  330. }, {
  331. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa0, 0xa0, 0x93,
  332. 0xb6, 0xc4, 0xb4, 0xb5, 0xc8, 0xaa, 0x94, 0xa9,
  333. 0x8c, 0xb2, 0xc0, 0xb0, 0x00, 0x97, 0x00, 0x7a,
  334. 0x00, 0xaf,
  335. }, {
  336. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa3, 0xa7, 0x96,
  337. 0xb3, 0xc2, 0xb0, 0xba, 0xcb, 0xb0, 0x94, 0xa8,
  338. 0x8c, 0xb0, 0xbf, 0xaf, 0x00, 0x9f, 0x00, 0x83,
  339. 0x00, 0xb9,
  340. }, {
  341. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0x9d, 0xa2, 0x90,
  342. 0xb6, 0xc5, 0xb3, 0xb8, 0xc9, 0xae, 0x94, 0xa8,
  343. 0x8d, 0xaf, 0xbd, 0xad, 0x00, 0xa4, 0x00, 0x88,
  344. 0x00, 0xbf,
  345. }, {
  346. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa6, 0xac, 0x97,
  347. 0xb4, 0xc4, 0xb1, 0xbb, 0xcb, 0xb2, 0x93, 0xa7,
  348. 0x8d, 0xae, 0xbc, 0xad, 0x00, 0xa7, 0x00, 0x8c,
  349. 0x00, 0xc3,
  350. }, {
  351. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa2, 0xa9, 0x93,
  352. 0xb6, 0xc5, 0xb2, 0xba, 0xc9, 0xb0, 0x93, 0xa7,
  353. 0x8d, 0xae, 0xbb, 0xac, 0x00, 0xab, 0x00, 0x90,
  354. 0x00, 0xc8,
  355. }, {
  356. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0x9e, 0xa6, 0x8f,
  357. 0xb7, 0xc6, 0xb3, 0xb8, 0xc8, 0xb0, 0x93, 0xa6,
  358. 0x8c, 0xae, 0xbb, 0xad, 0x00, 0xae, 0x00, 0x93,
  359. 0x00, 0xcc,
  360. }, {
  361. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xab, 0xb4, 0x9c,
  362. 0xb3, 0xc3, 0xaf, 0xb7, 0xc7, 0xaf, 0x93, 0xa6,
  363. 0x8c, 0xaf, 0xbc, 0xad, 0x00, 0xb1, 0x00, 0x97,
  364. 0x00, 0xcf,
  365. }, {
  366. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa6, 0xb1, 0x98,
  367. 0xb1, 0xc2, 0xab, 0xba, 0xc9, 0xb2, 0x93, 0xa6,
  368. 0x8d, 0xae, 0xba, 0xab, 0x00, 0xb5, 0x00, 0x9b,
  369. 0x00, 0xd4,
  370. }, {
  371. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa3, 0xae, 0x94,
  372. 0xb2, 0xc3, 0xac, 0xbb, 0xca, 0xb4, 0x91, 0xa4,
  373. 0x8a, 0xae, 0xba, 0xac, 0x00, 0xb8, 0x00, 0x9e,
  374. 0x00, 0xd8,
  375. }, {
  376. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xab, 0xb7, 0x9c,
  377. 0xae, 0xc0, 0xa9, 0xba, 0xc9, 0xb3, 0x92, 0xa5,
  378. 0x8b, 0xad, 0xb9, 0xab, 0x00, 0xbb, 0x00, 0xa1,
  379. 0x00, 0xdc,
  380. }, {
  381. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa7, 0xb4, 0x97,
  382. 0xb0, 0xc1, 0xaa, 0xb9, 0xc8, 0xb2, 0x92, 0xa5,
  383. 0x8c, 0xae, 0xb9, 0xab, 0x00, 0xbe, 0x00, 0xa4,
  384. 0x00, 0xdf,
  385. }, {
  386. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa3, 0xb0, 0x94,
  387. 0xb0, 0xc2, 0xab, 0xbb, 0xc9, 0xb3, 0x91, 0xa4,
  388. 0x8b, 0xad, 0xb8, 0xaa, 0x00, 0xc1, 0x00, 0xa8,
  389. 0x00, 0xe2,
  390. }, {
  391. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa3, 0xb0, 0x94,
  392. 0xae, 0xbf, 0xa8, 0xb9, 0xc8, 0xb3, 0x92, 0xa4,
  393. 0x8b, 0xad, 0xb7, 0xa9, 0x00, 0xc4, 0x00, 0xab,
  394. 0x00, 0xe6,
  395. }, {
  396. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa7, 0xb6, 0x98,
  397. 0xaf, 0xc0, 0xa8, 0xb8, 0xc7, 0xb2, 0x93, 0xa5,
  398. 0x8d, 0xad, 0xb7, 0xa9, 0x00, 0xc7, 0x00, 0xae,
  399. 0x00, 0xe9,
  400. }, {
  401. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa4, 0xb3, 0x95,
  402. 0xaf, 0xc1, 0xa9, 0xb9, 0xc8, 0xb3, 0x92, 0xa4,
  403. 0x8b, 0xad, 0xb7, 0xaa, 0x00, 0xc9, 0x00, 0xb0,
  404. 0x00, 0xec,
  405. }, {
  406. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa4, 0xb3, 0x95,
  407. 0xac, 0xbe, 0xa6, 0xbb, 0xc9, 0xb4, 0x90, 0xa3,
  408. 0x8a, 0xad, 0xb7, 0xa9, 0x00, 0xcc, 0x00, 0xb4,
  409. 0x00, 0xf0,
  410. }, {
  411. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa0, 0xb0, 0x91,
  412. 0xae, 0xc0, 0xa6, 0xba, 0xc8, 0xb4, 0x91, 0xa4,
  413. 0x8b, 0xad, 0xb7, 0xa9, 0x00, 0xcf, 0x00, 0xb7,
  414. 0x00, 0xf3,
  415. }, {
  416. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa7, 0xb8, 0x98,
  417. 0xab, 0xbd, 0xa4, 0xbb, 0xc9, 0xb5, 0x91, 0xa3,
  418. 0x8b, 0xac, 0xb6, 0xa8, 0x00, 0xd1, 0x00, 0xb9,
  419. 0x00, 0xf6,
  420. }, {
  421. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa4, 0xb5, 0x95,
  422. 0xa9, 0xbc, 0xa1, 0xbb, 0xc9, 0xb5, 0x91, 0xa3,
  423. 0x8a, 0xad, 0xb6, 0xa8, 0x00, 0xd6, 0x00, 0xbf,
  424. 0x00, 0xfc,
  425. },
  426. };
  427. static const s6e8aa0_gamma_table s6e8aa0_gamma_tables_v96[GAMMA_LEVEL_NUM] = {
  428. {
  429. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x00, 0xff,
  430. 0xdf, 0x1f, 0xd7, 0xdc, 0xb7, 0xe1, 0xc0, 0xaf,
  431. 0xc4, 0xd2, 0xd0, 0xcf, 0x00, 0x4d, 0x00, 0x40,
  432. 0x00, 0x5f,
  433. }, {
  434. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x00, 0xff,
  435. 0xd5, 0x35, 0xcf, 0xdc, 0xc1, 0xe1, 0xbf, 0xb3,
  436. 0xc1, 0xd2, 0xd1, 0xce, 0x00, 0x53, 0x00, 0x46,
  437. 0x00, 0x67,
  438. }, {
  439. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x00, 0xff,
  440. 0xd2, 0x64, 0xcf, 0xdb, 0xc6, 0xe1, 0xbd, 0xb3,
  441. 0xbd, 0xd2, 0xd2, 0xce, 0x00, 0x59, 0x00, 0x4b,
  442. 0x00, 0x6e,
  443. }, {
  444. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x00, 0xff,
  445. 0xd0, 0x7c, 0xcf, 0xdb, 0xc9, 0xe0, 0xbc, 0xb4,
  446. 0xbb, 0xcf, 0xd1, 0xcc, 0x00, 0x5f, 0x00, 0x50,
  447. 0x00, 0x75,
  448. }, {
  449. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x00, 0xff,
  450. 0xd0, 0x8e, 0xd1, 0xdb, 0xcc, 0xdf, 0xbb, 0xb6,
  451. 0xb9, 0xd0, 0xd1, 0xcd, 0x00, 0x63, 0x00, 0x54,
  452. 0x00, 0x7a,
  453. }, {
  454. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x00, 0xff,
  455. 0xd1, 0x9e, 0xd5, 0xda, 0xcd, 0xdd, 0xbb, 0xb7,
  456. 0xb9, 0xce, 0xce, 0xc9, 0x00, 0x68, 0x00, 0x59,
  457. 0x00, 0x81,
  458. }, {
  459. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x00, 0xff,
  460. 0xd0, 0xa5, 0xd6, 0xda, 0xcf, 0xdd, 0xbb, 0xb7,
  461. 0xb8, 0xcc, 0xcd, 0xc7, 0x00, 0x6c, 0x00, 0x5c,
  462. 0x00, 0x86,
  463. }, {
  464. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x1f, 0xfe,
  465. 0xd0, 0xae, 0xd7, 0xd9, 0xd0, 0xdb, 0xb9, 0xb6,
  466. 0xb5, 0xca, 0xcc, 0xc5, 0x00, 0x74, 0x00, 0x63,
  467. 0x00, 0x90,
  468. }, {
  469. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x1f, 0xf9,
  470. 0xcf, 0xb0, 0xd6, 0xd9, 0xd1, 0xdb, 0xb9, 0xb6,
  471. 0xb4, 0xca, 0xcb, 0xc5, 0x00, 0x77, 0x00, 0x66,
  472. 0x00, 0x94,
  473. }, {
  474. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x1f, 0xf7,
  475. 0xcf, 0xb3, 0xd7, 0xd8, 0xd1, 0xd9, 0xb7, 0xb6,
  476. 0xb3, 0xc9, 0xca, 0xc3, 0x00, 0x7b, 0x00, 0x69,
  477. 0x00, 0x99,
  478. }, {
  479. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xfd, 0x2f, 0xf7,
  480. 0xdf, 0xb5, 0xd6, 0xd8, 0xd1, 0xd8, 0xb6, 0xb5,
  481. 0xb2, 0xca, 0xcb, 0xc4, 0x00, 0x7e, 0x00, 0x6c,
  482. 0x00, 0x9d,
  483. }, {
  484. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xfa, 0x2f, 0xf5,
  485. 0xce, 0xb6, 0xd5, 0xd7, 0xd2, 0xd8, 0xb6, 0xb4,
  486. 0xb0, 0xc7, 0xc9, 0xc1, 0x00, 0x84, 0x00, 0x71,
  487. 0x00, 0xa5,
  488. }, {
  489. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xf7, 0x2f, 0xf2,
  490. 0xce, 0xb9, 0xd5, 0xd8, 0xd2, 0xd8, 0xb4, 0xb4,
  491. 0xaf, 0xc7, 0xc9, 0xc1, 0x00, 0x87, 0x00, 0x73,
  492. 0x00, 0xa8,
  493. }, {
  494. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xf5, 0x2f, 0xf0,
  495. 0xdf, 0xba, 0xd5, 0xd7, 0xd2, 0xd7, 0xb4, 0xb4,
  496. 0xaf, 0xc5, 0xc7, 0xbf, 0x00, 0x8a, 0x00, 0x76,
  497. 0x00, 0xac,
  498. }, {
  499. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xf2, 0x2f, 0xed,
  500. 0xcE, 0xbb, 0xd4, 0xd6, 0xd2, 0xd6, 0xb5, 0xb4,
  501. 0xaF, 0xc5, 0xc7, 0xbf, 0x00, 0x8c, 0x00, 0x78,
  502. 0x00, 0xaf,
  503. }, {
  504. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xef, 0x2f, 0xeb,
  505. 0xcd, 0xbb, 0xd2, 0xd7, 0xd3, 0xd6, 0xb3, 0xb4,
  506. 0xae, 0xc5, 0xc6, 0xbe, 0x00, 0x91, 0x00, 0x7d,
  507. 0x00, 0xb6,
  508. }, {
  509. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xee, 0x2f, 0xea,
  510. 0xce, 0xbd, 0xd4, 0xd6, 0xd2, 0xd5, 0xb2, 0xb3,
  511. 0xad, 0xc3, 0xc4, 0xbb, 0x00, 0x94, 0x00, 0x7f,
  512. 0x00, 0xba,
  513. }, {
  514. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xec, 0x2f, 0xe8,
  515. 0xce, 0xbe, 0xd3, 0xd6, 0xd3, 0xd5, 0xb2, 0xb2,
  516. 0xac, 0xc3, 0xc5, 0xbc, 0x00, 0x96, 0x00, 0x81,
  517. 0x00, 0xbd,
  518. }, {
  519. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xeb, 0x2f, 0xe7,
  520. 0xce, 0xbf, 0xd3, 0xd6, 0xd2, 0xd5, 0xb1, 0xb2,
  521. 0xab, 0xc2, 0xc4, 0xbb, 0x00, 0x99, 0x00, 0x83,
  522. 0x00, 0xc0,
  523. }, {
  524. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xef, 0x5f, 0xe9,
  525. 0xca, 0xbf, 0xd3, 0xd5, 0xd2, 0xd4, 0xb2, 0xb2,
  526. 0xab, 0xc1, 0xc4, 0xba, 0x00, 0x9b, 0x00, 0x85,
  527. 0x00, 0xc3,
  528. }, {
  529. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xea, 0x5f, 0xe8,
  530. 0xee, 0xbf, 0xd2, 0xd5, 0xd2, 0xd4, 0xb1, 0xb2,
  531. 0xab, 0xc1, 0xc2, 0xb9, 0x00, 0x9D, 0x00, 0x87,
  532. 0x00, 0xc6,
  533. }, {
  534. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xe9, 0x5f, 0xe7,
  535. 0xcd, 0xbf, 0xd2, 0xd6, 0xd2, 0xd4, 0xb1, 0xb2,
  536. 0xab, 0xbe, 0xc0, 0xb7, 0x00, 0xa1, 0x00, 0x8a,
  537. 0x00, 0xca,
  538. }, {
  539. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xe8, 0x61, 0xe6,
  540. 0xcd, 0xbf, 0xd1, 0xd6, 0xd3, 0xd4, 0xaf, 0xb0,
  541. 0xa9, 0xbe, 0xc1, 0xb7, 0x00, 0xa3, 0x00, 0x8b,
  542. 0x00, 0xce,
  543. }, {
  544. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xe8, 0x62, 0xe5,
  545. 0xcc, 0xc0, 0xd0, 0xd6, 0xd2, 0xd4, 0xaf, 0xb1,
  546. 0xa9, 0xbd, 0xc0, 0xb6, 0x00, 0xa5, 0x00, 0x8d,
  547. 0x00, 0xd0,
  548. }, {
  549. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xe7, 0x7f, 0xe3,
  550. 0xcc, 0xc1, 0xd0, 0xd5, 0xd3, 0xd3, 0xae, 0xaf,
  551. 0xa8, 0xbe, 0xc0, 0xb7, 0x00, 0xa8, 0x00, 0x90,
  552. 0x00, 0xd3,
  553. }
  554. };
  555. static const s6e8aa0_gamma_table s6e8aa0_gamma_tables_v32[GAMMA_LEVEL_NUM] = {
  556. {
  557. 0xfa, 0x01, 0x43, 0x14, 0x45, 0x72, 0x5e, 0x6b,
  558. 0xa1, 0xa7, 0x9a, 0xb4, 0xcb, 0xb8, 0x92, 0xac,
  559. 0x97, 0xb4, 0xc3, 0xb5, 0x00, 0x4e, 0x00, 0x37,
  560. 0x00, 0x58,
  561. }, {
  562. 0xfa, 0x01, 0x43, 0x14, 0x45, 0x85, 0x71, 0x7d,
  563. 0xa6, 0xb6, 0xa1, 0xb5, 0xca, 0xba, 0x93, 0xac,
  564. 0x98, 0xb2, 0xc0, 0xaf, 0x00, 0x59, 0x00, 0x43,
  565. 0x00, 0x64,
  566. }, {
  567. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xa4, 0x94, 0x9e,
  568. 0xa0, 0xbb, 0x9c, 0xc3, 0xd2, 0xc6, 0x93, 0xaa,
  569. 0x95, 0xb7, 0xc2, 0xb4, 0x00, 0x65, 0x00, 0x50,
  570. 0x00, 0x74,
  571. }, {
  572. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xa1, 0xa6,
  573. 0xa0, 0xb9, 0x9b, 0xc3, 0xd1, 0xc8, 0x90, 0xa6,
  574. 0x90, 0xbb, 0xc3, 0xb7, 0x00, 0x6f, 0x00, 0x5b,
  575. 0x00, 0x80,
  576. }, {
  577. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xa6, 0x9d, 0x9f,
  578. 0x9f, 0xb8, 0x9a, 0xc7, 0xd5, 0xcc, 0x90, 0xa5,
  579. 0x8f, 0xb8, 0xc1, 0xb6, 0x00, 0x74, 0x00, 0x60,
  580. 0x00, 0x85,
  581. }, {
  582. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb3, 0xae, 0xae,
  583. 0x9e, 0xb7, 0x9a, 0xc8, 0xd6, 0xce, 0x91, 0xa6,
  584. 0x90, 0xb6, 0xc0, 0xb3, 0x00, 0x78, 0x00, 0x65,
  585. 0x00, 0x8a,
  586. }, {
  587. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xa9, 0xa8,
  588. 0xa3, 0xb9, 0x9e, 0xc4, 0xd3, 0xcb, 0x94, 0xa6,
  589. 0x90, 0xb6, 0xbf, 0xb3, 0x00, 0x7c, 0x00, 0x69,
  590. 0x00, 0x8e,
  591. }, {
  592. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xaf, 0xaf, 0xa9,
  593. 0xa5, 0xbc, 0xa2, 0xc7, 0xd5, 0xcd, 0x93, 0xa5,
  594. 0x8f, 0xb4, 0xbd, 0xb1, 0x00, 0x83, 0x00, 0x70,
  595. 0x00, 0x96,
  596. }, {
  597. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xa9, 0xab, 0xa3,
  598. 0xaa, 0xbf, 0xa7, 0xc5, 0xd3, 0xcb, 0x93, 0xa5,
  599. 0x8f, 0xb2, 0xbb, 0xb0, 0x00, 0x86, 0x00, 0x74,
  600. 0x00, 0x9b,
  601. }, {
  602. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb1, 0xb5, 0xab,
  603. 0xab, 0xc0, 0xa9, 0xc7, 0xd4, 0xcc, 0x94, 0xa4,
  604. 0x8f, 0xb1, 0xbb, 0xaf, 0x00, 0x8a, 0x00, 0x77,
  605. 0x00, 0x9e,
  606. }, {
  607. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xb2, 0xa7,
  608. 0xae, 0xc2, 0xab, 0xc5, 0xd3, 0xca, 0x93, 0xa4,
  609. 0x8f, 0xb1, 0xba, 0xae, 0x00, 0x8d, 0x00, 0x7b,
  610. 0x00, 0xa2,
  611. }, {
  612. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xa9, 0xaf, 0xa3,
  613. 0xb0, 0xc3, 0xae, 0xc4, 0xd1, 0xc8, 0x93, 0xa4,
  614. 0x8f, 0xb1, 0xba, 0xaf, 0x00, 0x8f, 0x00, 0x7d,
  615. 0x00, 0xa5,
  616. }, {
  617. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb4, 0xbd, 0xaf,
  618. 0xae, 0xc1, 0xab, 0xc2, 0xd0, 0xc6, 0x94, 0xa4,
  619. 0x8f, 0xb1, 0xba, 0xaf, 0x00, 0x92, 0x00, 0x80,
  620. 0x00, 0xa8,
  621. }, {
  622. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb0, 0xb9, 0xac,
  623. 0xad, 0xc1, 0xab, 0xc4, 0xd1, 0xc7, 0x95, 0xa4,
  624. 0x90, 0xb0, 0xb9, 0xad, 0x00, 0x95, 0x00, 0x84,
  625. 0x00, 0xac,
  626. }, {
  627. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xb6, 0xa7,
  628. 0xaf, 0xc2, 0xae, 0xc5, 0xd1, 0xc7, 0x93, 0xa3,
  629. 0x8e, 0xb0, 0xb9, 0xad, 0x00, 0x98, 0x00, 0x86,
  630. 0x00, 0xaf,
  631. }, {
  632. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb4, 0xbf, 0xaf,
  633. 0xad, 0xc1, 0xab, 0xc3, 0xd0, 0xc6, 0x94, 0xa3,
  634. 0x8f, 0xaf, 0xb8, 0xac, 0x00, 0x9a, 0x00, 0x89,
  635. 0x00, 0xb2,
  636. }, {
  637. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb0, 0xbc, 0xac,
  638. 0xaf, 0xc2, 0xad, 0xc2, 0xcf, 0xc4, 0x94, 0xa3,
  639. 0x90, 0xaf, 0xb8, 0xad, 0x00, 0x9c, 0x00, 0x8b,
  640. 0x00, 0xb5,
  641. }, {
  642. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xb9, 0xa7,
  643. 0xb1, 0xc4, 0xaf, 0xc3, 0xcf, 0xc5, 0x94, 0xa3,
  644. 0x8f, 0xae, 0xb7, 0xac, 0x00, 0x9f, 0x00, 0x8e,
  645. 0x00, 0xb8,
  646. }, {
  647. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xb9, 0xa7,
  648. 0xaf, 0xc2, 0xad, 0xc1, 0xce, 0xc3, 0x95, 0xa3,
  649. 0x90, 0xad, 0xb6, 0xab, 0x00, 0xa2, 0x00, 0x91,
  650. 0x00, 0xbb,
  651. }, {
  652. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb1, 0xbe, 0xac,
  653. 0xb1, 0xc4, 0xaf, 0xc1, 0xcd, 0xc1, 0x95, 0xa4,
  654. 0x91, 0xad, 0xb6, 0xab, 0x00, 0xa4, 0x00, 0x93,
  655. 0x00, 0xbd,
  656. }, {
  657. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xbb, 0xa8,
  658. 0xb3, 0xc5, 0xb2, 0xc1, 0xcd, 0xc2, 0x95, 0xa3,
  659. 0x90, 0xad, 0xb6, 0xab, 0x00, 0xa6, 0x00, 0x95,
  660. 0x00, 0xc0,
  661. }, {
  662. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xbb, 0xa8,
  663. 0xb0, 0xc3, 0xaf, 0xc2, 0xce, 0xc2, 0x94, 0xa2,
  664. 0x90, 0xac, 0xb6, 0xab, 0x00, 0xa8, 0x00, 0x98,
  665. 0x00, 0xc3,
  666. }, {
  667. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xa9, 0xb8, 0xa5,
  668. 0xb3, 0xc5, 0xb2, 0xc1, 0xcc, 0xc0, 0x95, 0xa2,
  669. 0x90, 0xad, 0xb6, 0xab, 0x00, 0xaa, 0x00, 0x9a,
  670. 0x00, 0xc5,
  671. }, {
  672. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb0, 0xc0, 0xac,
  673. 0xb0, 0xc3, 0xaf, 0xc1, 0xcd, 0xc1, 0x95, 0xa2,
  674. 0x90, 0xac, 0xb5, 0xa9, 0x00, 0xac, 0x00, 0x9c,
  675. 0x00, 0xc8,
  676. }, {
  677. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xbd, 0xa8,
  678. 0xaf, 0xc2, 0xaf, 0xc1, 0xcc, 0xc0, 0x95, 0xa2,
  679. 0x90, 0xac, 0xb5, 0xaa, 0x00, 0xb1, 0x00, 0xa1,
  680. 0x00, 0xcc,
  681. },
  682. };
  683. static const struct s6e8aa0_variant s6e8aa0_variants[] = {
  684. {
  685. .version = 32,
  686. .gamma_tables = s6e8aa0_gamma_tables_v32,
  687. }, {
  688. .version = 96,
  689. .gamma_tables = s6e8aa0_gamma_tables_v96,
  690. }, {
  691. .version = 142,
  692. .gamma_tables = s6e8aa0_gamma_tables_v142,
  693. }, {
  694. .version = 210,
  695. .gamma_tables = s6e8aa0_gamma_tables_v142,
  696. }
  697. };
  698. static void s6e8aa0_brightness_set(struct s6e8aa0 *ctx)
  699. {
  700. const u8 *gamma;
  701. if (ctx->error)
  702. return;
  703. gamma = ctx->variant->gamma_tables[ctx->brightness];
  704. if (ctx->version >= 142)
  705. s6e8aa0_elvss_nvm_set(ctx);
  706. s6e8aa0_dcs_write(ctx, gamma, GAMMA_TABLE_LEN);
  707. /* update gamma table. */
  708. s6e8aa0_dcs_write_seq_static(ctx, 0xf7, 0x03);
  709. }
  710. static void s6e8aa0_panel_init(struct s6e8aa0 *ctx)
  711. {
  712. s6e8aa0_apply_level_1_key(ctx);
  713. s6e8aa0_apply_level_2_key(ctx);
  714. msleep(20);
  715. s6e8aa0_dcs_write_seq_static(ctx, MIPI_DCS_EXIT_SLEEP_MODE);
  716. msleep(40);
  717. s6e8aa0_panel_cond_set(ctx);
  718. s6e8aa0_display_condition_set(ctx);
  719. s6e8aa0_brightness_set(ctx);
  720. s6e8aa0_etc_source_control(ctx);
  721. s6e8aa0_etc_pentile_control(ctx);
  722. s6e8aa0_elvss_nvm_set(ctx);
  723. s6e8aa0_etc_power_control(ctx);
  724. s6e8aa0_etc_elvss_control(ctx);
  725. msleep(ctx->init_delay);
  726. }
  727. static void s6e8aa0_set_maximum_return_packet_size(struct s6e8aa0 *ctx,
  728. int size)
  729. {
  730. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  731. const struct mipi_dsi_host_ops *ops = dsi->host->ops;
  732. u8 buf[] = {size, 0};
  733. struct mipi_dsi_msg msg = {
  734. .channel = dsi->channel,
  735. .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
  736. .tx_len = sizeof(buf),
  737. .tx_buf = buf
  738. };
  739. int ret;
  740. if (ctx->error < 0)
  741. return;
  742. if (!ops || !ops->transfer)
  743. ret = -EIO;
  744. else
  745. ret = ops->transfer(dsi->host, &msg);
  746. if (ret < 0) {
  747. dev_err(ctx->dev,
  748. "error %d setting maximum return packet size to %d\n",
  749. ret, size);
  750. ctx->error = ret;
  751. }
  752. }
  753. static void s6e8aa0_read_mtp_id(struct s6e8aa0 *ctx)
  754. {
  755. u8 id[3];
  756. int ret, i;
  757. ret = s6e8aa0_dcs_read(ctx, 0xd1, id, ARRAY_SIZE(id));
  758. if (ret < ARRAY_SIZE(id) || id[0] == 0x00) {
  759. dev_err(ctx->dev, "read id failed\n");
  760. ctx->error = -EIO;
  761. return;
  762. }
  763. dev_info(ctx->dev, "ID: 0x%2x, 0x%2x, 0x%2x\n", id[0], id[1], id[2]);
  764. for (i = 0; i < ARRAY_SIZE(s6e8aa0_variants); ++i) {
  765. if (id[1] == s6e8aa0_variants[i].version)
  766. break;
  767. }
  768. if (i >= ARRAY_SIZE(s6e8aa0_variants)) {
  769. dev_err(ctx->dev, "unsupported display version %d\n", id[1]);
  770. ctx->error = -EINVAL;
  771. return;
  772. }
  773. ctx->variant = &s6e8aa0_variants[i];
  774. ctx->version = id[1];
  775. ctx->id = id[2];
  776. }
  777. static void s6e8aa0_set_sequence(struct s6e8aa0 *ctx)
  778. {
  779. s6e8aa0_set_maximum_return_packet_size(ctx, 3);
  780. s6e8aa0_read_mtp_id(ctx);
  781. s6e8aa0_panel_init(ctx);
  782. s6e8aa0_dcs_write_seq_static(ctx, MIPI_DCS_SET_DISPLAY_ON);
  783. }
  784. static int s6e8aa0_power_on(struct s6e8aa0 *ctx)
  785. {
  786. int ret;
  787. ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
  788. if (ret < 0)
  789. return ret;
  790. msleep(ctx->power_on_delay);
  791. gpiod_set_value(ctx->reset_gpio, 0);
  792. usleep_range(10000, 11000);
  793. gpiod_set_value(ctx->reset_gpio, 1);
  794. msleep(ctx->reset_delay);
  795. return 0;
  796. }
  797. static int s6e8aa0_power_off(struct s6e8aa0 *ctx)
  798. {
  799. return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
  800. }
  801. static int s6e8aa0_disable(struct drm_panel *panel)
  802. {
  803. struct s6e8aa0 *ctx = panel_to_s6e8aa0(panel);
  804. s6e8aa0_dcs_write_seq_static(ctx, MIPI_DCS_ENTER_SLEEP_MODE);
  805. s6e8aa0_dcs_write_seq_static(ctx, MIPI_DCS_SET_DISPLAY_OFF);
  806. msleep(40);
  807. s6e8aa0_clear_error(ctx);
  808. return s6e8aa0_power_off(ctx);
  809. }
  810. static int s6e8aa0_enable(struct drm_panel *panel)
  811. {
  812. struct s6e8aa0 *ctx = panel_to_s6e8aa0(panel);
  813. int ret;
  814. ret = s6e8aa0_power_on(ctx);
  815. if (ret < 0)
  816. return ret;
  817. s6e8aa0_set_sequence(ctx);
  818. ret = ctx->error;
  819. if (ret < 0)
  820. s6e8aa0_disable(panel);
  821. return ret;
  822. }
  823. static int s6e8aa0_get_modes(struct drm_panel *panel)
  824. {
  825. struct drm_connector *connector = panel->connector;
  826. struct s6e8aa0 *ctx = panel_to_s6e8aa0(panel);
  827. struct drm_display_mode *mode;
  828. mode = drm_mode_create(connector->dev);
  829. if (!mode) {
  830. DRM_ERROR("failed to create a new display mode\n");
  831. return 0;
  832. }
  833. drm_display_mode_from_videomode(&ctx->vm, mode);
  834. mode->width_mm = ctx->width_mm;
  835. mode->height_mm = ctx->height_mm;
  836. connector->display_info.width_mm = mode->width_mm;
  837. connector->display_info.height_mm = mode->height_mm;
  838. mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
  839. drm_mode_probed_add(connector, mode);
  840. return 1;
  841. }
  842. static const struct drm_panel_funcs s6e8aa0_drm_funcs = {
  843. .disable = s6e8aa0_disable,
  844. .enable = s6e8aa0_enable,
  845. .get_modes = s6e8aa0_get_modes,
  846. };
  847. static int s6e8aa0_parse_dt(struct s6e8aa0 *ctx)
  848. {
  849. struct device *dev = ctx->dev;
  850. struct device_node *np = dev->of_node;
  851. int ret;
  852. ret = of_get_videomode(np, &ctx->vm, 0);
  853. if (ret < 0)
  854. return ret;
  855. of_property_read_u32(np, "power-on-delay", &ctx->power_on_delay);
  856. of_property_read_u32(np, "reset-delay", &ctx->reset_delay);
  857. of_property_read_u32(np, "init-delay", &ctx->init_delay);
  858. of_property_read_u32(np, "panel-width-mm", &ctx->width_mm);
  859. of_property_read_u32(np, "panel-height-mm", &ctx->height_mm);
  860. ctx->flip_horizontal = of_property_read_bool(np, "flip-horizontal");
  861. ctx->flip_vertical = of_property_read_bool(np, "flip-vertical");
  862. return 0;
  863. }
  864. static int s6e8aa0_probe(struct mipi_dsi_device *dsi)
  865. {
  866. struct device *dev = &dsi->dev;
  867. struct s6e8aa0 *ctx;
  868. int ret;
  869. ctx = devm_kzalloc(dev, sizeof(struct s6e8aa0), GFP_KERNEL);
  870. if (!ctx)
  871. return -ENOMEM;
  872. mipi_dsi_set_drvdata(dsi, ctx);
  873. ctx->dev = dev;
  874. dsi->lanes = 4;
  875. dsi->format = MIPI_DSI_FMT_RGB888;
  876. dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST
  877. | MIPI_DSI_MODE_VIDEO_HFP | MIPI_DSI_MODE_VIDEO_HBP
  878. | MIPI_DSI_MODE_VIDEO_HSA | MIPI_DSI_MODE_EOT_PACKET
  879. | MIPI_DSI_MODE_VSYNC_FLUSH | MIPI_DSI_MODE_VIDEO_AUTO_VERT;
  880. ret = s6e8aa0_parse_dt(ctx);
  881. if (ret < 0)
  882. return ret;
  883. ctx->supplies[0].supply = "vdd3";
  884. ctx->supplies[1].supply = "vci";
  885. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
  886. ctx->supplies);
  887. if (ret < 0) {
  888. dev_err(dev, "failed to get regulators: %d\n", ret);
  889. return ret;
  890. }
  891. ctx->reset_gpio = devm_gpiod_get(dev, "reset");
  892. if (IS_ERR(ctx->reset_gpio)) {
  893. dev_err(dev, "cannot get reset-gpios %ld\n",
  894. PTR_ERR(ctx->reset_gpio));
  895. return PTR_ERR(ctx->reset_gpio);
  896. }
  897. ret = gpiod_direction_output(ctx->reset_gpio, 1);
  898. if (ret < 0) {
  899. dev_err(dev, "cannot configure reset-gpios %d\n", ret);
  900. return ret;
  901. }
  902. ctx->brightness = GAMMA_LEVEL_NUM - 1;
  903. drm_panel_init(&ctx->panel);
  904. ctx->panel.dev = dev;
  905. ctx->panel.funcs = &s6e8aa0_drm_funcs;
  906. ret = drm_panel_add(&ctx->panel);
  907. if (ret < 0)
  908. return ret;
  909. ret = mipi_dsi_attach(dsi);
  910. if (ret < 0)
  911. drm_panel_remove(&ctx->panel);
  912. return ret;
  913. }
  914. static int s6e8aa0_remove(struct mipi_dsi_device *dsi)
  915. {
  916. struct s6e8aa0 *ctx = mipi_dsi_get_drvdata(dsi);
  917. mipi_dsi_detach(dsi);
  918. drm_panel_remove(&ctx->panel);
  919. return 0;
  920. }
  921. static struct of_device_id s6e8aa0_of_match[] = {
  922. { .compatible = "samsung,s6e8aa0" },
  923. { }
  924. };
  925. MODULE_DEVICE_TABLE(of, s6e8aa0_of_match);
  926. static struct mipi_dsi_driver s6e8aa0_driver = {
  927. .probe = s6e8aa0_probe,
  928. .remove = s6e8aa0_remove,
  929. .driver = {
  930. .name = "panel_s6e8aa0",
  931. .owner = THIS_MODULE,
  932. .of_match_table = s6e8aa0_of_match,
  933. },
  934. };
  935. module_mipi_dsi_driver(s6e8aa0_driver);
  936. MODULE_AUTHOR("Donghwa Lee <dh09.lee@samsung.com>");
  937. MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>");
  938. MODULE_AUTHOR("Joongmock Shin <jmock.shin@samsung.com>");
  939. MODULE_AUTHOR("Eunchul Kim <chulspro.kim@samsung.com>");
  940. MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
  941. MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
  942. MODULE_DESCRIPTION("MIPI-DSI based s6e8aa0 AMOLED LCD Panel Driver");
  943. MODULE_LICENSE("GPL v2");