msm_drv.h 8.1 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #ifndef __MSM_DRV_H__
  18. #define __MSM_DRV_H__
  19. #include <linux/kernel.h>
  20. #include <linux/clk.h>
  21. #include <linux/cpufreq.h>
  22. #include <linux/module.h>
  23. #include <linux/component.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/pm.h>
  26. #include <linux/pm_runtime.h>
  27. #include <linux/slab.h>
  28. #include <linux/list.h>
  29. #include <linux/iommu.h>
  30. #include <linux/types.h>
  31. #include <asm/sizes.h>
  32. #if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_ARCH_QCOM)
  33. /* stubs we need for compile-test: */
  34. static inline struct device *msm_iommu_get_ctx(const char *ctx_name)
  35. {
  36. return NULL;
  37. }
  38. #endif
  39. #ifndef CONFIG_OF
  40. #include <mach/board.h>
  41. #include <mach/socinfo.h>
  42. #include <mach/iommu_domains.h>
  43. #endif
  44. #include <drm/drmP.h>
  45. #include <drm/drm_crtc_helper.h>
  46. #include <drm/drm_fb_helper.h>
  47. #include <drm/msm_drm.h>
  48. struct msm_kms;
  49. struct msm_gpu;
  50. struct msm_mmu;
  51. struct msm_rd_state;
  52. struct msm_perf_state;
  53. struct msm_gem_submit;
  54. #define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
  55. struct msm_file_private {
  56. /* currently we don't do anything useful with this.. but when
  57. * per-context address spaces are supported we'd keep track of
  58. * the context's page-tables here.
  59. */
  60. int dummy;
  61. };
  62. struct msm_drm_private {
  63. struct msm_kms *kms;
  64. /* subordinate devices, if present: */
  65. struct platform_device *hdmi_pdev, *gpu_pdev;
  66. /* when we have more than one 'msm_gpu' these need to be an array: */
  67. struct msm_gpu *gpu;
  68. struct msm_file_private *lastctx;
  69. struct drm_fb_helper *fbdev;
  70. uint32_t next_fence, completed_fence;
  71. wait_queue_head_t fence_event;
  72. struct msm_rd_state *rd;
  73. struct msm_perf_state *perf;
  74. /* list of GEM objects: */
  75. struct list_head inactive_list;
  76. struct workqueue_struct *wq;
  77. /* callbacks deferred until bo is inactive: */
  78. struct list_head fence_cbs;
  79. /* registered MMUs: */
  80. unsigned int num_mmus;
  81. struct msm_mmu *mmus[NUM_DOMAINS];
  82. unsigned int num_planes;
  83. struct drm_plane *planes[8];
  84. unsigned int num_crtcs;
  85. struct drm_crtc *crtcs[8];
  86. unsigned int num_encoders;
  87. struct drm_encoder *encoders[8];
  88. unsigned int num_bridges;
  89. struct drm_bridge *bridges[8];
  90. unsigned int num_connectors;
  91. struct drm_connector *connectors[8];
  92. /* VRAM carveout, used when no IOMMU: */
  93. struct {
  94. unsigned long size;
  95. dma_addr_t paddr;
  96. /* NOTE: mm managed at the page level, size is in # of pages
  97. * and position mm_node->start is in # of pages:
  98. */
  99. struct drm_mm mm;
  100. } vram;
  101. };
  102. struct msm_format {
  103. uint32_t pixel_format;
  104. };
  105. /* callback from wq once fence has passed: */
  106. struct msm_fence_cb {
  107. struct work_struct work;
  108. uint32_t fence;
  109. void (*func)(struct msm_fence_cb *cb);
  110. };
  111. void __msm_fence_worker(struct work_struct *work);
  112. #define INIT_FENCE_CB(_cb, _func) do { \
  113. INIT_WORK(&(_cb)->work, __msm_fence_worker); \
  114. (_cb)->func = _func; \
  115. } while (0)
  116. int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
  117. int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
  118. struct timespec *timeout);
  119. void msm_update_fence(struct drm_device *dev, uint32_t fence);
  120. int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
  121. struct drm_file *file);
  122. int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
  123. int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
  124. uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
  125. int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
  126. uint32_t *iova);
  127. int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
  128. struct page **msm_gem_get_pages(struct drm_gem_object *obj);
  129. void msm_gem_put_pages(struct drm_gem_object *obj);
  130. void msm_gem_put_iova(struct drm_gem_object *obj, int id);
  131. int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
  132. struct drm_mode_create_dumb *args);
  133. int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
  134. uint32_t handle, uint64_t *offset);
  135. struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
  136. void *msm_gem_prime_vmap(struct drm_gem_object *obj);
  137. void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
  138. struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
  139. size_t size, struct sg_table *sg);
  140. int msm_gem_prime_pin(struct drm_gem_object *obj);
  141. void msm_gem_prime_unpin(struct drm_gem_object *obj);
  142. void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
  143. void *msm_gem_vaddr(struct drm_gem_object *obj);
  144. int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
  145. struct msm_fence_cb *cb);
  146. void msm_gem_move_to_active(struct drm_gem_object *obj,
  147. struct msm_gpu *gpu, bool write, uint32_t fence);
  148. void msm_gem_move_to_inactive(struct drm_gem_object *obj);
  149. int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
  150. struct timespec *timeout);
  151. int msm_gem_cpu_fini(struct drm_gem_object *obj);
  152. void msm_gem_free_object(struct drm_gem_object *obj);
  153. int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
  154. uint32_t size, uint32_t flags, uint32_t *handle);
  155. struct drm_gem_object *msm_gem_new(struct drm_device *dev,
  156. uint32_t size, uint32_t flags);
  157. struct drm_gem_object *msm_gem_import(struct drm_device *dev,
  158. uint32_t size, struct sg_table *sgt);
  159. struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
  160. const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
  161. struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
  162. struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
  163. struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
  164. struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd);
  165. struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
  166. struct hdmi;
  167. struct hdmi *hdmi_init(struct drm_device *dev, struct drm_encoder *encoder);
  168. irqreturn_t hdmi_irq(int irq, void *dev_id);
  169. void __init hdmi_register(void);
  170. void __exit hdmi_unregister(void);
  171. #ifdef CONFIG_DEBUG_FS
  172. void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
  173. void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
  174. void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
  175. int msm_debugfs_late_init(struct drm_device *dev);
  176. int msm_rd_debugfs_init(struct drm_minor *minor);
  177. void msm_rd_debugfs_cleanup(struct drm_minor *minor);
  178. void msm_rd_dump_submit(struct msm_gem_submit *submit);
  179. int msm_perf_debugfs_init(struct drm_minor *minor);
  180. void msm_perf_debugfs_cleanup(struct drm_minor *minor);
  181. #else
  182. static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
  183. static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
  184. #endif
  185. void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
  186. const char *dbgname);
  187. void msm_writel(u32 data, void __iomem *addr);
  188. u32 msm_readl(const void __iomem *addr);
  189. #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  190. #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  191. static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
  192. {
  193. struct msm_drm_private *priv = dev->dev_private;
  194. return priv->completed_fence >= fence;
  195. }
  196. static inline int align_pitch(int width, int bpp)
  197. {
  198. int bytespp = (bpp + 7) / 8;
  199. /* adreno needs pitch aligned to 32 pixels: */
  200. return bytespp * ALIGN(width, 32);
  201. }
  202. /* for the generated headers: */
  203. #define INVALID_IDX(idx) ({BUG(); 0;})
  204. #define fui(x) ({BUG(); 0;})
  205. #define util_float_to_half(x) ({BUG(); 0;})
  206. #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
  207. /* for conditionally setting boolean flag(s): */
  208. #define COND(bool, val) ((bool) ? (val) : 0)
  209. #endif /* __MSM_DRV_H__ */