hdmi_bridge.c 6.2 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include "hdmi.h"
  18. struct hdmi_bridge {
  19. struct drm_bridge base;
  20. struct hdmi *hdmi;
  21. };
  22. #define to_hdmi_bridge(x) container_of(x, struct hdmi_bridge, base)
  23. static void hdmi_bridge_destroy(struct drm_bridge *bridge)
  24. {
  25. struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  26. hdmi_unreference(hdmi_bridge->hdmi);
  27. drm_bridge_cleanup(bridge);
  28. kfree(hdmi_bridge);
  29. }
  30. static void power_on(struct drm_bridge *bridge)
  31. {
  32. struct drm_device *dev = bridge->dev;
  33. struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  34. struct hdmi *hdmi = hdmi_bridge->hdmi;
  35. const struct hdmi_platform_config *config = hdmi->config;
  36. int i, ret;
  37. for (i = 0; i < config->pwr_reg_cnt; i++) {
  38. ret = regulator_enable(hdmi->pwr_regs[i]);
  39. if (ret) {
  40. dev_err(dev->dev, "failed to enable pwr regulator: %s (%d)\n",
  41. config->pwr_reg_names[i], ret);
  42. }
  43. }
  44. if (config->pwr_clk_cnt > 0) {
  45. DBG("pixclock: %lu", hdmi->pixclock);
  46. ret = clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock);
  47. if (ret) {
  48. dev_err(dev->dev, "failed to set pixel clk: %s (%d)\n",
  49. config->pwr_clk_names[0], ret);
  50. }
  51. }
  52. for (i = 0; i < config->pwr_clk_cnt; i++) {
  53. ret = clk_prepare_enable(hdmi->pwr_clks[i]);
  54. if (ret) {
  55. dev_err(dev->dev, "failed to enable pwr clk: %s (%d)\n",
  56. config->pwr_clk_names[i], ret);
  57. }
  58. }
  59. }
  60. static void power_off(struct drm_bridge *bridge)
  61. {
  62. struct drm_device *dev = bridge->dev;
  63. struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  64. struct hdmi *hdmi = hdmi_bridge->hdmi;
  65. const struct hdmi_platform_config *config = hdmi->config;
  66. int i, ret;
  67. /* TODO do we need to wait for final vblank somewhere before
  68. * cutting the clocks?
  69. */
  70. mdelay(16 + 4);
  71. for (i = 0; i < config->pwr_clk_cnt; i++)
  72. clk_disable_unprepare(hdmi->pwr_clks[i]);
  73. for (i = 0; i < config->pwr_reg_cnt; i++) {
  74. ret = regulator_disable(hdmi->pwr_regs[i]);
  75. if (ret) {
  76. dev_err(dev->dev, "failed to disable pwr regulator: %s (%d)\n",
  77. config->pwr_reg_names[i], ret);
  78. }
  79. }
  80. }
  81. static void hdmi_bridge_pre_enable(struct drm_bridge *bridge)
  82. {
  83. struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  84. struct hdmi *hdmi = hdmi_bridge->hdmi;
  85. struct hdmi_phy *phy = hdmi->phy;
  86. DBG("power up");
  87. if (!hdmi->power_on) {
  88. power_on(bridge);
  89. hdmi->power_on = true;
  90. hdmi_audio_update(hdmi);
  91. }
  92. phy->funcs->powerup(phy, hdmi->pixclock);
  93. hdmi_set_mode(hdmi, true);
  94. }
  95. static void hdmi_bridge_enable(struct drm_bridge *bridge)
  96. {
  97. }
  98. static void hdmi_bridge_disable(struct drm_bridge *bridge)
  99. {
  100. }
  101. static void hdmi_bridge_post_disable(struct drm_bridge *bridge)
  102. {
  103. struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  104. struct hdmi *hdmi = hdmi_bridge->hdmi;
  105. struct hdmi_phy *phy = hdmi->phy;
  106. DBG("power down");
  107. hdmi_set_mode(hdmi, false);
  108. phy->funcs->powerdown(phy);
  109. if (hdmi->power_on) {
  110. power_off(bridge);
  111. hdmi->power_on = false;
  112. hdmi_audio_update(hdmi);
  113. }
  114. }
  115. static void hdmi_bridge_mode_set(struct drm_bridge *bridge,
  116. struct drm_display_mode *mode,
  117. struct drm_display_mode *adjusted_mode)
  118. {
  119. struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  120. struct hdmi *hdmi = hdmi_bridge->hdmi;
  121. int hstart, hend, vstart, vend;
  122. uint32_t frame_ctrl;
  123. mode = adjusted_mode;
  124. hdmi->pixclock = mode->clock * 1000;
  125. hdmi->hdmi_mode = drm_match_cea_mode(mode) > 1;
  126. hstart = mode->htotal - mode->hsync_start;
  127. hend = mode->htotal - mode->hsync_start + mode->hdisplay;
  128. vstart = mode->vtotal - mode->vsync_start - 1;
  129. vend = mode->vtotal - mode->vsync_start + mode->vdisplay - 1;
  130. DBG("htotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d",
  131. mode->htotal, mode->vtotal, hstart, hend, vstart, vend);
  132. hdmi_write(hdmi, REG_HDMI_TOTAL,
  133. HDMI_TOTAL_H_TOTAL(mode->htotal - 1) |
  134. HDMI_TOTAL_V_TOTAL(mode->vtotal - 1));
  135. hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC,
  136. HDMI_ACTIVE_HSYNC_START(hstart) |
  137. HDMI_ACTIVE_HSYNC_END(hend));
  138. hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC,
  139. HDMI_ACTIVE_VSYNC_START(vstart) |
  140. HDMI_ACTIVE_VSYNC_END(vend));
  141. if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
  142. hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
  143. HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal));
  144. hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
  145. HDMI_VSYNC_ACTIVE_F2_START(vstart + 1) |
  146. HDMI_VSYNC_ACTIVE_F2_END(vend + 1));
  147. } else {
  148. hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
  149. HDMI_VSYNC_TOTAL_F2_V_TOTAL(0));
  150. hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
  151. HDMI_VSYNC_ACTIVE_F2_START(0) |
  152. HDMI_VSYNC_ACTIVE_F2_END(0));
  153. }
  154. frame_ctrl = 0;
  155. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  156. frame_ctrl |= HDMI_FRAME_CTRL_HSYNC_LOW;
  157. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  158. frame_ctrl |= HDMI_FRAME_CTRL_VSYNC_LOW;
  159. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  160. frame_ctrl |= HDMI_FRAME_CTRL_INTERLACED_EN;
  161. DBG("frame_ctrl=%08x", frame_ctrl);
  162. hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl);
  163. hdmi_audio_update(hdmi);
  164. }
  165. static const struct drm_bridge_funcs hdmi_bridge_funcs = {
  166. .pre_enable = hdmi_bridge_pre_enable,
  167. .enable = hdmi_bridge_enable,
  168. .disable = hdmi_bridge_disable,
  169. .post_disable = hdmi_bridge_post_disable,
  170. .mode_set = hdmi_bridge_mode_set,
  171. .destroy = hdmi_bridge_destroy,
  172. };
  173. /* initialize bridge */
  174. struct drm_bridge *hdmi_bridge_init(struct hdmi *hdmi)
  175. {
  176. struct drm_bridge *bridge = NULL;
  177. struct hdmi_bridge *hdmi_bridge;
  178. int ret;
  179. hdmi_bridge = kzalloc(sizeof(*hdmi_bridge), GFP_KERNEL);
  180. if (!hdmi_bridge) {
  181. ret = -ENOMEM;
  182. goto fail;
  183. }
  184. hdmi_bridge->hdmi = hdmi_reference(hdmi);
  185. bridge = &hdmi_bridge->base;
  186. drm_bridge_init(hdmi->dev, bridge, &hdmi_bridge_funcs);
  187. return bridge;
  188. fail:
  189. if (bridge)
  190. hdmi_bridge_destroy(bridge);
  191. return ERR_PTR(ret);
  192. }