intel_sdvo.c 92 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/export.h>
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_edid.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "intel_sdvo_regs.h"
  39. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  40. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  41. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  42. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
  43. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  44. SDVO_TV_MASK)
  45. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  46. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  47. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  48. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  49. #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
  50. static const char *tv_format_names[] = {
  51. "NTSC_M" , "NTSC_J" , "NTSC_443",
  52. "PAL_B" , "PAL_D" , "PAL_G" ,
  53. "PAL_H" , "PAL_I" , "PAL_M" ,
  54. "PAL_N" , "PAL_NC" , "PAL_60" ,
  55. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  56. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  57. "SECAM_60"
  58. };
  59. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  60. struct intel_sdvo {
  61. struct intel_encoder base;
  62. struct i2c_adapter *i2c;
  63. u8 slave_addr;
  64. struct i2c_adapter ddc;
  65. /* Register for the SDVO device: SDVOB or SDVOC */
  66. uint32_t sdvo_reg;
  67. /* Active outputs controlled by this SDVO output */
  68. uint16_t controlled_output;
  69. /*
  70. * Capabilities of the SDVO device returned by
  71. * intel_sdvo_get_capabilities()
  72. */
  73. struct intel_sdvo_caps caps;
  74. /* Pixel clock limitations reported by the SDVO device, in kHz */
  75. int pixel_clock_min, pixel_clock_max;
  76. /*
  77. * For multiple function SDVO device,
  78. * this is for current attached outputs.
  79. */
  80. uint16_t attached_output;
  81. /*
  82. * Hotplug activation bits for this device
  83. */
  84. uint16_t hotplug_active;
  85. /**
  86. * This is used to select the color range of RBG outputs in HDMI mode.
  87. * It is only valid when using TMDS encoding and 8 bit per color mode.
  88. */
  89. uint32_t color_range;
  90. bool color_range_auto;
  91. /**
  92. * This is set if we're going to treat the device as TV-out.
  93. *
  94. * While we have these nice friendly flags for output types that ought
  95. * to decide this for us, the S-Video output on our HDMI+S-Video card
  96. * shows up as RGB1 (VGA).
  97. */
  98. bool is_tv;
  99. /* On different gens SDVOB is at different places. */
  100. bool is_sdvob;
  101. /* This is for current tv format name */
  102. int tv_format_index;
  103. /**
  104. * This is set if we treat the device as HDMI, instead of DVI.
  105. */
  106. bool is_hdmi;
  107. bool has_hdmi_monitor;
  108. bool has_hdmi_audio;
  109. bool rgb_quant_range_selectable;
  110. /**
  111. * This is set if we detect output of sdvo device as LVDS and
  112. * have a valid fixed mode to use with the panel.
  113. */
  114. bool is_lvds;
  115. /**
  116. * This is sdvo fixed pannel mode pointer
  117. */
  118. struct drm_display_mode *sdvo_lvds_fixed_mode;
  119. /* DDC bus used by this SDVO encoder */
  120. uint8_t ddc_bus;
  121. /*
  122. * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
  123. */
  124. uint8_t dtd_sdvo_flags;
  125. };
  126. struct intel_sdvo_connector {
  127. struct intel_connector base;
  128. /* Mark the type of connector */
  129. uint16_t output_flag;
  130. enum hdmi_force_audio force_audio;
  131. /* This contains all current supported TV format */
  132. u8 tv_format_supported[TV_FORMAT_NUM];
  133. int format_supported_num;
  134. struct drm_property *tv_format;
  135. /* add the property for the SDVO-TV */
  136. struct drm_property *left;
  137. struct drm_property *right;
  138. struct drm_property *top;
  139. struct drm_property *bottom;
  140. struct drm_property *hpos;
  141. struct drm_property *vpos;
  142. struct drm_property *contrast;
  143. struct drm_property *saturation;
  144. struct drm_property *hue;
  145. struct drm_property *sharpness;
  146. struct drm_property *flicker_filter;
  147. struct drm_property *flicker_filter_adaptive;
  148. struct drm_property *flicker_filter_2d;
  149. struct drm_property *tv_chroma_filter;
  150. struct drm_property *tv_luma_filter;
  151. struct drm_property *dot_crawl;
  152. /* add the property for the SDVO-TV/LVDS */
  153. struct drm_property *brightness;
  154. /* Add variable to record current setting for the above property */
  155. u32 left_margin, right_margin, top_margin, bottom_margin;
  156. /* this is to get the range of margin.*/
  157. u32 max_hscan, max_vscan;
  158. u32 max_hpos, cur_hpos;
  159. u32 max_vpos, cur_vpos;
  160. u32 cur_brightness, max_brightness;
  161. u32 cur_contrast, max_contrast;
  162. u32 cur_saturation, max_saturation;
  163. u32 cur_hue, max_hue;
  164. u32 cur_sharpness, max_sharpness;
  165. u32 cur_flicker_filter, max_flicker_filter;
  166. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  167. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  168. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  169. u32 cur_tv_luma_filter, max_tv_luma_filter;
  170. u32 cur_dot_crawl, max_dot_crawl;
  171. };
  172. static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
  173. {
  174. return container_of(encoder, struct intel_sdvo, base);
  175. }
  176. static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  177. {
  178. return to_sdvo(intel_attached_encoder(connector));
  179. }
  180. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  181. {
  182. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  183. }
  184. static bool
  185. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  186. static bool
  187. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  188. struct intel_sdvo_connector *intel_sdvo_connector,
  189. int type);
  190. static bool
  191. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  192. struct intel_sdvo_connector *intel_sdvo_connector);
  193. /**
  194. * Writes the SDVOB or SDVOC with the given value, but always writes both
  195. * SDVOB and SDVOC to work around apparent hardware issues (according to
  196. * comments in the BIOS).
  197. */
  198. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  199. {
  200. struct drm_device *dev = intel_sdvo->base.base.dev;
  201. struct drm_i915_private *dev_priv = dev->dev_private;
  202. u32 bval = val, cval = val;
  203. int i;
  204. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  205. I915_WRITE(intel_sdvo->sdvo_reg, val);
  206. I915_READ(intel_sdvo->sdvo_reg);
  207. return;
  208. }
  209. if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
  210. cval = I915_READ(GEN3_SDVOC);
  211. else
  212. bval = I915_READ(GEN3_SDVOB);
  213. /*
  214. * Write the registers twice for luck. Sometimes,
  215. * writing them only once doesn't appear to 'stick'.
  216. * The BIOS does this too. Yay, magic
  217. */
  218. for (i = 0; i < 2; i++)
  219. {
  220. I915_WRITE(GEN3_SDVOB, bval);
  221. I915_READ(GEN3_SDVOB);
  222. I915_WRITE(GEN3_SDVOC, cval);
  223. I915_READ(GEN3_SDVOC);
  224. }
  225. }
  226. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  227. {
  228. struct i2c_msg msgs[] = {
  229. {
  230. .addr = intel_sdvo->slave_addr,
  231. .flags = 0,
  232. .len = 1,
  233. .buf = &addr,
  234. },
  235. {
  236. .addr = intel_sdvo->slave_addr,
  237. .flags = I2C_M_RD,
  238. .len = 1,
  239. .buf = ch,
  240. }
  241. };
  242. int ret;
  243. if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
  244. return true;
  245. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  246. return false;
  247. }
  248. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  249. /** Mapping of command numbers to names, for debug output */
  250. static const struct _sdvo_cmd_name {
  251. u8 cmd;
  252. const char *name;
  253. } sdvo_cmd_names[] = {
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  297. /* Add the op code for SDVO enhancements */
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  342. /* HDMI op code */
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  355. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  356. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  357. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  358. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  359. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  360. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  361. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  362. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  363. };
  364. #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
  365. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  366. const void *args, int args_len)
  367. {
  368. int i, pos = 0;
  369. #define BUF_LEN 256
  370. char buffer[BUF_LEN];
  371. #define BUF_PRINT(args...) \
  372. pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
  373. for (i = 0; i < args_len; i++) {
  374. BUF_PRINT("%02X ", ((u8 *)args)[i]);
  375. }
  376. for (; i < 8; i++) {
  377. BUF_PRINT(" ");
  378. }
  379. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  380. if (cmd == sdvo_cmd_names[i].cmd) {
  381. BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
  382. break;
  383. }
  384. }
  385. if (i == ARRAY_SIZE(sdvo_cmd_names)) {
  386. BUF_PRINT("(%02X)", cmd);
  387. }
  388. BUG_ON(pos >= BUF_LEN - 1);
  389. #undef BUF_PRINT
  390. #undef BUF_LEN
  391. DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
  392. }
  393. static const char *cmd_status_names[] = {
  394. "Power on",
  395. "Success",
  396. "Not supported",
  397. "Invalid arg",
  398. "Pending",
  399. "Target not specified",
  400. "Scaling not supported"
  401. };
  402. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  403. const void *args, int args_len)
  404. {
  405. u8 *buf, status;
  406. struct i2c_msg *msgs;
  407. int i, ret = true;
  408. /* Would be simpler to allocate both in one go ? */
  409. buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
  410. if (!buf)
  411. return false;
  412. msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
  413. if (!msgs) {
  414. kfree(buf);
  415. return false;
  416. }
  417. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  418. for (i = 0; i < args_len; i++) {
  419. msgs[i].addr = intel_sdvo->slave_addr;
  420. msgs[i].flags = 0;
  421. msgs[i].len = 2;
  422. msgs[i].buf = buf + 2 *i;
  423. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  424. buf[2*i + 1] = ((u8*)args)[i];
  425. }
  426. msgs[i].addr = intel_sdvo->slave_addr;
  427. msgs[i].flags = 0;
  428. msgs[i].len = 2;
  429. msgs[i].buf = buf + 2*i;
  430. buf[2*i + 0] = SDVO_I2C_OPCODE;
  431. buf[2*i + 1] = cmd;
  432. /* the following two are to read the response */
  433. status = SDVO_I2C_CMD_STATUS;
  434. msgs[i+1].addr = intel_sdvo->slave_addr;
  435. msgs[i+1].flags = 0;
  436. msgs[i+1].len = 1;
  437. msgs[i+1].buf = &status;
  438. msgs[i+2].addr = intel_sdvo->slave_addr;
  439. msgs[i+2].flags = I2C_M_RD;
  440. msgs[i+2].len = 1;
  441. msgs[i+2].buf = &status;
  442. ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
  443. if (ret < 0) {
  444. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  445. ret = false;
  446. goto out;
  447. }
  448. if (ret != i+3) {
  449. /* failure in I2C transfer */
  450. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  451. ret = false;
  452. }
  453. out:
  454. kfree(msgs);
  455. kfree(buf);
  456. return ret;
  457. }
  458. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  459. void *response, int response_len)
  460. {
  461. u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
  462. u8 status;
  463. int i, pos = 0;
  464. #define BUF_LEN 256
  465. char buffer[BUF_LEN];
  466. /*
  467. * The documentation states that all commands will be
  468. * processed within 15µs, and that we need only poll
  469. * the status byte a maximum of 3 times in order for the
  470. * command to be complete.
  471. *
  472. * Check 5 times in case the hardware failed to read the docs.
  473. *
  474. * Also beware that the first response by many devices is to
  475. * reply PENDING and stall for time. TVs are notorious for
  476. * requiring longer than specified to complete their replies.
  477. * Originally (in the DDX long ago), the delay was only ever 15ms
  478. * with an additional delay of 30ms applied for TVs added later after
  479. * many experiments. To accommodate both sets of delays, we do a
  480. * sequence of slow checks if the device is falling behind and fails
  481. * to reply within 5*15µs.
  482. */
  483. if (!intel_sdvo_read_byte(intel_sdvo,
  484. SDVO_I2C_CMD_STATUS,
  485. &status))
  486. goto log_fail;
  487. while ((status == SDVO_CMD_STATUS_PENDING ||
  488. status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
  489. if (retry < 10)
  490. msleep(15);
  491. else
  492. udelay(15);
  493. if (!intel_sdvo_read_byte(intel_sdvo,
  494. SDVO_I2C_CMD_STATUS,
  495. &status))
  496. goto log_fail;
  497. }
  498. #define BUF_PRINT(args...) \
  499. pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
  500. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  501. BUF_PRINT("(%s)", cmd_status_names[status]);
  502. else
  503. BUF_PRINT("(??? %d)", status);
  504. if (status != SDVO_CMD_STATUS_SUCCESS)
  505. goto log_fail;
  506. /* Read the command response */
  507. for (i = 0; i < response_len; i++) {
  508. if (!intel_sdvo_read_byte(intel_sdvo,
  509. SDVO_I2C_RETURN_0 + i,
  510. &((u8 *)response)[i]))
  511. goto log_fail;
  512. BUF_PRINT(" %02X", ((u8 *)response)[i]);
  513. }
  514. BUG_ON(pos >= BUF_LEN - 1);
  515. #undef BUF_PRINT
  516. #undef BUF_LEN
  517. DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
  518. return true;
  519. log_fail:
  520. DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
  521. return false;
  522. }
  523. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  524. {
  525. if (mode->clock >= 100000)
  526. return 1;
  527. else if (mode->clock >= 50000)
  528. return 2;
  529. else
  530. return 4;
  531. }
  532. static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  533. u8 ddc_bus)
  534. {
  535. /* This must be the immediately preceding write before the i2c xfer */
  536. return intel_sdvo_write_cmd(intel_sdvo,
  537. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  538. &ddc_bus, 1);
  539. }
  540. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  541. {
  542. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  543. return false;
  544. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  545. }
  546. static bool
  547. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  548. {
  549. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  550. return false;
  551. return intel_sdvo_read_response(intel_sdvo, value, len);
  552. }
  553. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  554. {
  555. struct intel_sdvo_set_target_input_args targets = {0};
  556. return intel_sdvo_set_value(intel_sdvo,
  557. SDVO_CMD_SET_TARGET_INPUT,
  558. &targets, sizeof(targets));
  559. }
  560. /**
  561. * Return whether each input is trained.
  562. *
  563. * This function is making an assumption about the layout of the response,
  564. * which should be checked against the docs.
  565. */
  566. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  567. {
  568. struct intel_sdvo_get_trained_inputs_response response;
  569. BUILD_BUG_ON(sizeof(response) != 1);
  570. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  571. &response, sizeof(response)))
  572. return false;
  573. *input_1 = response.input0_trained;
  574. *input_2 = response.input1_trained;
  575. return true;
  576. }
  577. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  578. u16 outputs)
  579. {
  580. return intel_sdvo_set_value(intel_sdvo,
  581. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  582. &outputs, sizeof(outputs));
  583. }
  584. static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
  585. u16 *outputs)
  586. {
  587. return intel_sdvo_get_value(intel_sdvo,
  588. SDVO_CMD_GET_ACTIVE_OUTPUTS,
  589. outputs, sizeof(*outputs));
  590. }
  591. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  592. int mode)
  593. {
  594. u8 state = SDVO_ENCODER_STATE_ON;
  595. switch (mode) {
  596. case DRM_MODE_DPMS_ON:
  597. state = SDVO_ENCODER_STATE_ON;
  598. break;
  599. case DRM_MODE_DPMS_STANDBY:
  600. state = SDVO_ENCODER_STATE_STANDBY;
  601. break;
  602. case DRM_MODE_DPMS_SUSPEND:
  603. state = SDVO_ENCODER_STATE_SUSPEND;
  604. break;
  605. case DRM_MODE_DPMS_OFF:
  606. state = SDVO_ENCODER_STATE_OFF;
  607. break;
  608. }
  609. return intel_sdvo_set_value(intel_sdvo,
  610. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  611. }
  612. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  613. int *clock_min,
  614. int *clock_max)
  615. {
  616. struct intel_sdvo_pixel_clock_range clocks;
  617. BUILD_BUG_ON(sizeof(clocks) != 4);
  618. if (!intel_sdvo_get_value(intel_sdvo,
  619. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  620. &clocks, sizeof(clocks)))
  621. return false;
  622. /* Convert the values from units of 10 kHz to kHz. */
  623. *clock_min = clocks.min * 10;
  624. *clock_max = clocks.max * 10;
  625. return true;
  626. }
  627. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  628. u16 outputs)
  629. {
  630. return intel_sdvo_set_value(intel_sdvo,
  631. SDVO_CMD_SET_TARGET_OUTPUT,
  632. &outputs, sizeof(outputs));
  633. }
  634. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  635. struct intel_sdvo_dtd *dtd)
  636. {
  637. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  638. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  639. }
  640. static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  641. struct intel_sdvo_dtd *dtd)
  642. {
  643. return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  644. intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  645. }
  646. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  647. struct intel_sdvo_dtd *dtd)
  648. {
  649. return intel_sdvo_set_timing(intel_sdvo,
  650. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  651. }
  652. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  653. struct intel_sdvo_dtd *dtd)
  654. {
  655. return intel_sdvo_set_timing(intel_sdvo,
  656. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  657. }
  658. static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
  659. struct intel_sdvo_dtd *dtd)
  660. {
  661. return intel_sdvo_get_timing(intel_sdvo,
  662. SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
  663. }
  664. static bool
  665. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  666. uint16_t clock,
  667. uint16_t width,
  668. uint16_t height)
  669. {
  670. struct intel_sdvo_preferred_input_timing_args args;
  671. memset(&args, 0, sizeof(args));
  672. args.clock = clock;
  673. args.width = width;
  674. args.height = height;
  675. args.interlace = 0;
  676. if (intel_sdvo->is_lvds &&
  677. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  678. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  679. args.scaled = 1;
  680. return intel_sdvo_set_value(intel_sdvo,
  681. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  682. &args, sizeof(args));
  683. }
  684. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  685. struct intel_sdvo_dtd *dtd)
  686. {
  687. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  688. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  689. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  690. &dtd->part1, sizeof(dtd->part1)) &&
  691. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  692. &dtd->part2, sizeof(dtd->part2));
  693. }
  694. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  695. {
  696. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  697. }
  698. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  699. const struct drm_display_mode *mode)
  700. {
  701. uint16_t width, height;
  702. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  703. uint16_t h_sync_offset, v_sync_offset;
  704. int mode_clock;
  705. memset(dtd, 0, sizeof(*dtd));
  706. width = mode->hdisplay;
  707. height = mode->vdisplay;
  708. /* do some mode translations */
  709. h_blank_len = mode->htotal - mode->hdisplay;
  710. h_sync_len = mode->hsync_end - mode->hsync_start;
  711. v_blank_len = mode->vtotal - mode->vdisplay;
  712. v_sync_len = mode->vsync_end - mode->vsync_start;
  713. h_sync_offset = mode->hsync_start - mode->hdisplay;
  714. v_sync_offset = mode->vsync_start - mode->vdisplay;
  715. mode_clock = mode->clock;
  716. mode_clock /= 10;
  717. dtd->part1.clock = mode_clock;
  718. dtd->part1.h_active = width & 0xff;
  719. dtd->part1.h_blank = h_blank_len & 0xff;
  720. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  721. ((h_blank_len >> 8) & 0xf);
  722. dtd->part1.v_active = height & 0xff;
  723. dtd->part1.v_blank = v_blank_len & 0xff;
  724. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  725. ((v_blank_len >> 8) & 0xf);
  726. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  727. dtd->part2.h_sync_width = h_sync_len & 0xff;
  728. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  729. (v_sync_len & 0xf);
  730. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  731. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  732. ((v_sync_len & 0x30) >> 4);
  733. dtd->part2.dtd_flags = 0x18;
  734. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  735. dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
  736. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  737. dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
  738. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  739. dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
  740. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  741. }
  742. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
  743. const struct intel_sdvo_dtd *dtd)
  744. {
  745. struct drm_display_mode mode = {};
  746. mode.hdisplay = dtd->part1.h_active;
  747. mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  748. mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
  749. mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  750. mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
  751. mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  752. mode.htotal = mode.hdisplay + dtd->part1.h_blank;
  753. mode.htotal += (dtd->part1.h_high & 0xf) << 8;
  754. mode.vdisplay = dtd->part1.v_active;
  755. mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  756. mode.vsync_start = mode.vdisplay;
  757. mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  758. mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  759. mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  760. mode.vsync_end = mode.vsync_start +
  761. (dtd->part2.v_sync_off_width & 0xf);
  762. mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  763. mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
  764. mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
  765. mode.clock = dtd->part1.clock * 10;
  766. if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
  767. mode.flags |= DRM_MODE_FLAG_INTERLACE;
  768. if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
  769. mode.flags |= DRM_MODE_FLAG_PHSYNC;
  770. else
  771. mode.flags |= DRM_MODE_FLAG_NHSYNC;
  772. if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
  773. mode.flags |= DRM_MODE_FLAG_PVSYNC;
  774. else
  775. mode.flags |= DRM_MODE_FLAG_NVSYNC;
  776. drm_mode_set_crtcinfo(&mode, 0);
  777. drm_mode_copy(pmode, &mode);
  778. }
  779. static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
  780. {
  781. struct intel_sdvo_encode encode;
  782. BUILD_BUG_ON(sizeof(encode) != 2);
  783. return intel_sdvo_get_value(intel_sdvo,
  784. SDVO_CMD_GET_SUPP_ENCODE,
  785. &encode, sizeof(encode));
  786. }
  787. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  788. uint8_t mode)
  789. {
  790. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  791. }
  792. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  793. uint8_t mode)
  794. {
  795. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  796. }
  797. #if 0
  798. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  799. {
  800. int i, j;
  801. uint8_t set_buf_index[2];
  802. uint8_t av_split;
  803. uint8_t buf_size;
  804. uint8_t buf[48];
  805. uint8_t *pos;
  806. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  807. for (i = 0; i <= av_split; i++) {
  808. set_buf_index[0] = i; set_buf_index[1] = 0;
  809. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  810. set_buf_index, 2);
  811. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  812. intel_sdvo_read_response(encoder, &buf_size, 1);
  813. pos = buf;
  814. for (j = 0; j <= buf_size; j += 8) {
  815. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  816. NULL, 0);
  817. intel_sdvo_read_response(encoder, pos, 8);
  818. pos += 8;
  819. }
  820. }
  821. }
  822. #endif
  823. static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
  824. unsigned if_index, uint8_t tx_rate,
  825. const uint8_t *data, unsigned length)
  826. {
  827. uint8_t set_buf_index[2] = { if_index, 0 };
  828. uint8_t hbuf_size, tmp[8];
  829. int i;
  830. if (!intel_sdvo_set_value(intel_sdvo,
  831. SDVO_CMD_SET_HBUF_INDEX,
  832. set_buf_index, 2))
  833. return false;
  834. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
  835. &hbuf_size, 1))
  836. return false;
  837. /* Buffer size is 0 based, hooray! */
  838. hbuf_size++;
  839. DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
  840. if_index, length, hbuf_size);
  841. for (i = 0; i < hbuf_size; i += 8) {
  842. memset(tmp, 0, 8);
  843. if (i < length)
  844. memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
  845. if (!intel_sdvo_set_value(intel_sdvo,
  846. SDVO_CMD_SET_HBUF_DATA,
  847. tmp, 8))
  848. return false;
  849. }
  850. return intel_sdvo_set_value(intel_sdvo,
  851. SDVO_CMD_SET_HBUF_TXRATE,
  852. &tx_rate, 1);
  853. }
  854. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
  855. const struct drm_display_mode *adjusted_mode)
  856. {
  857. uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
  858. struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
  859. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  860. union hdmi_infoframe frame;
  861. int ret;
  862. ssize_t len;
  863. ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
  864. adjusted_mode);
  865. if (ret < 0) {
  866. DRM_ERROR("couldn't fill AVI infoframe\n");
  867. return false;
  868. }
  869. if (intel_sdvo->rgb_quant_range_selectable) {
  870. if (intel_crtc->config.limited_color_range)
  871. frame.avi.quantization_range =
  872. HDMI_QUANTIZATION_RANGE_LIMITED;
  873. else
  874. frame.avi.quantization_range =
  875. HDMI_QUANTIZATION_RANGE_FULL;
  876. }
  877. len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
  878. if (len < 0)
  879. return false;
  880. return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
  881. SDVO_HBUF_TX_VSYNC,
  882. sdvo_data, sizeof(sdvo_data));
  883. }
  884. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  885. {
  886. struct intel_sdvo_tv_format format;
  887. uint32_t format_map;
  888. format_map = 1 << intel_sdvo->tv_format_index;
  889. memset(&format, 0, sizeof(format));
  890. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  891. BUILD_BUG_ON(sizeof(format) != 6);
  892. return intel_sdvo_set_value(intel_sdvo,
  893. SDVO_CMD_SET_TV_FORMAT,
  894. &format, sizeof(format));
  895. }
  896. static bool
  897. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  898. const struct drm_display_mode *mode)
  899. {
  900. struct intel_sdvo_dtd output_dtd;
  901. if (!intel_sdvo_set_target_output(intel_sdvo,
  902. intel_sdvo->attached_output))
  903. return false;
  904. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  905. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  906. return false;
  907. return true;
  908. }
  909. /* Asks the sdvo controller for the preferred input mode given the output mode.
  910. * Unfortunately we have to set up the full output mode to do that. */
  911. static bool
  912. intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
  913. const struct drm_display_mode *mode,
  914. struct drm_display_mode *adjusted_mode)
  915. {
  916. struct intel_sdvo_dtd input_dtd;
  917. /* Reset the input timing to the screen. Assume always input 0. */
  918. if (!intel_sdvo_set_target_input(intel_sdvo))
  919. return false;
  920. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  921. mode->clock / 10,
  922. mode->hdisplay,
  923. mode->vdisplay))
  924. return false;
  925. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  926. &input_dtd))
  927. return false;
  928. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  929. intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
  930. return true;
  931. }
  932. static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
  933. {
  934. unsigned dotclock = pipe_config->port_clock;
  935. struct dpll *clock = &pipe_config->dpll;
  936. /* SDVO TV has fixed PLL values depend on its clock range,
  937. this mirrors vbios setting. */
  938. if (dotclock >= 100000 && dotclock < 140500) {
  939. clock->p1 = 2;
  940. clock->p2 = 10;
  941. clock->n = 3;
  942. clock->m1 = 16;
  943. clock->m2 = 8;
  944. } else if (dotclock >= 140500 && dotclock <= 200000) {
  945. clock->p1 = 1;
  946. clock->p2 = 10;
  947. clock->n = 6;
  948. clock->m1 = 12;
  949. clock->m2 = 8;
  950. } else {
  951. WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
  952. }
  953. pipe_config->clock_set = true;
  954. }
  955. static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
  956. struct intel_crtc_config *pipe_config)
  957. {
  958. struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
  959. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  960. struct drm_display_mode *mode = &pipe_config->requested_mode;
  961. DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
  962. pipe_config->pipe_bpp = 8*3;
  963. if (HAS_PCH_SPLIT(encoder->base.dev))
  964. pipe_config->has_pch_encoder = true;
  965. /* We need to construct preferred input timings based on our
  966. * output timings. To do that, we have to set the output
  967. * timings, even though this isn't really the right place in
  968. * the sequence to do it. Oh well.
  969. */
  970. if (intel_sdvo->is_tv) {
  971. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  972. return false;
  973. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  974. mode,
  975. adjusted_mode);
  976. pipe_config->sdvo_tv_clock = true;
  977. } else if (intel_sdvo->is_lvds) {
  978. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  979. intel_sdvo->sdvo_lvds_fixed_mode))
  980. return false;
  981. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  982. mode,
  983. adjusted_mode);
  984. }
  985. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  986. * SDVO device will factor out the multiplier during mode_set.
  987. */
  988. pipe_config->pixel_multiplier =
  989. intel_sdvo_get_pixel_multiplier(adjusted_mode);
  990. pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
  991. if (intel_sdvo->color_range_auto) {
  992. /* See CEA-861-E - 5.1 Default Encoding Parameters */
  993. /* FIXME: This bit is only valid when using TMDS encoding and 8
  994. * bit per color mode. */
  995. if (pipe_config->has_hdmi_sink &&
  996. drm_match_cea_mode(adjusted_mode) > 1)
  997. pipe_config->limited_color_range = true;
  998. } else {
  999. if (pipe_config->has_hdmi_sink &&
  1000. intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235)
  1001. pipe_config->limited_color_range = true;
  1002. }
  1003. /* Clock computation needs to happen after pixel multiplier. */
  1004. if (intel_sdvo->is_tv)
  1005. i9xx_adjust_sdvo_tv_clock(pipe_config);
  1006. return true;
  1007. }
  1008. static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
  1009. {
  1010. struct drm_device *dev = intel_encoder->base.dev;
  1011. struct drm_i915_private *dev_priv = dev->dev_private;
  1012. struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
  1013. struct drm_display_mode *adjusted_mode =
  1014. &crtc->config.adjusted_mode;
  1015. struct drm_display_mode *mode = &crtc->config.requested_mode;
  1016. struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
  1017. u32 sdvox;
  1018. struct intel_sdvo_in_out_map in_out;
  1019. struct intel_sdvo_dtd input_dtd, output_dtd;
  1020. int rate;
  1021. if (!mode)
  1022. return;
  1023. /* First, set the input mapping for the first input to our controlled
  1024. * output. This is only correct if we're a single-input device, in
  1025. * which case the first input is the output from the appropriate SDVO
  1026. * channel on the motherboard. In a two-input device, the first input
  1027. * will be SDVOB and the second SDVOC.
  1028. */
  1029. in_out.in0 = intel_sdvo->attached_output;
  1030. in_out.in1 = 0;
  1031. intel_sdvo_set_value(intel_sdvo,
  1032. SDVO_CMD_SET_IN_OUT_MAP,
  1033. &in_out, sizeof(in_out));
  1034. /* Set the output timings to the screen */
  1035. if (!intel_sdvo_set_target_output(intel_sdvo,
  1036. intel_sdvo->attached_output))
  1037. return;
  1038. /* lvds has a special fixed output timing. */
  1039. if (intel_sdvo->is_lvds)
  1040. intel_sdvo_get_dtd_from_mode(&output_dtd,
  1041. intel_sdvo->sdvo_lvds_fixed_mode);
  1042. else
  1043. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  1044. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  1045. DRM_INFO("Setting output timings on %s failed\n",
  1046. SDVO_NAME(intel_sdvo));
  1047. /* Set the input timing to the screen. Assume always input 0. */
  1048. if (!intel_sdvo_set_target_input(intel_sdvo))
  1049. return;
  1050. if (crtc->config.has_hdmi_sink) {
  1051. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  1052. intel_sdvo_set_colorimetry(intel_sdvo,
  1053. SDVO_COLORIMETRY_RGB256);
  1054. intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
  1055. } else
  1056. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
  1057. if (intel_sdvo->is_tv &&
  1058. !intel_sdvo_set_tv_format(intel_sdvo))
  1059. return;
  1060. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  1061. if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
  1062. input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
  1063. if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
  1064. DRM_INFO("Setting input timings on %s failed\n",
  1065. SDVO_NAME(intel_sdvo));
  1066. switch (crtc->config.pixel_multiplier) {
  1067. default:
  1068. WARN(1, "unknown pixel mutlipler specified\n");
  1069. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  1070. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  1071. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  1072. }
  1073. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  1074. return;
  1075. /* Set the SDVO control regs. */
  1076. if (INTEL_INFO(dev)->gen >= 4) {
  1077. /* The real mode polarity is set by the SDVO commands, using
  1078. * struct intel_sdvo_dtd. */
  1079. sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
  1080. if (!HAS_PCH_SPLIT(dev) && crtc->config.limited_color_range)
  1081. sdvox |= HDMI_COLOR_RANGE_16_235;
  1082. if (INTEL_INFO(dev)->gen < 5)
  1083. sdvox |= SDVO_BORDER_ENABLE;
  1084. } else {
  1085. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  1086. switch (intel_sdvo->sdvo_reg) {
  1087. case GEN3_SDVOB:
  1088. sdvox &= SDVOB_PRESERVE_MASK;
  1089. break;
  1090. case GEN3_SDVOC:
  1091. sdvox &= SDVOC_PRESERVE_MASK;
  1092. break;
  1093. }
  1094. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  1095. }
  1096. if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
  1097. sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
  1098. else
  1099. sdvox |= SDVO_PIPE_SEL(crtc->pipe);
  1100. if (intel_sdvo->has_hdmi_audio)
  1101. sdvox |= SDVO_AUDIO_ENABLE;
  1102. if (INTEL_INFO(dev)->gen >= 4) {
  1103. /* done in crtc_mode_set as the dpll_md reg must be written early */
  1104. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  1105. /* done in crtc_mode_set as it lives inside the dpll register */
  1106. } else {
  1107. sdvox |= (crtc->config.pixel_multiplier - 1)
  1108. << SDVO_PORT_MULTIPLY_SHIFT;
  1109. }
  1110. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
  1111. INTEL_INFO(dev)->gen < 5)
  1112. sdvox |= SDVO_STALL_SELECT;
  1113. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  1114. }
  1115. static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
  1116. {
  1117. struct intel_sdvo_connector *intel_sdvo_connector =
  1118. to_intel_sdvo_connector(&connector->base);
  1119. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
  1120. u16 active_outputs = 0;
  1121. intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
  1122. if (active_outputs & intel_sdvo_connector->output_flag)
  1123. return true;
  1124. else
  1125. return false;
  1126. }
  1127. static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
  1128. enum pipe *pipe)
  1129. {
  1130. struct drm_device *dev = encoder->base.dev;
  1131. struct drm_i915_private *dev_priv = dev->dev_private;
  1132. struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
  1133. u16 active_outputs = 0;
  1134. u32 tmp;
  1135. tmp = I915_READ(intel_sdvo->sdvo_reg);
  1136. intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
  1137. if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
  1138. return false;
  1139. if (HAS_PCH_CPT(dev))
  1140. *pipe = PORT_TO_PIPE_CPT(tmp);
  1141. else
  1142. *pipe = PORT_TO_PIPE(tmp);
  1143. return true;
  1144. }
  1145. static void intel_sdvo_get_config(struct intel_encoder *encoder,
  1146. struct intel_crtc_config *pipe_config)
  1147. {
  1148. struct drm_device *dev = encoder->base.dev;
  1149. struct drm_i915_private *dev_priv = dev->dev_private;
  1150. struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
  1151. struct intel_sdvo_dtd dtd;
  1152. int encoder_pixel_multiplier = 0;
  1153. int dotclock;
  1154. u32 flags = 0, sdvox;
  1155. u8 val;
  1156. bool ret;
  1157. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  1158. ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
  1159. if (!ret) {
  1160. /* Some sdvo encoders are not spec compliant and don't
  1161. * implement the mandatory get_timings function. */
  1162. DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
  1163. pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
  1164. } else {
  1165. if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
  1166. flags |= DRM_MODE_FLAG_PHSYNC;
  1167. else
  1168. flags |= DRM_MODE_FLAG_NHSYNC;
  1169. if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
  1170. flags |= DRM_MODE_FLAG_PVSYNC;
  1171. else
  1172. flags |= DRM_MODE_FLAG_NVSYNC;
  1173. }
  1174. pipe_config->adjusted_mode.flags |= flags;
  1175. /*
  1176. * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
  1177. * the sdvo port register, on all other platforms it is part of the dpll
  1178. * state. Since the general pipe state readout happens before the
  1179. * encoder->get_config we so already have a valid pixel multplier on all
  1180. * other platfroms.
  1181. */
  1182. if (IS_I915G(dev) || IS_I915GM(dev)) {
  1183. pipe_config->pixel_multiplier =
  1184. ((sdvox & SDVO_PORT_MULTIPLY_MASK)
  1185. >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
  1186. }
  1187. dotclock = pipe_config->port_clock;
  1188. if (pipe_config->pixel_multiplier)
  1189. dotclock /= pipe_config->pixel_multiplier;
  1190. if (HAS_PCH_SPLIT(dev))
  1191. ironlake_check_encoder_dotclock(pipe_config, dotclock);
  1192. pipe_config->adjusted_mode.crtc_clock = dotclock;
  1193. /* Cross check the port pixel multiplier with the sdvo encoder state. */
  1194. if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
  1195. &val, 1)) {
  1196. switch (val) {
  1197. case SDVO_CLOCK_RATE_MULT_1X:
  1198. encoder_pixel_multiplier = 1;
  1199. break;
  1200. case SDVO_CLOCK_RATE_MULT_2X:
  1201. encoder_pixel_multiplier = 2;
  1202. break;
  1203. case SDVO_CLOCK_RATE_MULT_4X:
  1204. encoder_pixel_multiplier = 4;
  1205. break;
  1206. }
  1207. }
  1208. if (sdvox & HDMI_COLOR_RANGE_16_235)
  1209. pipe_config->limited_color_range = true;
  1210. if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
  1211. &val, 1)) {
  1212. if (val == SDVO_ENCODE_HDMI)
  1213. pipe_config->has_hdmi_sink = true;
  1214. }
  1215. WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
  1216. "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
  1217. pipe_config->pixel_multiplier, encoder_pixel_multiplier);
  1218. }
  1219. static void intel_disable_sdvo(struct intel_encoder *encoder)
  1220. {
  1221. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  1222. struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
  1223. u32 temp;
  1224. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1225. if (0)
  1226. intel_sdvo_set_encoder_power_state(intel_sdvo,
  1227. DRM_MODE_DPMS_OFF);
  1228. temp = I915_READ(intel_sdvo->sdvo_reg);
  1229. if ((temp & SDVO_ENABLE) != 0) {
  1230. /* HW workaround for IBX, we need to move the port to
  1231. * transcoder A before disabling it. */
  1232. if (HAS_PCH_IBX(encoder->base.dev)) {
  1233. struct drm_crtc *crtc = encoder->base.crtc;
  1234. int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  1235. if (temp & SDVO_PIPE_B_SELECT) {
  1236. temp &= ~SDVO_PIPE_B_SELECT;
  1237. I915_WRITE(intel_sdvo->sdvo_reg, temp);
  1238. POSTING_READ(intel_sdvo->sdvo_reg);
  1239. /* Again we need to write this twice. */
  1240. I915_WRITE(intel_sdvo->sdvo_reg, temp);
  1241. POSTING_READ(intel_sdvo->sdvo_reg);
  1242. /* Transcoder selection bits only update
  1243. * effectively on vblank. */
  1244. if (crtc)
  1245. intel_wait_for_vblank(encoder->base.dev, pipe);
  1246. else
  1247. msleep(50);
  1248. }
  1249. }
  1250. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  1251. }
  1252. }
  1253. static void intel_enable_sdvo(struct intel_encoder *encoder)
  1254. {
  1255. struct drm_device *dev = encoder->base.dev;
  1256. struct drm_i915_private *dev_priv = dev->dev_private;
  1257. struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
  1258. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  1259. u32 temp;
  1260. bool input1, input2;
  1261. int i;
  1262. bool success;
  1263. temp = I915_READ(intel_sdvo->sdvo_reg);
  1264. if ((temp & SDVO_ENABLE) == 0) {
  1265. /* HW workaround for IBX, we need to move the port
  1266. * to transcoder A before disabling it, so restore it here. */
  1267. if (HAS_PCH_IBX(dev))
  1268. temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
  1269. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  1270. }
  1271. for (i = 0; i < 2; i++)
  1272. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1273. success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  1274. /* Warn if the device reported failure to sync.
  1275. * A lot of SDVO devices fail to notify of sync, but it's
  1276. * a given it the status is a success, we succeeded.
  1277. */
  1278. if (success && !input1) {
  1279. DRM_DEBUG_KMS("First %s output reported failure to "
  1280. "sync\n", SDVO_NAME(intel_sdvo));
  1281. }
  1282. if (0)
  1283. intel_sdvo_set_encoder_power_state(intel_sdvo,
  1284. DRM_MODE_DPMS_ON);
  1285. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1286. }
  1287. /* Special dpms function to support cloning between dvo/sdvo/crt. */
  1288. static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
  1289. {
  1290. struct drm_crtc *crtc;
  1291. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1292. /* dvo supports only 2 dpms states. */
  1293. if (mode != DRM_MODE_DPMS_ON)
  1294. mode = DRM_MODE_DPMS_OFF;
  1295. if (mode == connector->dpms)
  1296. return;
  1297. connector->dpms = mode;
  1298. /* Only need to change hw state when actually enabled */
  1299. crtc = intel_sdvo->base.base.crtc;
  1300. if (!crtc) {
  1301. intel_sdvo->base.connectors_active = false;
  1302. return;
  1303. }
  1304. /* We set active outputs manually below in case pipe dpms doesn't change
  1305. * due to cloning. */
  1306. if (mode != DRM_MODE_DPMS_ON) {
  1307. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1308. if (0)
  1309. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1310. intel_sdvo->base.connectors_active = false;
  1311. intel_crtc_update_dpms(crtc);
  1312. } else {
  1313. intel_sdvo->base.connectors_active = true;
  1314. intel_crtc_update_dpms(crtc);
  1315. if (0)
  1316. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1317. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1318. }
  1319. intel_modeset_check_state(connector->dev);
  1320. }
  1321. static enum drm_mode_status
  1322. intel_sdvo_mode_valid(struct drm_connector *connector,
  1323. struct drm_display_mode *mode)
  1324. {
  1325. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1326. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1327. return MODE_NO_DBLESCAN;
  1328. if (intel_sdvo->pixel_clock_min > mode->clock)
  1329. return MODE_CLOCK_LOW;
  1330. if (intel_sdvo->pixel_clock_max < mode->clock)
  1331. return MODE_CLOCK_HIGH;
  1332. if (intel_sdvo->is_lvds) {
  1333. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1334. return MODE_PANEL;
  1335. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1336. return MODE_PANEL;
  1337. }
  1338. return MODE_OK;
  1339. }
  1340. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1341. {
  1342. BUILD_BUG_ON(sizeof(*caps) != 8);
  1343. if (!intel_sdvo_get_value(intel_sdvo,
  1344. SDVO_CMD_GET_DEVICE_CAPS,
  1345. caps, sizeof(*caps)))
  1346. return false;
  1347. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1348. " vendor_id: %d\n"
  1349. " device_id: %d\n"
  1350. " device_rev_id: %d\n"
  1351. " sdvo_version_major: %d\n"
  1352. " sdvo_version_minor: %d\n"
  1353. " sdvo_inputs_mask: %d\n"
  1354. " smooth_scaling: %d\n"
  1355. " sharp_scaling: %d\n"
  1356. " up_scaling: %d\n"
  1357. " down_scaling: %d\n"
  1358. " stall_support: %d\n"
  1359. " output_flags: %d\n",
  1360. caps->vendor_id,
  1361. caps->device_id,
  1362. caps->device_rev_id,
  1363. caps->sdvo_version_major,
  1364. caps->sdvo_version_minor,
  1365. caps->sdvo_inputs_mask,
  1366. caps->smooth_scaling,
  1367. caps->sharp_scaling,
  1368. caps->up_scaling,
  1369. caps->down_scaling,
  1370. caps->stall_support,
  1371. caps->output_flags);
  1372. return true;
  1373. }
  1374. static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
  1375. {
  1376. struct drm_device *dev = intel_sdvo->base.base.dev;
  1377. uint16_t hotplug;
  1378. /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
  1379. * on the line. */
  1380. if (IS_I945G(dev) || IS_I945GM(dev))
  1381. return 0;
  1382. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1383. &hotplug, sizeof(hotplug)))
  1384. return 0;
  1385. return hotplug;
  1386. }
  1387. static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
  1388. {
  1389. struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
  1390. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
  1391. &intel_sdvo->hotplug_active, 2);
  1392. }
  1393. static bool
  1394. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1395. {
  1396. /* Is there more than one type of output? */
  1397. return hweight16(intel_sdvo->caps.output_flags) > 1;
  1398. }
  1399. static struct edid *
  1400. intel_sdvo_get_edid(struct drm_connector *connector)
  1401. {
  1402. struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1403. return drm_get_edid(connector, &sdvo->ddc);
  1404. }
  1405. /* Mac mini hack -- use the same DDC as the analog connector */
  1406. static struct edid *
  1407. intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1408. {
  1409. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1410. return drm_get_edid(connector,
  1411. intel_gmbus_get_adapter(dev_priv,
  1412. dev_priv->vbt.crt_ddc_pin));
  1413. }
  1414. static enum drm_connector_status
  1415. intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
  1416. {
  1417. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1418. enum drm_connector_status status;
  1419. struct edid *edid;
  1420. edid = intel_sdvo_get_edid(connector);
  1421. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1422. u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
  1423. /*
  1424. * Don't use the 1 as the argument of DDC bus switch to get
  1425. * the EDID. It is used for SDVO SPD ROM.
  1426. */
  1427. for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1428. intel_sdvo->ddc_bus = ddc;
  1429. edid = intel_sdvo_get_edid(connector);
  1430. if (edid)
  1431. break;
  1432. }
  1433. /*
  1434. * If we found the EDID on the other bus,
  1435. * assume that is the correct DDC bus.
  1436. */
  1437. if (edid == NULL)
  1438. intel_sdvo->ddc_bus = saved_ddc;
  1439. }
  1440. /*
  1441. * When there is no edid and no monitor is connected with VGA
  1442. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1443. */
  1444. if (edid == NULL)
  1445. edid = intel_sdvo_get_analog_edid(connector);
  1446. status = connector_status_unknown;
  1447. if (edid != NULL) {
  1448. /* DDC bus is shared, match EDID to connector type */
  1449. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1450. status = connector_status_connected;
  1451. if (intel_sdvo->is_hdmi) {
  1452. intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1453. intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1454. intel_sdvo->rgb_quant_range_selectable =
  1455. drm_rgb_quant_range_selectable(edid);
  1456. }
  1457. } else
  1458. status = connector_status_disconnected;
  1459. kfree(edid);
  1460. }
  1461. if (status == connector_status_connected) {
  1462. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1463. if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
  1464. intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
  1465. }
  1466. return status;
  1467. }
  1468. static bool
  1469. intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
  1470. struct edid *edid)
  1471. {
  1472. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1473. bool connector_is_digital = !!IS_DIGITAL(sdvo);
  1474. DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
  1475. connector_is_digital, monitor_is_digital);
  1476. return connector_is_digital == monitor_is_digital;
  1477. }
  1478. static enum drm_connector_status
  1479. intel_sdvo_detect(struct drm_connector *connector, bool force)
  1480. {
  1481. uint16_t response;
  1482. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1483. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1484. enum drm_connector_status ret;
  1485. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  1486. connector->base.id, connector->name);
  1487. if (!intel_sdvo_get_value(intel_sdvo,
  1488. SDVO_CMD_GET_ATTACHED_DISPLAYS,
  1489. &response, 2))
  1490. return connector_status_unknown;
  1491. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1492. response & 0xff, response >> 8,
  1493. intel_sdvo_connector->output_flag);
  1494. if (response == 0)
  1495. return connector_status_disconnected;
  1496. intel_sdvo->attached_output = response;
  1497. intel_sdvo->has_hdmi_monitor = false;
  1498. intel_sdvo->has_hdmi_audio = false;
  1499. intel_sdvo->rgb_quant_range_selectable = false;
  1500. if ((intel_sdvo_connector->output_flag & response) == 0)
  1501. ret = connector_status_disconnected;
  1502. else if (IS_TMDS(intel_sdvo_connector))
  1503. ret = intel_sdvo_tmds_sink_detect(connector);
  1504. else {
  1505. struct edid *edid;
  1506. /* if we have an edid check it matches the connection */
  1507. edid = intel_sdvo_get_edid(connector);
  1508. if (edid == NULL)
  1509. edid = intel_sdvo_get_analog_edid(connector);
  1510. if (edid != NULL) {
  1511. if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
  1512. edid))
  1513. ret = connector_status_connected;
  1514. else
  1515. ret = connector_status_disconnected;
  1516. kfree(edid);
  1517. } else
  1518. ret = connector_status_connected;
  1519. }
  1520. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1521. if (ret == connector_status_connected) {
  1522. intel_sdvo->is_tv = false;
  1523. intel_sdvo->is_lvds = false;
  1524. if (response & SDVO_TV_MASK)
  1525. intel_sdvo->is_tv = true;
  1526. if (response & SDVO_LVDS_MASK)
  1527. intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1528. }
  1529. return ret;
  1530. }
  1531. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1532. {
  1533. struct edid *edid;
  1534. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  1535. connector->base.id, connector->name);
  1536. /* set the bus switch and get the modes */
  1537. edid = intel_sdvo_get_edid(connector);
  1538. /*
  1539. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1540. * link between analog and digital outputs. So, if the regular SDVO
  1541. * DDC fails, check to see if the analog output is disconnected, in
  1542. * which case we'll look there for the digital DDC data.
  1543. */
  1544. if (edid == NULL)
  1545. edid = intel_sdvo_get_analog_edid(connector);
  1546. if (edid != NULL) {
  1547. if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
  1548. edid)) {
  1549. drm_mode_connector_update_edid_property(connector, edid);
  1550. drm_add_edid_modes(connector, edid);
  1551. }
  1552. kfree(edid);
  1553. }
  1554. }
  1555. /*
  1556. * Set of SDVO TV modes.
  1557. * Note! This is in reply order (see loop in get_tv_modes).
  1558. * XXX: all 60Hz refresh?
  1559. */
  1560. static const struct drm_display_mode sdvo_tv_modes[] = {
  1561. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1562. 416, 0, 200, 201, 232, 233, 0,
  1563. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1564. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1565. 416, 0, 240, 241, 272, 273, 0,
  1566. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1567. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1568. 496, 0, 300, 301, 332, 333, 0,
  1569. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1570. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1571. 736, 0, 350, 351, 382, 383, 0,
  1572. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1573. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1574. 736, 0, 400, 401, 432, 433, 0,
  1575. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1576. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1577. 736, 0, 480, 481, 512, 513, 0,
  1578. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1579. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1580. 800, 0, 480, 481, 512, 513, 0,
  1581. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1582. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1583. 800, 0, 576, 577, 608, 609, 0,
  1584. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1585. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1586. 816, 0, 350, 351, 382, 383, 0,
  1587. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1588. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1589. 816, 0, 400, 401, 432, 433, 0,
  1590. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1591. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1592. 816, 0, 480, 481, 512, 513, 0,
  1593. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1594. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1595. 816, 0, 540, 541, 572, 573, 0,
  1596. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1597. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1598. 816, 0, 576, 577, 608, 609, 0,
  1599. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1600. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1601. 864, 0, 576, 577, 608, 609, 0,
  1602. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1603. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1604. 896, 0, 600, 601, 632, 633, 0,
  1605. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1606. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1607. 928, 0, 624, 625, 656, 657, 0,
  1608. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1609. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1610. 1016, 0, 766, 767, 798, 799, 0,
  1611. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1612. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1613. 1120, 0, 768, 769, 800, 801, 0,
  1614. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1615. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1616. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1617. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1618. };
  1619. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1620. {
  1621. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1622. struct intel_sdvo_sdtv_resolution_request tv_res;
  1623. uint32_t reply = 0, format_map = 0;
  1624. int i;
  1625. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  1626. connector->base.id, connector->name);
  1627. /* Read the list of supported input resolutions for the selected TV
  1628. * format.
  1629. */
  1630. format_map = 1 << intel_sdvo->tv_format_index;
  1631. memcpy(&tv_res, &format_map,
  1632. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1633. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1634. return;
  1635. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1636. if (!intel_sdvo_write_cmd(intel_sdvo,
  1637. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1638. &tv_res, sizeof(tv_res)))
  1639. return;
  1640. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1641. return;
  1642. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1643. if (reply & (1 << i)) {
  1644. struct drm_display_mode *nmode;
  1645. nmode = drm_mode_duplicate(connector->dev,
  1646. &sdvo_tv_modes[i]);
  1647. if (nmode)
  1648. drm_mode_probed_add(connector, nmode);
  1649. }
  1650. }
  1651. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1652. {
  1653. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1654. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1655. struct drm_display_mode *newmode;
  1656. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  1657. connector->base.id, connector->name);
  1658. /*
  1659. * Fetch modes from VBT. For SDVO prefer the VBT mode since some
  1660. * SDVO->LVDS transcoders can't cope with the EDID mode.
  1661. */
  1662. if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
  1663. newmode = drm_mode_duplicate(connector->dev,
  1664. dev_priv->vbt.sdvo_lvds_vbt_mode);
  1665. if (newmode != NULL) {
  1666. /* Guarantee the mode is preferred */
  1667. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1668. DRM_MODE_TYPE_DRIVER);
  1669. drm_mode_probed_add(connector, newmode);
  1670. }
  1671. }
  1672. /*
  1673. * Attempt to get the mode list from DDC.
  1674. * Assume that the preferred modes are
  1675. * arranged in priority order.
  1676. */
  1677. intel_ddc_get_modes(connector, &intel_sdvo->ddc);
  1678. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1679. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1680. intel_sdvo->sdvo_lvds_fixed_mode =
  1681. drm_mode_duplicate(connector->dev, newmode);
  1682. intel_sdvo->is_lvds = true;
  1683. break;
  1684. }
  1685. }
  1686. }
  1687. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1688. {
  1689. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1690. if (IS_TV(intel_sdvo_connector))
  1691. intel_sdvo_get_tv_modes(connector);
  1692. else if (IS_LVDS(intel_sdvo_connector))
  1693. intel_sdvo_get_lvds_modes(connector);
  1694. else
  1695. intel_sdvo_get_ddc_modes(connector);
  1696. return !list_empty(&connector->probed_modes);
  1697. }
  1698. static void
  1699. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1700. {
  1701. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1702. struct drm_device *dev = connector->dev;
  1703. if (intel_sdvo_connector->left)
  1704. drm_property_destroy(dev, intel_sdvo_connector->left);
  1705. if (intel_sdvo_connector->right)
  1706. drm_property_destroy(dev, intel_sdvo_connector->right);
  1707. if (intel_sdvo_connector->top)
  1708. drm_property_destroy(dev, intel_sdvo_connector->top);
  1709. if (intel_sdvo_connector->bottom)
  1710. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1711. if (intel_sdvo_connector->hpos)
  1712. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1713. if (intel_sdvo_connector->vpos)
  1714. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1715. if (intel_sdvo_connector->saturation)
  1716. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1717. if (intel_sdvo_connector->contrast)
  1718. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1719. if (intel_sdvo_connector->hue)
  1720. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1721. if (intel_sdvo_connector->sharpness)
  1722. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1723. if (intel_sdvo_connector->flicker_filter)
  1724. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1725. if (intel_sdvo_connector->flicker_filter_2d)
  1726. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1727. if (intel_sdvo_connector->flicker_filter_adaptive)
  1728. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1729. if (intel_sdvo_connector->tv_luma_filter)
  1730. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1731. if (intel_sdvo_connector->tv_chroma_filter)
  1732. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1733. if (intel_sdvo_connector->dot_crawl)
  1734. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1735. if (intel_sdvo_connector->brightness)
  1736. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1737. }
  1738. static void intel_sdvo_destroy(struct drm_connector *connector)
  1739. {
  1740. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1741. if (intel_sdvo_connector->tv_format)
  1742. drm_property_destroy(connector->dev,
  1743. intel_sdvo_connector->tv_format);
  1744. intel_sdvo_destroy_enhance_property(connector);
  1745. drm_connector_cleanup(connector);
  1746. kfree(intel_sdvo_connector);
  1747. }
  1748. static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1749. {
  1750. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1751. struct edid *edid;
  1752. bool has_audio = false;
  1753. if (!intel_sdvo->is_hdmi)
  1754. return false;
  1755. edid = intel_sdvo_get_edid(connector);
  1756. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1757. has_audio = drm_detect_monitor_audio(edid);
  1758. kfree(edid);
  1759. return has_audio;
  1760. }
  1761. static int
  1762. intel_sdvo_set_property(struct drm_connector *connector,
  1763. struct drm_property *property,
  1764. uint64_t val)
  1765. {
  1766. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1767. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1768. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1769. uint16_t temp_value;
  1770. uint8_t cmd;
  1771. int ret;
  1772. ret = drm_object_property_set_value(&connector->base, property, val);
  1773. if (ret)
  1774. return ret;
  1775. if (property == dev_priv->force_audio_property) {
  1776. int i = val;
  1777. bool has_audio;
  1778. if (i == intel_sdvo_connector->force_audio)
  1779. return 0;
  1780. intel_sdvo_connector->force_audio = i;
  1781. if (i == HDMI_AUDIO_AUTO)
  1782. has_audio = intel_sdvo_detect_hdmi_audio(connector);
  1783. else
  1784. has_audio = (i == HDMI_AUDIO_ON);
  1785. if (has_audio == intel_sdvo->has_hdmi_audio)
  1786. return 0;
  1787. intel_sdvo->has_hdmi_audio = has_audio;
  1788. goto done;
  1789. }
  1790. if (property == dev_priv->broadcast_rgb_property) {
  1791. bool old_auto = intel_sdvo->color_range_auto;
  1792. uint32_t old_range = intel_sdvo->color_range;
  1793. switch (val) {
  1794. case INTEL_BROADCAST_RGB_AUTO:
  1795. intel_sdvo->color_range_auto = true;
  1796. break;
  1797. case INTEL_BROADCAST_RGB_FULL:
  1798. intel_sdvo->color_range_auto = false;
  1799. intel_sdvo->color_range = 0;
  1800. break;
  1801. case INTEL_BROADCAST_RGB_LIMITED:
  1802. intel_sdvo->color_range_auto = false;
  1803. /* FIXME: this bit is only valid when using TMDS
  1804. * encoding and 8 bit per color mode. */
  1805. intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
  1806. break;
  1807. default:
  1808. return -EINVAL;
  1809. }
  1810. if (old_auto == intel_sdvo->color_range_auto &&
  1811. old_range == intel_sdvo->color_range)
  1812. return 0;
  1813. goto done;
  1814. }
  1815. #define CHECK_PROPERTY(name, NAME) \
  1816. if (intel_sdvo_connector->name == property) { \
  1817. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1818. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1819. cmd = SDVO_CMD_SET_##NAME; \
  1820. intel_sdvo_connector->cur_##name = temp_value; \
  1821. goto set_value; \
  1822. }
  1823. if (property == intel_sdvo_connector->tv_format) {
  1824. if (val >= TV_FORMAT_NUM)
  1825. return -EINVAL;
  1826. if (intel_sdvo->tv_format_index ==
  1827. intel_sdvo_connector->tv_format_supported[val])
  1828. return 0;
  1829. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1830. goto done;
  1831. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1832. temp_value = val;
  1833. if (intel_sdvo_connector->left == property) {
  1834. drm_object_property_set_value(&connector->base,
  1835. intel_sdvo_connector->right, val);
  1836. if (intel_sdvo_connector->left_margin == temp_value)
  1837. return 0;
  1838. intel_sdvo_connector->left_margin = temp_value;
  1839. intel_sdvo_connector->right_margin = temp_value;
  1840. temp_value = intel_sdvo_connector->max_hscan -
  1841. intel_sdvo_connector->left_margin;
  1842. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1843. goto set_value;
  1844. } else if (intel_sdvo_connector->right == property) {
  1845. drm_object_property_set_value(&connector->base,
  1846. intel_sdvo_connector->left, val);
  1847. if (intel_sdvo_connector->right_margin == temp_value)
  1848. return 0;
  1849. intel_sdvo_connector->left_margin = temp_value;
  1850. intel_sdvo_connector->right_margin = temp_value;
  1851. temp_value = intel_sdvo_connector->max_hscan -
  1852. intel_sdvo_connector->left_margin;
  1853. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1854. goto set_value;
  1855. } else if (intel_sdvo_connector->top == property) {
  1856. drm_object_property_set_value(&connector->base,
  1857. intel_sdvo_connector->bottom, val);
  1858. if (intel_sdvo_connector->top_margin == temp_value)
  1859. return 0;
  1860. intel_sdvo_connector->top_margin = temp_value;
  1861. intel_sdvo_connector->bottom_margin = temp_value;
  1862. temp_value = intel_sdvo_connector->max_vscan -
  1863. intel_sdvo_connector->top_margin;
  1864. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1865. goto set_value;
  1866. } else if (intel_sdvo_connector->bottom == property) {
  1867. drm_object_property_set_value(&connector->base,
  1868. intel_sdvo_connector->top, val);
  1869. if (intel_sdvo_connector->bottom_margin == temp_value)
  1870. return 0;
  1871. intel_sdvo_connector->top_margin = temp_value;
  1872. intel_sdvo_connector->bottom_margin = temp_value;
  1873. temp_value = intel_sdvo_connector->max_vscan -
  1874. intel_sdvo_connector->top_margin;
  1875. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1876. goto set_value;
  1877. }
  1878. CHECK_PROPERTY(hpos, HPOS)
  1879. CHECK_PROPERTY(vpos, VPOS)
  1880. CHECK_PROPERTY(saturation, SATURATION)
  1881. CHECK_PROPERTY(contrast, CONTRAST)
  1882. CHECK_PROPERTY(hue, HUE)
  1883. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1884. CHECK_PROPERTY(sharpness, SHARPNESS)
  1885. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1886. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1887. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1888. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1889. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1890. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1891. }
  1892. return -EINVAL; /* unknown property */
  1893. set_value:
  1894. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1895. return -EIO;
  1896. done:
  1897. if (intel_sdvo->base.base.crtc)
  1898. intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
  1899. return 0;
  1900. #undef CHECK_PROPERTY
  1901. }
  1902. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1903. .dpms = intel_sdvo_dpms,
  1904. .detect = intel_sdvo_detect,
  1905. .fill_modes = drm_helper_probe_single_connector_modes,
  1906. .set_property = intel_sdvo_set_property,
  1907. .destroy = intel_sdvo_destroy,
  1908. };
  1909. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1910. .get_modes = intel_sdvo_get_modes,
  1911. .mode_valid = intel_sdvo_mode_valid,
  1912. .best_encoder = intel_best_encoder,
  1913. };
  1914. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1915. {
  1916. struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
  1917. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1918. drm_mode_destroy(encoder->dev,
  1919. intel_sdvo->sdvo_lvds_fixed_mode);
  1920. i2c_del_adapter(&intel_sdvo->ddc);
  1921. intel_encoder_destroy(encoder);
  1922. }
  1923. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1924. .destroy = intel_sdvo_enc_destroy,
  1925. };
  1926. static void
  1927. intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  1928. {
  1929. uint16_t mask = 0;
  1930. unsigned int num_bits;
  1931. /* Make a mask of outputs less than or equal to our own priority in the
  1932. * list.
  1933. */
  1934. switch (sdvo->controlled_output) {
  1935. case SDVO_OUTPUT_LVDS1:
  1936. mask |= SDVO_OUTPUT_LVDS1;
  1937. case SDVO_OUTPUT_LVDS0:
  1938. mask |= SDVO_OUTPUT_LVDS0;
  1939. case SDVO_OUTPUT_TMDS1:
  1940. mask |= SDVO_OUTPUT_TMDS1;
  1941. case SDVO_OUTPUT_TMDS0:
  1942. mask |= SDVO_OUTPUT_TMDS0;
  1943. case SDVO_OUTPUT_RGB1:
  1944. mask |= SDVO_OUTPUT_RGB1;
  1945. case SDVO_OUTPUT_RGB0:
  1946. mask |= SDVO_OUTPUT_RGB0;
  1947. break;
  1948. }
  1949. /* Count bits to find what number we are in the priority list. */
  1950. mask &= sdvo->caps.output_flags;
  1951. num_bits = hweight16(mask);
  1952. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1953. if (num_bits > 3)
  1954. num_bits = 3;
  1955. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1956. sdvo->ddc_bus = 1 << num_bits;
  1957. }
  1958. /**
  1959. * Choose the appropriate DDC bus for control bus switch command for this
  1960. * SDVO output based on the controlled output.
  1961. *
  1962. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1963. * outputs, then LVDS outputs.
  1964. */
  1965. static void
  1966. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1967. struct intel_sdvo *sdvo, u32 reg)
  1968. {
  1969. struct sdvo_device_mapping *mapping;
  1970. if (sdvo->is_sdvob)
  1971. mapping = &(dev_priv->sdvo_mappings[0]);
  1972. else
  1973. mapping = &(dev_priv->sdvo_mappings[1]);
  1974. if (mapping->initialized)
  1975. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1976. else
  1977. intel_sdvo_guess_ddc_bus(sdvo);
  1978. }
  1979. static void
  1980. intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
  1981. struct intel_sdvo *sdvo, u32 reg)
  1982. {
  1983. struct sdvo_device_mapping *mapping;
  1984. u8 pin;
  1985. if (sdvo->is_sdvob)
  1986. mapping = &dev_priv->sdvo_mappings[0];
  1987. else
  1988. mapping = &dev_priv->sdvo_mappings[1];
  1989. if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
  1990. pin = mapping->i2c_pin;
  1991. else
  1992. pin = GMBUS_PORT_DPB;
  1993. sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
  1994. /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
  1995. * our code totally fails once we start using gmbus. Hence fall back to
  1996. * bit banging for now. */
  1997. intel_gmbus_force_bit(sdvo->i2c, true);
  1998. }
  1999. /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
  2000. static void
  2001. intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
  2002. {
  2003. intel_gmbus_force_bit(sdvo->i2c, false);
  2004. }
  2005. static bool
  2006. intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
  2007. {
  2008. return intel_sdvo_check_supp_encode(intel_sdvo);
  2009. }
  2010. static u8
  2011. intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
  2012. {
  2013. struct drm_i915_private *dev_priv = dev->dev_private;
  2014. struct sdvo_device_mapping *my_mapping, *other_mapping;
  2015. if (sdvo->is_sdvob) {
  2016. my_mapping = &dev_priv->sdvo_mappings[0];
  2017. other_mapping = &dev_priv->sdvo_mappings[1];
  2018. } else {
  2019. my_mapping = &dev_priv->sdvo_mappings[1];
  2020. other_mapping = &dev_priv->sdvo_mappings[0];
  2021. }
  2022. /* If the BIOS described our SDVO device, take advantage of it. */
  2023. if (my_mapping->slave_addr)
  2024. return my_mapping->slave_addr;
  2025. /* If the BIOS only described a different SDVO device, use the
  2026. * address that it isn't using.
  2027. */
  2028. if (other_mapping->slave_addr) {
  2029. if (other_mapping->slave_addr == 0x70)
  2030. return 0x72;
  2031. else
  2032. return 0x70;
  2033. }
  2034. /* No SDVO device info is found for another DVO port,
  2035. * so use mapping assumption we had before BIOS parsing.
  2036. */
  2037. if (sdvo->is_sdvob)
  2038. return 0x70;
  2039. else
  2040. return 0x72;
  2041. }
  2042. static void
  2043. intel_sdvo_connector_unregister(struct intel_connector *intel_connector)
  2044. {
  2045. struct drm_connector *drm_connector;
  2046. struct intel_sdvo *sdvo_encoder;
  2047. drm_connector = &intel_connector->base;
  2048. sdvo_encoder = intel_attached_sdvo(&intel_connector->base);
  2049. sysfs_remove_link(&drm_connector->kdev->kobj,
  2050. sdvo_encoder->ddc.dev.kobj.name);
  2051. intel_connector_unregister(intel_connector);
  2052. }
  2053. static int
  2054. intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
  2055. struct intel_sdvo *encoder)
  2056. {
  2057. struct drm_connector *drm_connector;
  2058. int ret;
  2059. drm_connector = &connector->base.base;
  2060. ret = drm_connector_init(encoder->base.base.dev,
  2061. drm_connector,
  2062. &intel_sdvo_connector_funcs,
  2063. connector->base.base.connector_type);
  2064. if (ret < 0)
  2065. return ret;
  2066. drm_connector_helper_add(drm_connector,
  2067. &intel_sdvo_connector_helper_funcs);
  2068. connector->base.base.interlace_allowed = 1;
  2069. connector->base.base.doublescan_allowed = 0;
  2070. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  2071. connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
  2072. connector->base.unregister = intel_sdvo_connector_unregister;
  2073. intel_connector_attach_encoder(&connector->base, &encoder->base);
  2074. ret = drm_sysfs_connector_add(drm_connector);
  2075. if (ret < 0)
  2076. goto err1;
  2077. ret = sysfs_create_link(&drm_connector->kdev->kobj,
  2078. &encoder->ddc.dev.kobj,
  2079. encoder->ddc.dev.kobj.name);
  2080. if (ret < 0)
  2081. goto err2;
  2082. return 0;
  2083. err2:
  2084. drm_sysfs_connector_remove(drm_connector);
  2085. err1:
  2086. drm_connector_cleanup(drm_connector);
  2087. return ret;
  2088. }
  2089. static void
  2090. intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
  2091. struct intel_sdvo_connector *connector)
  2092. {
  2093. struct drm_device *dev = connector->base.base.dev;
  2094. intel_attach_force_audio_property(&connector->base.base);
  2095. if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
  2096. intel_attach_broadcast_rgb_property(&connector->base.base);
  2097. intel_sdvo->color_range_auto = true;
  2098. }
  2099. }
  2100. static bool
  2101. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  2102. {
  2103. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2104. struct drm_connector *connector;
  2105. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  2106. struct intel_connector *intel_connector;
  2107. struct intel_sdvo_connector *intel_sdvo_connector;
  2108. DRM_DEBUG_KMS("initialising DVI device %d\n", device);
  2109. intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
  2110. if (!intel_sdvo_connector)
  2111. return false;
  2112. if (device == 0) {
  2113. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  2114. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  2115. } else if (device == 1) {
  2116. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  2117. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  2118. }
  2119. intel_connector = &intel_sdvo_connector->base;
  2120. connector = &intel_connector->base;
  2121. if (intel_sdvo_get_hotplug_support(intel_sdvo) &
  2122. intel_sdvo_connector->output_flag) {
  2123. intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
  2124. /* Some SDVO devices have one-shot hotplug interrupts.
  2125. * Ensure that they get re-enabled when an interrupt happens.
  2126. */
  2127. intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
  2128. intel_sdvo_enable_hotplug(intel_encoder);
  2129. } else {
  2130. intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  2131. }
  2132. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  2133. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  2134. if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
  2135. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  2136. intel_sdvo->is_hdmi = true;
  2137. }
  2138. if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
  2139. kfree(intel_sdvo_connector);
  2140. return false;
  2141. }
  2142. if (intel_sdvo->is_hdmi)
  2143. intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
  2144. return true;
  2145. }
  2146. static bool
  2147. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  2148. {
  2149. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2150. struct drm_connector *connector;
  2151. struct intel_connector *intel_connector;
  2152. struct intel_sdvo_connector *intel_sdvo_connector;
  2153. DRM_DEBUG_KMS("initialising TV type %d\n", type);
  2154. intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
  2155. if (!intel_sdvo_connector)
  2156. return false;
  2157. intel_connector = &intel_sdvo_connector->base;
  2158. connector = &intel_connector->base;
  2159. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  2160. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  2161. intel_sdvo->controlled_output |= type;
  2162. intel_sdvo_connector->output_flag = type;
  2163. intel_sdvo->is_tv = true;
  2164. if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
  2165. kfree(intel_sdvo_connector);
  2166. return false;
  2167. }
  2168. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  2169. goto err;
  2170. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  2171. goto err;
  2172. return true;
  2173. err:
  2174. drm_sysfs_connector_remove(connector);
  2175. intel_sdvo_destroy(connector);
  2176. return false;
  2177. }
  2178. static bool
  2179. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  2180. {
  2181. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2182. struct drm_connector *connector;
  2183. struct intel_connector *intel_connector;
  2184. struct intel_sdvo_connector *intel_sdvo_connector;
  2185. DRM_DEBUG_KMS("initialising analog device %d\n", device);
  2186. intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
  2187. if (!intel_sdvo_connector)
  2188. return false;
  2189. intel_connector = &intel_sdvo_connector->base;
  2190. connector = &intel_connector->base;
  2191. intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  2192. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  2193. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  2194. if (device == 0) {
  2195. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  2196. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  2197. } else if (device == 1) {
  2198. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  2199. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  2200. }
  2201. if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
  2202. kfree(intel_sdvo_connector);
  2203. return false;
  2204. }
  2205. return true;
  2206. }
  2207. static bool
  2208. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  2209. {
  2210. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2211. struct drm_connector *connector;
  2212. struct intel_connector *intel_connector;
  2213. struct intel_sdvo_connector *intel_sdvo_connector;
  2214. DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
  2215. intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
  2216. if (!intel_sdvo_connector)
  2217. return false;
  2218. intel_connector = &intel_sdvo_connector->base;
  2219. connector = &intel_connector->base;
  2220. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  2221. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  2222. if (device == 0) {
  2223. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  2224. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  2225. } else if (device == 1) {
  2226. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  2227. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  2228. }
  2229. if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
  2230. kfree(intel_sdvo_connector);
  2231. return false;
  2232. }
  2233. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  2234. goto err;
  2235. return true;
  2236. err:
  2237. drm_sysfs_connector_remove(connector);
  2238. intel_sdvo_destroy(connector);
  2239. return false;
  2240. }
  2241. static bool
  2242. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  2243. {
  2244. intel_sdvo->is_tv = false;
  2245. intel_sdvo->is_lvds = false;
  2246. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  2247. if (flags & SDVO_OUTPUT_TMDS0)
  2248. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  2249. return false;
  2250. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  2251. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  2252. return false;
  2253. /* TV has no XXX1 function block */
  2254. if (flags & SDVO_OUTPUT_SVID0)
  2255. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  2256. return false;
  2257. if (flags & SDVO_OUTPUT_CVBS0)
  2258. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  2259. return false;
  2260. if (flags & SDVO_OUTPUT_YPRPB0)
  2261. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
  2262. return false;
  2263. if (flags & SDVO_OUTPUT_RGB0)
  2264. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  2265. return false;
  2266. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  2267. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  2268. return false;
  2269. if (flags & SDVO_OUTPUT_LVDS0)
  2270. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  2271. return false;
  2272. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  2273. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  2274. return false;
  2275. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  2276. unsigned char bytes[2];
  2277. intel_sdvo->controlled_output = 0;
  2278. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  2279. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  2280. SDVO_NAME(intel_sdvo),
  2281. bytes[0], bytes[1]);
  2282. return false;
  2283. }
  2284. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  2285. return true;
  2286. }
  2287. static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
  2288. {
  2289. struct drm_device *dev = intel_sdvo->base.base.dev;
  2290. struct drm_connector *connector, *tmp;
  2291. list_for_each_entry_safe(connector, tmp,
  2292. &dev->mode_config.connector_list, head) {
  2293. if (intel_attached_encoder(connector) == &intel_sdvo->base) {
  2294. drm_sysfs_connector_remove(connector);
  2295. intel_sdvo_destroy(connector);
  2296. }
  2297. }
  2298. }
  2299. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  2300. struct intel_sdvo_connector *intel_sdvo_connector,
  2301. int type)
  2302. {
  2303. struct drm_device *dev = intel_sdvo->base.base.dev;
  2304. struct intel_sdvo_tv_format format;
  2305. uint32_t format_map, i;
  2306. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  2307. return false;
  2308. BUILD_BUG_ON(sizeof(format) != 6);
  2309. if (!intel_sdvo_get_value(intel_sdvo,
  2310. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  2311. &format, sizeof(format)))
  2312. return false;
  2313. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  2314. if (format_map == 0)
  2315. return false;
  2316. intel_sdvo_connector->format_supported_num = 0;
  2317. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  2318. if (format_map & (1 << i))
  2319. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  2320. intel_sdvo_connector->tv_format =
  2321. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  2322. "mode", intel_sdvo_connector->format_supported_num);
  2323. if (!intel_sdvo_connector->tv_format)
  2324. return false;
  2325. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  2326. drm_property_add_enum(
  2327. intel_sdvo_connector->tv_format, i,
  2328. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  2329. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  2330. drm_object_attach_property(&intel_sdvo_connector->base.base.base,
  2331. intel_sdvo_connector->tv_format, 0);
  2332. return true;
  2333. }
  2334. #define ENHANCEMENT(name, NAME) do { \
  2335. if (enhancements.name) { \
  2336. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  2337. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  2338. return false; \
  2339. intel_sdvo_connector->max_##name = data_value[0]; \
  2340. intel_sdvo_connector->cur_##name = response; \
  2341. intel_sdvo_connector->name = \
  2342. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  2343. if (!intel_sdvo_connector->name) return false; \
  2344. drm_object_attach_property(&connector->base, \
  2345. intel_sdvo_connector->name, \
  2346. intel_sdvo_connector->cur_##name); \
  2347. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  2348. data_value[0], data_value[1], response); \
  2349. } \
  2350. } while (0)
  2351. static bool
  2352. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  2353. struct intel_sdvo_connector *intel_sdvo_connector,
  2354. struct intel_sdvo_enhancements_reply enhancements)
  2355. {
  2356. struct drm_device *dev = intel_sdvo->base.base.dev;
  2357. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2358. uint16_t response, data_value[2];
  2359. /* when horizontal overscan is supported, Add the left/right property */
  2360. if (enhancements.overscan_h) {
  2361. if (!intel_sdvo_get_value(intel_sdvo,
  2362. SDVO_CMD_GET_MAX_OVERSCAN_H,
  2363. &data_value, 4))
  2364. return false;
  2365. if (!intel_sdvo_get_value(intel_sdvo,
  2366. SDVO_CMD_GET_OVERSCAN_H,
  2367. &response, 2))
  2368. return false;
  2369. intel_sdvo_connector->max_hscan = data_value[0];
  2370. intel_sdvo_connector->left_margin = data_value[0] - response;
  2371. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  2372. intel_sdvo_connector->left =
  2373. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  2374. if (!intel_sdvo_connector->left)
  2375. return false;
  2376. drm_object_attach_property(&connector->base,
  2377. intel_sdvo_connector->left,
  2378. intel_sdvo_connector->left_margin);
  2379. intel_sdvo_connector->right =
  2380. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  2381. if (!intel_sdvo_connector->right)
  2382. return false;
  2383. drm_object_attach_property(&connector->base,
  2384. intel_sdvo_connector->right,
  2385. intel_sdvo_connector->right_margin);
  2386. DRM_DEBUG_KMS("h_overscan: max %d, "
  2387. "default %d, current %d\n",
  2388. data_value[0], data_value[1], response);
  2389. }
  2390. if (enhancements.overscan_v) {
  2391. if (!intel_sdvo_get_value(intel_sdvo,
  2392. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2393. &data_value, 4))
  2394. return false;
  2395. if (!intel_sdvo_get_value(intel_sdvo,
  2396. SDVO_CMD_GET_OVERSCAN_V,
  2397. &response, 2))
  2398. return false;
  2399. intel_sdvo_connector->max_vscan = data_value[0];
  2400. intel_sdvo_connector->top_margin = data_value[0] - response;
  2401. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2402. intel_sdvo_connector->top =
  2403. drm_property_create_range(dev, 0,
  2404. "top_margin", 0, data_value[0]);
  2405. if (!intel_sdvo_connector->top)
  2406. return false;
  2407. drm_object_attach_property(&connector->base,
  2408. intel_sdvo_connector->top,
  2409. intel_sdvo_connector->top_margin);
  2410. intel_sdvo_connector->bottom =
  2411. drm_property_create_range(dev, 0,
  2412. "bottom_margin", 0, data_value[0]);
  2413. if (!intel_sdvo_connector->bottom)
  2414. return false;
  2415. drm_object_attach_property(&connector->base,
  2416. intel_sdvo_connector->bottom,
  2417. intel_sdvo_connector->bottom_margin);
  2418. DRM_DEBUG_KMS("v_overscan: max %d, "
  2419. "default %d, current %d\n",
  2420. data_value[0], data_value[1], response);
  2421. }
  2422. ENHANCEMENT(hpos, HPOS);
  2423. ENHANCEMENT(vpos, VPOS);
  2424. ENHANCEMENT(saturation, SATURATION);
  2425. ENHANCEMENT(contrast, CONTRAST);
  2426. ENHANCEMENT(hue, HUE);
  2427. ENHANCEMENT(sharpness, SHARPNESS);
  2428. ENHANCEMENT(brightness, BRIGHTNESS);
  2429. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2430. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2431. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2432. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2433. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2434. if (enhancements.dot_crawl) {
  2435. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2436. return false;
  2437. intel_sdvo_connector->max_dot_crawl = 1;
  2438. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2439. intel_sdvo_connector->dot_crawl =
  2440. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2441. if (!intel_sdvo_connector->dot_crawl)
  2442. return false;
  2443. drm_object_attach_property(&connector->base,
  2444. intel_sdvo_connector->dot_crawl,
  2445. intel_sdvo_connector->cur_dot_crawl);
  2446. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2447. }
  2448. return true;
  2449. }
  2450. static bool
  2451. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2452. struct intel_sdvo_connector *intel_sdvo_connector,
  2453. struct intel_sdvo_enhancements_reply enhancements)
  2454. {
  2455. struct drm_device *dev = intel_sdvo->base.base.dev;
  2456. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2457. uint16_t response, data_value[2];
  2458. ENHANCEMENT(brightness, BRIGHTNESS);
  2459. return true;
  2460. }
  2461. #undef ENHANCEMENT
  2462. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2463. struct intel_sdvo_connector *intel_sdvo_connector)
  2464. {
  2465. union {
  2466. struct intel_sdvo_enhancements_reply reply;
  2467. uint16_t response;
  2468. } enhancements;
  2469. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2470. enhancements.response = 0;
  2471. intel_sdvo_get_value(intel_sdvo,
  2472. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2473. &enhancements, sizeof(enhancements));
  2474. if (enhancements.response == 0) {
  2475. DRM_DEBUG_KMS("No enhancement is supported\n");
  2476. return true;
  2477. }
  2478. if (IS_TV(intel_sdvo_connector))
  2479. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2480. else if (IS_LVDS(intel_sdvo_connector))
  2481. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2482. else
  2483. return true;
  2484. }
  2485. static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2486. struct i2c_msg *msgs,
  2487. int num)
  2488. {
  2489. struct intel_sdvo *sdvo = adapter->algo_data;
  2490. if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2491. return -EIO;
  2492. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2493. }
  2494. static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2495. {
  2496. struct intel_sdvo *sdvo = adapter->algo_data;
  2497. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2498. }
  2499. static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
  2500. .master_xfer = intel_sdvo_ddc_proxy_xfer,
  2501. .functionality = intel_sdvo_ddc_proxy_func
  2502. };
  2503. static bool
  2504. intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
  2505. struct drm_device *dev)
  2506. {
  2507. sdvo->ddc.owner = THIS_MODULE;
  2508. sdvo->ddc.class = I2C_CLASS_DDC;
  2509. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2510. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2511. sdvo->ddc.algo_data = sdvo;
  2512. sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
  2513. return i2c_add_adapter(&sdvo->ddc) == 0;
  2514. }
  2515. bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
  2516. {
  2517. struct drm_i915_private *dev_priv = dev->dev_private;
  2518. struct intel_encoder *intel_encoder;
  2519. struct intel_sdvo *intel_sdvo;
  2520. int i;
  2521. intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
  2522. if (!intel_sdvo)
  2523. return false;
  2524. intel_sdvo->sdvo_reg = sdvo_reg;
  2525. intel_sdvo->is_sdvob = is_sdvob;
  2526. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
  2527. intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
  2528. if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
  2529. goto err_i2c_bus;
  2530. /* encoder type will be decided later */
  2531. intel_encoder = &intel_sdvo->base;
  2532. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2533. drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
  2534. /* Read the regs to test if we can talk to the device */
  2535. for (i = 0; i < 0x40; i++) {
  2536. u8 byte;
  2537. if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
  2538. DRM_DEBUG_KMS("No SDVO device found on %s\n",
  2539. SDVO_NAME(intel_sdvo));
  2540. goto err;
  2541. }
  2542. }
  2543. intel_encoder->compute_config = intel_sdvo_compute_config;
  2544. intel_encoder->disable = intel_disable_sdvo;
  2545. intel_encoder->pre_enable = intel_sdvo_pre_enable;
  2546. intel_encoder->enable = intel_enable_sdvo;
  2547. intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
  2548. intel_encoder->get_config = intel_sdvo_get_config;
  2549. /* In default case sdvo lvds is false */
  2550. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2551. goto err;
  2552. if (intel_sdvo_output_setup(intel_sdvo,
  2553. intel_sdvo->caps.output_flags) != true) {
  2554. DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
  2555. SDVO_NAME(intel_sdvo));
  2556. /* Output_setup can leave behind connectors! */
  2557. goto err_output;
  2558. }
  2559. /* Only enable the hotplug irq if we need it, to work around noisy
  2560. * hotplug lines.
  2561. */
  2562. if (intel_sdvo->hotplug_active) {
  2563. intel_encoder->hpd_pin =
  2564. intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
  2565. }
  2566. /*
  2567. * Cloning SDVO with anything is often impossible, since the SDVO
  2568. * encoder can request a special input timing mode. And even if that's
  2569. * not the case we have evidence that cloning a plain unscaled mode with
  2570. * VGA doesn't really work. Furthermore the cloning flags are way too
  2571. * simplistic anyway to express such constraints, so just give up on
  2572. * cloning for SDVO encoders.
  2573. */
  2574. intel_sdvo->base.cloneable = 0;
  2575. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2576. /* Set the input timing to the screen. Assume always input 0. */
  2577. if (!intel_sdvo_set_target_input(intel_sdvo))
  2578. goto err_output;
  2579. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2580. &intel_sdvo->pixel_clock_min,
  2581. &intel_sdvo->pixel_clock_max))
  2582. goto err_output;
  2583. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2584. "clock range %dMHz - %dMHz, "
  2585. "input 1: %c, input 2: %c, "
  2586. "output 1: %c, output 2: %c\n",
  2587. SDVO_NAME(intel_sdvo),
  2588. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2589. intel_sdvo->caps.device_rev_id,
  2590. intel_sdvo->pixel_clock_min / 1000,
  2591. intel_sdvo->pixel_clock_max / 1000,
  2592. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2593. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2594. /* check currently supported outputs */
  2595. intel_sdvo->caps.output_flags &
  2596. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2597. intel_sdvo->caps.output_flags &
  2598. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2599. return true;
  2600. err_output:
  2601. intel_sdvo_output_cleanup(intel_sdvo);
  2602. err:
  2603. drm_encoder_cleanup(&intel_encoder->base);
  2604. i2c_del_adapter(&intel_sdvo->ddc);
  2605. err_i2c_bus:
  2606. intel_sdvo_unselect_i2c_bus(intel_sdvo);
  2607. kfree(intel_sdvo);
  2608. return false;
  2609. }