intel_dsi.c 23 KB

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  1. /*
  2. * Copyright © 2013 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Author: Jani Nikula <jani.nikula@intel.com>
  24. */
  25. #include <drm/drmP.h>
  26. #include <drm/drm_crtc.h>
  27. #include <drm/drm_edid.h>
  28. #include <drm/i915_drm.h>
  29. #include <linux/slab.h>
  30. #include "i915_drv.h"
  31. #include "intel_drv.h"
  32. #include "intel_dsi.h"
  33. #include "intel_dsi_cmd.h"
  34. /* the sub-encoders aka panel drivers */
  35. static const struct intel_dsi_device intel_dsi_devices[] = {
  36. {
  37. .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
  38. .name = "vbt-generic-dsi-vid-mode-display",
  39. .dev_ops = &vbt_generic_dsi_display_ops,
  40. },
  41. };
  42. static void band_gap_reset(struct drm_i915_private *dev_priv)
  43. {
  44. mutex_lock(&dev_priv->dpio_lock);
  45. vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
  46. vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
  47. vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
  48. udelay(150);
  49. vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
  50. vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
  51. mutex_unlock(&dev_priv->dpio_lock);
  52. }
  53. static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
  54. {
  55. return container_of(intel_attached_encoder(connector),
  56. struct intel_dsi, base);
  57. }
  58. static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
  59. {
  60. return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
  61. }
  62. static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
  63. {
  64. return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
  65. }
  66. static void intel_dsi_hot_plug(struct intel_encoder *encoder)
  67. {
  68. DRM_DEBUG_KMS("\n");
  69. }
  70. static bool intel_dsi_compute_config(struct intel_encoder *encoder,
  71. struct intel_crtc_config *config)
  72. {
  73. struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
  74. base);
  75. struct intel_connector *intel_connector = intel_dsi->attached_connector;
  76. struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  77. struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
  78. struct drm_display_mode *mode = &config->requested_mode;
  79. DRM_DEBUG_KMS("\n");
  80. if (fixed_mode)
  81. intel_fixed_panel_mode(fixed_mode, adjusted_mode);
  82. if (intel_dsi->dev.dev_ops->mode_fixup)
  83. return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
  84. mode, adjusted_mode);
  85. return true;
  86. }
  87. static void intel_dsi_device_ready(struct intel_encoder *encoder)
  88. {
  89. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  90. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  91. int pipe = intel_crtc->pipe;
  92. u32 val;
  93. DRM_DEBUG_KMS("\n");
  94. mutex_lock(&dev_priv->dpio_lock);
  95. /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
  96. * needed everytime after power gate */
  97. vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
  98. mutex_unlock(&dev_priv->dpio_lock);
  99. /* bandgap reset is needed after everytime we do power gate */
  100. band_gap_reset(dev_priv);
  101. I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
  102. usleep_range(2500, 3000);
  103. val = I915_READ(MIPI_PORT_CTRL(pipe));
  104. I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
  105. usleep_range(1000, 1500);
  106. I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
  107. usleep_range(2500, 3000);
  108. I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
  109. usleep_range(2500, 3000);
  110. }
  111. static void intel_dsi_enable(struct intel_encoder *encoder)
  112. {
  113. struct drm_device *dev = encoder->base.dev;
  114. struct drm_i915_private *dev_priv = dev->dev_private;
  115. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  116. struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  117. int pipe = intel_crtc->pipe;
  118. u32 temp;
  119. DRM_DEBUG_KMS("\n");
  120. if (is_cmd_mode(intel_dsi))
  121. I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
  122. else {
  123. msleep(20); /* XXX */
  124. dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN);
  125. msleep(100);
  126. if (intel_dsi->dev.dev_ops->enable)
  127. intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
  128. /* assert ip_tg_enable signal */
  129. temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
  130. temp = temp | intel_dsi->port_bits;
  131. I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
  132. POSTING_READ(MIPI_PORT_CTRL(pipe));
  133. }
  134. }
  135. static void intel_dsi_pre_enable(struct intel_encoder *encoder)
  136. {
  137. struct drm_device *dev = encoder->base.dev;
  138. struct drm_i915_private *dev_priv = dev->dev_private;
  139. struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  140. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  141. enum pipe pipe = intel_crtc->pipe;
  142. u32 tmp;
  143. DRM_DEBUG_KMS("\n");
  144. /* Disable DPOunit clock gating, can stall pipe
  145. * and we need DPLL REFA always enabled */
  146. tmp = I915_READ(DPLL(pipe));
  147. tmp |= DPLL_REFA_CLK_ENABLE_VLV;
  148. I915_WRITE(DPLL(pipe), tmp);
  149. tmp = I915_READ(DSPCLK_GATE_D);
  150. tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
  151. I915_WRITE(DSPCLK_GATE_D, tmp);
  152. /* put device in ready state */
  153. intel_dsi_device_ready(encoder);
  154. msleep(intel_dsi->panel_on_delay);
  155. if (intel_dsi->dev.dev_ops->panel_reset)
  156. intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
  157. if (intel_dsi->dev.dev_ops->send_otp_cmds)
  158. intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
  159. /* Enable port in pre-enable phase itself because as per hw team
  160. * recommendation, port should be enabled befor plane & pipe */
  161. intel_dsi_enable(encoder);
  162. }
  163. static void intel_dsi_enable_nop(struct intel_encoder *encoder)
  164. {
  165. DRM_DEBUG_KMS("\n");
  166. /* for DSI port enable has to be done before pipe
  167. * and plane enable, so port enable is done in
  168. * pre_enable phase itself unlike other encoders
  169. */
  170. }
  171. static void intel_dsi_pre_disable(struct intel_encoder *encoder)
  172. {
  173. struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  174. DRM_DEBUG_KMS("\n");
  175. if (is_vid_mode(intel_dsi)) {
  176. /* Send Shutdown command to the panel in LP mode */
  177. dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN);
  178. msleep(10);
  179. }
  180. }
  181. static void intel_dsi_disable(struct intel_encoder *encoder)
  182. {
  183. struct drm_device *dev = encoder->base.dev;
  184. struct drm_i915_private *dev_priv = dev->dev_private;
  185. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  186. struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  187. int pipe = intel_crtc->pipe;
  188. u32 temp;
  189. DRM_DEBUG_KMS("\n");
  190. if (is_vid_mode(intel_dsi)) {
  191. /* de-assert ip_tg_enable signal */
  192. temp = I915_READ(MIPI_PORT_CTRL(pipe));
  193. I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
  194. POSTING_READ(MIPI_PORT_CTRL(pipe));
  195. msleep(2);
  196. }
  197. /* Panel commands can be sent when clock is in LP11 */
  198. I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0);
  199. temp = I915_READ(MIPI_CTRL(pipe));
  200. temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
  201. I915_WRITE(MIPI_CTRL(pipe), temp |
  202. intel_dsi->escape_clk_div <<
  203. ESCAPE_CLOCK_DIVIDER_SHIFT);
  204. I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP);
  205. temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe));
  206. temp &= ~VID_MODE_FORMAT_MASK;
  207. I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp);
  208. I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1);
  209. /* if disable packets are sent before sending shutdown packet then in
  210. * some next enable sequence send turn on packet error is observed */
  211. if (intel_dsi->dev.dev_ops->disable)
  212. intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
  213. }
  214. static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
  215. {
  216. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  217. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  218. int pipe = intel_crtc->pipe;
  219. u32 val;
  220. DRM_DEBUG_KMS("\n");
  221. I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER);
  222. usleep_range(2000, 2500);
  223. I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
  224. usleep_range(2000, 2500);
  225. I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER);
  226. usleep_range(2000, 2500);
  227. if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
  228. == 0x00000), 30))
  229. DRM_ERROR("DSI LP not going Low\n");
  230. val = I915_READ(MIPI_PORT_CTRL(pipe));
  231. I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
  232. usleep_range(1000, 1500);
  233. I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
  234. usleep_range(2000, 2500);
  235. vlv_disable_dsi_pll(encoder);
  236. }
  237. static void intel_dsi_post_disable(struct intel_encoder *encoder)
  238. {
  239. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  240. struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  241. u32 val;
  242. DRM_DEBUG_KMS("\n");
  243. intel_dsi_disable(encoder);
  244. intel_dsi_clear_device_ready(encoder);
  245. val = I915_READ(DSPCLK_GATE_D);
  246. val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
  247. I915_WRITE(DSPCLK_GATE_D, val);
  248. if (intel_dsi->dev.dev_ops->disable_panel_power)
  249. intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
  250. msleep(intel_dsi->panel_off_delay);
  251. msleep(intel_dsi->panel_pwr_cycle_delay);
  252. }
  253. static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
  254. enum pipe *pipe)
  255. {
  256. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  257. enum intel_display_power_domain power_domain;
  258. u32 port, func;
  259. enum pipe p;
  260. DRM_DEBUG_KMS("\n");
  261. power_domain = intel_display_port_power_domain(encoder);
  262. if (!intel_display_power_enabled(dev_priv, power_domain))
  263. return false;
  264. /* XXX: this only works for one DSI output */
  265. for (p = PIPE_A; p <= PIPE_B; p++) {
  266. port = I915_READ(MIPI_PORT_CTRL(p));
  267. func = I915_READ(MIPI_DSI_FUNC_PRG(p));
  268. if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
  269. if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
  270. *pipe = p;
  271. return true;
  272. }
  273. }
  274. }
  275. return false;
  276. }
  277. static void intel_dsi_get_config(struct intel_encoder *encoder,
  278. struct intel_crtc_config *pipe_config)
  279. {
  280. DRM_DEBUG_KMS("\n");
  281. /* XXX: read flags, set to adjusted_mode */
  282. }
  283. static enum drm_mode_status
  284. intel_dsi_mode_valid(struct drm_connector *connector,
  285. struct drm_display_mode *mode)
  286. {
  287. struct intel_connector *intel_connector = to_intel_connector(connector);
  288. struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  289. struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
  290. DRM_DEBUG_KMS("\n");
  291. if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
  292. DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
  293. return MODE_NO_DBLESCAN;
  294. }
  295. if (fixed_mode) {
  296. if (mode->hdisplay > fixed_mode->hdisplay)
  297. return MODE_PANEL;
  298. if (mode->vdisplay > fixed_mode->vdisplay)
  299. return MODE_PANEL;
  300. }
  301. return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
  302. }
  303. /* return txclkesc cycles in terms of divider and duration in us */
  304. static u16 txclkesc(u32 divider, unsigned int us)
  305. {
  306. switch (divider) {
  307. case ESCAPE_CLOCK_DIVIDER_1:
  308. default:
  309. return 20 * us;
  310. case ESCAPE_CLOCK_DIVIDER_2:
  311. return 10 * us;
  312. case ESCAPE_CLOCK_DIVIDER_4:
  313. return 5 * us;
  314. }
  315. }
  316. /* return pixels in terms of txbyteclkhs */
  317. static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
  318. {
  319. return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
  320. }
  321. static void set_dsi_timings(struct drm_encoder *encoder,
  322. const struct drm_display_mode *mode)
  323. {
  324. struct drm_device *dev = encoder->dev;
  325. struct drm_i915_private *dev_priv = dev->dev_private;
  326. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  327. struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
  328. int pipe = intel_crtc->pipe;
  329. unsigned int bpp = intel_crtc->config.pipe_bpp;
  330. unsigned int lane_count = intel_dsi->lane_count;
  331. u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
  332. hactive = mode->hdisplay;
  333. hfp = mode->hsync_start - mode->hdisplay;
  334. hsync = mode->hsync_end - mode->hsync_start;
  335. hbp = mode->htotal - mode->hsync_end;
  336. vfp = mode->vsync_start - mode->vdisplay;
  337. vsync = mode->vsync_end - mode->vsync_start;
  338. vbp = mode->vtotal - mode->vsync_end;
  339. /* horizontal values are in terms of high speed byte clock */
  340. hactive = txbyteclkhs(hactive, bpp, lane_count);
  341. hfp = txbyteclkhs(hfp, bpp, lane_count);
  342. hsync = txbyteclkhs(hsync, bpp, lane_count);
  343. hbp = txbyteclkhs(hbp, bpp, lane_count);
  344. I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
  345. I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
  346. /* meaningful for video mode non-burst sync pulse mode only, can be zero
  347. * for non-burst sync events and burst modes */
  348. I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
  349. I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
  350. /* vertical values are in terms of lines */
  351. I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
  352. I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
  353. I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
  354. }
  355. static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
  356. {
  357. struct drm_encoder *encoder = &intel_encoder->base;
  358. struct drm_device *dev = encoder->dev;
  359. struct drm_i915_private *dev_priv = dev->dev_private;
  360. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  361. struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
  362. struct drm_display_mode *adjusted_mode =
  363. &intel_crtc->config.adjusted_mode;
  364. int pipe = intel_crtc->pipe;
  365. unsigned int bpp = intel_crtc->config.pipe_bpp;
  366. u32 val, tmp;
  367. DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
  368. /* escape clock divider, 20MHz, shared for A and C. device ready must be
  369. * off when doing this! txclkesc? */
  370. tmp = I915_READ(MIPI_CTRL(0));
  371. tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
  372. I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
  373. /* read request priority is per pipe */
  374. tmp = I915_READ(MIPI_CTRL(pipe));
  375. tmp &= ~READ_REQUEST_PRIORITY_MASK;
  376. I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
  377. /* XXX: why here, why like this? handling in irq handler?! */
  378. I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
  379. I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
  380. I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg);
  381. I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
  382. adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
  383. adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
  384. set_dsi_timings(encoder, adjusted_mode);
  385. val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
  386. if (is_cmd_mode(intel_dsi)) {
  387. val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
  388. val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
  389. } else {
  390. val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
  391. /* XXX: cross-check bpp vs. pixel format? */
  392. val |= intel_dsi->pixel_format;
  393. }
  394. I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
  395. /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
  396. * stop state. */
  397. /*
  398. * In burst mode, value greater than one DPI line Time in byte clock
  399. * (txbyteclkhs) To timeout this timer 1+ of the above said value is
  400. * recommended.
  401. *
  402. * In non-burst mode, Value greater than one DPI frame time in byte
  403. * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
  404. * is recommended.
  405. *
  406. * In DBI only mode, value greater than one DBI frame time in byte
  407. * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
  408. * is recommended.
  409. */
  410. if (is_vid_mode(intel_dsi) &&
  411. intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
  412. I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
  413. txbyteclkhs(adjusted_mode->htotal, bpp,
  414. intel_dsi->lane_count) + 1);
  415. } else {
  416. I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
  417. txbyteclkhs(adjusted_mode->vtotal *
  418. adjusted_mode->htotal,
  419. bpp, intel_dsi->lane_count) + 1);
  420. }
  421. I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
  422. I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
  423. I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val);
  424. /* dphy stuff */
  425. /* in terms of low power clock */
  426. I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100));
  427. val = 0;
  428. if (intel_dsi->eotp_pkt == 0)
  429. val |= EOT_DISABLE;
  430. if (intel_dsi->clock_stop)
  431. val |= CLOCKSTOP;
  432. /* recovery disables */
  433. I915_WRITE(MIPI_EOT_DISABLE(pipe), val);
  434. /* in terms of low power clock */
  435. I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count);
  436. /* in terms of txbyteclkhs. actual high to low switch +
  437. * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
  438. *
  439. * XXX: write MIPI_STOP_STATE_STALL?
  440. */
  441. I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
  442. intel_dsi->hs_to_lp_count);
  443. /* XXX: low power clock equivalence in terms of byte clock. the number
  444. * of byte clocks occupied in one low power clock. based on txbyteclkhs
  445. * and txclkesc. txclkesc time / txbyteclk time * (105 +
  446. * MIPI_STOP_STATE_STALL) / 105.???
  447. */
  448. I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk);
  449. /* the bw essential for transmitting 16 long packets containing 252
  450. * bytes meant for dcs write memory command is programmed in this
  451. * register in terms of byte clocks. based on dsi transfer rate and the
  452. * number of lanes configured the time taken to transmit 16 long packets
  453. * in a dsi stream varies. */
  454. I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer);
  455. I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
  456. intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
  457. intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
  458. if (is_vid_mode(intel_dsi))
  459. /* Some panels might have resolution which is not a multiple of
  460. * 64 like 1366 x 768. Enable RANDOM resolution support for such
  461. * panels by default */
  462. I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
  463. intel_dsi->video_frmt_cfg_bits |
  464. intel_dsi->video_mode_format |
  465. IP_TG_CONFIG |
  466. RANDOM_DPI_DISPLAY_RESOLUTION);
  467. }
  468. static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
  469. {
  470. DRM_DEBUG_KMS("\n");
  471. intel_dsi_prepare(encoder);
  472. vlv_enable_dsi_pll(encoder);
  473. }
  474. static enum drm_connector_status
  475. intel_dsi_detect(struct drm_connector *connector, bool force)
  476. {
  477. struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
  478. struct intel_encoder *intel_encoder = &intel_dsi->base;
  479. enum intel_display_power_domain power_domain;
  480. enum drm_connector_status connector_status;
  481. struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private;
  482. DRM_DEBUG_KMS("\n");
  483. power_domain = intel_display_port_power_domain(intel_encoder);
  484. intel_display_power_get(dev_priv, power_domain);
  485. connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
  486. intel_display_power_put(dev_priv, power_domain);
  487. return connector_status;
  488. }
  489. static int intel_dsi_get_modes(struct drm_connector *connector)
  490. {
  491. struct intel_connector *intel_connector = to_intel_connector(connector);
  492. struct drm_display_mode *mode;
  493. DRM_DEBUG_KMS("\n");
  494. if (!intel_connector->panel.fixed_mode) {
  495. DRM_DEBUG_KMS("no fixed mode\n");
  496. return 0;
  497. }
  498. mode = drm_mode_duplicate(connector->dev,
  499. intel_connector->panel.fixed_mode);
  500. if (!mode) {
  501. DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
  502. return 0;
  503. }
  504. drm_mode_probed_add(connector, mode);
  505. return 1;
  506. }
  507. static void intel_dsi_destroy(struct drm_connector *connector)
  508. {
  509. struct intel_connector *intel_connector = to_intel_connector(connector);
  510. DRM_DEBUG_KMS("\n");
  511. intel_panel_fini(&intel_connector->panel);
  512. drm_connector_cleanup(connector);
  513. kfree(connector);
  514. }
  515. static const struct drm_encoder_funcs intel_dsi_funcs = {
  516. .destroy = intel_encoder_destroy,
  517. };
  518. static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
  519. .get_modes = intel_dsi_get_modes,
  520. .mode_valid = intel_dsi_mode_valid,
  521. .best_encoder = intel_best_encoder,
  522. };
  523. static const struct drm_connector_funcs intel_dsi_connector_funcs = {
  524. .dpms = intel_connector_dpms,
  525. .detect = intel_dsi_detect,
  526. .destroy = intel_dsi_destroy,
  527. .fill_modes = drm_helper_probe_single_connector_modes,
  528. };
  529. bool intel_dsi_init(struct drm_device *dev)
  530. {
  531. struct intel_dsi *intel_dsi;
  532. struct intel_encoder *intel_encoder;
  533. struct drm_encoder *encoder;
  534. struct intel_connector *intel_connector;
  535. struct drm_connector *connector;
  536. struct drm_display_mode *fixed_mode = NULL;
  537. struct drm_i915_private *dev_priv = dev->dev_private;
  538. const struct intel_dsi_device *dsi;
  539. unsigned int i;
  540. DRM_DEBUG_KMS("\n");
  541. /* There is no detection method for MIPI so rely on VBT */
  542. if (!dev_priv->vbt.has_mipi)
  543. return false;
  544. intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
  545. if (!intel_dsi)
  546. return false;
  547. intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
  548. if (!intel_connector) {
  549. kfree(intel_dsi);
  550. return false;
  551. }
  552. intel_encoder = &intel_dsi->base;
  553. encoder = &intel_encoder->base;
  554. intel_dsi->attached_connector = intel_connector;
  555. if (IS_VALLEYVIEW(dev)) {
  556. dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
  557. } else {
  558. DRM_ERROR("Unsupported Mipi device to reg base");
  559. return false;
  560. }
  561. connector = &intel_connector->base;
  562. drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
  563. /* XXX: very likely not all of these are needed */
  564. intel_encoder->hot_plug = intel_dsi_hot_plug;
  565. intel_encoder->compute_config = intel_dsi_compute_config;
  566. intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
  567. intel_encoder->pre_enable = intel_dsi_pre_enable;
  568. intel_encoder->enable = intel_dsi_enable_nop;
  569. intel_encoder->disable = intel_dsi_pre_disable;
  570. intel_encoder->post_disable = intel_dsi_post_disable;
  571. intel_encoder->get_hw_state = intel_dsi_get_hw_state;
  572. intel_encoder->get_config = intel_dsi_get_config;
  573. intel_connector->get_hw_state = intel_connector_get_hw_state;
  574. intel_connector->unregister = intel_connector_unregister;
  575. for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
  576. dsi = &intel_dsi_devices[i];
  577. intel_dsi->dev = *dsi;
  578. if (dsi->dev_ops->init(&intel_dsi->dev))
  579. break;
  580. }
  581. if (i == ARRAY_SIZE(intel_dsi_devices)) {
  582. DRM_DEBUG_KMS("no device found\n");
  583. goto err;
  584. }
  585. intel_encoder->type = INTEL_OUTPUT_DSI;
  586. intel_encoder->crtc_mask = (1 << 0); /* XXX */
  587. intel_encoder->cloneable = 0;
  588. drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
  589. DRM_MODE_CONNECTOR_DSI);
  590. drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
  591. connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
  592. connector->interlace_allowed = false;
  593. connector->doublescan_allowed = false;
  594. intel_connector_attach_encoder(intel_connector, intel_encoder);
  595. drm_sysfs_connector_add(connector);
  596. fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
  597. if (!fixed_mode) {
  598. DRM_DEBUG_KMS("no fixed mode\n");
  599. goto err;
  600. }
  601. fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
  602. intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
  603. return true;
  604. err:
  605. drm_encoder_cleanup(&intel_encoder->base);
  606. kfree(intel_dsi);
  607. kfree(intel_connector);
  608. return false;
  609. }